Flip chip integrated circuit package with spacer

Abstract

Embodiments of the present application relate to an apparatus and method for flip-chip packaged integrated circuits. In the described example, an apparatus (FIG. 4, 400) includes a semiconductor substrate (403) and at least two columnar bumps (405) formed on an active surface of the semiconductor substrate (403), the at least two columnar bumps (405) extending away from the active surface and having ends spaced apart from the semiconductor substrate, wherein solder material (413) is provided at the ends of the at least two columnar bumps. At least one spacer (411) is formed on the active surface of the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A packaging substrate (409) has a die mounting area on a first surface, the die mounting area including portions that receive the ends of the at least two columnar bumps and receive the ends of the at least one spacer. A molding compound (433) covers the semiconductor substrate, the at least two columnar bumps, the at least one spacer, and at least a portion of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates generally to packaged integrated circuits having stud bumps for flip chip connection to a substrate, and more particularly to an apparatus and method for flip chipping a packaged integrated circuit. Background Art

[0002] In assembling integrated circuits, semiconductor processing is used to form devices on semiconductor wafers. Once processed to a completion stage, individual integrated circuit devices can be separated or "singulated" from each other. The individual devices may be referred to as "bare chips" or as "integrated circuit chips". During the completion of the semiconductor process of forming the circuit on the die, terminals are formed for providing signal and power electrical connections to the circuit within the die. For example, the die may have aluminum or copper bonding pads on the active surface or "face" of the device, which are terminals. The most recent type of packaging that provides packaged integrated circuits for surface mounting to system boards or modules includes "flip chips" on lead frame assemblies disposed within molded packages. In a flip chip integrated circuit package, the integrated circuit has pillars or columns formed on bonding pads on the active surface and extending away from the active surface of the die. The columns may have copper. Solder is formed on the ends of the columns to form columnar bumps. The columns are conductive and the columnar bumps form electrical connections to the bonding pads.

[0003] The individual integrated circuits are then removed from the semiconductor wafer by singulation to form an integrated circuit die. In assembly, the integrated circuit die is positioned so that the active surface of the integrated circuit device faces the surface of the package substrate (for example, a lead frame) in the die mounting area. The conductor in the package substrate may have a conductive pad corresponding to the columnar bump for electrical and physical connection with the die. The solder of the columnar bump is bonded to the package substrate using a thermal reflow process. During the thermal reflow process, heat sufficient to melt the solder is applied. The solder reflows onto the substrate (for example, a lead frame) and then forms a solder joint that physically bonds and electrically connects the integrated circuit die to the package substrate. Unevenly sized pillars or pillars at the ends of the columnar bumps and / or solder materials with uneven solder thickness can form uneven bond wire thicknesses in the solder joints formed during assembly of the packaged integrated circuit. Summary of the invention

[0004] In the described example, an apparatus includes: a semiconductor substrate having an active surface with bonding pads; at least two columnar bumps formed on at least two of the bonding pads, the at least two columnar bumps extending away from the active surface and having ends spaced apart from the semiconductor substrate, wherein solder material is provided at the ends of the at least two columnar bumps. At least one spacer is formed on the active surface of the semiconductor substrate and extends away from the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A package substrate has a die mounting area on a first surface for mounting the semiconductor substrate, the die mounting area including portions that receive the ends of the at least two columnar bumps and receive the ends of the at least one spacer. A molding compound covers the semiconductor substrate, the at least two columns, the at least one spacer, and at least a portion of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a cross-sectional view of a semiconductor substrate having a stud bump.

[0006] Figure 2 is a cross-sectional view of an integrated circuit die with stud bumps mounted on a package substrate.

[0007] Figure 3 is a cross-sectional view of an arrangement including an integrated circuit die having a spacer mounted on a surface of a packaging substrate.

[0008] Figure 4 is a cross-sectional view of an arrangement including an integrated circuit die with stud bumps and spacers after being mounted to a package substrate.

[0009] Figures 5A to 5D is a flow chart of a method for forming stud bumps and spacers on a semiconductor substrate.

[0010] Fig. 6A to N is a diagram illustrating an example Figures 5A to 5D A cross-sectional view of the result of the method for forming an arrangement shown in FIG.

[0011] Figures 7A to 7B Example bump feature shapes for stud bumps for use with several arrangements are illustrated in plan view.

[0012] Figures 8A to 8B Each illustrates an arrangement for mounting an integrated circuit die with a spacer on a package substrate with a lock structure.

[0013] Fig. 9is a cross section illustrating an arrangement of an integrated circuit die mounted on a surface of a lead frame with a spacer in a lock configuration.

[0014] Fig.10 is a cross section illustrating a packaged integrated circuit arrangement.

[0015] Fig.11 is a plan view of a lead frame for use with an arrangement in which the locations of spacers are indicated. DETAILED DESCRIPTION

[0016] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are not necessarily drawn to scale. As further described below, specific structures and surfaces are described as "parallel" to each other. For the purposes of the present invention, when two elements are intended to be located in planes that will not intersect when extended, the elements are "parallel". However, the term "parallel" as used herein also includes surfaces that may be slightly deviated in direction due to manufacturing tolerances. If two surfaces are generally located in planes that are spaced apart and will not intersect when extended infinitely (if the surfaces are made without these deviations), then these surfaces are also parallel.

[0017] As further described below, certain structures and surfaces are described as being "perpendicular" to each other. For purposes of the present invention, when two elements are intended to form a 90-degree angle at the intersection, the elements are "perpendicular". However, the term "perpendicular" as used herein also includes surfaces that may deviate slightly from 90 degrees due to manufacturing tolerances. As further described below, an integrated circuit die including pillar bumps may be mounted to the surface of a "package substrate". As used herein, a package substrate is a substrate for mounting an integrated circuit die when packaging an integrated circuit and may be, for example: a lead frame; a molded interconnect substrate; a pre-molded lead frame; a pre-plated lead frame, a copper substrate; a printed circuit board (PCB); a film with a conductor formed thereon; a strip with a conductor formed thereon; a multilayer substrate having conductors on the surface and at different layers; or a laminate with conductors thereon.

[0018] Figure 1 1 is a cross-sectional view of a portion of a semiconductor substrate (e.g., a semiconductor wafer) (or an individual integrated circuit die) 100 having pillars or posts formed on a surface. There may be one pillar, two pillars, at least two pillars, or many pillars depending on the functionality of the integrated circuits on the semiconductor substrate and the number of signals received by or transmitted from the integrated circuits. Figure 1 In the embodiment, the semiconductor substrate 103 is oriented with the active surface facing upward or "face-up", such as Figure 1oriented and shown in . The semiconductor substrate 103 may have active or passive devices formed within the semiconductor substrate or formed on or above the active surface 104 of the semiconductor substrate 103. In an example, active devices such as transistors or diodes and / or passive devices such as inductors, capacitors, or resistors are formed during semiconductor manufacturing. P-type and N-type regions may be formed in the semiconductor substrate using optical lithography and ion implantation techniques to define the pn junction of the transistor or diode. Dielectric materials such as oxides, nitrides, oxynitrides, and other dielectrics may be thermally grown or deposited above the active surface of the semiconductor substrate or wafer. The dielectric may form an isolation material, form a gate oxide of a transistor, or may form a capacitor dielectric. The dielectric may also electrically isolate a conductive material layer formed above the active surface of the semiconductor substrate. An interconnect conductor may be formed using a conductive material layer comprising a metal or alloy and using optical lithography to define a conductor pattern. Copper conductors may be formed using a chemical mechanical polishing (CMP) process and a metal damascene process or copper plating. Conductive vias or conductive plugs may be used to make vertical connections between conductor layers. Aluminum conductors can be formed using sputtering layers and electroless deposition or electroplating. The semiconductor fabrication process forms multiple identical integrated circuit dies separated from each other by scribe lines on the active surface of the semiconductor substrate. The complete integrated circuit dies can be separated from each other using singulation methods to cut or scribe through the scribe lines and thus form individual integrated circuit dies.

[0019] exist Figure 1 , a semiconductor substrate 103 or a portion thereof is shown, wherein a pillar or column 105 is formed on an active surface 104. The column 105 has a solder bump 107 formed at an end away from the active surface 104 of the semiconductor substrate 103. The complete column with the solder bump is often referred to as a "pillar bump". Since the material of the column is often copper, which is frequently used in semiconductor fabrication, the complete structure 110 is sometimes referred to as a "copper pillar bump". It is more economical to use copper, which has low electrical resistance and can form a low resistance electrical connection. However, other conductive materials can be used to form the column 105. For example Figure 1As shown in , deviations in column size or shape and deviations in process conditions and materials can cause inconsistent column heights of columns 105 (where height is the distance extending away from the active surface 104 of the semiconductor substrate 103). The column may have varying diameters or shapes in different locations on the active surface, which can produce different heights when the column is formed. The solder material can also be deposited in different sizes and heights, and different thickness solder joints can be formed between the column and the substrate during subsequent thermal reflow. As further described below, this height deviation can cause misalignment or device failure when columnar bumps are used to mount the integrated circuit die to the package substrate during solder reflow. Failures may include non-wetting of the plating material on the package substrate during hot solder reflow, and the alignment of the columnar bumps with the substrate may be affected, resulting in misalignment. During testing, the solder joint may fail or be found to be a high resistance joint. The package substrate may be a lead frame. The lead frame may have a pre-plated pad for soldering, the pre-plated pad comprising a thin solderable plating layer, such as nickel, gold, silver, and palladium. Silver spot plating can be used on the lead frame. Gold or nickel gold coating on copper lead frame is used. The stud bumps need to be aligned to the points or pads plated onto the lead frame. In an alternative, an overall pre-plating coating covering all surfaces or only a portion of the lead frame can be used.

[0020] Figure 2 Mounting an integrated circuit with stud bumps to a package substrate is illustrated in cross-sectional view 200. Figure 2 For clarity, Figure 1 Like reference numerals are used for similar elements in FIG. 1 . For example, column 205 corresponds to Figure 1 Column 105. Figure 2 , the integrated circuit die 203 is shown oriented face-down, or "flipped," for assembly as a flip-chip device. Figure 1 In contrast, the semiconductor substrate 103 is shown facing upward.)

[0021] exist Figure 2In the operation shown in , the integrated circuit die 203 (which is a single integrated circuit device obtained from a complete semiconductor substrate or wafer) is shown aligned to be flip-chip mounted to the packaging substrate 209. In one arrangement, the packaging substrate 209 may be a lead frame with conductive pads (not shown) corresponding to the positions of the pillar bumps 210. The pillar bumps 210 include pillars 205 and solder bumps 207. The lead frame may have copper or another conductive material. For example, an alloy such as alloy 42 (a nickel-iron alloy that is 42% nickel and has good electrical conductivity and low thermal expansion and is used for lead frames of semiconductor packages) can be used as a lead frame. In additional alternatives, other metals and conductive metals and alloys can also be used to form the lead frame. In alternative arrangements, the packaging substrate 209 may be a printed circuit board (PCB), a molded interconnect substrate, a pre-molded lead frame, or another substrate for electrical components to be surface mounted. In these alternatives, the packaging substrate may have conductive pads arranged corresponding to the positions of the pillar bumps 210. The conductive pads may be plated with materials that assist solderability, for example, the pads may have nickel, gold or palladium coatings and combinations of these, including: electroless nickel immersion gold (ENIG), electroless nickel, electroless palladium, immersion gold (ENEPIG) and other coatings used for solderability when the components are surface mounted with solder joints. These coatings are very thin, such as a few microns, and are therefore not shown in the figures. In an alternative method, a bare copper portion of the lead frame is used for the pads. In yet another alternative method, the lead frame has a pre-plating layer formed over the entire die mounting surface for use in flip chip mounting. This pre-plating layer may be a material that assists soldering the columnar bumps to the lead frame, for example, nickel and palladium, ENIG, ENEPIG or other combinations of nickel, palladium and gold may be used as pre-plating layers. In another alternative, the bare copper lead frame may be coated with an organic coating such as OSP ("organic solderability preservative") to maintain solderability by preventing oxidation of the copper surface.

[0022] like Figure 2As shown in , when the column 205 has a varying height "D" (the height is the distance that the column extends away from the active surface 204 of the integrated circuit die 203), the solder bond wire formed during the subsequent solder thermal reflow process will have a varying thickness or size. In some cases, the integrated circuit die 203 may even tilt away from the horizontal position during the thermal solder reflow process. If the height variation between the columns 205 is large enough, the variation in the height of the columnar bump 210 may cause an open or weak solder joint to be formed after the solder reflow. If a high resistance solder joint is formed due to the height variation, a field failure such as a solder joint cracking may occur when the solder joint is exposed to current in package testing or later when current flows while passing through the solder joint (when the integrated circuit die is used in operation). If the die tilts when the solder is in a molten state during the thermal reflow, causing the die to move, misalignment may occur between the columnar bump 210 and the pad on the package substrate 209 or during the solder reflow.

[0023] Figure 3 An arrangement including an integrated circuit die 303 having pillars 305 and solder bumps 307 forming pillar bumps 310 is illustrated in cross-sectional view 300. Figure 3 For clarity, Figure 2 Reference numbers for elements similar to those shown in are similar. For example, Figure 2The integrated circuit die 203 corresponds to the integrated circuit die 303. The spacers 311 also extend from the active surface of the integrated circuit die 303 to a height D1 measured from the surface 304 of the integrated circuit die 303. The spacers 311 do not have solder on the spacer ends 312 because in the arrangement, the spacers are not used to couple electrical signals from the integrated circuit die 303 to the substrate 309. Instead, these spacers 311 are used to control the spacing between the active surface of the integrated circuit die 303 and the surface of the package substrate 309 after the integrated circuit die 303 is mounted. A portion of the package substrate 309 is a die mounting area (not shown) where the integrated circuit die 303 will be mounted to the package substrate 309. In an example, the spacers 311 can be formed of the same material as the pillars 305. The spacers 311 will have equal sizes to each other, but not necessarily the same shape, size or diameter as the pillars 305. In one example, the spacers 311 and the pillars 305 are formed simultaneously during the plating process. However, in an alternative arrangement, the spacer 311 may be formed in a process independent of the process of forming the column 305. In an example, the column 305 and the spacer 311 may be formed of copper. In an alternative, the column and the spacer 311 may be formed of another conductive material. In yet another alternative example, the spacer 311 and the column 305 may be formed of different materials. In an alternative, the spacer is formed of another non-reflowable metal. Copper is a convenient material for the spacer because the column is also conveniently formed of copper. Nickel and palladium or nickel and palladium plating can be used. These materials are also commonly used as plating and can therefore be used in the process. The spacer 311 does not need to be conductive, although the spacer can be formed of a conductive material. The spacer 311 should not deform during subsequent processes including thermal reflow.

[0024] Figure 4 An arrangement including an integrated circuit die 403 having pillars 405 forming stud bumps and solder 413 on the pillars 405 is illustrated in cross-sectional view 400. The arrangement is covered with a mold compound 433 covering the integrated circuit die, the pillars 405 and the solder joints 421 and a portion of the package substrate 409. Figure 4 For clarity, Figure 2 Reference numerals for elements similar to those shown in FIG. 4 are similar. For example, integrated circuit die 403 corresponds to Figure 2 203 of . Figure 4 , the result of mounting an integrated circuit die 403 having spacers 411 and pillars 405 with solder joints 421 to a package substrate 409 using a solder reflow process is shown. The integrated circuit die is flip-chip mounted with the active surface facing the package substrate. The solder 413 melts during the heat reflow process and bonds to the surface of the package substrate 409 (the upper surface of the package substrate 409, such as the upper surface of the package substrate 409). Figure 4oriented in the figure) is shown to form a solder joint 421. The ends of the spacers 411 contact the surface of the package substrate 409 and provide a spacing of a predetermined distance D1 which is the height of the spacers 411. Since the spacers 411 have a common and fixed height D1 (due to the use of non-reflowable materials and by using the same feature size among the spacers), the distance D1 is a controlled spacing between the active surface of the integrated circuit die 403 and the surface of the package substrate 409. This controlled predetermined spacing also determines the solder bond line thickness produced after solder reflow of the solder bumps 413 and achieves a predetermined solder bond line thickness as a process parameter. By using spacers arranged as shown in FIG. Figure 2 After assembly, a molding compound such as epoxy is applied to cover the semiconductor die, spacers 411, stud bumps 410, and a portion of package substrate 409 to complete the packaged integrated circuit.

[0025] Figures 5A to 5D The flowchart for forming the arrangement ( Figure 5A ) of the spacer and columnar bump and the main steps for forming the column, solder bump and spacer ( Figures 5B to 5D ) detailed process steps. Figures 6A to 6N Diagrammatic illustration in cross section Figures 5A to 5D The results of the various steps of the flowchart are further described below.

[0026] Figure 5A The main steps for forming the arrangement are illustrated in the flow chart. In step 501, a first portion of a column and a spacer are formed on an active surface of a semiconductor substrate. In step 503, a solder bump is formed on the column. The solder bump and the column form a columnar bump. In step 505, the spacer is extended to a predetermined distance ( Figure 4 In D1, for example), the predetermined distance is the full height of the spacer extending from the surface of the semiconductor substrate. Figures 6A to 6N The result of these steps is shown in cross-section 600 in FIG. 5 , as further described below.

[0027] exist Figure 5B In another flowchart, step 501 is shown (in Figure 5A Details of the Figures 6A to 6E The result of these steps is shown in the cross section 600 shown in FIG. In step 5011, a seed layer or under bump material (UBM) is sputtered on the active surface of the semiconductor substrate. Fig. 6AAs shown in the cross-section 600 of FIG. 600 , the semiconductor substrate 603 has a protective overcoat 621. The protective overcoat 621 may be a nitride, oxide, oxynitride, or other dielectric layer. A bonding pad 623 is shown at the surface of the semiconductor substrate 603 (in this example, the bonding pad 623 is aluminum (Al)). Other metals and alloys may be used as bonding pads, for example, copper may be used. Fig. 6A In an example, a redistribution layer (RDL) 627 is formed over the bonding pad 623. In an example, a copper-on-aluminum (COA) RDL is used by forming a copper layer over the aluminum bonding pad. The RDL layer 627 is formed in the passivation layer 625. In an example, the passivation layer 625 can be polyimide (PI). Fig. 6A , a portion of layer 627 is exposed through an opening in passivation layer 625. A seed layer 631 is formed on the surface of the semiconductor substrate and covers RDL layer 627 and passivation layer 625.

[0028] Return to Figure 5B The method continues at step 5013 of coating the active surface of the semiconductor substrate 603 with a first photoresist 633. The photoresist 633 may be a positive or negative photoresist. The photoresist 633 is located above the seed layer 631.

[0029] Return to Figure 5B The method continues to step 5015 where the first photoresist is patterned to define openings 636, 637 for both the pillars and the spacers. The photoresist is patterned and exposed. Figure 5B In step 5017, the photoresist is developed. Figure 6C The result of this step is shown in a cross-section of , in which the first photoresist 633 is formed with openings, exposing the seed layer 631 in a location 636 above layer 627 for forming a pillar and in a second location 637 above layer 625 and seed layer 631 where the spacer will be formed.

[0030] Return to Figure 5B At step 5019, a plating operation is performed to form a portion of the arranged posts and spacers. Fig.6D The result of the plating operation is shown in the cross section of FIG. In the example described herein, at this stage, like the seed layer 631, the pillar 641 and the spacer 643 are also formed of copper. The plating can be an electroplating process. In an alternative, an electroless plating operation can be performed. The plating operation fills the openings in the first photoresist 633 with material to form the first portion of the pillar 641 and the spacer 643.

[0031] exist Figure 5B The method continues to step 5021, where the first photoresist layer ( Fig.6D633 in ). Fig. 6E The results of the steps are shown in Fig. 6E In FIG. 6 , the seed layer 631 is now exposed because the photoresist 633 is removed (in Fig.6D In the exemplary process, a photoresist stripping process is used. Fig. 6E The result is shown in , where pillars 641 and spacers 643 are shown after removal of the photoresist.

[0032] Return to Figure 5A ,exist Figure 5C The next major step 503 of forming solder material at the ends of the pillars to form pillar bumps is detailed in the flowchart of Figures 6F to 6I The results of the steps are shown in the cross-section illustrated in FIG. Figure 5C In the method, Figure 5B The last step 5021 in the process continues to step 5031. At step 5031, a second photoresist is formed to coat the active surface of the semiconductor wafer. Fig. 6F The result of this step is shown in the cross section of FIG. A second photoresist layer 635 coating the pillars 641 and the spacers 643 is shown.

[0033] Figure 5C The method continues at step 5033, where a second photoresist ( Fig. 6F At step 5035, the second photoresist is developed to expose the ends of the pillars. Figure 6G The result of these steps is shown in the cross section in . The ends of pillars 641 are exposed for further processing while the second photoresist 635 protects spacers 643 .

[0034] Figure 5C The method continues at step 5037, where a solder material is formed on the pillar to form a pillar bump. Figure 6H The result of this step is shown in the cross section of FIG, where a solder layer 645 is shown formed over the end of the pillar 641. Solder is plated over the end of the pillar 641. In an example, a lead-free solder of a tin-silver (SnAg) composition is plated. Other lead-free solders such as tin-silver-copper (SnAgCu or "SAC") may be used. In an alternative, a lead-containing solder such as PbSn may be used. A solder layer 645 is formed over the pillar 641 but not over the spacer 643.

[0035] Figure 5C The method continues at step 5039 where the second photoresist layer is removed. Fig.6I The cross section in shows the result of this step, where the formed pillar bump 610 includes a pillar 641 and a solder layer 645.

[0036] Return to Figure 5A , performing step 505 of forming additional spacer material. Figure 5D The process of step 505 is detailed in the flowchart in . Beginning at step 5051, a semiconductor wafer is coated with a third photoresist layer. Figure 6J The result of step 5051 is shown in the cross-section of , where a third photoresist layer 661 is shown to be formed over the pillars 641 and the spacers 643.

[0037] Figure 5D The method of continues at steps 5053 and 5055, where the third photoresist layer 661 is patterned using an optical lithography step and a photomask, and the patterned photoresist is developed to form openings that expose the ends of the spacers. Figure 6K The result of these steps is shown in the cross-section at , where opening 651 is shown located over spacer 643 while a third photoresist layer remains covering the stud bump formed by stud 641 and solder layer 645 .

[0038] Figure 5D The method continues at step 5057. At step 5057, the spacer is extended by additional electroplating or electroless plating of the spacer material. In an example, the spacer material is copper and the additional copper is plated to extend the spacer to a desired height extending away from the surface of the semiconductor wafer. In an example, the spacer height determines the predetermined distance. Figure 5A After the method to D and the integrated circuit die including the pillar bumps and the spacer is flip-chip mounted to the package substrate (as described above), the length of any one of the at least two pillars plus the thickness of the solder joint formed between the end of the selected pillar and the surface of the package substrate does not differ from the predetermined distance by more than 10%. In the alternative, the additional spacer material may be another material plated on the spacer, such as nickel, palladium, or other materials that are conducive to electroplating or electroless plating. Figure 6L The result of this step is shown in FIG. 6 , where the spacer 643 has an additional portion 653 ( Figure 6K ).

[0039] Figure 5D The method continues at step 5059, where the third photoresist layer 661 (in Figure 6L ), such as Figure 6M The complete pillar bump (610) and the complete spacer (611) formed by the portions 643 and 653 are exposed. The spacer 611 extends from the surface of the semiconductor wafer to a predetermined distance D1 (see Figure 6N By adjusting process conditions during the spacer formation process, the predetermined distance D1 can be controlled, which is determined when the integrated circuit die is later mounted to a packaging substrate (such as a package substrate) in a flip chip arrangement. Figure 4 and described above) provides control of the spacing between the semiconductor surface and the packaging substrate.

[0040] exist Figure 5D The method is completed at step 5061 in which the UBM material is removed. Figure 6N The result of this step is shown in the cross section of FIG. 6 , where the seed layer 631 (at Figure 6M In the exemplary process, an ashing (etching) step is performed to remove the UBM. Figure 6N , a complete pillar bump 610 including pillars 641 and solder layers 645 and a complete spacer 611 are formed at different heights. Distance D1 is a predetermined distance of the spacer 611. Since the spacer height is controlled and can be formed at a predetermined distance, the distance D1 can be used to control the solder bond line thickness achieved during the subsequent flip chip assembly and thermal solder reflow process. The spacers form mechanical support and spacing control for the assembled arrangement.

[0041] Fig. 7A and 7B The bump feature sizes of two stud bumps of different sizes are illustrated in two plan views. Fig. 7A In FIG. 7 , the circular columnar bump feature 751 is shown having a diameter of “X”. In the example, the diameter is in the range of 50 to 150 microns. Figure 7B , the elliptical bump feature 753 is shown to have a width "Y" of approximately 100 microns and a length "Z" of approximately 300 microns. In additional examples, the elliptical bump feature may have a width between 50 and 200 microns; and a length between 100 and 400 microns. Other shapes may be used, and other sizes may be used. When determining the columnar bump feature, the selection of size and shape may be determined by the current that will be carried by the columnar bump for a specific signal from (or to) the integrated circuit. The spacer may also have a size and shape different from the shape of the column, but in a specific arrangement the spacer should all have the same size and shape for a given integrated circuit die. In an example, the first spacer has a first cross-sectional shape and area, and the remaining spacers have a first cross-sectional shape and area. By using the same size and shape for all spacers, the coplanarity of the complete spacer can be maintained. In this way, the spacing distance obtained and the thickness of the solder bond wire formed after solder reflow are uniform across the integrated circuit die when later mounted on the package substrate.

[0042] Fig. 8A and 8B Two additional arrangements in which locking features are provided in the package substrate are illustrated in two cross-sectional views. Fig. 8A In the embodiment, the integrated circuit bare chip 803 (in Fig. 8A803 is shown in the figure) has a spacer 811, and the integrated circuit die 803 has additional spacers and pillar bumps (not shown). The package substrate 809 has a lock structure 819, which is an opening or slot configured to receive the end of the spacer when the integrated circuit die 803 is flip-chip mounted to the package substrate 809. The lock structure 819 provides an alignment guide for the assembly so that the integrated circuit die 803 is properly positioned when the spacer 811 is aligned with the lock structure 819 and inserted into the lock structure 819. Fig. 8A In the embodiment, the locks can be formed by etching the package substrate 809. In an example, the package substrate 809 is a copper lead frame.

[0043] Figure 8B The cross section diagram illustrates the Fig. 8A An alternative arrangement of the lock structure 819 is formed in a manner similar to that of the embodiment of the present invention, however, a stamping or punching operation is used to form the lock structure 819 in the package substrate 809. Again, the integrated circuit die 803 has a spacer 811 in a position such that when the spacer end is inserted into the lock structure 819, a stud bump (also not shown) is provided that is coupled to a pad (also not shown) on the package substrate 809. Figures 8A to 8B The integrated circuit die (not shown in FIG. 1 ) is in the correct alignment for assembling the flip chip integrated circuit die to the package substrate. The use of a package substrate including a lock feature reduces or eliminates the need to pre-plate pads on the substrate to provide alignment between the pillar bumps and the substrate. In an arrangement in which the package substrate includes a lock feature, alignment during solder reflow is maintained by using locks and spacers (some of which are positioned in the locks). For example, pre-plating of pads on leads on a lead frame used as a package substrate may not be required in an application in which a copper lead frame and lock features are used with spacers. Reliable solder joints in the correct position can be formed without pre-plated pads when the lock feature controls the alignment between the flip chip integrated circuit and the package substrate. In an example, a thin pre-plating coating can be provided over the entire lead frame before assembly without forming specific pads that engage specific pillar bumps.

[0044] Fig. 9 An arrangement in which an integrated circuit die 903 is mounted to a package substrate 909 is illustrated in cross section. Fig. 9 For the sake of clarity, Figure 4 Similar elements shown in FIG. 1 are numbered similarly. For example, the package substrate 909 corresponds to Figure 4 The packaging substrate 409 in the Fig. 9 , stud bump 910 is shown after reflow. Fig. 9, after the spacer 911 is placed to extend into the lock structure 919, the surface of the integrated circuit die 903 and the package substrate 909 are spaced a predetermined distance D2. Figures 8A to 8B By comparison, distance D2 is less than the length D1 of the spacer because in this arrangement the spacer extends into the locking structure 919 in the package substrate 909. In this arrangement, the height of the spacer minus the depth of the locking structure forms a predetermined spacing D2 between the active surface of the integrated circuit and the surface of the package substrate. The locking structure 919 may be etched into the package substrate 909 (e.g., Fig. 8A in) or can be stamped into the package substrate (as in Figure 8B The spacing distance D2 can be adjusted by controlling the length of the spacer 911.

[0045] Fig.10 A packaged integrated circuit 1000 including an arrangement is illustrated in cross-sectional view. For clarity, Fig.10 The reference numerals correspond to Fig. 9 For example, the integrated circuit die 1003 corresponds to Fig. 9 The die 903 in Fig.10 1, an integrated circuit die 1003 with stud bumps 1010 and spacers 1011 is flip-chip mounted to a package substrate 1009, for example, a copper leadframe. A latch 1019 is shown with the spacer 1011 inserted into the latch 1019. A mold compound 1033 forms a complete package and surrounds the integrated circuit die 1003, stud bumps 1010 and spacers 1011, and a portion of the package substrate 1009. Thus, the combination of the mold compound, the integrated circuit die, and the package substrate forms a packaged integrated circuit. Other portions of the package substrate 1109, which is a copper leadframe in this example, form external terminals or thermal pads for the complete package and these portions (not shown) are not covered in the mold compound 1033. The mold compound 1033 may be an epoxy, resin, or thermosetting epoxy formed in a block molder. The molding process may be referred to as an "encapsulation" process, even though portions of the package substrate 1009 will be free of molding compound after the "encapsulation" is complete. In an exemplary process, after molding a leadframe strip including a plurality of leadframes receiving a plurality of individual integrated circuit devices, the individual packaged integrated circuits are separated from one another by a sawing or laser operation that cuts through the leadframe material and the molding compound to form the package. Portions of the leadframe are not covered by the molding compound but remain exposed, and these exposed leadframe portions form the external terminals of the packaged integrated circuits. In another example, the complete package may be a quad flat no-lead (QFN) package for surface mounting to a system board.

[0046] Fig.11The package substrate 1109 is illustrated in plan view with the leads 1121 patterned and pads for receiving stud bumps of an integrated circuit die (see, for example, Fig. 9 903 in ). It should be noted that Fig. 9 and 10 The example cross section of does not correspond to Fig.11 A plan view of an additional example packaging substrate in FIG. Fig.11 In FIG. 1 , the elliptical pad 1141 is arranged on the package substrate 1109 to receive the elliptical columnar bump, and the circular pad 1143 is arranged to receive the circular columnar bump.

[0047] exist Fig.11 In FIG. 1 , the package substrate 1109 has a die mounting area indicated as 1135 and a portion 1131 identifying possible locations of spacers on an integrated circuit die to be mounted to the substrate 1109. Note that no Fig.11 , instead, location 1131 indicates where a spacer may be used. Fig.11 The outline of the die mounting area portion 1135 in indicates the location and size of the integrated circuit to be mounted on the substrate 1109. In one example, the spacers are placed at the outer corners of the integrated circuit die. For example, a first spacer may be placed in the first corner of the integrated circuit die, and additional spacers may be placed at the remaining three corners, so that there is a spacer in each of the four corners of the integrated circuit die to be mounted to the substrate 1109. In an additional alternative example marked as 1131, the internal position without the pillar bump may also have a spacer at the position to provide additional mechanical support during thermal reflow and provide solder bond wire thickness control. Since the integrated circuit die and lead frame pattern vary with different integrated circuit designs, the spacer position will also vary depending on the available space and size of the integrated circuit die. Misalignment, die warping, and die tilt can be avoided or reduced by using additional spacers for larger integrated circuit dies.

[0048] Modifications are possible in the arrangements described, and other alternative arrangements are possible within the scope of the claims.

Claims

1. A semiconductor device comprising: a semiconductor substrate having an active surface with bonding pads thereon; at least two stud bumps formed on at least two of the bond pads, the at least two stud bumps extending away from the active surface and having ends spaced apart from the semiconductor substrate, wherein solder material is provided at the ends of the at least two stud bumps; at least one spacer formed of a single metal, the at least one spacer being formed on the active surface of the semiconductor substrate and extending away from the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate; a package substrate having a die mounting area on a first surface for mounting the semiconductor substrate, the die mounting area including portions receiving the ends of the at least two pillar bumps and receiving an end of the at least one spacer; and a molding compound covering the semiconductor substrate, the at least two pillar bumps, the at least one spacer, and at least a portion of the package substrate, The predetermined distance of the at least one spacer determines a spacing between the first surface of the packaging substrate and the active surface of the semiconductor substrate. 2 . The semiconductor device of claim 1 , wherein the solder material at the ends of the at least two stud bumps forms a solder joint on the die mounting area of ​​the package substrate. 3 . The semiconductor device of claim 2 , wherein a thickness of the solder joint formed between the at least two stud bumps and the die mounting area of ​​the package substrate is determined by the predetermined distance of the at least one spacer. 4 . The semiconductor device according to claim 1 , wherein the at least two stud bumps are made of a material selected from one of copper and an alloy thereof. 5 . The semiconductor device of claim 1 , wherein the solder material is one selected from the group consisting of: tin and silver; tin, silver, and copper; and tin and lead.

6. The semiconductor device of claim 1 , wherein the semiconductor substrate is an integrated circuit die having four corners, the at least one spacer is located at one of the four corners, and the device further comprises additional spacers placed at the remaining three corners on the active surface of the integrated circuit die. The semiconductor device of claim 1 , wherein the at least one spacer is a conductive material. The semiconductor device according to claim 7 , wherein the conductive material is copper. 9 . The semiconductor device of claim 1 , wherein the at least one spacer and the at least two stud bumps further comprise copper. 10 . The semiconductor device of claim 1 , wherein the at least two stud bumps have different heights. 11 . The semiconductor device according to claim 10 , wherein the predetermined distance of the spacer is equal to the height of the at least two stud bumps and equal to a height of the solder material attached to each of the at least two stud bumps.

12. A method for semiconductors, comprising: forming at least two pillars and at least one spacer on an active surface of a semiconductor substrate, wherein the at least one spacer is formed of a single metal; forming a solder material at ends of the at least two pillars to form at least two pillar-shaped bumps; adding additional material to extend the at least one spacer to a predetermined distance away from the active surface of the semiconductor substrate; mounting the semiconductor substrate to a packaging substrate, wherein the solder material of the at least two stud bumps forms a solder joint on a surface of the packaging substrate and an end of the at least one spacer contacts the packaging substrate such that the semiconductor substrate is spaced apart from the packaging substrate by the predetermined distance; and The semiconductor substrate, the at least two stud bumps, the at least one spacer, and a portion of the packaging substrate are covered with a molding compound.

13. The method of claim 12, wherein forming the at least two pillars and the at least one spacer further comprises: sputtering a seed layer onto the active surface of the semiconductor substrate; coating the active surface of the semiconductor substrate with a photoresist; patterning the photoresist to define the at least two posts at locations corresponding to bond pads on the active surface of the semiconductor substrate and the at least one spacer at a spacer location; developing the photoresist to expose the seed layer at the location; plating a material onto the seed layer at the locations to form the at least two posts and the at least one spacer; and The photoresist is removed.

14. The method according to claim 13, wherein the photoresist is a first photoresist, and forming the solder material further comprises: coating the active surface with a second photoresist; patterning the second photoresist to define openings corresponding to the at least two pillars while leaving the at least one spacer covered; exposing the photoresist; developing the photoresist to form openings in the second photoresist exposing the ends of the at least two pillars; plating a solder material onto the ends of the at least two posts; and The second photoresist is removed.

15. The method of claim 14, wherein forming the additional material of the at least one spacer further comprises: coating the active surface with a third photoresist; patterning the third photoresist to form at least one opening corresponding to the at least one spacer; developing the third photoresist to form an opening in the third photoresist to expose the at least one spacer; and Additional material is plated on the at least one spacer to extend the at least one spacer away from the active surface to form a spacer end at the predetermined distance from the active surface.

16. The method of claim 15, wherein the at least one spacer has a first cross-sectional shape and area, and the method further comprises forming additional spacers having the first cross-sectional shape and area on the active surface of the semiconductor substrate.

17. The method of claim 16, wherein a sum of a length of any one of the at least two pillars and a thickness of a solder joint formed between an end of a selected one of the at least two pillars and the surface of the packaging substrate differs from the predetermined distance by no more than 10%.

18. The method of claim 12, wherein the semiconductor substrate is an integrated circuit die and the mold compound together with the integrated circuit die and the packaging substrate forms a packaged integrated circuit.

19. A semiconductor device comprising: a lead frame having a die mounting area on a first surface and having a lock structure extending from the first surface into the lead frame; and A semiconductor substrate having an active surface, the semiconductor substrate further comprising: at least two posts on bonding pads on the active surface of the semiconductor substrate, the at least two posts extending away from the active surface and having solder material disposed on ends of the at least two posts to form at least two stud bumps; and at least one spacer extending from the active surface of the semiconductor substrate to be a predetermined distance from the active surface of the semiconductor substrate and having a spacer end; wherein the semiconductor substrate, the at least two columnar bumps and the at least one spacer are flip-chip mounted to the die mounting area of ​​the lead frame, the solder material forms a solder joint between the first surface of the lead frame and the at least two columnar bumps, and the spacer end and a portion of the at least one spacer are positioned in a selected one of the locking structures extending into the lead frame.

20. The semiconductor device of claim 19, wherein the lock structure is etched into the first surface of the leadframe.

21. The semiconductor device of claim 19, wherein the locking structure is formed by stamping the lead frame.

22. The semiconductor device of claim 19, wherein the predetermined distance is formed by subtracting a depth of the lock structure from a length of the spacer. 23 . The semiconductor device of claim 22 , wherein the predetermined distance of the spacer is equal to a height of the at least two stud bumps and equal to a height of the solder material attached to each of the at least two stud bumps.

24. The semiconductor device of claim 19, further comprising a molding compound covering the semiconductor substrate, the at least two stud bumps, the at least one spacer, and portions of the leadframe.

25. The semiconductor apparatus of claim 24, wherein the semiconductor substrate is an integrated circuit die, and the molding compound together with the leadframe and the integrated circuit die forms a packaged integrated circuit. 26 . The semiconductor device of claim 19 , wherein the at least two stud bumps have different heights.

27. The semiconductor device of claim 19, wherein a surface of each of the lock structures is plated with nickel, gold, palladium, or a combination thereof.

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