A dynamic comparator offset calibration circuit based on adjustable charge pump

Abstract

The present invention proposes a dynamic comparator offset calibration circuit based on an adjustable charge pump, comprising: a comparator, a charge pump circuit, and a logic control circuit. The calibration input of the comparator serves as the output of the circuit, the output of the comparator is connected to the input of the charge pump circuit, and the control end of the charge pump circuit is connected to the output of the logic control circuit. Whenever the output of the comparator changes, the logic control circuit generates a corresponding pulse to control the on / off switching of the charge pump circuit to adjust the charge and discharge rate of the charge pump. The present invention implements a novel calibration technique for high-speed dynamic comparators. The circuit utilizes an adjustable charge pump circuit based on capacitor charge sharing to control the calibration process, thereby reducing the offset voltage of the comparator. The selection of such a value provides a sufficient calibration range and generates negligible calibration noise.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a dynamic comparator offset calibration circuit based on an adjustable charge pump. Background Art

[0002] ADCs (analog-to-digital converters) are core components in future 5G base stations, test and measurement instruments, and other applications, offering broad potential for development. Massive MIMO, a key 5G technology, utilizes a large number of array antennas in base station transceivers. This structure requires corresponding RF transceiver units, leading to a significant increase in the number of RF components used. Modular RF front-end components are no longer sufficient to meet market demand, and the trend toward digitalization is becoming increasingly pronounced. Therefore, the implementation of ADCs is becoming increasingly important. Thanks to the continuous reduction in CMOS feature sizes, the size of various consumer electronics products is also shrinking. Furthermore, communications infrastructure demands higher bandwidth and faster data rates, placing higher demands on ADC performance. SAR (successive approximation register) ADCs, with their low power consumption, small footprint, and simple structure, are a hot topic of research in academia and industry. Based on a binary search algorithm, SAR ADCs compare the input voltage with a reference level and, through successive approximation, produce a final digital output. The comparator is a key module in SAR ADCs, and comparator offset and delay factors play a decisive role in the conversion speed, accuracy, and overall power consumption of the ADC system. Comparator offset voltage is caused by two factors: first, mismatch in the input transistors; second, mismatch in parasitic capacitance at nodes along the differential path. To avoid large fluctuations in the calibration voltage after ADC calibration, which could result in calibration noise, the calibration voltage step must be relatively small. Furthermore, the calibration range must be sufficiently large to compensate for the worst-case mismatch in the comparator. Therefore, designing a comparator offset correction circuit is essential to reducing comparator offset voltage.

[0003] The current comparator offset calibration methods include pre-amplifier current adjustment or load capacitance adjustment, such as Figure 1 As shown. Current regulation is to adjust the substrate of the comparator input transistor, and no additional transistor is required, so the speed of the comparator is less affected. However, if the substrate voltage of the input transistor is too high, the transistor may not be turned off normally. Current regulation can be achieved by directly changing the substrate voltage of the input pair tube, or by introducing a variable current source. However, changing the substrate voltage of the MOS tube requires the use of a relatively expensive double-well process. Load regulation is to achieve calibration by adjusting the size of the load capacitance at the output end of the comparator. Load regulation can either use the capacitance in the capacitor array to change the size of the capacitance, or use a voltage-controlled MOS tube. But at the same time, the load capacitance may affect the operating speed of the comparator. Therefore, the present invention uses a calibration input pair to provide a calibration current for the comparator. Summary of the Invention

[0004] In order to overcome the shortcomings of the existing calibration method, the present invention provides a dynamic comparator offset calibration circuit based on an adjustable charge pump. The circuit provides a calibration current for the comparator to reduce the offset of the comparator.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A dynamic comparator offset calibration circuit based on an adjustable charge pump includes a comparator, a charge pump circuit, and a logic control circuit. The comparator's calibration input serves as the circuit's output, the comparator's output is connected to the charge pump circuit's input, and the charge pump circuit's control terminal is connected to the logic control circuit's output. Whenever the comparator's output changes, the logic control circuit generates corresponding pulses to control the charge pump circuit's on and off, thereby adjusting the charge and discharge rates of the charge pump. The charge pump circuit includes an upper capacitor and a lower capacitor. The upper capacitor is selectively coupled to a power supply voltage or a calibration input voltage, while the lower capacitor is selectively coupled to a ground voltage or the calibration input voltage.

[0007] Furthermore, the comparator is a pre-amplification dynamic comparator, including a pre-amplification stage and a latch stage. The pre-amplification stage can increase the voltage difference of the input signal and improve the speed of the comparator comparison. The pre-amplification stage is used to amplify the differential input voltage and suppress the kick-back noise, and the latch stage uses positive feedback to pull the output voltage to a high level and a low level. The transistor MC1 of the pre-amplification stage in the comparator is connected to the transistor M5 of the latch stage through the node P, and the transistor MC2 of the pre-amplification stage is connected to the transistor M6 of the latch stage through the node Q. Among them, the pre-amplification stage includes input transistors M1, M2, calibration input tubes MC1, MC2, switch tubes MSW1, MSW2, tail current tube M tail1 , and transistors M3 and M4. The gates of M1 and M2 are connected to the input terminals VIP and VIN respectively, and are connected to M3 and MC1, M4 and MC2 respectively through their drains, and are connected to the switch tubes MSW1 and MSW2 respectively through their sources. The gates of the switch tubes MSW1 and MSW2 are connected to the nodes Q and P respectively, and are connected to the tail current tube M through their sources. tail1 Tail current tube M tail1 The gate of transistors M3 and M4 is connected to CLK and the source is connected to the power supply. The gates of transistors MC1 and MC2 are connected to nodes Q and P and the source is connected to the power supply. The latch stage includes the tail current transistor M tail2 , transistor M5-M 10 Tail current tube M tail2 The gate is connected to the inverted CLKB of the clock CLK, the source is connected to the power supply, and the drain is connected to the transistors M9 and M 10 Transistors M9, M10 Through the comparator output node OUT P OUT N The source and drain of transistors M5 and M6 are connected to the source and drain of M7 and M8 respectively, and the source is grounded.

[0008] Under the condition that the CLK frequency is equal to 500MS / s and the VDD voltage is equal to 1.2V, the comparator is simulated 200 times (including mismatch and process errors) to obtain the offset voltage σ of the comparator. offset =24.0mV. Therefore, a calibration circuit is needed to reduce the offset of the comparator. The present invention uses an adjustable charge pump circuit to control the calibration process to balance the mismatch caused by process variations by injecting current through internal nodes.

[0009] Furthermore, the present invention introduces a calibration input pair M in the comparator. c3 、M c4 . Transistor M c3 、M c4 is a voltage-controlled current source. M c3 The gate of the M is connected to the reference voltage VCAL_P, and the VCAL_N regulated by the charge pump circuit is connected to the M C4 The gate. M c3 、M c4 The source and drain of the charge pump are connected to the source and drain of M1 and M2, respectively. The adjustable charge pump circuit consists of two stages. The first stage, consisting of MOS transistors MP1, MP2, MN1, and MN2, operates with a current of 2I and is responsible for the rapid settling of V CAL_N. The second stage, consisting of MOS transistors MP3, MN3, MP4, and MN4, operates with a current of I and provides a stable low current. The gates of MP2 and MN2 are connected to the control logic outputs S1 and S2, while the gates of MP1, MN1, MP3, and MN3 are connected to the comparator output. In calibration mode, the comparator inputs are connected to the common-mode voltage. At the beginning of calibration, the charge pump starts with a current of 3I, achieving the highest pumping speed. MP2 and MN2 are then controlled to disable the first stage, reducing the current to I until V CAL_N stabilizes near a reference level. The partially activated charge pump circuit allows adjustment of the charge pump circuit current. Even the largest mismatch in the comparator can be compensated by adding or subtracting an appropriate number of stages. Partial current in the charge pump circuit can be shut off, enabling regulation of the circuit's output current without consuming static power.

[0010] Furthermore, the charge pump circuit is a charge pump based on capacitor charge sharing, and the circuit is composed of MOS tubes MP1 and MP2, MN1 and MN2 and capacitor C up 、C dn 、C calnMP1 and MN1 are connected to MP2 and MN2 through the X and Y nodes. The sources of MP2 and MN2 are connected to the power supply and ground respectively. up 、C dn The upper plate is connected to the X and Y nodes respectively, and the lower plate is grounded. caln The upper plate of the comparator is connected to VCAL_N, and the lower plate is grounded. When the charge pump is in the precharge state, MP2 and MN2 are turned on, and the X and Y points are precharged to VDD and GND. During the calibration phase, if the offset voltage of the comparator is positive, that is, the comparator output OUT P =1,OUT N =0, then MP1 is turned on, capacitor C caln and C up Charge sharing occurs between them, causing the voltage of VCAL_N to rise.

[0011] Furthermore, the digital control circuit includes an inverter and a NAND gate. The input terminal of the digital control circuit is connected to the output terminal OUT of the comparator. P OUT N The output terminal is connected to the gate of MP2 and MN2. P After three inverters and NAND gate and node UP pre Connected, OUT N Then through an inverter and node DN pre If the comparator offset voltage is positive, OUT N The rising edge of controls MP2 and MN2 through a trigger to close the first stage, thereby controlling the charge and discharge rate of the charge pump.

[0012] The beneficial effects of the present invention are as follows: the present invention implements a novel calibration technique for high-speed dynamic comparators. The circuit utilizes an adjustable charge pump circuit based on capacitor charge sharing to control the calibration process, thereby reducing the offset voltage of the comparator. This value selection provides a sufficient calibration range and generates negligible calibration noise. According to Monte-Carlo simulation results, the offset voltage σ of the comparator after calibration is offset It is 0.69mV, which is a significant improvement compared to the previous 24.0mV. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a schematic diagram of a current regulation or load capacitance regulation structure of a pre-amplifier stage for comparator offset calibration.

[0014] Figure 2 This is a structural principle diagram of a dynamic comparator for providing offset voltage provided by the present invention.

[0015] Figure 3 This is a schematic diagram of the structure of an adjustable charge pump for offset calibration provided by the present invention.

[0016] Figure 4 A schematic diagram of a control logic structure provided by the present invention.

[0017] Figure 5 This is a simulation diagram of the comparator offset voltage before calibration provided by the present invention.

[0018] Figure 6 This is a simulation diagram of the offset voltage of the comparator after calibration provided by the present invention.

[0019] Figure 7 This is a schematic diagram of the SAR ADC structure implemented in the present invention. DETAILED DESCRIPTION

[0020] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

[0021] This embodiment provides a dynamic comparator offset calibration circuit based on an adjustable charge pump, such as Figure 3 As shown, it includes: a comparator, a charge pump circuit and a logic control circuit.

[0022] The circuit structure is as follows Figure 3 The comparator is a pre-amplifier dynamic comparator, which consists of a pre-amplifier stage and a latch stage. The input of the comparator is VIP, VIN, and the output is OUT. P OUT N , the clock signal is CLK. When CLK is low, M3 and M4 are turned on, and the P and Q points are charged to VDD. M5 and M6 are turned on, and the output terminal OUT P =OUT N =0. When CLK is high, M3 and M4 are disconnected, and points P and Q begin to discharge. Assuming VIP>VIN, the discharge speed of point P is faster than that of Q. As the voltage at point P drops, MC2 begins to turn on. The voltage at point Q is quickly pulled up to VDD. MC1 remains in the off state, and the voltage at P is pulled down to GND. The voltage difference between points P and Q increases exponentially, reducing the latch regeneration time of the comparator. The offset voltage of the comparator comes from: first, the mismatch of the input transistors, and second, the mismatch of the parasitic capacitance of the nodes on the differential path. The comparator is simulated 200 times (including mismatch and process errors) to obtain the offset voltage σ of the comparator. offset =24.0mV. Therefore, the present invention adds a calibration input to M C3 、M C4 To calibrate the comparator offset voltage.

[0023] like Figure 3As shown, the adjustable charge pump circuit consists of two stages. The first stage, consisting of MOS transistors MP1, MP2, MN1, and MN2, operates with a current of 2I and is responsible for quickly establishing V CAL_N. The second stage, consisting of MOS transistors MP3, MN3, MP4, and MN4, operates with a current of I and provides a stable low current. The gates of MP2 and MN2 are connected to the control logic outputs S1 and S2, respectively. The gates of MP1, MN1, MP3, and MN3 are connected to the comparator output. In calibration mode, the comparator inputs are connected to the common-mode voltage. At the beginning of calibration, the charge pump starts with a current of 3I, achieving the highest pumping speed. MP2 and MN2 are then controlled to shut down the first stage, reducing the current to I until V CAL_N stabilizes near a reference level.

[0024] like Figure 3 As shown, the charge pump circuit based on capacitor charge sharing consists of MOS tubes MP1 and MP2, MN1 and MN2 and capacitor C up 、C dn 、C caln MP1 and MN1 are connected to MP2 and MN2 through the X and Y nodes. The sources of MP2 and MN2 are connected to the power supply and ground respectively. up 、C dn The upper plate is connected to the X and Y nodes respectively, and the lower plate is grounded. caln The upper plate of the comparator is connected to VCAL_N, and the lower plate is grounded. When the charge pump is in the precharge state, MP2 and MN2 are turned on, and the X and Y points are precharged to VDD and GND. During the calibration phase, if the offset voltage of the comparator is positive, that is, the comparator output OUT P =1,OUT N =0, then MP1 is turned on, capacitor C caln and C up Charge sharing occurs between them, causing the voltage of VCAL_N to rise.

[0025] like Figure 4 As shown, the digital control circuit includes an inverter and a NAND gate. The input end of the digital control circuit is connected to the output end OUT of the comparator. P OUT N The output terminal is connected to the gate of MP2 and MN2. P After three inverters and NAND gate and node UP pre Connected, OUT N Then through an inverter and node DN pre If the comparator offset voltage is positive, OUT N The rising edge of passes through a trigger to control MP2 and MN2 to close the first stage.

[0026] like Figure 5-6As shown in Figure 1, the offset voltage simulation diagram of the comparator before and after calibration is shown. According to the Monte-Carlo simulation results, after adding the comparator offset calibration circuit, the offset voltage σ offset = 0.69mV, a significant improvement over the previous 24.0mV. The partially activated charge pump circuit allows adjustment of the charge pump circuit current. Even the largest mismatch in the comparator can be compensated by adding or subtracting the appropriate number of stages. Part of the charge pump circuit current can be shut off, enabling regulation of the circuit's output current without consuming static power.

[0027] Figure 7 Figure 2 shows the schematic diagram of the SAR ADC architecture implemented in the present invention. The sample-and-hold circuit samples the analog input signal into the ADC system. Based on the comparator's comparison results, the capacitor array CDAC generates the input level for the next comparison through SAR logic control. A reference voltage buffer circuit provides a reference level for the CDAC.

[0028] The present invention's dynamic comparator offset calibration circuit based on an adjustable charge pump implements a novel calibration technique for high-speed dynamic comparators. This circuit utilizes an adjustable charge pump circuit based on capacitor charge sharing to control the calibration process, reducing the comparator's offset voltage. This value provides sufficient calibration range and generates negligible calibration noise.

[0029] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Those skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be based on the claims.

Claims

1. A dynamic comparator offset calibration circuit based on an adjustable charge pump, comprising: Comparator, charge pump circuit and logic control circuit; The calibration input terminal of the comparator serves as the output terminal of the circuit. The output terminal of the comparator is connected to the input terminal of the charge pump circuit. The control terminal of the charge pump circuit is connected to the output terminal of the logic control circuit. When the output of the comparator changes, the logic control circuit generates a corresponding pulse to control the on and off of the charge pump circuit to adjust the charge and discharge rate of the charge pump. The charge pump circuit includes an upper capacitor and a lower capacitor. The upper capacitor is selectively coupled to the power supply voltage or the calibration input voltage, and the lower capacitor is selectively coupled to the ground voltage or the calibration input voltage. The adjustable charge pump circuit includes two stages. The first stage is composed of MOS tubes MP1, MP2, MN1 and MN2. The current is 2I and the negative The second stage includes MOS transistors MP3, MN3, MP4, and MN4, with a current of I, providing a stable low current. The gates of MP2 and MN2 are connected to the output terminals S1 and S2 of the control logic, and the gates of MP1, MN1, MP3, and MN3 are connected to the output of the comparator. At the beginning of calibration, the charge pump starts with a current of 3I to form the highest pump speed. Then, MP2 and MN2 are controlled to close the first stage, reducing the current to I until VCAL_N stabilizes near a certain reference level. The charge pump circuit is a charge pump based on capacitor charge sharing. Its circuit consists of MOS transistors MP1, MP2, MN1, and MN2 and capacitor C up 、C dn 、C caln MP1 and MN1 are connected to MP2 and MN2 through X and Y nodes; the sources of MP2 and MN2 are connected to the power supply and ground respectively; C up 、C dn The upper plate is connected to the X and Y nodes respectively, and the lower plate is grounded; caln The upper plate is connected to VCAL_N, and the lower plate is grounded. When the charge pump is in the precharge state, MP2 and MN2 are turned on, and the X and Y points are precharged to VDD and GND. In the calibration phase, if the offset voltage of the comparator is positive, that is, the comparator output OUT P =1,OUT N =0, then MP1 is turned on, capacitor C caln and C up Charge sharing occurs between them, causing the voltage of VCAL_N to rise.

2. The dynamic comparator offset calibration circuit based on an adjustable charge pump according to claim 1, wherein: The comparator is a pre-amplifier dynamic comparator, including a pre-amplifier stage and a latch stage. The pre-amplifier stage is used to amplify the differential input voltage and suppress the kickback noise. The latch stage uses positive feedback to pull the output voltage to a high level and a low level.

3. The dynamic comparator offset calibration circuit based on an adjustable charge pump according to claim 2, wherein: The pre-amplifier stage includes input transistors M1, M2, calibration input tubes MC1, MC2, switch tubes MSW1, MSW2, tail current tube M tail1 , and transistors M3 and M4; the gates of M1 and M2 are connected to the input terminals VIP and VIN respectively, and are connected to M3, MC1, M4 and MC2 respectively through their drains, and are connected to the switch tubes MSW1 and MSW2 respectively through their sources; the gates of the switch tubes MSW1 and MSW2 are connected to the nodes Q and P respectively, and are connected to the tail current tube M through their sources. tail1 Connected; tail current tube M tail1 The gate of transistors M3 and M4 is connected to the input clock CLK of the comparator, and the source is grounded; the gate of transistors M3 and M4 is connected to CLK, and the source is connected to the power supply; The gates of transistors MC1 and MC2 are connected to nodes Q and P, and the sources are connected to the power supply; The latch stage includes the tail current tube M tail2 , transistor M5-M 10 ; Tail current tube M tail2 The gate is connected to the inverted CLKB of the clock CLK, the source is connected to the power supply, and the drain is connected to the transistors M9 and M 10 Connected; transistors M9, M 10 Through the comparator output node OUT P OUT N are connected to M7 and M8 respectively; the source and drain of transistors M5 and M6 are connected to the source and drain of M7 and M8 respectively, and the source is grounded; The transistor MC1 of the pre-amplifier stage is connected to the transistor M5 of the latch stage via the node P, and the transistor MC2 of the pre-amplifier stage is connected to the transistor M6 of the latch stage via the node Q.

4. The dynamic comparator offset calibration circuit based on an adjustable charge pump according to claim 3, wherein: The input terminal of the digital control circuit and the output terminal OUT of the comparator P OUT N The output terminal is connected to the gate of MP2 and MN2; OUT P After three inverters and NAND gate and node UP pre Connected, OUT N Then through an inverter and node DN pre connected.

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