Semiconductor packaging system

Abstract

A semiconductor packaging system is provided, the semiconductor packaging system comprising a substrate, a first semiconductor package, a second semiconductor package, a first heat-conducting layer, a first passive device and a heat radiation structure. The first semiconductor package, the second semiconductor package and the first passive device may be mounted on the top surface of the substrate. The first semiconductor package may include a first semiconductor chip, and the first semiconductor chip includes a plurality of logic circuits. The first heat-conducting layer may be located on the first semiconductor package. The heat radiation structure may be located on the first heat-conducting layer, the second semiconductor package and the first passive device. The heat radiation structure may include a first bottom surface and a second bottom surface, the first bottom surface is in physical contact with the first heat-conducting layer, and the second bottom surface is located at a level higher than the level of the first bottom surface. The second bottom surface may be located on the second semiconductor package and / or the first passive device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0055079 filed in the Korean Intellectual Property Office on May 14, 2018, Korean Patent Application No. 10-2018-0055081 filed in the Korean Intellectual Property Office on May 14, 2018, and Korean Patent Application No. 10-2018-0110518 filed in the Korean Intellectual Property Office on September 14, 2018. The entire contents of each of the above applications are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a semiconductor packaging system, and more particularly, to a semiconductor packaging system provided with a heat radiation structure. Background Art

[0004] Semiconductor packages can be provided to implement integrated circuit chips and thus approved for use in electronic products. The higher the speed and capacity of the semiconductor package, the greater the power consumption of the semiconductor package. Thermal characteristics are increasingly being recognized as important features in semiconductor packages. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a packaging system having improved thermal characteristics and a semiconductor module including the same.

[0006] According to some example embodiments of the inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package mounted on a top surface of the substrate, the first semiconductor package including a first semiconductor chip, the first semiconductor chip including a plurality of logic circuits; a first heat-conducting layer located on the first semiconductor package; a second semiconductor package mounted on the top surface of the substrate; a first passive device mounted on the top surface of the substrate; and a heat radiation structure located on the first heat-conducting layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface and a second bottom surface. The first bottom surface may be in physical contact with the first heat-conducting layer, and the level of the second bottom surface may be higher than the level of the first bottom surface. The second bottom surface may be disposed on the second semiconductor package, or on the first passive device, or on both the second semiconductor package and the first passive device.

[0007] According to some example embodiments of the present inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package mounted on the substrate; a second semiconductor package mounted on the substrate; a passive device mounted on the substrate; a heat radiation structure located on the first semiconductor package, the second semiconductor package and the passive device; and a plurality of heat conductive layers in physical contact with the heat radiation structure. The first bottom surface of the heat radiation structure may include a groove. When viewed from a top view, the groove may overlap with one or more of the second semiconductor package and the passive device. The heat conductive layer may include a first heat conductive layer located on a top surface of the first semiconductor package. The first heat conductive layer may be thinner than any other heat conductive layer among the plurality of heat conductive layers.

[0008] According to some example embodiments of the present inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package mounted on the substrate; a passive device mounted on the substrate; a heat radiation structure located on the first semiconductor package and the passive device; and a first heat conduction layer located between the first semiconductor package and the heat radiation structure. The height of the passive device may be equal to or greater than the sum of the height of the first semiconductor package and the height of the first heat conduction layer. The heat radiation structure may include a first bottom surface and a second bottom surface. The first bottom surface may be in physical contact with the first heat conduction layer, and the level of the second bottom surface may be higher than the level of the first bottom surface. The second bottom surface of the heat radiation structure may be located on the passive device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A top view showing a packaging system according to some example embodiments is shown.

[0010] Figure 1B A top view showing a packaging system according to some example embodiments is shown.

[0011] Figure 1C Shown along Figure 1A A cross-sectional view taken along line I-II in FIG.

[0012] Figure 1D Shows Figure 1C Magnified view of portion A in FIG.

[0013] Figure 1E Shows Figure 1C Magnified view of portion B in FIG.

[0014] Figure 1F Shown along Figure 1A A cross-sectional view taken along line III-III'.

[0015] Figure 1G A top view showing a first semiconductor package according to some example embodiments is illustrated.

[0016] Figure 1H Shown along Figure 1G A cross-sectional view taken along line I'-II' in FIG. Figure 1G Shows Figure 1C Magnified view of section V in FIG.

[0017] Fig. 1I and Figure 1J 1 shows a cross-sectional view of a first semiconductor package according to some example embodiments, corresponding to a cross-sectional view along Figure 1G The cross-sectional view taken along the line I'-II' in FIG. Figure 1C Magnified view of section V in FIG.

[0018] Figure 1K and 1L A cross-sectional view showing a second semiconductor package according to some example embodiments is shown, corresponding to Figure 1C Magnified view of section V' in FIG.

[0019] Figure 1M and Figure 1N A cross-sectional view showing a third semiconductor package according to some example embodiments is shown, corresponding to Figure 1C Magnified view of section V”.

[0020] Figure 2A A top view showing a packaging system according to some example embodiments is shown.

[0021] Figure 2B Shown along Figure 2A A cross-sectional view taken along line I-II in FIG.

[0022] Figure 2C A top view showing a packaging system according to some example embodiments is shown.

[0023] Figure 2D Shown along Figure 2C A cross-sectional view taken along line I-II in FIG.

[0024] Figure 2E FIG. 1 shows a diagram showing a method of performing a Figure 2C A cross-sectional view of the packaging system taken along line I-II in FIG.

[0025] FIG. 3A to FIG. 3D FIG. 1 shows a diagram showing a method of performing a Figure 2C A cross-sectional view of the packaging system taken along line I-II in FIG.

[0026] Figure 4 Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments.

[0027] Figure 5A A cross-sectional view of a semiconductor module according to some example embodiments is illustrated.

[0028] Figure 5B Shows Figure 5A FIG. 1 is an enlarged view of a portion C in FIG. 1 to show a second passive device according to some example embodiments.

[0029] Figure 5C A cross-sectional view showing a lower pad and a conductive terminal according to some example embodiments is illustrated.

[0030] Figure 5D A cross-sectional view showing a lower pad according to some example embodiments is illustrated. DETAILED DESCRIPTION

[0031] In this specification, the same reference numerals may represent the same components. A packaging system according to the present invention and a semiconductor module including the packaging system will be described below. In the following description, the semiconductor packaging system may be a packaging system or a semiconductor module including the packaging system. Throughout this specification, when a component is described as being located on another component, the one component does not necessarily physically contact the other component. In addition, throughout this specification, the height of any component refers to the maximum distance from the bottom surface of the component to its top surface.

[0032] Figure 1A A top view showing a packaging system according to some example embodiments is shown. Figure 1B A top view showing a packaging system according to some example embodiments is shown. Figure 1C Shown along Figure 1A A cross-sectional view taken along line I-II in FIG. Figure 1D Shows Figure 1C Magnified view of section A in FIG. Figure 1E Shows Figure 1C Magnified view of portion B. Figure 1F Shown along Figure 1A A cross-sectional view taken along line III-III'.

[0033] Reference Figure 1A , Figure 1B , Figure 1C and 1D, the packaging system 1 may include a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive device 400, a heat radiation structure 600, and a first heat conductive layer 710. For example, a printed circuit board (PCB) having a circuit pattern may be used as the substrate 500. The conductive terminal 550 may be disposed on the bottom surface of the substrate 500. The conductive terminal 550 may include one or more of a solder ball, a bump, and a column. The conductive terminal 550 may include a metal.

[0034] The first semiconductor package 100 may be mounted on the top surface 500a of the substrate 500. As will be discussed below, the first semiconductor package 100 may include a system-on-chip or a logic chip. The first connection terminal 150 may be arranged between the substrate 500 and the first semiconductor package 100. The first semiconductor package 100 may be electrically connected to the substrate 500 through the first connection terminal 150. In this specification, the phrase "electrically connected / coupled to the substrate 500" may mean "electrically connected / coupled to the wiring 505 in the substrate 500". The first connection terminal 150 may include a solder ball, a column, a bump, or a ball grid array. The first semiconductor package 100 mounted on the substrate 500 may have a height H1, which is defined as the height including the first connection terminal 150.

[0035] The second semiconductor package 200 may be mounted on the top surface 500a of the substrate 500. When viewed from a top view, the second semiconductor package 200 may be arranged to be spaced apart from the first semiconductor package 100. The type of the second semiconductor package 200 may be different from the type of the first semiconductor package 100. The second connection terminal 250 may be arranged between the substrate 500 and the second semiconductor package 200. The second semiconductor package 200 may be electrically connected to the substrate 500 through the second connection terminal 250. The second connection terminal 250 may include a solder ball, a column, a bump, or a ball grid array. The second semiconductor package 200 mounted on the substrate 500 may have a height H2, which includes the height of the second connection terminal 250. The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200. For example, the level at which the top surface 100a of the first semiconductor package 100 is located may be higher than the level at which the top surface 200a of the second semiconductor package 200 is located. A plurality of second semiconductor packages 200 may be provided.

[0036] The third semiconductor package 300 may be mounted on the top surface 500a of the substrate 500. When viewed from a top view, the third semiconductor package 300 may be disposed to be spaced apart from the first semiconductor package 100 and the second semiconductor package 200. The type of the third semiconductor package 300 may be different from the type of the first semiconductor package 100 and the type of the second semiconductor package 200. Figure 1A As shown, a single third semiconductor package 300 may be provided. Figure 1B As shown, a plurality of third semiconductor packages 300 may be provided. In this case, the third semiconductor packages 300 may be provided to be spaced apart from each other. The number and plane arrangement of the third semiconductor packages 300 may be variously changed. Figure 1C As shown, the third connection terminal 350 may be arranged between the substrate 500 and the third semiconductor package 300. The third semiconductor package 300 may be electrically connected to the substrate 500 through the third connection terminal 350. The third connection terminal 350 may include a solder ball, a pillar, a bump, or a ball grid array. The third semiconductor package 300 mounted on the substrate 500 may have a height H3, and the height H3 includes the height of the third connection terminal 350. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the mounted third semiconductor package 300. For example, the level at which the top surface 100a of the first semiconductor package 100 is located may be higher than the level at which the top surface 300a of the third semiconductor package 300 is located.

[0037] The first semiconductor package 100 may be electrically connected to the second semiconductor package 200 and the third semiconductor package 300 through the wiring 505 of the substrate 500 and electrically connected to the conductive terminal 550. The second semiconductor package 200 may be electrically connected to the first semiconductor package 100 and the third semiconductor package 300 through the substrate 500 and electrically connected to the conductive terminal 550. The third semiconductor package 300 may be electrically connected to the first semiconductor package 100 and the second semiconductor package 200 through the substrate 500 and electrically connected to the conductive terminal 550.

[0038] The first passive device 400 may be mounted on the top surface 500a of the substrate 500. When viewed from a top view, the first passive device 400 may be disposed to be spaced apart from the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. The first passive device 400 may include one or more of an inductor, a resistor, and a capacitor. Figure 1DAs shown, the first connector 411 may be further disposed between the substrate 500 and the first passive device 400. In this case, the first passive device 400 mounted on the substrate 500 may have a height H4, which is defined as including a height H41 of the first connector 411. For example, the height H4 of the mounted first passive device 400 may be equal to the sum of the height H41 of the first connector 411 and the height H40 of the first passive device 400' before being mounted on the substrate 500. The first connector 411 may include a solder ball, a column, or a bump. For simplicity, in addition to Figure 1D The first connector 411 is not shown in other drawings, but the present inventive concept is not limited thereto.

[0039] The heat radiation structure 600 may be disposed on the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 and on the first passive device 400. The heat radiation structure 600 may be spaced apart from the substrate 500. The heat radiation structure 600 may have a top surface 600a and a first bottom surface 601b facing each other. The first bottom surface 601b of the heat radiation structure 600 may be parallel to the top surface 500a of the substrate 500. The first bottom surface 601b of the heat radiation structure 600 may be disposed on the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. The heat radiation structure 600 may include a thermally conductive material. The thermally conductive material may include a metal material (e.g., copper and / or aluminum) or a carbonaceous material (e.g., graphene, graphite, and / or carbon nanotubes). The heat radiation structure 600 may have a relatively high thermal conductivity. For example, a single metal layer or a plurality of stacked metal layers may be used as the heat radiation structure 600. For another example, the heat radiation structure 600 may include a heat sink or a heat pipe. For another example, the heat radiation structure 600 may be configured to use water cooling.

[0040] The first heat conducting layer 710 may be arranged between the first semiconductor package 100 and the heat radiation structure 600. The first heat conducting layer 710 may be in physical contact with the top surface 100a of the first semiconductor package 100 and the first bottom surface 601b of the heat radiation structure 600. The first heat conducting layer 710 may include a thermal interface material (TIM). The thermal interface material may include, for example, a polymer and heat conductive particles. The heat conductive particles may be distributed in the polymer. When the first semiconductor package 100 is operating, the heat generated from the first semiconductor package 100 may be discharged outwardly through the first heat conducting layer 710 and the heat radiation structure 600.

[0041] The second heat-conducting layer 720 may be disposed between the second semiconductor package 200 and the heat radiation structure 600. The second heat-conducting layer 720 may be in physical contact with the top surface 200a of the second semiconductor package 200 and the first bottom surface 601b of the heat radiation structure 600. The second heat-conducting layer 720 may include, for example, a thermal interface material (TIM). When the second semiconductor package 200 is operating, heat generated from the second semiconductor package 200 may be transferred to the heat radiation structure 600 through the second heat-conducting layer 720.

[0042] The third heat-conducting layer 730 may be disposed between the third semiconductor package 300 and the heat radiation structure 600. The third heat-conducting layer 730 may be in physical contact with the top surface 300a of the third semiconductor package 300 and the first bottom surface 601b of the heat radiation structure 600. The third heat-conducting layer 730 may include, for example, a thermal interface material (TIM). When the third semiconductor package 300 operates, heat generated from the third semiconductor package 300 may be transferred to the heat radiation structure 600 through the third heat-conducting layer 730.

[0043] When the packaging system 1 is working, the first semiconductor package 100 generates a large amount of heat. For example, the amount of heat generated from the first semiconductor package 100 may be greater than the amount of heat from the second semiconductor package 200, the third semiconductor package 300, and the first passive device 400. The thermal characteristics of the first semiconductor package 100 may have a greater impact on the operating performance of the packaging system 1 than the thermal characteristics of the second semiconductor package 200 and the third semiconductor package 300. The more the thermal characteristics of the first semiconductor package 100 are improved, the more the operating characteristics of the packaging system 1 are improved. The thermal conductivity of each of the first heat conductive layer 710, the second heat conductive layer 720, and the third heat conductive layer 730 may be lower than the thermal conductivity of the heat radiation structure 600. As the height A1 of the first heat conductive layer 710 decreases, the heat generated from the first semiconductor package 100 can be discharged at a higher rate. In some embodiments, the height A1 of the first heat-conducting layer 710 may be the minimum height among the heights of the heat-conducting layers in contact with the bottom surface (e.g., the first bottom surface 601b) of the heat radiation structure 600. In this case, the heat-conducting layer may include the first heat-conducting layer 710, the second heat-conducting layer 720, and the third heat-conducting layer 730. For another example, the heat-conducting layer may further include adhesive patterns 741 and 742, which will be referred to in detail. Figure 2A and Figure 2B The height A1 of the first heat conducting layer 710 may be less than the height A2 of the second heat conducting layer 720 and may be less than the height A3 of the third heat conducting layer 730. Therefore, the heat generated from the first semiconductor package 100 may be quickly transferred to the heat radiation structure 600. In summary, the operating characteristics of the packaging system 1 may be improved.

[0044] The heat radiation structure 600 may have a groove. The groove may extend from the first bottom surface 601b of the heat radiation structure 600 toward the top surface 600a. When viewed from a top view, the groove may overlap with one or more of the first passive device 400, the second semiconductor package 200, and the third semiconductor package 300. In some embodiments, the groove may be a first groove 691 disposed on the first bottom surface 601b of the heat radiation structure 600. The first groove 691 may enable the heat radiation structure 600 to have a second bottom surface 602b. The second bottom surface 602b of the heat radiation structure 600 may correspond to the bottom surface of the first groove 691. The level at which the second bottom surface 602b is located may be higher than the level of the first bottom surface 601b and lower than the level of the top surface 600a. The second bottom surface 602b of the heat radiation structure 600 may be disposed on or above the first passive device 400, and when viewed from a top view, the second bottom surface 602b of the heat radiation structure 600 may overlap with the first passive device 400. The second bottom surface 602b of the heat radiation structure 600 may face the top surface of the first passive device 400. The level at which the top surface of the first passive device 400 is located may be the same as that of the second bottom surface 602b, or may be lower than that of the second bottom surface 602b.

[0045] In some embodiments, the height H4 of the mounted first passive device 400 may be equal to or greater than the sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conducting layer 710. The horizontal height at which the top surface of the first passive device 400 is located may be the same as the horizontal height of the top surface of the first heat conducting layer 710, or may be higher than the horizontal height of the top surface of the first heat conducting layer 710. In the case where the heat radiation structure 600 does not have the first groove 691, the first passive device 400 mounted on the substrate 500 may increase the distance between the top surface 500a of the substrate 500 and the first bottom surface 601b of the heat radiation structure 600. This situation may increase the height A1 of the first heat conducting layer 710, the height A2 of the second heat conducting layer 720, and the height A3 of the third heat conducting layer 730. In some embodiments, when from Figure 1A When viewed in the top view shown, the first groove 691 may overlap with the first passive device 400. Even if the first passive device 400 is mounted on the top surface 500a of the substrate 500, the height A1 of the first heat conducting layer 710 may be relatively small. Therefore, the thermal characteristics of the first semiconductor package 100 may be improved. Similarly, the thermal characteristics of the second semiconductor package 200 and the thermal characteristics of the third semiconductor package 300 may also be improved. The horizontal height of the second bottom surface 602b of the heat radiation structure 600 may depend on the height H4 of the mounted first passive device 400.

[0046] A plurality of first passive components 400 may be provided. The plurality of first passive components 400 may be spaced apart from each other. Figure 1A and Figure 1F As shown, the first groove 691 may overlap with a plurality of first passive components 400. The first passive component 400 may include a first sub-passive component 401, a second sub-passive component 402, and a third sub-passive component 403. The respective heights H4, H4', and H4" of the first sub-passive component 401, the second sub-passive component 402, and the third sub-passive component 403 mounted on the substrate 500 may be different from each other. For example, the height H4 of the mounted first sub-passive component 401 may be greater than the height H4' of the mounted second sub-passive component 402 and may be greater than the height H4" of the mounted third sub-passive component 403. The height H4 of the mounted first sub-passive component 401 may be equal to or greater than the sum of the height H1 of the first semiconductor package 100 and the height A1 of the first heat conducting layer 710. As seen in the top view, the first groove 691 may overlap with the first sub-passive component 401, the second sub-passive component 402, and the third sub-passive component 403. The level of the second bottom surface 602b of the heat radiation structure 600 may depend on the maximum height among the height H4 of the first passive sub-component 401, the height H4' of the second passive sub-component 402, and the height H4" of the third passive sub-component 403. For example, the level at which the second bottom surface 602b of the heat radiation structure 600 is located may be the same as the level of the top surface of the first passive sub-component 401, or may be higher than the level of the top surface of the first passive sub-component 401. Figure 1B As shown, a plurality of first trenches 691 may be provided. The first trenches 691 may overlap with corresponding first passive components 400. A single first passive component 400 and a single first trench 691 will be described below.

[0047] An electronic device 430 may also be mounted on the top surface 500a of the substrate 500. The electronic device 430 may include a real-time clock or an oscillator such as a crystal oscillator. Figure 1EAs shown, the conductive connection terminal 413 may be further disposed between the electronic device 430 and the top surface 500a of the substrate 500 to electrically connect the electronic device 430 and the substrate 500 to each other. In this case, the electronic device 430 mounted on the substrate 500 may have a height H7, which is defined as a height H71 including the conductive connection terminal 413. The height H7 of the mounted electronic device 430 may be equal to, for example, the sum of the height H71 of the conductive connection terminal 413 and the height H70 of the electronic device 430' before being mounted on the substrate 500. The sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conducting layer 710 may be greater than the height H7 of the mounted electronic device 430. The level at which the top surface of the electronic device 430 is located may be the same as the level of the top surface of the first heat conducting layer 710, or lower than the level of the top surface of the first heat conducting layer 710. Although the electronic device 430 is disposed on the top surface 500a of the substrate 500, the heat generated from the first semiconductor package 100 can also be discharged to the heat radiation structure 600 through the first heat conduction layer 710. For another example, the electronic device 430 may not be disposed on the top surface 500a of the substrate 500. Figure 1E The conductive connection terminal 413 is not shown in other drawings, but the inventive concept is not limited thereto.

[0048] The first bottom filling layer 160 may be disposed in the gap between the substrate 500 and the first semiconductor package 100 to encapsulate the first connection terminal 150. The second bottom filling layer 260 may be disposed in the gap between the substrate 500 and the second semiconductor package 200 to encapsulate the second connection terminal 250. The third bottom filling layer 360 may be disposed in the gap between the substrate 500 and the third semiconductor package 300 to encapsulate the third connection terminal 350. The first bottom filling layer 160, the second bottom filling layer 260, and the third bottom filling layer 360 may include a dielectric polymer such as an epoxy polymer. The first bottom filling layer 160, the second bottom filling layer 260, and the third bottom filling layer 360 may improve the bonding reliability of the first connection terminal 150, the second connection terminal 250, and the third connection terminal 350. Unlike the illustrated case, one or more of the first bottom filling layer 160, the second bottom filling layer 260, and the third bottom filling layer 360 may not be provided.

[0049] The dam structure 590 may be further disposed on the top surface 500a of the substrate 500. The dam structure 590 may be disposed between the third semiconductor package 300 and the first passive device 400. Even if the bottom filling material of the third bottom filling layer 360 flows, the dam structure 590 may also help to install the first passive device 400. The dam structure 590 may include a liquid resin. Although not shown, the substrate 500 may include a plurality of layers, and the uppermost layer may include a dielectric polymer such as a solder resist material. For example, the dam structure 590 may be formed integrally with the uppermost layer of the substrate 500. In this case, the dam structure 590 and the uppermost layer of the substrate 500 may be connected without a boundary between them. In some embodiments, the dam structure 590 may include a material different from that of the substrate 500. For example, the dam structure 590 may be formed of the same material as that of one of the first bottom filling layer 160, the second bottom filling layer 260, and the third bottom filling layer 360. The height of the dam structure 590 may be equal to or less than the sum of the height H1 of the first semiconductor package 100 and the height A1 of the first heat conductive layer 710 .

[0050] The number and arrangement of the dam structure 590 may be variously changed. For example, the dam structure 590 may be provided in plurality. For another example, the dam structure 590 may be provided between the first semiconductor package 100 and the first passive device 400. For another example, the dam structure 590 may be provided between the second semiconductor package 200 and the first passive device 400.

[0051] Figure 1G Shows Figure 1A 0 is an enlarged view of a portion IV in FIG. 1 to show a first semiconductor package according to some example embodiments. Figure 1H Shown along Figure 1G The cross-sectional view taken along the line I'-II' in FIG. Figure 1C Magnified view of section V in FIG.

[0052] Reference Figure 1C , Figure 1G and Figure 1H, the first semiconductor package 100 may include a first package substrate 110, a first semiconductor chip 120, and a first mold layer 130. For example, a printed circuit board (PCB) or a redistribution layer may be used as the first package substrate 110. The first semiconductor chip 120 may be mounted on the first package substrate 110 in a flip chip manner. The built-in component may be arranged between the first semiconductor chip 120 and the first package substrate 110. The built-in component may include a solder ball, a column, or a ball grid array. The built-in component may include a conductive material such as a metal. The first semiconductor chip 120 may be a system on chip (SOC), a logic chip, or an application processor (AP). The first semiconductor chip 120 may include circuits with different functions. For example, the first semiconductor chip 120 may include a logic circuit and a storage circuit. The first semiconductor chip 120 may also include one or more of a digital integrated circuit (IC), a wireless radio frequency integrated circuit (RFIC), and an input / output circuit. Generating heat from the first semiconductor package 100 during operation of the first semiconductor package 100 may mean generating heat from the first semiconductor chip 120.

[0053] The first mold layer 130 may be disposed on the first package substrate 110 to encapsulate the first semiconductor chip 120. The first mold layer 130 may cover the side surface and the top surface of the first semiconductor chip 120. In this case, the top surface 100a of the first semiconductor package 100 may correspond to the top surface of the first mold layer 130. The first mold layer 130 may include a dielectric polymer such as an epoxy mold compound. The first mold layer 130 may also extend into the gap between the first package substrate 110 and the first semiconductor chip 120. Unlike the case shown, an underfill pattern may also be provided to the gap between the first package substrate 110 and the first semiconductor chip 120. The underfill pattern may be formed by performing a hot pressing process on a non-conductive paste or a non-conductive film, or the underfill pattern may be formed by performing a capillary underfill process. The height H1 of the mounted first semiconductor package 100 may be equal to the sum of the height of the first connection terminal 150, the height of the first package substrate 110, and the height of the first mold layer 130.

[0054] The first mark 190 may be disposed on the first mold layer 130. For example, the first mark 190 may be disposed on the top surface of the first mold layer 130. For another example, the first mark 190 may be disposed on the side surface of the first mold layer 130. The first mark 190 may be a recessed portion of the first mold layer 130. The formation of the first mark 190 may include removing a portion of the first mold layer 130. When the first mark 190 is formed on the first semiconductor chip 120, the first semiconductor chip 120 may be damaged during the formation of the first mark 190. For example, a crack may be formed on or in the first semiconductor chip 120. In some embodiments, because the first mark 190 is disposed on the first mold layer 130, the first semiconductor chip 120 may be limited and / or prevented from being damaged during the formation of the first mark 190. The first mark 190 may represent information about the first semiconductor package 100. For simplicity, in addition to Figure 1G and Figure 1H The first mark 190 is not shown in other drawings, but the present inventive concept is not limited thereto.

[0055] The first heat-conducting layer 710 may be disposed on the top surface 100a of the first semiconductor package 100. The formation of the first heat-conducting layer 710 may include providing a thermal interface material on the first semiconductor package 100 and curing the thermal interface material. The thermal interface material may have fluidity before being cured. When the first heat-conducting layer 710 is formed, although the thermal interface material located on the edge region of the top surface 100a of the first semiconductor package 100 flows downward along the side surface 100c of the first semiconductor package 100, the thermal interface material located on the central region of the top surface 100a of the first semiconductor package 100 does not flow downward. The first heat-conducting layer 710 may fill the gap between the heat radiation structure 600 and the central region of the top surface 100a of the first semiconductor package 100 as expected. For example, the top surface 710a of the first heat-conducting layer 710 located on the central region of the first semiconductor package 100 may be in physical contact with the heat radiation structure 600. Since the first mold layer 130 is provided, the central area of ​​the first semiconductor package 100 may correspond to the area where the first semiconductor chip 120 is provided. Even if the thermal interface material flows downward during the formation of the first heat conductive layer 710, the first heat conductive layer 710 may successfully transfer heat generated from the first semiconductor chip 120. When the first mark 190 is provided on the first mold layer 130, the first heat conductive layer 710 may extend into the first mark 190.

[0056] Fig. 1I A first semiconductor package according to some example embodiments is shown to correspond to Figure 1C is an enlarged view of a portion V of Figure 1GA cross-sectional view taken along line I'-II' in FIG.

[0057] Reference Figure 1C , Figure 1G and Fig. 1I , the first semiconductor package 100 may include a first package substrate 110 , a first semiconductor chip 120 , a first mold layer 130 , a first adhesive layer 141 , and a first heat conduction structure 140 .

[0058] The first heat conducting structure 140 may include Figures 1A to 1C The thermally conductive material discussed in the example of . And may have a relatively high thermal conductivity. The first heat-conducting structure 140 may include a metal layer, a heat sink, or a heat pipe. The first adhesive layer 141 may be disposed between the first molding layer 130 and the first heat-conducting structure 140. The first adhesive layer 141 may attach the first heat-conducting structure 140 to the first molding layer 130. The first adhesive layer 141 may include a thermal interface material. When the first semiconductor package 100 is operating, the heat generated from the first semiconductor chip 120 may be transferred to the heat radiation structure 600 through the first adhesive layer 141, the first heat-conducting structure 140, and the first heat-conducting layer 710.

[0059] In some embodiments, the top surface 100a of the first semiconductor package 100 may correspond to the top surface of the first heat conducting structure 140. The height H1 of the mounted first semiconductor package 100 may be equal to the sum of the height of the first connection terminal 150, the height of the first package substrate 110, the height of the first mold layer 130, the height of the first adhesive layer 141, and the height of the first heat conducting structure 140. For example, even if the top surface of the first mold layer 130 is located at a level lower than the level of the top surface 200a of the second semiconductor package 200 and lower than the level of the top surface 300a of the third semiconductor package 300, because the first adhesive layer 141 and the first heat conducting structure 140 are provided, the height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200 and may be greater than the height H3 of the mounted third semiconductor package 300. Therefore, the height A1 of the first heat conducting layer 710 may be less than the height A2 of the second heat conducting layer 720 and may be less than the height A3 of the third heat conducting layer 730. Thermal characteristics of the first semiconductor package 100 may be improved.

[0060] Figure 1J A first semiconductor package according to some example embodiments is shown to correspond to Figure 1G The cross-sectional view taken along the line I'-II' in FIG. Figure 1C Magnified view of section V in FIG.

[0061] Reference Figure 1C , Figure 1G and Figure 1J , the first semiconductor package 100 may include a first semiconductor chip 120, a first mold layer 130, a first adhesive layer 141, and a first heat conducting structure 140. The first mold layer 130 may cover the side surface of the first semiconductor chip 120, and may expose the top surface of the first semiconductor chip 120. In this case, the top surface 100a of the first semiconductor package 100 may correspond to the top surface of the first mold layer 130 and the top surface of the first semiconductor chip 120, and the top surface of the first semiconductor chip 120 is exposed through the first mold layer 130. The exposed top surface of the first semiconductor chip 120 may be in direct physical contact with the first adhesive layer 141. Therefore, the heat radiation characteristics of the first semiconductor package 100 may be improved.

[0062] Figure 1K Shows Figure 1C 0 is an enlarged view of a portion V' in FIG. 4 to show a second semiconductor package according to some example embodiments.

[0063] Reference Figure 1C and Figure 1K , the second semiconductor package 200 may include a second package substrate 210, a second semiconductor chip 220, and a second molding layer 230. A printed circuit board (PCB) or a redistribution layer may be used as the second package substrate 210. The second semiconductor chip 220 may be mounted in a flip chip manner or a wire bonding manner. The type of the second semiconductor chip 220 may be different from the type of the first semiconductor chip 120. For example, the second semiconductor chip 220 may be used as a memory chip. The memory chip may include a DRAM. For another example, the memory chip may include an SRAM, an MRAM, or a NAND flash memory. Generating heat from the second semiconductor package 200 during operation of the second semiconductor package 200 may mean generating heat from the second semiconductor chip 220. The second semiconductor package 200 may include a plurality of second semiconductor chips 220. For another example, the second semiconductor package 200 may include a single second semiconductor chip 220. For the sake of brevity of description, an example of setting a single second semiconductor chip 220 will be described below.

[0064] The second mold layer 230 may be disposed on the second package substrate 210 to cover the second semiconductor chip 220. The second mold layer 230 may include a dielectric polymer such as an epoxy polymer. When the second semiconductor chip 220 is mounted in a flip chip manner, the second mold layer 230 may further extend into the gap between the second semiconductor chip 220 and the second package substrate 210. For another example, an underfill pattern (not shown) may be further provided to fill the gap between the second package substrate 210 and the second semiconductor chip 220. The second mold layer 230 may cover the side surface and the top surface of the second semiconductor chip 220. In this case, the top surface 200a of the second semiconductor package 200 may correspond to the top surface of the second mold layer 230. For another example, the second mold layer 230 may cover the side surface of the second semiconductor chip 220 and may expose the top surface of the second semiconductor chip 220. In this case, the top surface 200a of the second semiconductor package 200 may correspond to the top surface of the second mold layer 230 and the top surface of the second semiconductor chip 220, and the top surface of the second semiconductor chip 220 is exposed through the second mold layer 230. The height H2 of the mounted second semiconductor package 200 may be defined as the sum of the height of the second connection terminal 250, the height of the second package substrate 210, and the height of the second mold layer 230.

[0065] A second mark 290 may be further provided on the second mold layer 230. The second mark 290 may be a recessed portion of the second mold layer 230. The second mark 290 may represent information about the second semiconductor package 200.

[0066] The second heat-conducting layer 720 may be formed on the top surface of the second molding layer 230. The second heat-conducting layer 720 may be formed by the same method as that used to form the first heat-conducting layer 710. Even if the thermal interface material partially flows downward when forming the second heat-conducting layer 720, the second heat-conducting layer 720 may desirably fill the gap between the heat radiation structure 600 and the central area of ​​the top surface 200a of the second semiconductor package 200. The central area of ​​the top surface 200a of the second semiconductor package 200 may correspond to the area where the second semiconductor chip 220 is disposed. Therefore, the second heat-conducting layer 720 may successfully transfer the heat generated from the second semiconductor chip 220. The second heat-conducting layer 720 may further extend into the second mark 290.

[0067] Figure 1L Shows Figure 1C 8 is an enlarged view of a portion V' in FIG. 1 to illustrate a second semiconductor package according to some example embodiments.

[0068] Reference Figure 1C and Figure 1L, the second semiconductor package 200 may include a second package substrate 210, a second semiconductor chip 220, a second mold layer 230, a second adhesive layer 241 and a second heat-conducting structure 240. The second heat-conducting structure 240 may include a heat-conducting material and may have a relatively high thermal conductivity. The second heat-conducting structure 240 may include a metal layer, a heat sink or a heat pipe. The second adhesive layer 241 may be disposed between the second mold layer 230 and the second heat-conducting structure 240. The second adhesive layer 241 may include a thermal interface material. When the second semiconductor package 200 is operating, the heat generated from the second semiconductor chip 220 may be transferred to the second heat-conducting layer 720 through the second adhesive layer 241 and the second heat-conducting structure 240.

[0069] The top surface 200a of the second semiconductor package 200 may correspond to the top surface of the second heat conducting structure 240. The height H2 of the mounted second semiconductor package 200 may be equal to the sum of the height of the second connection terminal 250, the height of the second package substrate 210, the height of the second mold layer 230, the height of the second adhesive layer 241, and the height of the second heat conducting structure 240.

[0070] Figure 1M Shows Figure 1C ” is an enlarged view of a portion V” in FIG. 1 to illustrate a third semiconductor package according to some example embodiments.

[0071] Reference Figure 1C and Figure 1M, the third semiconductor package 300 may include a third package substrate 310, a third semiconductor chip 320, and a third mold layer 330. A redistribution layer or a printed circuit board may be used as the third package substrate 310. The type of the third semiconductor chip 320 may be different from the type of the first semiconductor chip 120 and the type of the second semiconductor chip 220. For example, the third semiconductor chip 320 may include a power management integrated circuit (PMIC) and may be used as a power management chip. Generating heat from the third semiconductor package 300 during operation of the third semiconductor package 300 may mean generating heat from the third semiconductor chip 320. The third mold layer 330 may be disposed on the third package substrate 310 to cover the third semiconductor chip 320. The third mold layer 330 may cover the top surface and the side surface of the third semiconductor chip 320. In this case, the top surface 300a of the third semiconductor package 300 may correspond to the top surface of the third mold layer 330. For another example, the third mold layer 330 may cover the side surface of the third semiconductor chip 320 and may expose the top surface of the third semiconductor chip 320. In this case, the top surface 300a of the third semiconductor package 300 may correspond to the top surface of the third mold layer 330 and the top surface of the third semiconductor chip 320, and the top surface of the third semiconductor chip 320 is exposed through the third mold layer 330. The third mold layer 330 may include a dielectric polymer such as an epoxy polymer. The height H3 of the mounted third semiconductor package 300 may be defined as the sum of the height of the third connection terminal 350, the height of the third package substrate 310, and the height of the third mold layer 330.

[0072] The third semiconductor package 300 may be formed as a fan-out panel-level package or a fan-out wafer-level package. The formation of the third semiconductor package 300 may include: disposing a third semiconductor chip 320 on a carrier substrate (not shown); forming a third mold layer 330 to cover the third semiconductor chip 320; removing the carrier substrate to expose the bottom surface of the third semiconductor chip 320; and forming a redistribution layer on the exposed bottom surface of the third semiconductor chip 320 and the bottom surface of the third mold layer 330. The redistribution layer may be used as the third package substrate 310.

[0073] Figure 1N Shows Figure 1C ” is an enlarged view of a portion V” in FIG. 1 to illustrate a third semiconductor package according to some example embodiments.

[0074] Reference Figure 1C and Figure 1N, the third semiconductor package 300 may include a third package substrate 310, a third semiconductor chip 320, a third mold layer 330 and a third heat-conducting structure 340. The third heat-conducting structure 340 may include a heat-conducting material and may have a relatively high thermal conductivity. The third heat-conducting structure 340 may include a metal layer, a heat sink or a heat pipe. The third adhesive layer 341 may be disposed between the third mold layer 330 and the third heat-conducting structure 340. The third adhesive layer 341 may include a thermal interface material. When the third semiconductor package 300 is in operation, the heat generated from the third semiconductor chip 320 may be transferred to the third heat-conducting layer 730 through the third adhesive layer 341 and the third heat-conducting structure 340.

[0075] The top surface 300a of the third semiconductor package 300 may correspond to the top surface of the third heat conducting structure 340. The height H3 of the mounted third semiconductor package 300 may be equal to the sum of the height of the third connection terminal 350, the height of the third package substrate 310, the height of the third mold layer 330, the height of the third adhesive layer 341, and the height of the third heat conducting structure 340.

[0076] A third mark 390 may be further disposed on the third mold layer 330. The third mark 390 may be a recessed portion of the third mold layer 330.

[0077] Reference Figure 1C , Figure 1M and Figure 1N , the third heat-conducting layer 730 may be formed on the top surface 300a of the third semiconductor package 300. The third heat-conducting layer 730 may be formed by the same method as the method for forming the first heat-conducting layer 710. Even if the thermal interface material located on the edge region of the top surface 300a of the third semiconductor package 300 partially flows downward, the third heat-conducting layer 730 may desirably fill the gap between the heat radiation structure 600 and the central region of the top surface 300a of the third semiconductor package 300. The central region of the top surface 300a of the third semiconductor package 300 may correspond to the region where the third semiconductor chip 320 is disposed. Therefore, the third heat-conducting layer 730 may successfully transfer the heat generated from the third semiconductor package 300.

[0078] Figure 2A A top view illustrating a packaging system according to some example embodiments is shown. Figure 2B Shown along Figure 2A A cross-sectional view taken along line I-II in FIG.

[0079] Reference Figure 2A and Figure 2BThe packaging system 1a may include a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive device 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat radiation structure 600. The description of the substrate 500, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive device 400, the first heat-conducting layer 710, the second heat-conducting layer 720, the third heat-conducting layer 730, and the heat radiation structure 600 may be the same as that described above with reference to FIG. Figures 1A to 1N Same discussion.

[0080] The ground pad 510G may be disposed on the top surface 500a of the substrate 500. One or more conductive terminals 550 may be used as ground terminals. A ground voltage may be applied to the ground pad 510G through the ground terminal and the substrate 500.

[0081] The heat radiation structure 600 may include a main body portion 601 and a leg portion 602. The main body portion 601 of the heat radiation structure 600 may be similar to the above reference Figures 1A to 1C The heat radiation structure 600 discussed. For example, the body portion 601 may be disposed on the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 and may be disposed on the first passive device 400. A groove may be formed on the first bottom surface 601b of the body portion 601. The groove may be a reference Figures 1A to 1C The first groove 691 in question. The first bottom surface 601b and the second bottom surface 602b of the heat radiation structure 600 may be disposed on the body portion 601. The first heat conductive layer 710 may be in physical contact with the first bottom surface 601b of the heat radiation structure 600.

[0082] The branch portion 602 of the heat radiation structure 600 may be disposed between the substrate 500 and the edge region of the main body portion 601. The branch portion 602 of the heat radiation structure 600 may be connected to the main body portion 601 of the heat radiation structure 600. Figure 2A As shown, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, and the first passive device 400 may be spaced apart from the branch portion 602 of the heat radiation structure 600. The branch portion 602 may be disposed on an edge region of the substrate 500 when viewed from a top plan view.

[0083] The adhesive patterns 741 and 742 may be disposed between the substrate 500 and the branch portion 602 of the heat radiation structure 600 to fix the heat radiation structure 600 to the substrate 500. The adhesive patterns 741 and 742 may include a conductive adhesive pattern 741 and a dielectric adhesive pattern 742. The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the bottom surface of the branch portion 602 of the heat radiation structure 600. The heat radiation structure 600 may be coupled to the ground pad 510G through the conductive adhesive pattern 741.

[0084] When a certain amount of charge is accumulated on the heat radiation structure 600, the charge may flow from the heat radiation structure 600 into other conductive components, which may cause damage to the conductive components. The conductive components may include one or more of the following: integrated circuits and wiring in the first semiconductor chip 120, the second semiconductor chip 220, and the third semiconductor chip 320; wiring in the first package substrate 110, the second package substrate 210, and the third package substrate 310; the first connection terminal 150, the second connection terminal 250, and the third connection terminal 350; and wiring in the substrate 500. In some embodiments, a ground voltage may be applied to the heat radiation structure 600 through the conductive adhesive pattern 741. Then, the heat radiation structure 600 can limit and / or prevent electrical damage to the packaging system 1a due to electrostatic discharge (ESD).

[0085] The heat radiation structure 600 may have electrical conductivity, and thus may shield electromagnetic interference (EMI) of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. Electromagnetic interference may refer to interference caused by electromagnetic waves emitted or transmitted from other electrical components to the communication operation of an electrical component. The heat radiation structure 600 may limit and / or prevent the operation of the first passive device 400 and the operation of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 from being interrupted or interfered with by the operation of other packages.

[0086] The dielectric adhesive pattern 742 may be disposed between the substrate 500 and the heat radiation structure 600. Therefore, the heat radiation structure 600 may be insulated from the substrate 500, which may suppress electrical short circuits. The height of the dielectric adhesive pattern 742 may be the same as the height A5 of the conductive adhesive pattern 741.

[0087] Reference Figure 2B, the height B of the branch portion 602 of the heat radiation structure 600 may be the same as the maximum vertical length of the inner side surface of the heat radiation structure 600. The height B of the branch portion 602 of the heat radiation structure 600 may be less than the height H1 of the mounted first semiconductor package 100. Therefore, the height A1 of the first heat conductive layer 710 may be less than the height A5 of the conductive adhesive pattern 741. Because the height A1 of the first heat conductive layer 710 is relatively small, the heat generated from the first semiconductor package 100 may be quickly transferred to the heat radiation structure 600 through the first heat conductive layer 710.

[0088] Figure 2C A top view showing a packaging system according to some example embodiments is shown. Figure 2D Shown along Figure 2C A cross-sectional view taken along line I-II in FIG.

[0089] Reference Figure 2C and Figure 2D , the packaging system 1b may include a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive device 400, a first heat conducting layer 710, a second heat conducting layer 720, a third heat conducting layer 730, and a heat radiation structure 600. The description of the heat radiation structure 600 may be the same as Figure 2A and Figure 2B For example, the heat radiation structure 600 may include a main body portion 601 and a branch portion 602 .

[0090] The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the branch portion 602 of the heat radiation structure 600 to electrically connect the heat radiation structure 600 and the ground pad 510G to each other. The height A1 of the first heat conductive layer 710 may be less than the height A5 of the conductive adhesive pattern 741. Figure 2A and Figure 2B Unlike the example of FIG. 7 , the dielectric adhesive pattern 742 may not be provided.

[0091] Figure 2E Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments.

[0092] Reference Figure 2C and Figure 2E The packaging system 1c may include a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 , a third semiconductor package 300 , a first passive device 400 , a first heat conducting layer 710 , a second heat conducting layer 720 , a third heat conducting layer 730 and a heat radiation structure 600 .

[0093] The heat radiation structure 600 may include a first heat radiation structure 610, a second heat radiation structure 620, and a heat radiation adhesive layer 630. The first heat radiation structure 610 may be the same as that described above. Figure 2A and Figure 2B The examples discussed are the same as those in the reference above. Figure 2C and Figure 2D The examples discussed are the same. For example, the first heat radiation structure 610 may include a main body portion 601 and a branch portion 602. The first groove 691 may be provided on the first bottom surface 601b of the first heat radiation structure 610. The conductive adhesive pattern 741 may be provided between the ground pad 510G and the first heat radiation structure 610. For another example, a dielectric adhesive pattern 742 may also be provided, as described above with reference to Figure 2A and Figure 2B As discussed.

[0094] The second heat radiation structure 620 may be disposed on the first heat radiation structure 610. The second heat radiation structure 620 may be the same as the first heat radiation structure 610. Figures 1A to 1C The discussed heat radiation structure 600 is the same. In contrast, the second heat radiation structure 620 may not have the groove. The second heat radiation structure 620 may have a flat bottom surface.

[0095] The heat radiating adhesive layer 630 may be disposed between the first heat radiating structure 610 and the second heat radiating structure 620. The second heat radiating structure 620 may be attached to the first heat radiating structure 610 by the heat radiating adhesive layer 630. The heat radiating adhesive layer 630 may include, for example, a thermal interface material.

[0096] Figure 3A Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments.

[0097] Reference Figure 2C and 3A The packaging system 1d may include a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive device 400, a first heat conducting layer 710, a second heat conducting layer 720, a third heat conducting layer 730, and a heat radiation structure 600. The width of the first heat radiation structure 610 may be equal to or greater than the width of the second heat radiation structure 620.

[0098] The height H2 of the mounted second semiconductor package 200 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. For example, the top surface 200a of the second semiconductor package 200 may be at the same level as the top surface 100a of the first semiconductor package 100, or higher than the top surface 100a of the first semiconductor package 100.

[0099] The second groove 692 may be disposed on the first bottom surface 601b of the heat radiation structure 600. The level at which the third bottom surface 603b of the heat radiation structure 600 is located may be higher than the level of the first bottom surface 601b. The third bottom surface 603b may correspond to the bottom surface of the second groove 692. The third bottom surface 603b of the heat radiation structure 600 may be disposed on the second semiconductor package 200. When viewed from a top view, the second groove 692 may overlap with the second semiconductor package 200. The second heat conducting layer 720 may be disposed on the top surface 200a of the second semiconductor package 200, and may be in physical contact with the bottom surface (i.e., the third bottom surface 603b) of the second groove 692. At least a portion of the side surface of the second heat conducting layer 720 may face the sidewall of the second groove 692. In some embodiments, even if the height H2 of the second semiconductor package 200 is large, the height A1 of the first heat conducting layer 710 may be smaller than the height A2 of the second heat conducting layer 720 due to the second trench 692. Therefore, the thermal characteristics of the package system 1d may be improved.

[0100] When a plurality of second semiconductor packages 200 are provided, a plurality of second trenches 692 may be provided. The second trenches 692 may overlap corresponding second semiconductor packages 200. For another example, each second trench 692 may overlap at least two second semiconductor packages 200.

[0101] The sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conducting layer 710 may be greater than the height H4 of the first passive device 400. For example, the level at which the top surface of the first heat conducting layer 710 is located may be higher than the level at which the top surface of the first passive device 400 is located. The first trench 691 may not be provided. The top surface of the first passive device 400 may face the first bottom surface 601b of the heat radiation structure 600.

[0102] Figure 3B Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments.

[0103] Reference Figure 2C and Figure 3BThe packaging system 1e may include a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 , a third semiconductor package 300 , a first passive device 400 , a first heat conducting layer 710 , a second heat conducting layer 720 , a third heat conducting layer 730 and a heat radiation structure 600 .

[0104] The height H3 of the mounted third semiconductor package 300 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. For example, the top surface 300a of the third semiconductor package 300 may be at the same level as the top surface 100a of the first semiconductor package 100, or may be higher than the top surface 100a of the first semiconductor package 100.

[0105] The third groove 693 may be disposed on the first bottom surface 601b of the heat radiation structure 600. The level at which the fourth bottom surface 604b of the heat radiation structure 600 is located may be higher than the level of the first bottom surface 601b. The fourth bottom surface 604b may correspond to the bottom surface of the third groove 693. The fourth bottom surface 604b of the heat radiation structure 600 may be disposed on the third semiconductor package 300. When viewed from a top view, the third groove 693 may overlap with the third semiconductor package 300. The third heat conducting layer 730 may be disposed on the top surface 300a of the third semiconductor package 300, and may be in physical contact with the bottom surface (i.e., the fourth bottom surface 604b) of the third groove 693. At least a portion of the side surface of the third heat conducting layer 730 may face the sidewall of the third groove 693. In some embodiments, even if the height H3 of the third semiconductor package 300 is large, the height A1 of the first heat conducting layer 710 may be smaller than the height A3 of the third heat conducting layer 730 due to the third trench 693. Therefore, the thermal characteristics of the package system 1e may be improved.

[0106] A height H1 of the first semiconductor package 100 may be greater than a height H2 of the second semiconductor package 200 . A height A1 of the first heat-conducting layer 710 may be less than a height A2 of the second heat-conducting layer 720 .

[0107] The sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conductive layer 710 may be greater than the height H4 of the first passive device 400. The first trench 691 may not be provided, and the top surface of the first passive device 400 may face the first bottom surface 601b of the heat radiation structure 600.

[0108] Figure 3C Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments. Figure 3D Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments.

[0109] Reference Figure 2C , Figure 3C and Figure 3D Any one of the packaging systems 1f and 1g may include a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive device 400, a first heat conducting layer 710, a second heat conducting layer 720, a third heat conducting layer 730 and a heat radiation structure 600.

[0110] The heat radiation structure 600 may include a first groove 691 and a second groove 692. The first groove 691 and the second groove 692 may be provided on the first bottom surface 601b of the heat radiation structure 600. Therefore, the heat radiation structure 600 may have a first bottom surface 601b, a second bottom surface 602b, and a third bottom surface 603b.

[0111] The height H4 of the mounted first passive device 400 may be equal to or greater than the sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conducting layer 710. Since the first trench 691 is provided, even if the first passive device 400 is provided on the top surface 500a of the substrate 500, the height A1 of the first heat conducting layer 710 may be small.

[0112] The height H2 of the mounted second semiconductor package 200 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. When viewed from a top view, the second trench 692 may overlap the second semiconductor package 200. The second heat conducting layer 720 may be in physical contact with the third bottom surface 603b of the heat radiation structure 600. The height A1 of the first heat conducting layer 710 may be less than the height A2 of the second heat conducting layer 720. The third bottom surface 603b of the heat radiation structure 600 may be disposed at a level that is the same as or different from that of the second bottom surface 602b.

[0113] The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the mounted third semiconductor package 300 , and the third trench 693 may not be provided.

[0114] Reference Figure 3D, the heat radiation structure 600 may include a third groove 693 in addition to the first groove 691 and the second groove 692. The first groove 691, the second groove 692, and the third groove 693 may be disposed on the first bottom surface 601b of the heat radiation structure 600. Therefore, the heat radiation structure 600 may have a first bottom surface 601b, a second bottom surface 602b, a third bottom surface 603b, and a fourth bottom surface 604b.

[0115] The height H3 of the mounted third semiconductor package 300 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. The third heat conducting layer 730 may be in physical contact with the fourth bottom surface 604b of the heat radiation structure 600. The horizontal height of the fourth bottom surface 604b of the heat radiation structure 600 may depend on the height H1 of the mounted first semiconductor package 100, the height H3 of the mounted third semiconductor package 300, and the height A1 of the first heat conducting layer 710. Although Figure 3D The fourth bottom surface 604b of the heat radiation structure 600 is shown to be located at a different level than the second bottom surface 602b, but the fourth bottom surface 604b may be located at the same level as the second bottom surface 602b. When the fourth bottom surface 604b and the second bottom surface 602b are located at the same level, the first groove 691 and the third groove 693 may be integrally formed into one groove.

[0116] In some embodiments, whether the first groove 691, the second groove 692, and the third groove 693 are provided may depend on the height H4 of the mounted first passive device 400, the height H2 of the mounted second semiconductor package 200, and the height H3 of the mounted third semiconductor package. For example, when the height H4 of the mounted first passive device 400 is less than the sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conducting layer 710, the first groove 691 may not be provided. When the height H1 of the mounted first semiconductor package 100 is greater than the height H2 of the mounted second semiconductor package 200, the second groove 692 may not be provided. When the height H1 of the mounted first semiconductor package 100 is greater than the height H3 of the mounted third semiconductor package 300, the third groove 693 may not be provided.

[0117] Figure 4 Shown along Figure 2C 0 is a cross-sectional view taken along line I-II in FIG. 1 to illustrate a packaging system according to some example embodiments.

[0118] Reference Figure 2C and Figure 4, the packaging system 1h may include a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive device 400, a first heat conducting layer 710, a second heat conducting layer 720, a third heat conducting layer 730, a heat radiation structure 600, and a fourth heat conducting layer 740. The height H4 of the mounted first passive device 400 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. The first groove 691 may be provided on the first bottom surface 601b of the heat radiation structure 600.

[0119] The fourth heat-conducting layer 740 may be disposed between the first passive device 400 and the heat radiation structure 600. The fourth heat-conducting layer 740 may include a thermal interface material. The fourth heat-conducting layer 740 may contact the second bottom surface 602b of the heat radiation structure 600. The heat generated from the first passive device 400 may be transferred to the heat radiation structure 600 through the fourth heat-conducting layer 740. When the packaging system 1h is in operation, the heat generated by the first semiconductor package 100 may be greater than the heat generated from the first passive device 400. Since the first groove 691 is provided, the height A1 of the first heat-conducting layer 710 may be less than the height A4 of the fourth heat-conducting layer 740.

[0120] Unlike the illustrated case, when the height H4 of the mounted first passive device 400 is less than the height H1 of the mounted first semiconductor package 100, the first groove 691 may not be provided. In this case, the fourth heat conducting layer 740 may be in physical contact with the first bottom surface 601b of the heat radiation structure 600. For another example, one of the second groove 692 and the third groove 693 may be further provided on the first bottom surface 601b of the heat radiation structure 600.

[0121] exist FIG. 3A to FIG. 3D and Figure 4 In an example of , the second heat radiation structure 620 and the heat radiation adhesive layer 630 may not be provided. For another example, the first heat radiation structure 610 may not have the branch portion 602 and may be spaced apart from the substrate 500. In this case, the conductive adhesive pattern 741 may not be provided. For another example, the second heat radiation structure 620, the heat radiation adhesive layer 630, and the branch portion 602 of the heat radiation structure 600 may not be provided.

[0122] Figure 5A A cross-sectional view showing a semiconductor module according to some example embodiments is illustrated. Figure 5B Shows Figure 5A FIG. 1 is an enlarged view of a portion C in FIG. 1 to illustrate a second passive component according to some example embodiments. Figure 5C Shows Figure 5A VI is an enlarged view of a portion of FIG. 1 to illustrate a lower pad and a conductive terminal according to some example embodiments. Figure 5D Shows Figure 5A VI is an enlarged view of a portion of FIG. 1 to illustrate a lower pad according to some example embodiments.

[0123] Reference Figure 1A , Figure 5A and Figure 5B , the semiconductor module 10 may include a board 1000 and a packaging system 1. For example, a printed circuit board may be used as the board 1000. A conductive pad 1500 may be provided on a top surface 1000a of the board 1000. The conductive pad 1500 may be electrically connected to an internal wiring of the board 1000.

[0124] Reference Figures 1A to 1C The packaging system 1 discussed may be mounted on a board 1000, thereby forming a semiconductor module 10. For another example, the semiconductor module 10 may be formed by mounting one of the following packaging systems on the board 1000: Figure 2A and Figure 2B Packaging system 1a, Figure 2C and Figure 2D Packaging system 1b, Figure 2E Packaging system 1c, Figure 3A Packaging system 1d, Figure 3B Packaging system 1e, Figure 3C Packaging system 1f, Figure 3D The packaging system 1g and Figure 4 For ease of description, the following describes the packaging system 1h. Figures 1A to 1C The packaging system 1 of the semiconductor module 10 is mounted on the board 1000 , but the inventive concept is not limited thereto.

[0125] The installation of the packaging system 1 may include: arranging the packaging system 1 on the board 1000 so that the conductive terminals 550 face the board 1000; and coupling the conductive terminals 550 to the corresponding conductive pads 1500. The pitch of the conductive terminals 550 may be substantially the same as the pitch P4 of the conductive pads 1500. The pitch P4 of the conductive pads 1500 may be standardized. For example, the pitch P4 of the conductive pads 1500 may meet the Joint Electron Device Engineering Council (JEDEC) standard. The pitch P4 of the conductive pads 1500 may be relatively large. For example, the pitch P4 of the conductive pads 1500 may be equal to or greater than about 0.65 mm.

[0126] When the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 are directly mounted on the board 1000, the pitch P1 of the first connection terminals 150, the pitch P2 of the second connection terminals 250, and the pitch P3 of the third connection terminals 350 may all be required to be substantially the same as the pitch P4 of the conductive pads 1500. In some embodiments, the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may be coupled to the board 1000 through the substrate 500. Therefore, the pitch P1 of the first connection terminals 150, the pitch P2 of the second connection terminals 250, and the pitch P3 of the third connection terminals 350 may all be freely designed without being limited by the pitch P4 of the conductive pads 1500.

[0127] The pitch P1 of the first connection terminal 150 may be smaller than the pitch P4 of the conductive pad 1500. For example, the pitch P1 of the first connection terminal 150 may be equal to or less than about 0.4 mm. Therefore, the first connection terminal 150 may be more densely arranged to reduce the plane area of ​​the first semiconductor package 100. The pitch P2 of the second connection terminal 250 and the pitch P3 of the third connection terminal 350 may both be smaller than the pitch P4 of the conductive pad 1500. For example, the pitch P2 of the second connection terminal 250 and the pitch P3 of the third connection terminal 350 may both be equal to or less than about 0.4 mm. Therefore, the second semiconductor package 200 and the third semiconductor package 300 may become compact. Because the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 become compact, the distance between the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may be reduced. Therefore, it is possible to reduce the electrical path lengths among the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. Therefore, it is possible to improve the operation speed and reliability of the packaging system 1.

[0128] A fourth semiconductor package 800 may be further disposed on the bottom surface 1000b of the board 1000. The fourth semiconductor package 800 may include a fourth package substrate 810, a fourth semiconductor chip 820, and a fourth mold layer 830. A fourth connection terminal 850 may be arranged between the board 1000 and the fourth semiconductor package 800. The fourth semiconductor package 800 may be electrically connected to the board 1000 through the fourth connection terminal 850. The fourth connection terminal 850 may include one or more of a solder ball, a bump, and a column. The height H5 of the fourth semiconductor package 800 mounted on the board 1000 may be defined as including the height of the fourth connection terminal 850. For example, the height H5 of the mounted fourth semiconductor package 800 may be equal to the sum of the height of the fourth connection terminal 850, the height of the fourth package substrate 810, and the height of the fourth mold layer 830. The height H5 of the mounted fourth semiconductor package 800 may be greater than the height H1 of the mounted first semiconductor package 100. Even if the height H5 of the mounted fourth semiconductor package 800 is large, the fourth semiconductor package 800 may be electrically connected to the package system 1 through the board 1000 .

[0129] The fourth semiconductor package 800 may be electrically connected to one of the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, and the first passive device 400. The fourth semiconductor package 800 may overlap or be adjacent to one of the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, and the first passive device 400. Therefore, the signal path length between the fourth semiconductor package 800 and one of the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, and the first passive device 400 may be reduced. The fourth semiconductor package 800 may be provided in plurality. In this case, the heights H4 of the fourth semiconductor packages 800 may be the same as or different from each other.

[0130] The second passive device 420 may be mounted on the bottom surface 1000b of the board 1000. The second connector 412 may be further disposed between the board 1000 and the second passive device 420. The second passive device 420 may be coupled to the board 1000 via the second connector 412. The second connector 412 may include a soldering material. The height H6 of the second passive device 420 mounted on the board 1000 may be defined as including the height H61 of the second connector 412. For example, the height H4 of the mounted second passive device 420 may be equal to the sum of the height H61 of the second connector 412 and the height H60 of the second passive device 420' before being mounted on the board 1000. The height H6 of the mounted second passive device 420 may be greater than the sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat conducting layer 710. Even if the height H6 of the mounted second passive device 420 is large, the second passive device 420 may be electrically connected to the packaging system 1 via the board 1000.

[0131] The second passive device 420 may be electrically connected to one of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. When viewed from a top view, the second passive device 420 may overlap or be adjacent to one of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. Therefore, the electrical path length between the second passive device 420 and one of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may be reduced. The second passive device 420 may be provided in plurality. In this case, the heights H6 of the second passive devices 420 may be the same as or different from each other. This will be described below with reference to Figure 5C and Figure 5D The conductive terminal 550 and the lower pad 540 are depicted.

[0132] Reference FIG. 5A to FIG. 5C , the lower pad 540 may be disposed on the bottom surface 500b of the substrate 500. The lower pad 540 may include a connection pad 541 and a test pad 542. During the manufacture of the packaging system 1 or before the packaging system 1 is mounted on the board 1000, a process of evaluating the electrical characteristics of the packaging system 1 may be performed. The test pad 542 may be used to evaluate the electrical characteristics of the packaging system 1. For example, a probe (not shown) may contact the test pad 542 to evaluate the electrical characteristics of one or more of the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive device 400, and the electronic device 430. Thereafter, the conductive terminal 550 may be formed, and the packaging system 1 may be mounted on the board 1000.

[0133] like Figure 5CAs shown, the conductive terminal 550 may be disposed on the corresponding bottom surface of the lower pad 540. The conductive terminal 550 may include a first terminal 551 and a second terminal 552. The first terminal 551 may be coupled to the connecting pad 541. The first terminal 551 may electrically connect the board 1000 to one or more of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. The first terminal 551 may be used as a signal path.

[0134] The second terminal 552 may be coupled to the test pad 542. For example, the second terminal 552 may be used as a ground terminal and a ground voltage may be applied thereto. The test pad 542 may be provided as a supply path for the ground voltage. For another example, the second terminal 552 may be used as a dummy terminal and may not be electrically connected to the conductive pad 1500.

[0135] like Figure 5D As shown, the second terminal 552 may not be provided. The test pad 542 may not be physically and electrically connected to the board 1000. Although not shown, an underfill material may be further provided to fill the gap between the board 1000 and the test pad 542. The underfill material may include a dielectric polymer.

[0136] According to the present inventive concept, the first heat conducting layer may be disposed on the first semiconductor package. When viewed from a top view, the groove may overlap with one or more of the second semiconductor package and the third semiconductor package. Therefore, the height of the first heat conducting layer may be less than the height of the second heat conducting layer and may be less than the height of the third heat conducting layer. The more the height of the first heat conducting layer is reduced, the more the thermal characteristics of the first semiconductor package are improved. The improvement of the thermal characteristics of the first semiconductor package can improve the thermal characteristics of the packaging system.

[0137] The detailed description of the present inventive concept should not be construed as being limited to the embodiments set forth herein, and the present inventive concept is intended to cover various combinations, modifications, and changes without departing from the spirit and scope of the present inventive concept.

Claims

1. A semiconductor packaging system, comprising: substrate; a first semiconductor package mounted on a top surface of the substrate and including a first semiconductor chip including a plurality of logic circuits; a first heat-conducting layer, the first heat-conducting layer being located on the first semiconductor package; a second semiconductor package mounted on the top surface of the substrate; a second heat-conducting layer, the second heat-conducting layer being located on the second semiconductor package, a first passive component mounted on the top surface of the substrate; as well as a heat radiation structure, wherein the heat radiation structure is located on the first heat conducting layer, the second heat conducting layer and the first passive component, The heat radiation structure includes a first bottom surface and a second bottom surface, The first bottom surface is in physical contact with the first thermally conductive layer, The level of the second bottom surface is higher than the level of the first bottom surface, The second bottom surface is located on the second heat-conducting layer, or on the first passive component, or on both the second heat-conducting layer and the first passive component. The level of the first bottom surface and the level of the bottom surface of the second heat-conducting layer where the heat radiation structure physically contacts are set so that the height of the first heat-conducting layer is smaller than the height of the second heat-conducting layer.

2. The semiconductor packaging system according to claim 1, wherein: The height of the second semiconductor package is equal to or greater than the height of the first semiconductor package, The second bottom surface of the heat radiation structure is located on the second heat conductive layer.

3. The semiconductor packaging system according to claim 2, wherein: The second thermally conductive layer is in physical contact with the second bottom surface.

4. The semiconductor packaging system according to claim 1, wherein: The second semiconductor package comprises a package substrate, a second semiconductor chip and a molding layer, The second semiconductor chip includes a memory circuit or a power management integrated circuit.

5. The semiconductor packaging system according to claim 1, wherein: The height of the first passive component is equal to or greater than the sum of the height of the first semiconductor package and the height of the first heat conducting layer. The second bottom surface of the heat radiation structure is located on the first passive component.

6. The semiconductor packaging system according to claim 1, wherein: The heat radiation structure further includes a third bottom surface, The level of the third bottom surface is higher than the level of the first bottom surface, the third bottom surface is located on the second semiconductor package, the second bottom surface is located on the first passive component, The third bottom surface has a level different from that of the second bottom surface.

7. The semiconductor packaging system according to claim 1, further comprising: a ground pattern located on the top surface of the substrate and configured to be supplied with a ground voltage; as well as a conductive adhesive pattern, the conductive adhesive pattern being located between the ground pattern and the heat radiation structure, wherein The heat radiation structure is electrically connected to the ground pattern through the conductive adhesive pattern.

8. The semiconductor packaging system according to claim 1, further comprising: a plate located on a bottom surface of the base plate; as well as A plurality of conductive terminals are coupled to the substrate and the board.

9. The semiconductor packaging system according to claim 8, further comprising: a second passive component mounted on the bottom surface of the board, wherein The height of the second passive component is greater than the sum of the height of the first semiconductor package and the height of the first heat conducting layer.

10. A semiconductor packaging system, comprising: substrate; a first semiconductor package mounted on the substrate; a second semiconductor package mounted on the substrate; Passive components, the passive components are mounted on the substrate; a heat radiation structure located on the first semiconductor package, the second semiconductor package, and the passive device, a first bottom surface of the heat radiation structure comprising a groove, and when viewed from a top view, the groove overlaps one or more of the second semiconductor package and the passive device; and a plurality of heat-conducting layers, the plurality of heat-conducting layers being in physical contact with the heat-radiating structure, The plurality of heat-conducting layers include a first heat-conducting layer located on a top surface of the first semiconductor package, The level of the bottom surface of the heat radiation structure including the groove is set so that the first heat conductive layer is thinner than any other heat conductive layer among the plurality of heat conductive layers.

11. The semiconductor packaging system according to claim 10, wherein: The height of the passive component is equal to or greater than the sum of the height of the first semiconductor package and the height of the first heat conducting layer. When viewed from a top plan view, the trench overlaps the passive device.

12. The semiconductor packaging system according to claim 10, wherein: The plurality of thermally conductive layers further includes a second thermally conductive layer located on a top surface of the second semiconductor package.

13. The semiconductor packaging system according to claim 12, wherein: The height of the second semiconductor package is equal to or greater than the height of the first semiconductor package, When viewed from a top plan view, the trench overlaps the second semiconductor package.

14. The semiconductor packaging system according to claim 10, wherein: The first semiconductor package includes a first substrate, a first semiconductor chip and a first molding layer. The first semiconductor chip includes a system on chip.

15. The semiconductor packaging system according to claim 14, wherein: The second semiconductor package includes a power management chip or a memory chip.

16. The semiconductor packaging system according to claim 10, wherein: The groove includes a first groove and a second groove, In a top view, the first trench overlaps with the passive device, and the second trench overlaps with the second semiconductor package. A bottom surface of the second groove is at a different level from a bottom surface of the first groove.

17. A semiconductor packaging system, comprising: substrate; a first semiconductor package mounted on the substrate; Passive components, the passive components are mounted on the substrate; A first heat conducting layer; a second semiconductor package mounted on the substrate; a second heat-conducting layer, the second heat-conducting layer being located on the second semiconductor package, wherein a height of the first heat-conducting layer is smaller than a height of the second heat-conducting layer; as well as a heat radiation structure, the heat radiation structure being located on the first semiconductor package and the passive device, The heat radiation structure includes a first bottom surface and a second bottom surface, The first bottom surface is in physical contact with the first heat-conducting layer, the first heat-conducting layer is located between the first semiconductor package and the heat radiation structure, the second bottom surface is located on the passive component, and the level of the second bottom surface is higher than the level of the first bottom surface, so that when the height of the passive component is equal to or greater than the sum of the height of the first semiconductor package and the height of the first heat-conducting layer, the height of the first heat-conducting layer does not increase.

18. The semiconductor packaging system according to claim 17, wherein: The first semiconductor package includes a system on chip.

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