Advanced AI agents for modeling physical interactions

Abstract

An advanced artificial intelligence agent for modeling physical interactions is described herein. An apparatus for providing an active artificial intelligence (AI) agent includes at least one database for storing physical interaction data and a computing cluster coupled to the at least one database. The computing cluster automatically obtains the physical interaction data from a data collection module without manual interaction, stores the physical interaction data in at least one database, and automatically trains different sets of machine learning program units to simulate physical interactions using each individual program unit with a different model based on the applied physical interaction data.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via general-purpose graphics processing units. In particular, embodiments relate to advanced artificial intelligence agents for modeling physical interactions. Background Art

[0002] Current parallel graphics data processing includes the development of systems and methods for performing specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling these processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempts to process as much graphics data as possible in parallel in different parts of the graphics pipeline. Parallel graphics processors with a single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of the software and hardware of the SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013).

[0004] In artificial intelligence, an intelligent agent (IA) is an autonomous entity that observes through sensors and acts on its environment using actuators, and directs its activities towards achieving a goal. Current IAs work in a passive manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Thus, a more particular description of the embodiments briefly summarized above may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings depict only typical embodiments and are therefore not to be considered limiting of the scope thereof.

[0006] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0007] Figures 2A-2D shows a parallel processor assembly according to an embodiment;

[0008] Figures 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0009] Figures 4A-4FAn exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0010] Figure 5 shows a graphics processing pipeline according to an embodiment;

[0011] Figure 6 A method 600 of an advanced proactive artificial intelligence agent for modeling physical interactions is shown, according to one embodiment;

[0012] Figure 7 A block diagram of a system (e.g., apparatus) having an advanced active artificial intelligence agent for modeling physical interactions is shown according to one embodiment;

[0013] Figure 8 shows a machine learning software stack according to an embodiment;

[0014] Figure 9 shows a highly parallel general purpose graphics processing unit according to an embodiment;

[0015] Figure 10 A multi-GPU computing system according to an embodiment is shown;

[0016] Figure 11A -B shows the layers of an exemplary deep neural network;

[0017] Figure 12 An exemplary recurrent neural network is shown;

[0018] Figure 13 Demonstrates the training and deployment of deep neural networks;

[0019] Figure 14 is a block diagram illustrating distributed learning;

[0020] Figure 15 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is shown;

[0021] Figure 16 is a block diagram of a processing system 1600 according to an embodiment;

[0022] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A-1702N, an integrated memory controller 1714, and an integrated graphics processor 1708;

[0023] Figure 18 is a block diagram of a graphics processor 1800 , which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores;

[0024] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments;

[0025] Figure 20 is a block diagram of another embodiment of a graphics processor 2000;

[0026] Figure 21 Thread execution logic 2100 is shown, which includes an array of processing elements employed in some embodiments of a GPE;

[0027] Figure 22 is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments;

[0028] Figure 23 is a block diagram of another embodiment of a graphics processor 2300;

[0029] Figure 24A is a block diagram illustrating a graphics processor command format 2400 according to some embodiments;

[0030] Figure 24B is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment;

[0031] Figure 25 illustrates an exemplary graphics software architecture for data processing system 2500 according to some embodiments;

[0032] Figure 26 is a block diagram illustrating an IP core development system 2600 that may be used to fabricate integrated circuits for performing operations according to an embodiment; and

[0033] Figures 27-29 An exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein are shown. DETAILED DESCRIPTION

[0034] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0035] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiments.

[0036] System Overview

[0037] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104 communicating via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset assembly or may be integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107 that may enable computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may enable a display controller, which may be included in one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0038] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters, such as, for example, a multiple integrated core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 110B.

[0039] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, as well as various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more wireless radios.

[0040] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components in the system may be implemented using any suitable protocol, for example, a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express), or any other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols known in the art).

[0041] In one embodiment, one or more parallel processors 112 include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuits optimized for general-purpose processing while retaining the underlying computing architecture, which will be described in more detail herein. In yet another embodiment, the components of computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, (multiple) processors 102, and I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0042] It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112, can be modified as desired. For example, in some embodiments, the system memory 104 is directly connected to the processor(s) 102 rather than being connected to the processor(s) 102 through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than being connected to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments can include two or more sets of processors 102 attached via multiple sockets, which can be coupled to two or more instances of the parallel processor(s) 112.

[0043] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Additionally, some architectures may be different from those described in the preceding text. Figure 1 Components similar to those shown in FIG are referred to using different terminology. For example, memory hub 105 may be referred to as a north bridge in some architectures, while I / O hub 107 may be referred to as a south bridge.

[0044] Figure 2A1 shows a parallel processor 200 according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The parallel processor 200 shown is a processor according to an embodiment. Figure 1 A variation of one or more parallel processors 112 is shown in .

[0045] In one embodiment, parallel processor 200 includes parallel processing unit (PPU) 202. PPU includes I / O unit 204, which enables communication with other devices, including other instances of PPU 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 connects to other devices using a hub or switch interface (e.g., memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within PPU 202, I / O unit 204 is connected to host interface 206, which receives commands for executing processing operations, and memory crossbar switch 216, which receives commands for executing memory operations.

[0046] When host interface 206 receives command buffers via I / O unit 204, it can direct work operations for executing these commands to front-end 208. In one embodiment, front-end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is correctly configured and in a valid state before tasks are distributed to processing clusters within processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executing on a microcontroller. A microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, enabling fast preemption and context switching of threads executing on processing array 212. In one embodiment, host software can qualify workloads for scheduling on processing array 212 via one of multiple graphics processing doorbells. The workload can then be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

[0047] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N in the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may assign work to the clusters 214A-214N in the processing cluster array 212 using a variety of scheduling and / or work distribution algorithms that may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210 or may be assisted in part by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N in the processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0048] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0049] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0050] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better implement the distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0051] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include an index of the following data to be processed: for example, surface (image block (patch)) data, primitive data, vertex data and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). The scheduler 210 may be configured to obtain an index corresponding to a task, or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to be in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is started.

[0052] Each of the one or more instances of parallel processing unit 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar switch 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion (e.g., memory cells) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0053] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Render targets such as frame buffers or texture maps may be stored across the memory units 224A-224N, allowing the partition units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, the local instance of the parallel processor memory 222 may be eliminated to support a unified memory design that utilizes system memory in combination with local cache memory.

[0054] In one embodiment, any of the clusters 214A-214N in the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. Memory crossbar 216 can be configured to route the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N that can perform additional processing operations on the output. Each cluster 214A-214N can communicate with memory interface 218 via memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has connections to memory interface 218 for communication with I / O unit 204, as well as connections to local instances of parallel processor memory 222, enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0055] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in one embodiment, some instances of parallel processing unit 202 may include floating point units with higher precision than other instances. Systems including one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0056] Figure 2B is a block diagram of the partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2. As shown in the figure, partition unit 220 includes L2 cache 221, frame buffer interface 225 and ROP 226 (raster operation unit). L2 cache 221 is a read / write cache that is configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent writeback requests are output by L2 cache 221 to frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via frame buffer interface 225 for processing. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in parallel processor memory (e.g., memory units 224A-224N of FIG. 2 (e.g., within parallel processor memory 222)).

[0057] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stenciling, z-testing, blending, etc.). ROP 226 then outputs the processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0058] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2 ), rather than within partition unit 220. In such embodiments, read requests and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 216. The processed graphics data may be displayed on a display device (e.g., Figure 1 100 ), is routed for further processing by the processor(s) 102 , or is routed for Figure 2A One of the processing entities within the parallel processor 200 further processes.

[0059] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of Figure 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of usually synchronized threads using a common instruction unit, which is configured to issue instructions to a group of processing engines within each processing cluster in the processing cluster. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow different execution paths through a given thread program. It will be understood by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0060] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of these instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 shown is an illustrative example of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0061] Each graphics multiprocessor 234 within a processing cluster 214 may include a set of identical function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0062] Instructions sent to processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0063] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can forgo the internal cache memory and use the cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to the L2 cache within a partition unit (e.g., partition units 220A-220N of FIG. 2 ), which is shared between all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. Embodiments in which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 can share common instructions and data that can be stored in the L1 cache 308.

[0064] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of Figure 2. The MMU 245 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tile stitching) and, optionally, to cache line indices. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality in order to allow efficient request interleaving between partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0065] In graphics and compute applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some embodiments, from an L1 cache within the graphics multiprocessor 234, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or for storage in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to a ROP unit, which may be located in conjunction with a partition unit (e.g., partition units 220A-220N of FIG. 2 ) as described herein. The preROP242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0066] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within a processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of a processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0067] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0068] In one embodiment, the instruction cache 252 receives an instruction stream to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched to be executed by the instruction unit 254. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 262. The instruction can access any of the local address space, the shared address space, or the global address space by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0069] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to graphics multiprocessor 324. In one embodiment, register file 258 is divided among each of the functional units so that each functional unit is allocated a dedicated portion of register file 258. In one embodiment, register file 258 is divided among the different warps being executed by graphics multiprocessor 324.

[0070] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be architecturally similar or architecturally different. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function units or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function logic or special-function logic.

[0071] In one embodiment, GPGPU core 262 includes SIMD logic that can execute a single instruction to multiple groups of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. The SIMD instructions of the GPGPU core can be generated by the shader compiler at compile time, or automatically generated when executing a program written and compiled for single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0072] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, resulting in very low latency for data transfers between the GPGPU core 262 and the register file 258. The shared memory 270 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. In addition to automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0073] Figures 3A-3B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0074] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. Figure 2DIn contrast to the graphics multiprocessor 234, the graphics multiprocessor 325 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture unit(s) 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache 342, and shared memory 346.

[0075] Various components can communicate via interconnect fabric 327. In one embodiment, interconnect fabric 327 includes one or more crossbar switches to enable communication between the various components of graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate high-speed network fabric layer upon which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via interconnect fabric 327. Interconnect fabric 327 can arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth distribution between components.

[0076] Figure 3B FIG3 shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A As shown. Execution resources 356A-356D can work with texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D can share multiple instances of instruction cache 354 and shared memory 362 as well as texture and / or data caches 358A-358B. Various components can be connected to the Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0077] Those skilled in the art will understand that Figure 1 、 Figures 2A-2D and Figures 3A-3BThe architecture described in the foregoing is illustrative and not intended to limit the scope of the present embodiments. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any suitably configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (e.g., parallel processing unit 202 of FIG. 2 ), and one or more graphics processors or special-purpose processing units.

[0078] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0079] Technologies for GPU to host processor interconnect

[0080] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0081] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444A-444B, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 497, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0082] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430A-430B, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430A-430B and 450-453 may use the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0083] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

[0084] Figure 4B 4 shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0085] The processor 407 shown includes multiple cores 460A-460D, each core having a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.), which are not shown to avoid obscuring the basic principles of the present invention. The caches 462A-462D may include a level 1 (L1) cache and a level 2 (L2) cache. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by the set of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 - 402 .

[0086] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 via inter-core communication over a coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented on the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and are not described in detail herein to avoid obscuring the underlying principles of the present invention.

[0087] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, allowing graphics acceleration module 446 to participate in a cache coherence protocol as a peer of the core. Specifically, interface 435 provides a connection to proxy circuitry 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0088] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N can each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N can include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In other words, the graphics acceleration module can be a GPU with multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N can be individual GPUs integrated on a common package, line card, or chip.

[0089] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, a cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, data stored in the cache 438 and graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and system memory 411. As mentioned above, this can be achieved via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates to cache 438 related to modifications / accesses to cache lines on processor caches 462A-462D, 456, and receiving updates from cache 438).

[0090] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 can perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, context management circuitry 448 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer). Context management circuitry 448 can then restore register values ​​upon returning to that context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0091] In one implementation, virtual / effective addresses from the graphics processing engine 431 are converted by the MMU 439 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" and the slices are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0092] Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0093] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped into the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear as independent units to the system.

[0094] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0095] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memories 433-434, M is data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, N) within the cores' caches 462A-462D, 456 and system memory 411.

[0096] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated into the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, any form of bus or interface protocol can be used) through the high-speed link 440. The accelerator integrated circuit 436 can perform operations related to Figure 4B The operations described are the same operations, but are performed with potentially higher throughput given their close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0097] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0098] In one embodiment of a dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0099] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. This shared model requires the hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0100] For the shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (i.e., calling system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0101] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to a GPU call 481 from an application 480 executing on processor 407. Process elements 483 contain the process state of the corresponding application 480. The work descriptor (WD) 484 contained in process element 483 may be a single job requested by the application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application address space 482.

[0102] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0103] In one implementation, a dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or individual graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and when the graphics acceleration module 446 is assigned, the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0104] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448, as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can process interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the effective addresses 493 generated by the graphics processing engines 431-432, N are converted into real addresses by the MMU 439.

[0105] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and this same set of registers 445 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0106] Table 1 - Registers initialized by the hypervisor

[0107] Slice Control Register Process area pointer for real address (RA) scheduling Permission Mask Override Register Interrupt vector table entry offset Interrupt vector table entry limit Status Register Logical partition ID Real Address (RA) Hypervisor Accelerator Utilizes Record Pointers Storage Description Register

[0108] Example registers that may be initialized by the operating system are shown in Table 2.

[0109] Table 2 - Registers initialized by the operating system

[0110] Process and thread identification Effective Address (EA) context save / restore pointer Virtual Address (VA) Accelerator Utilizes Record Pointers Virtual Address (VA) Segment Table Pointer Permission Masking Job Descriptor

[0111] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. A WD 484 contains all the information required by a graphics processing engine 431-432, N to do its work, or a WD 484 may be a pointer to a memory location in a command queue where an application has set up work to be done.

[0112] Figure 4E 4. Additional details of one embodiment of the sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine to the operating system 495.

[0113] The shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graph-directed sharing.

[0114] In this model, hypervisor 496 owns graphics acceleration module 446 and makes its functionality available to all operating systems 495. For graphics acceleration module 446 to support virtualization performed by hypervisor 496, graphics acceleration module 446 may adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 446 must provide a context save and restore mechanism. 2) Graphics acceleration module 446 guarantees that application job requests complete within a specified amount of time, including any translation errors, or graphics acceleration module 446 provides the ability to preempt processing of jobs. 3) When operating in a directed-sharing programming model, graphics acceleration module 446 must ensure fairness between processes.

[0115] In one embodiment, for the shared model, application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current permission mask overwrite register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of the area in the application's address space 482 used by the graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area may be fixed system memory.

[0116] Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0117] Table 3 - OS to hypervisor call parameters

[0118] Work Descriptor (WD) Authority Mask Register (AMR) value (potentially masked) Effective Address (EA) Context Save / Restore Region Pointer (CSRP) Processor ID (PID) and optional thread ID (TID) Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) Virtual address of the storage segment table pointer (SSTP) Logical Interrupt Service Number (LISN)

[0119] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has been registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places a process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0120] Table 4 - Process Element Information

[0121] Work Descriptor (WD) Authority Mask Register (AMR) value (potentially masked) Effective Address (EA) Context Save / Restore Region Pointer (CSRP) Process ID (PID) and optional thread ID (TID) Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) Virtual address of the storage segment table pointer (SSTP) Logical Interrupt Service Number (LISN) Interrupt vector table, derived from hypervisor call parameters Status register (SR) value 0 Logical Partition ID (LPID) 1 Real Address (RA) Hypervisor Accelerator Utilizes Record Pointers 2 Storage Descriptor Register (SDR)

[0122] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 490 registers 445 .

[0123] like Figure 4F As shown, one embodiment of the present invention employs a unified memory that is addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. Thus, the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0124] In one embodiment, bias / coherency management circuitry 494A-494E within one or more of MMUs 439A-439E ensures cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413 and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. Figure 4FMultiple instances of bias / coherence management circuits 494A- 494E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0125] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the typical performance drawbacks associated with full system cache coherence. The ability to access GPU-attached memory 420-423 as system memory without the heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead may be critical to the execution time of offloaded calculations. For example, in situations with a large amount of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU calculations all play a role in determining the effectiveness of GPU offloading.

[0126] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure that includes 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0127] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from the GPUs 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPUs whose pages are found in the host bias are forwarded to the processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from the processor 405 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests for pages in the GPU bias can be forwarded to the GPUs 410-413. Then, if the GPU is not currently using the page, the GPU can transfer the page to the host processor bias.

[0128] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, by a purely hardware-based mechanism.

[0129] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU directing it to change the bias state and, for certain transitions, perform a cache flush operation in the host. A cache flush operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0130] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that the GPU-biased pages are the pages requested by the GPU and not the pages requested by host processor 405, and vice versa.

[0131] Graphics processing pipeline

[0132] Figure 5 FIG. 5 shows a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein (e.g., parallel processor 200 of FIG. 2 , which in one embodiment is a graphics processor 200). Figure 12 ). Various parallel processing systems may implement graphics processing pipeline 500 via one or more instances of parallel processing units (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functionality of one or more of vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functionality of data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operations unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A-220N of FIG. 2 ). Graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG. 2 ) via memory interface 528, which may be an example of memory interface 218 in FIG. 2 .

[0133] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes the vertex shader program, lighting and transforming the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in cache memory, local memory, or system memory for processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0134] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, image tiles, etc., which are supported by various graphics processing application programming interfaces (APIs).

[0135] The tessellation control processing unit 508 treats the input vertices as control points for the geometric image patch. The control points are transformed from an input representation from the image patch (e.g., the basis of the image patch) into a representation suitable for surface estimation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric image patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the image patch and tessellate the image patch into a plurality of geometric primitives (e.g., line, triangle, or quadrilateral primitives), which are sent to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated image patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0136] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader programs. In one embodiment, the geometry processing unit 516 is programmed to tessellate the graphics primitives into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0137] In some embodiments, the geometry processing unit 516 can add or delete elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0138] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs these fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit that is configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing the fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0139] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2 and / or as shown in FIG. 3 ). Figure 1 Raster operations unit 526 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0140] Advanced AI agents for modeling physical interactions

[0141] Embodiments of the present design generate predicted physical interactions based on training of individual program units and a master program unit. In one example, compared to conventional approaches utilizing passive AI agents, the predicted physical interactions act like biological active AI agents. Here, the distinction between passive / active AI agents primarily refers to the training data collection process. Note that the current best-performing DNN architectures tend to have more stacked layers and more learnable parameters, and therefore require a large amount of well-annotated data to train a good model. However, data annotation is time-consuming and costly. With passive AI agents, training data is collected offline, for example, by downloading images or videos from the internet and requesting data from third-party vendors, and data annotation should be performed separately. With active AI agents, like human biological agents, these active agents collect data automatically and simultaneously (i.e., online). For the present design with active AI agents, most or all of the data is collected online (e.g., from a data collection module), and weak annotations are first automatically generated based on clustering and then refined during training, i.e., no manual interaction is required for active AI agents. Examples of weakly annotated training data include bounding boxes or image-level labels.

[0142] Figure 6 A method 600 of an advanced active artificial intelligence agent for modeling physical interactions is shown, according to one embodiment. The method 600 may be performed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. In one example, at least one of a training framework, a Bayesian program unit, a processor, a graphics multiprocessor, a GPGPU core, a compute cluster, and any hardware components discussed herein performs the operations of the method 600. For simplicity and clarity of presentation, the processes of the method 600 are shown in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order.

[0143] Method 600 begins at operation 602 by automatically obtaining physical interaction data (e.g., image-based data for images of physical interaction data, images of objects in different positions, images of objects when rotated, etc.) from a data collection module without manual interaction. The data collection module is associated with different target DNN models. Some existing knowledge (e.g., physical interaction concepts) can be integrated into the module to assist in the data collection process. At operation 604, the physical interaction data is stored in an appropriate database (e.g., at least one database, an image database, a first image database with images of a first object in different positions, a second image database with images of a second object in different positions, etc.). At operation 606, the method automatically trains different sets of machine learning program units (e.g., DNN models, DNN model 1, DNN model 2...DNN model n) to simulate physical interactions (e.g., pushing, grasping, rotating, etc.) using a training framework with physical interaction data. In one example, the physical interaction simulates any interaction between a person and a physical object. Each individual program unit (e.g., a Bayesian program unit) has a different model based on the applied physical interaction data. At operation 608 , a master program unit (eg, a master Bayesian program unit) is trained by jointly approximating and modeling the behavior of the entire set (eg, n DNN models) of each individual program unit.

[0144] A loss function or cost function is a function that maps the value of an event or one or more variables to a real number that intuitively represents the cost associated with the event. Optimization problems are designed to minimize the loss function. The objective function is either a loss function or a negative function (e.g., a reward function, profit function, utility function, etc.), in which case the function is designed to be maximized or minimized. For example, in deep learning, loss functions are often used to measure loss (i.e., misclassification).

[0145] Each individual Bayesian program unit (e.g., a total of n Bayesian program units) has a corresponding objective / loss function (which is the same as each other in the case where the objective function is a loss function, or different from each other in the case where the objective function is different from the loss function, with respect to how many tasks will be processed together) and a training subset. Once the training of all individual Bayesian program units has been completed, the method can obtain the corresponding model. Then, the objective / loss function of the master Bayesian program unit can be defined to minimize / maximize the average / sum of the corresponding objective / loss functions taking into account all individual Bayesian program units and the corresponding training subsets, and the master Bayesian program model can be obtained by solving this problem in a joint training (using conventional optimization techniques, such as least squares and group lasso methods).

[0146] At operation 610, the method applies the input to a master program unit (e.g., a master Bayesian program unit) to generate predicted physical interactions based on the training of the individual program units and the master program unit. In one example, the predicted physical interactions act like biological active AI agents, as compared to conventional methods that use passive AI agents. Biological active AI agents can be used for any type of physical interaction, including robotic applications.

[0147] Figure 7 A block diagram of a system (e.g., an apparatus) with an advanced active artificial intelligence agent for modeling physical interactions is shown according to one embodiment. System 700 can be implemented in any processor, graphics multiprocessor, GPGPU core, or computing cluster discussed herein. Once a given network is structured for a task, the neural network is trained using a training data set (e.g., physical interaction data, 1302). Various training frameworks (e.g., training framework 702, 1304) have been developed to enable hardware acceleration of the training process. For example, Figure 8The machine learning framework 804 can be configured as a training framework 804. The training framework 702 can access the untrained neural network 703 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network (e.g., trained neural network 1308). The system 700 includes a training framework 702, which includes an untrained neural network 703. The training framework 702 automatically obtains physical interaction data (e.g., image-based data for images of physical interaction data, images of objects in different positions, images of rotated objects, etc.) from a data collection module without manual interaction. The data collection module is associated with different target DNN models. Some existing knowledge (e.g., physical interaction concepts) can be integrated into the module to assist in the data collection process. The training framework 702 stores the physical interaction data in an appropriate database (e.g., databases 710...720, image databases, first image databases with images of the first object in different positions, second image databases with images of the second object in different positions, etc.). In one example, database 710 includes an image of an object (e.g., a book, an eraser) in a first position, and an image of the object (e.g., a book, an eraser) in a second position after being pushed in the direction of an arrow. In another example, database 720 includes an image of a cup in a first position, where upper line 722a represents a grip point, and lower line 722b also represents a grip point for gripping the cup. Another image shows the cup in a second rotated position (i.e., rotated counterclockwise), where lines 724a and 724b represent grip points for gripping the cup. Another image from database 720 shows a first L-shaped object on top of a second L-shaped object, where lines 726a and 726b represent the grip points for the first L-shaped object. Another image, captured after the first L-shaped object has been removed, shows only the second L-shaped object, where lines 728a and 728b represent the grip points for the second L-shaped object.

[0148] The training framework utilizes communications 712-714 to transmit physical interaction data to automatically train different sets of machine learning program units (e.g., DNN models, DNN model 1, DNN model 2...DNN model n) to simulate physical interactions (e.g., pushing, grasping, rotating, etc.). In one example, the physical interaction simulates any interaction between a person and a physical object. Each individual program unit has a different model based on the applied physical interaction data. The main program unit 750 (e.g., main Bayesian program unit 750) is trained by jointly approximating and modeling the behavior of the entire set of each individual program unit (e.g., n DNN models). The framework 702 utilizes communication 730 to send the DNN model to the main Bayesian program 750.

[0149] Input 760 (e.g., images, visual input) is applied to a master program unit 750 (e.g., master Bayesian program unit 750) to generate predicted physical interactions based on the training of the individual program units and the master program unit. In one example, the predicted physical interactions act like biological active AI agents, compared to conventional approaches that use passive AI agents. Biological active AI agents can be used for any type of physical interaction, including robotic applications.

[0150] Machine Learning Overview

[0151] Machine learning algorithms are algorithms that can learn from a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0152] One exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation that can be used to generate an output in the output layer. The nodes of the network are fully connected to the nodes in adjacent layers via edges, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights") associated with each of the edges connecting the layers. The output from a neural network algorithm can take a variety of forms, depending on the specific model represented by the algorithm being executed.

[0153] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data that represents the problem being modeled by the network, and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted as the error signal propagates backward through the layers of the network so as to minimize the error. The network is considered "trained" when the error for each of the outputs generated from the instances of the training data set is minimized.

[0154] The quality of the dataset used to train the algorithm can significantly affect the accuracy of the machine learning algorithm. The training process can be computationally intensive and can require a significant amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in the neural network naturally lend themselves to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of the parallel processing hardware within general-purpose graphics processing devices.

[0155] Figure 8 800 is an overview of a machine learning software stack. A machine learning application 802 can be configured to train a neural network using a training dataset, or to implement machine intelligence using a trained deep neural network. The machine learning application 802 can include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. The machine learning application 802 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0156] Hardware acceleration for machine learning applications 802 can be implemented via a machine learning framework 804. The machine learning framework 804 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 804, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning framework 804 to perform the necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 804 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0157] The machine learning framework 804 can process input data received from the machine learning application 802 and generate appropriate input to the computation framework 806. The computation framework 806 can abstract the underlying instructions provided to the GPGPU driver 808 to enable the machine learning framework 804 to take advantage of hardware acceleration via the GPGPU hardware 810 without requiring the machine learning framework 804 to have a deep understanding of the architecture of the GPGPU hardware 810. In addition, the computation framework 806 can implement hardware acceleration for the machine learning framework 804 across various types and generations of GPGPU hardware 810.

[0158] GPGPU machine learning acceleration

[0159] Figure 9 A highly parallel general purpose graphics processing unit 900 is shown in accordance with an embodiment. In one embodiment, the general purpose processing unit (GPGPU) 900 can be configured to be particularly efficient at processing the type of computational workload associated with training deep neural networks. Additionally, the GPGPU 900 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster to improve the training speed of particularly deep neural networks.

[0160] GPGPU 900 includes a host interface 902 for connecting to a host processor. In one embodiment, host interface 902 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 900 receives commands from the host processor and, using a global scheduler 904, distributes the execution threads associated with these commands to a set of compute clusters 906A-H. Compute clusters 906A-H share a cache memory 908. Cache memory 908 can serve as a higher-level cache than the cache memory within compute clusters 906A-H.

[0161] GPGPU 900 includes memory 914A-B coupled to compute clusters 906A-H via a set of memory controllers 912A-B. In various embodiments, memory 914A-B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0162] In one embodiment, each computing cluster GPLAB06A-H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the compute cluster includes multiple types of integer logic units and floating-point logic units that can perform computational operations with a range of precision, including those suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating-point units in each of the compute clusters 906A-H can be configured to perform 16-bit floating-point operations or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0163] Multiple instances of GPGPU 900 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary depending on the embodiment. In one embodiment, multiple instances of GPGPU 900 communicate via a host interface 902. In one embodiment, GPGPU 900 includes an I / O hub 907 that couples GPGPU 900 to a GPU link 910, which enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 910 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 900. In one embodiment, GPU link 910 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 900 are located in separate data processing systems and communicate via a network device accessible through host interface 902. In one embodiment, GPU link 910 can be configured to enable connections to a host processor in addition to or as an alternative to host interface 902.

[0164] While the illustrated configuration of GPGPU 900 can be configured to train neural networks, one embodiment provides an alternative configuration of GPGPU 900 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 900 includes fewer compute clusters 906A-H relative to the training configuration. Additionally, the memory technology associated with memory 914A-B can differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 900 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inference operations of neural networks for deployment.

[0165] Figure 10 A multi-GPU computing system 1000 is shown according to an embodiment. The multi-GPU computing system 1000 may include a processor 1002 coupled to a plurality of GPGPUs 1006A-D via a host interface switch 1004. In one embodiment, the host interface switch 1004 is a PCI Express switch device that couples the processor 1002 to a PCI Express bus, through which the processor 1002 can communicate with the set of GPGPUs 1006A-D. Each of the plurality of GPGPUs 1006A-D may be a Figure 9 GPGPU 900. GPGPUs 1006A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 1016. The high-speed GPU-to-GPU links may be connected via dedicated GPU links (e.g., Figure 9 1004 ). A P2P GPU link 1016 connects to each of the GPGPUs 1006A-D. P2P GPU link 1016 enables direct communication between each of the GPGPUs 1006A-D, without requiring communication over a host interface bus to which the processor 1002 is connected. With GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or communication with other instances of the multi-GPU computing system 1000, for example, via one or more network devices. While in the illustrated embodiment, the GPGPUs 1006A-D are connected to the processor 1002 via the host interface switch 1004, in one embodiment, the processor 1002 includes direct support for the P2P GPU link 1016 and can connect directly to the GPGPUs 1006A-D.

[0166] Machine Learning Neural Network Implementation

[0167] The computing architecture provided by the embodiments described herein can be configured to perform a type of parallel processing particularly well-suited for training and deploying neural networks for machine learning. A neural network can be summarized as a network of functions with graph relationships. As is known in the art, various types of neural network implementations are used in machine learning. One exemplary type of neural network is a feedforward network, as previously described.

[0168] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network designed to process data with a known grid-like topology, such as image data. CNNs are therefore commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. Calculations for a CNN involve applying a mathematical operation called convolution to each filter to produce the output of that filter. Convolution is a special type of mathematical operation that is performed on two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted through the training process of the neural network.

[0169] A recurrent neural network (RNN) is a series of feedforward neural networks that include feedback connections between layers. RNNs model sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. Loops represent the influence of the current value of a variable on its own value at future times, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of the language data that can be composed.

[0170] The figures described below present exemplary feedforward networks, CNN networks, and RNN networks, and describe the general process for training and deploying each of these types of networks, respectively. It should be understood that these descriptions are exemplary and non-limiting of any particular embodiment described herein, and that the concepts shown can generally be applied to deep neural networks and machine learning techniques.

[0171] The above-described exemplary neural network can be used to perform deep learning. Deep learning is a type of machine learning that uses deep neural networks. The deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers, rather than shallow neural networks containing only a single hidden layer. Training deeper neural networks is generally more computationally intensive. However, the network's additional hidden layers enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0172] A deep neural network used for deep learning typically includes a front-end network for performing feature recognition coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning makes it possible to perform machine learning without requiring hand-crafted feature engineering to be performed on the model. Instead, a deep neural network can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to the specific task to be performed, and different models will be used to perform different tasks.

[0173] Once a neural network is structured, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors using algorithms such as stochastic gradient descent to update the neural network's weights.

[0174] Figure 11A -B shows an exemplary convolutional neural network. Figure 11A The various layers within a CNN are shown. Figure 11A As shown, an exemplary CNN for modeling image processing can receive input 1102 describing the red, green, and blue (RGB) components of an input image. Input 1102 can be processed by multiple convolutional layers (e.g., convolutional layer 1104, convolutional layer 1106). The outputs from the multiple convolutional layers can optionally be processed by a set of fully connected layers 1108. The neurons in the fully connected layer have full connections with all activations in the previous layer, as previously described for the feedforward network. The outputs from the fully connected layer 1108 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activations within the fully connected layer 1108. Not all CNN implementations use the fully connected layer DPLA08. For example, in some implementations, the convolutional layer 1106 can generate the output of the CNN.

[0175] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1108. Traditional neural network layers are fully connected so that each output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the domain (rather than the corresponding state value of each node in the domain) is input to the nodes of the subsequent layer, as shown in the figure. The kernel associated with the convolutional layer performs the convolution operation, and its output is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0176] Figure 11B1 shows exemplary computational stages within a convolutional layer of a CNN. Input 1112 to a convolutional layer of the CNN can be processed in three stages of a convolutional layer 1114. These three stages can include a convolution stage 1116, a detector stage 1118, and a pooling stage 1120. The convolutional layer 1114 can then output data to a subsequent convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN.

[0177] In the convolution stage 1116, several convolutions are performed in parallel to produce a set of linear activations. The convolution stage 1116 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 1116 defines a set of linear activations that are processed by successive stages of the convolution layer 1114.

[0178] The linear activations may be processed by the detector stage 1118. In the detector stage 1118, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear nature of the entire network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the activations are thresholded at zero.

[0179] The pooling stage 1120 uses a pooling function that replaces the output of the convolution layer 1106 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations of the input do not change the pooled output. In scenarios where the presence of a feature in the input data is more important than the exact location of the feature, invariance to local translation can be useful. Various types of pooling functions can be used during the pooling stage 1120, including max pooling, average pooling, and l2-norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations replace and additional convolution stages with an increased stride relative to the previous convolution stage.

[0180] The output from the convolutional layer 1114 may then be processed by the next layer 1122. The next layer 1122 may be an additional convolutional layer or one of the fully connected layers 1108. For example, Figure 11AThe first convolutional layer 1104 can output to the second convolutional layer 1106, and the second convolutional layer can output to the first layer in the fully connected layer 1108.

[0181] Figure 12 An exemplary recurrent neural network 1200 is shown. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be constructed in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The illustrated RNN 1200 can be described as having an input layer 1202 that receives an input vector, a hidden layer 1204 that implements the recurrent function, a feedback mechanism 1205 that implements a "memory" of the previous state, and an output layer 1206 that outputs the result. RNN 1200 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1205. For a given time step, the state of the hidden layer 1204 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1204. The hidden layer 1204 can use the state information determined during the processing of the initial input (x1) to process the second input (x2). Given the state, it can be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. Function f is typically nonlinear, for example, a variant of the hyperbolic tangent function (Tanh) or a modified function f(x) = max(0, x). However, the specific mathematical function used in hidden layer 1204 may vary depending on the specific implementation details of RNN 1200.

[0182] In addition to the basic CNN networks and RNN networks described, variants of these networks can be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNN is able to learn the long-term dependencies necessary to process longer language sequences. A variant of CNN is the convolutional deep belief network, which has a structure similar to that of CNN and is trained in a manner similar to that of a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of random (random) variables. DBNs can be trained layer by layer using greedy unsupervised learning. Then, by determining the optimal initial set of weights for the neural network, the learned weights of the DBN can be used to provide a pre-trained neural network.

[0183] Figure 13The training and deployment of a deep neural network is shown. Once a given network has been structured for a task, the neural network is trained using a training dataset 1302. Various training frameworks 1304 have been developed to enable hardware acceleration of the training process. For example, Figure 8 The machine learning framework 804 can be configured as a training framework 804. The training framework 804 can access the untrained neural network 1306 and cause the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1308.

[0184] To start the training process, initial weights can be chosen randomly or by using a pre-trained deep belief network. The training cycle is then performed in a supervised or unsupervised manner.

[0185] Supervised learning is a learning method in which training is performed as an intermediate operation, for example, when the training dataset 1302 includes inputs paired with expected outputs for those inputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then propagated back through the system. The training framework 1304 can make adjustments to the weights controlling the untrained neural network 1306. The training framework 1304 can provide tools to monitor the degree to which the untrained neural network 1306 is converging toward a model suitable for generating correct answers based on known input data. The training process repeats as the network's weights are adjusted to refine the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected level of accuracy associated with the trained neural network 1308. The trained neural network 1308 can then be deployed to implement any number of machine learning operations.

[0186] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training data set 1302 will include input data without any associated output data. The untrained neural network 1306 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the entire data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1307 that can perform operations that help reduce the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input data set that deviate from normal data patterns.

[0187] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1302 includes a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1308 to adapt to new data 1312 without forgetting the knowledge instilled into the network during initial training.

[0188] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated by using a distributed network of computing nodes rather than a single computing node.

[0189] Figure 14 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more general processing nodes in the general processing nodes, such as, Figure 9 900. As shown, distributed learning can perform model parallelism 1402, data parallelism 1404, or a combination of model and data parallelism 1404.

[0190] In model parallelization 1402, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelization include the ability to scale to extremely large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers would not fit in the memory of a single computing node. In some instances, model parallelization is particularly useful when performing unsupervised training of large neural networks.

[0191] In data parallelization 1404, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different methods for data parallelization are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transmitting parameters from nodes to parameter servers, updates to the model are transmitted. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0192] Combined model and data parallelism 1406 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where separate GPUs within each node are used to train different parts of the model.

[0193] Distributed training increases overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0194] Example Machine Learning Applications

[0195] Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition and language processing. Computer vision is traditionally one of the most active research areas for machine learning applications. The scope of computer vision applications ranges from reproducing human visual abilities (e.g., recognizing faces) to creating new categories of visual abilities. For example, computer vision applications can be configured to identify sound waves from vibrations caused by visible objects in a video. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously feasible, and enables the use of low-power parallel processors to deploy inference systems.

[0196] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0197] Deep neural networks accelerated by parallel processors enable machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks enables the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0198] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. The automated learning process can utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0199] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 9 Highly parallel general purpose graphics processing unit 900 and Figure 10 The multi-GPU computing system 1000. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for products such as cameras, autonomous robots, and autonomous vehicles.

[0200] Figure 15 An exemplary inference system-on-chip (SOC) 1500 suitable for performing inference using a trained model is shown. The SOC 1500 can integrate processing components including a media processor 1502, a vision processor 1504, a GPGPU 1506, and a multi-core processor 1508. The SOC 1500 can further include on-chip memory 1505 that can implement a shared on-chip data pool accessible to each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1500 can be used as part of the main control system of an autonomous vehicle. In the case where the SOC 1500 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

[0201] During operation, the media processor 1502 and the vision processor 1504 can work together to accelerate computer vision operations. The media processor 1502 can implement low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1505. The vision processor 1504 can then parse the decoded video and perform preliminary processing operations on the frames in preparation for processing the frames of the decoded video using a trained image recognition model. For example, the vision processor 1504 can accelerate the convolution operations of a CNN used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1506.

[0202] The multi-core processor 1508 may include control logic to assist in sequencing and synchronizing data transfers and shared memory operations performed by the media processor 1502 and the vision processor 1504. The multi-core processor 1508 may also serve as an application processor for executing software applications that can utilize the inference computing capabilities of the GPGPU 1506. For example, at least a portion of the navigation and driving logic may be implemented in software executing on the multi-core processor 1508. Such software may issue computational workloads directly to the GPGPU 1506, or the computational workloads may be issued to the multi-core processor 1508, which may offload at least a portion of these operations to the GPGPU 1506.

[0203] GPGPU 1506 may include a compute cluster, such as a low-power configuration of compute clusters 906A-906H within a highly parallel general-purpose graphics processing unit 900. The compute cluster within GPGPU 1506 may support instructions specifically optimized for performing inference computations on trained neural networks. For example, GPGPU 1506 may support instructions for performing low-precision computations such as 8-bit integer vector operations and 4-bit integer vector operations.

[0204] System Overview

[0205] Figure 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device.

[0206] Embodiments of system 1600 may include or be incorporated into the following: a server-based gaming platform, a gaming console (including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console). In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Data processing system 1600 may also include a wearable device, coupled to or integrated into the wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0207] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions that, when executed, perform operations of the system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process a different instruction set 1609, which may include instructions that facilitate the simulation of other instruction sets. The processor core 1607 may also include other processing devices, such as a digital signal processor (DSP).

[0208] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (L23C)) (not shown), which may be shared between the processor cores 1607 using known cache coherence techniques. In addition, a register file 1606 is included in the processor 1602, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1602.

[0209] In some embodiments, processor 1602 is coupled to a processor bus 1610 to transmit communication signals, such as address signals, data signals, or control signals, between processor 1602 and other components in system 1600. In one embodiment, system 1600 utilizes an exemplary "hub" system architecture, including a memory controller hub 1616 and an input / output (I / O) controller hub 1630. Memory controller hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller hub (ICH) 1630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1616 is integrated within the processor.

[0210] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as process memory. In one embodiment, memory device 1620 may operate as system memory for system 1600, storing data 1622 and instructions 1621 for use when one or more processors 1602 execute applications or processes. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in processor 1602 to perform graphics and media operations.

[0211] In some embodiments, ICH 1630 enables peripheral devices to connect to memory devices 1620 and processor 1602 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices, such as a keyboard and mouse 1644 combination. A network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be appreciated that the illustrated system 1600 is exemplary and not limiting, as other types of differently configured data processing systems may also be used. For example, I / O controller hub 1630 may be integrated within one or more processors 1602 , or memory controller hub 1616 and I / O controller hub 1630 may be integrated into a separate external graphics processor (eg, external graphics processor 1612 ).

[0212] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A- 1702N, an integrated memory controller 1714 , and an integrated graphics processor 1708 . Figure 17 Elements in the drawings having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Processor 1700 may include additional cores, up to and including additional core 1702N represented by the dashed box. Each of processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core may also have access to one or more shared cache units 1706.

[0213] Internal cache units 1704A-1704N and shared cache unit 1706 represent a cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache before external memory being classified as 23C. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A-1704N.

[0214] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functions for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 for managing access to various external memory devices (not shown).

[0215] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A-1702N during multithreaded processing. The system agent core 1710 may also include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1702A-1702N and the graphics processor 1708.

[0216] In some embodiments, processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, graphics processor 1708 is coupled to the set of shared cache units 1706 and a system agent core 1710 (including one or more integrated memory controllers 1714). In some embodiments, a display controller 1711 is coupled to graphics processor 1708 for driving graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within graphics processor 1708 or system agent core 1710.

[0217] In some embodiments, a ring-based interconnect 1712 is used to couple the internal components of processor 1700. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, graphics processor 1708 is coupled to ring interconnect 1712 via I / O link 1713.

[0218] Exemplary I / O links 1713 represent at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702A-1702N and the graphics processor 1708 uses the embedded memory module 1718 as a shared last-level cache.

[0219] In some embodiments, processor cores 1702A-1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1702A-1702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1700 can be implemented on one or more chips having the components shown as well as other components or as a SoC integrated circuit having the components shown as well as other components.

[0220] Figure 181 is a block diagram of a graphics processor 1800, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with registers on the graphics processor via a memory-mapped I / O interface and using commands placed into processor memory. In some embodiments, graphics processor 1800 includes a memory interface 1814 for accessing memory. Memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0221] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for displaying and composing one or more overlay planes of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats (e.g., JPEG and Motion JPEG (MJPEG) formats).

[0222] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, GPE 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0223] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1812 includes both programmable and fixed-function elements that perform various tasks within the elements and / or yield execution threads to 3D / media subsystem 1815. While 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 specifically for performing media operations such as video post-processing and image enhancement.

[0224] In some embodiments, media pipeline 1816 includes fixed-function logic units or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of video codec engine 1806. In some embodiments, media pipeline 1816 further includes a thread generation unit for generating threads for execution on 3D / media subsystem 1815. The generated threads perform computations for media operations on one or more graphics execution units included in 3D / media subsystem 1815.

[0225] In some embodiments, 3D / media subsystem 1815 includes logic for executing threads generated by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipelines send thread execution requests to 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and store output data.

[0226] Graphics processing engine

[0227] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 1910 is Figure 18 A version of GPE 1810 is shown in . Figure 19 Elements in FIG. 1 having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. For example, FIG. 1 shows an example of an embodiment of a 3D image of FIG. 1 . Figure 181910. The 3D pipeline 1812 and the media pipeline 1816 of the GPE 1910 are shown in FIG. 1910. The media pipeline 1816 is optional in some embodiments of the GPE 1910 and may not be explicitly included within the GPE 1910. For example, in at least one embodiment, separate media and / or graphics processors are coupled to the GPE 1910.

[0228] In some embodiments, GPE 1910 is coupled to or includes a command streamer 1903, which provides a command stream to 3D pipeline 1812 and / or media pipeline 1816. In some embodiments, command streamer 1903 is coupled to memory, which may be system memory, or one or more of an internal cache and a shared cache. In some embodiments, command streamer 1903 receives commands from memory and sends them to 3D pipeline 1812 and / or media pipeline 1816. Commands are instructions retrieved from a ring buffer that stores commands for 3D pipeline 1812 and media pipeline 1816. In one embodiment, the ring buffer may also include a batch command buffer that stores batches of multiple commands. Commands for 3D pipeline 1812 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 1812 and / or image data and memory objects for media pipeline 1816. The 3D pipeline 1812 and the media pipeline 1816 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 1914 .

[0229] In various embodiments, the 3D pipeline 1812 can execute one or more shader programs, such as vertex shader programs, geometry shader programs, pixel shader programs, fragment shader programs, compute shader programs, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 1914. The graphics core array 1914 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within the graphics core array 1914 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0230] In some embodiments, graphics core array 1914 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units additionally include general purpose logic that can be programmed to perform parallel general purpose computing operations. The general purpose logic can be executed in parallel or in parallel with the graphics processing units. Figure 16 (multiple) processor cores 1607 or Figure 17The general logic within cores 1702A-1702N in the processor performs processing operations in combination.

[0231] Output data generated by threads executing on graphics core array 1914 can be output to memory in unified return buffer (URB) 1918. URB 1918 can store data for multiple threads. In some embodiments, URB 1918 can be used to send data between different threads executing on graphics core array 1914. In some embodiments, URB 1918 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared function logic 1920.

[0232] In some embodiments, graphics core array 1914 is scalable such that the array includes a variable number of graphics cores, each with a variable number of execution units, based on the target power and performance level of GPE 1910. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0233] Graphics core array 1914 is coupled to shared function logic 1920, which includes a number of resources shared between the graphics cores in the graphics core array. Shared functions within shared function logic 1920 are hardware logic units that provide specialized, supplemental functionality to graphics core array 1914. In various embodiments, shared function logic 1920 includes, but is not limited to, samplers 1921, math 1922, and inter-thread communication (ITC) 1923 logic. Additionally, some embodiments implement one or more caches 1925 within shared function logic 1920. Shared functions are implemented in situations where demand for a given specialized function is insufficient for inclusion within graphics core array 1914. Instead, a single instantiation of that specialized function is implemented as an independent entity within shared function logic 1920 and shared among execution resources within graphics core array 1914. The precise set of functionality shared between and included within graphics core array 1914 varies between embodiments.

[0234] Figure 20 is a block diagram of another embodiment of a graphics processor 2000 . Figure 20 Elements in the that have the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0235] In some embodiments, graphics processor 2000 includes ring interconnect 2002, pipeline front end 2004, media engine 2037, and graphics cores 2080A-2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0236] In some embodiments, graphics processor 2000 receives command batches via ring interconnect 2002. Incoming commands are interpreted by command streamer 2003 in pipeline front end 2004. In some embodiments, graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 2080A-2080N. For 3D geometry processing commands, command streamer 2003 provides commands to geometry pipeline 2036. For at least some media processing commands, command streamer 2003 provides commands to video front end 2034, which is coupled to media engine 2037. In some embodiments, media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, geometry pipeline 2036 and media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0237] In some embodiments, the graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes referred to as core slices), each of which has multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A-2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A-2080N, each of which includes a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. Each sub-core in the set of first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and a media / texture sampler 2054A-2054N. Each sub-core in the set of second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and a sampler 2064A-2064N. In some embodiments, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0238] Execution Unit

[0239] Figure 21 Thread execution logic 2100 is shown, comprising an array of processing elements employed in some embodiments of a GPE. Figure 21 Elements in the that have the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0240] In some embodiments, thread execution logic 2100 includes a shader processor 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including a plurality of execution units 2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2108A, 2108B, 2108C, 2108D through 2108N-1 and 2108N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 2100 includes one or more connections to a memory (e.g., system memory or cache memory) through one or more of the instruction cache 2106, the data port 2114, the sampler 2110, and the execution units 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, execution unit arrays 2108A-2108N are scalable to include any number of individual execution units.

[0241] In some embodiments, execution units 2108A-2108N are primarily used to execute shader programs. Shader processor 2102 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2104. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from the graphics pipeline and media pipeline and instantiating the requested threads on one or more execution units in execution units 2108A-2108N. For example, the geometry pipeline (e.g., Figure 21 2136) can dispatch a vertex shader, a tessellation shader, or a geometry shader to the thread execution logic 2100 ( Figure 21 ) for processing. In some embodiments, the thread dispatcher 2104 can also handle runtime thread generation requests from the executed shader program.

[0242] In some embodiments, execution units 2108A-2108N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs from graphics libraries (e.g., Direct3D and OpenGL) to execute with minimal conversion. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute shaders and media shaders). Each of execution units 2108A-2108N is capable of multi-issue single instruction, multiple data (SIMD) execution, and multithreaded operation enables an efficient execution environment in the face of higher-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is issued multiple times per clock to a pipeline capable of integer, single-precision, and double-precision floating-point operations, with SIMD branching capabilities, and capable of logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from one of the shared functions or memory, dependency logic within execution units 2108A-2108N puts the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

[0243] Each execution unit in execution units 2108A-2108N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes used for an instruction. An execution lane is the logic that performs data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, execution units 2108A-2108N support integer and floating point data types.

[0244] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process various elements based on the data size of the element. For example, when a 256-bit wide vector is operated, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector according to four separate 64-bit compact data elements (quad-word (QW) size data elements), eight separate 32-bit compact data elements (double-word (DW) size data elements), sixteen separate 16-bit compact data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0245] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes dedicated texture or media sampling functions to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0246] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 2100 via thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2102 is called to further calculate output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2102 then executes the pixel shader program or fragment shader program provided by the application programming interface (API). To execute the shader program, the shader processor 2102 dispatches a thread to an execution unit (e.g., 2108A) via the thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses the texture sampling logic in the sampler 2110 to access texture data stored in a texture map in memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0247] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0248] Figure 222 is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2200 described and illustrated are macroinstructions because they are instructions provided to the execution unit, rather than micro-operations generated by instruction decoding once the instruction is processed.

[0249] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 2210. Depending on the selected instruction, instruction options, and the number of operands, a 64-bit compressed instruction format 2230 may be used for certain instructions. The native 128-bit instruction format 2210 provides access to all instruction options, while some options and operations are restricted to the 64-bit instruction format 2230. The native instructions available in the 64-bit instruction format 2230 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 2213. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 2210.

[0250] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., deployment). For instructions in the 128-bit instruction format 2210, the exec-size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the exec-size field 2216 is not available for the 64-bit compressed instruction format 2230.

[0251] Some execution unit instructions have up to three operands, including two source operands src0 2220 and src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0252] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0253] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226 that specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0254] In one embodiment, the addressing mode portion of the access / addressing mode field 2226 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0255] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 2242 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares the five most significant bits (MSBs), where the move (mov) instruction is in the form of 0000xxxxb, while the logic instruction is in the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data lanes. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations such as dot product calculations on vector operands.

[0256] Graphics pipeline

[0257] Figure 23 is a block diagram of another embodiment of a graphics processor 2300 . Figure 23 Elements in the that have the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0258] In some embodiments, graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 2300 via ring interconnect 2302. In some embodiments, ring interconnect 2302 couples graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2302 are interpreted by command streamer 2303, which provides instructions to individual components of graphics pipeline 2320 or media pipeline 2330.

[0259] In some embodiments, command streamer 2303 directs the operation of vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2303. In some embodiments, vertex fetcher 2305 provides vertex data to vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A-2352B via thread dispatcher 2331.

[0260] In some embodiments, execution units 2352A-2352B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2352A-2352B have an attached L1 cache 2351, which is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0261] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 2311 configures the tessellation operation. The programmable domain shader 2317 provides back-end evaluation of the tessellation output. The tessellation 2313 operates at the direction of the hull shader 2311 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 2311, the tessellation 2313, and the domain shader 2317) can be bypassed.

[0262] In some embodiments, the complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A-2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on the entire geometric object, rather than on vertices or image blocks of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0263] Before rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 2373 in the render output pipeline 2370 dispatches a pixel shader to transform the geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, the application can bypass the rasterizer and depth test component 2373 and access the unrasterized vertex data via the stream output unit 2323.

[0264] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and message passing between the main components of the processor. In some embodiments, the execution units 2352A-2352B and the associated cache(s) 2351, texture and media sampler 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory access and communicate with the processor's rendering output pipeline components. In some embodiments, the sampler 2354, cache 2351, cache 2358, and execution units 2352A-2352B each have a separate memory access path.

[0265] In some embodiments, the rendering output pipeline 2370 includes a rasterizer and a depth test component 2373, which transforms vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. In some embodiments, associated rendering caches 2378 and depth caches 2379 are also available. A pixel operation component 2377 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 2341, or are replaced by a display controller 2343 using an overlay display plane when displayed. In some embodiments, a shared L3 cache 2375 can be used for all graphics components, thereby allowing data to be shared without using main system memory.

[0266] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front end 2334 processes media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes thread generation functionality for generating threads for dispatching to the thread execution logic 2350 via the thread dispatcher 2331.

[0267] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via a ring interconnect 2302 or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0268] In some embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on multiple graphics programming interfaces and media programming interfaces, and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a specific graphics library or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft. In some embodiments, the combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If mapping can be performed from the pipeline of a future API with a compatible 3D pipeline to the pipeline of the graphics processor, future API will also be supported.

[0269] Graphics pipeline programming

[0270] Figure 24A is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. Figure 24B is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment. Figure 24AThe solid-line boxes in show components that are typically included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 24A The exemplary graphics processor command format 2400 includes a data field for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and associated data for the command 2406. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0271] In some embodiments, client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to regulate further processing of the command and route the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 2404 and, if present, sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned to multiples of double words.

[0272] Figure 24B The flowchart in FIG. 24 illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these specific commands or this command sequence. Furthermore, commands can be issued as batches in a command sequence so that the graphics processor will process the command sequence at least partially concurrently.

[0273] In some embodiments, graphics processor command sequence 2410 may begin with a pipeline flush command 2412 to cause any active graphics pipeline to complete its currently pending commands. In some embodiments, 3D pipeline 2422 and media pipeline 2424 do not operate concurrently. A pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the graphics processor's command parser will suspend command processing until the active graphics engine completes pending operations and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the render cache may be flushed to memory. In some embodiments, pipeline flush command 2412 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0274] In some embodiments, a pipeline select command 2413 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 2413 is only required once within an execution context before issuing a pipeline command, unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 2412 is required immediately before switching pipelines via a pipeline select command 2413.

[0275] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and are used to program 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a command batch.

[0276] In some embodiments, commands for return buffer state 2416 are used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer state 2416 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0277] The remaining commands in the command sequence differ based on the active pipeline for operation.Based on pipeline determination 2420 , the command sequence is tailored for either 3D pipeline 2422 starting at 3D pipeline state 2430 or media pipeline 2424 starting at media pipeline state 2440 .

[0278] The commands used to configure the 3D pipeline state 2430 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API being used. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements if they will not be used.

[0279] In some embodiments, the 3D primitive 2432 command is used to submit 3D primitives for processing by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2432 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2432 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 2432 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches a shader execution thread to a graphics processor execution unit.

[0280] In some embodiments, the 3D pipeline 2422 is triggered via an execute 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing on 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for these operations.

[0281] In some embodiments, the graphics processor command sequence 2410 follows the media pipeline 2424 path when performing media operations. Typically, the specific purpose and programming of the media pipeline 2424 depends on the media operation or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0282] In some embodiments, media pipeline 2424 is configured in a similar manner to 3D pipeline 2422. A set of commands for configuring media pipeline state 2440 is dispatched or placed in a command queue before media object commands 2442. In some embodiments, commands for media pipeline state 2440 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding logic and video encoding logic within the media pipeline, such as encoding formats or decoding formats. In some embodiments, commands for media pipeline state 2440 also support the use of one or more pointers to "indirect" state elements that contain a set of state settings.

[0283] In some embodiments, media object command 2442 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing the video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2442. Once the pipeline state is configured and media object command 2442 is queued, media pipeline 2424 is triggered via execute command 2444 or an equivalent execute event (e.g., a register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0284] Graphics software architecture

[0285] Figure 25 An exemplary graphics software architecture for data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. Graphics application 2510 and operating system 2520 each execute in system memory 2550 of the data processing system.

[0286] In some embodiments, the 3D graphics application 2510 includes one or more shader programs that include shader instructions 2512. The shader language instructions can be in the form of a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in the form of a machine language suitable for execution by the general-purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0287] In some embodiments, operating system 2520 is from Microsoft Corporation Operating system, a proprietary UNIX-like operating system or an open source UNIX-like operating system of a variant of the Linux kernel. Operating system 2520 can support graphics API 2522, for example, Direct3D API, OpenGL API or Vulkan API. When using Direct3D API, operating system 2520 uses front-end shader compiler 2525 to compile any shader instruction 2512 in HLSL form into a lower-level shader language. Compilation can be just-in-time (JIT) compilation, or application can perform shader precompilation. In some embodiments, high-level shader is compiled into low-level shader during compilation of 3D graphics application 2510. In some embodiments, shader instruction 2512 is provided in an intermediate form, for example, a version of the standard portable intermediate representation (SPIR) used by Vulkan API.

[0288] In some embodiments, the user-mode graphics driver 2526 includes a backend shader compiler 2527 for converting shader instructions 2512 into hardware-specific representations. When using the OpenGL API, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0289] IP core implementation

[0290] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions that represent various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such representations, referred to as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities that load the hardware model onto a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured such that the circuit performs the operations described in association with any of the embodiments described herein.

[0291] Figure 262 is a block diagram illustrating an IP core development system 2600 that can be used to manufacture an integrated circuit for performing operations according to an embodiment. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SoC integrated circuits). A design facility 2630 can generate a software simulation 2610 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 2610 can be used to design, test, and verify the behavior of the IP core using a simulation model 2612. The simulation model 2612 can include functional simulation, behavioral simulation, and / or timing simulation. A register transfer level (RTL) design 2615 can then be created or synthesized based on the simulation model 2612. The RTL design 2615 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers (including associated logic executed using the modeled digital signals). In addition to the RTL design 2615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0292] The RTL design 2615 or equivalent can be further synthesized by the design facility into a hardware model 2620, which can be in the form of a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a third-party manufacturing facility 2665 using non-volatile storage 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design can be transmitted via a wired connection 2650 or a wireless connection 2660 (e.g., via the Internet). The manufacturing facility 2665 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0293] Exemplary System-on-Chip Integrated Circuit

[0294] Figures 27-29 An exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0295] Figure 272 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2700 that can be fabricated using one or more IP cores according to an embodiment. Exemplary integrated circuit 2700 includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be modular IP cores from the same or multiple different design facilities. Integrated circuit 2700 includes peripheral logic or bus logic, including a USB controller 2727, a UART controller 2730, an SPI / SDIO controller 2735, and an I2S / I2C controller 2740. Additionally, the integrated circuit may include a display device 2745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2750 and a Mobile Industry Processor Interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760, which includes flash memory and a flash memory controller. A memory interface may be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770 .

[0296] Figure 28 is a block diagram illustrating an exemplary graphics processor 2810 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 2810 may be Figure 27 The graphics processor 2810 includes a vertex processor 2805 and one or more fragment processors 2815A-2815N (e.g., 2815A, 2815B, 2815C, 2815D through 2815N-1 and 2815N). The graphics processor 2810 can execute different shader programs via separate logic, such that the vertex processor 2805 is optimized to perform operations for a vertex shader program, while the one or more fragment processors 2815A-2815N perform fragment (e.g., pixel) shading operations for a fragment shader program or pixel shader program. The vertex processor 2805 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 2815A-2815N use the primitives and vertex data generated by the vertex processor 2805 to generate a frame buffer for display on a display device. In one embodiment, the fragment processor(s) 2815A-2815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct3D API.

[0297] The graphics processor 2810 additionally includes one or more memory management units (MMUs) 2820A-2820B, cache(s) 2825A-2825B, and circuit interconnect(s) 2830A-2830B. The one or more MMUs 2820A-2820B provide virtual-to-physical address mapping for the graphics processor 2810 (including for the vertex processor 2805 and / or fragment processor(s) 2815A-2815N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2825A-2825B. In one embodiment, the one or more MMUs 2820A-2820B may synchronize with other MMUs within the system, including with Figure 27 One or more MMUs associated with one or more application processors 2705, graphics processor 2715, and / or video processor 2720 enable each processor 2705, 2710, 2715, 2720 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 2830A-2830B enable the graphics processor 2810 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0298] Figure 29 is a block diagram illustrating an additional exemplary graphics processor 2910 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 2910 may be Figure 27 A variant of the graphics processor 2710. The graphics processor 2910 includes Figure 28 One or more MMUs 2820A-2820B, cache(s) 2825A-2825B, and circuit interconnect(s) 2830A-2830B in graphics processor 2810.

[0299] The graphics processor 2910 includes one or more shader cores 2915A-2915N (e.g., 2915A, 2915B, 2915C, 2915D, 2915E, 2915F through 2715N-1 and 2715N) that provide a unified shader core architecture in which a single core or core type can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. In addition, the graphics processor 2910 includes an inter-core task manager 2905 and a tile stitching unit 2918, wherein the inter-core task manager 2905 acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2915A-2915N, and the tile stitching unit 2918 is used to accelerate tile stitching operations for tile-based rendering, where the rendering operations of the scene are subdivided in image space, for example, to exploit local spatial consistency within the scene or to optimize the use of internal caches.

[0300] The following examples relate to further embodiments. Example 1 is an apparatus for providing an active artificial intelligence (AI) agent, comprising: at least one database for storing physical interaction data; and a computing cluster coupled to the at least one database. The computing cluster is configured to automatically obtain the physical interaction data from a data collection module without manual interaction, store the physical interaction data in the at least one database, and automatically train different sets of machine learning program units to simulate physical interactions using each individual program unit having a different model based on the applied physical interaction data.

[0301] In Example 2, the subject matter of Example 1 can optionally include the computing cluster being used to train the master program unit by jointly approximating and modeling the behavior of the entire collection of each individual program unit.

[0302] In Example 3, the subject matter of any of Examples 1-2 can optionally include the computing cluster being operable to apply inputs including visual inputs to the master program unit to generate predicted physical interactions based on training of the individual program units and the master program unit.

[0303] In Example 4, the subject matter of any of Examples 1-3 can optionally include the predicted physical interactions functioning like a biologically active AI agent for robotic applications.

[0304] In Example 5, the subject matter of any one of Examples 1-4 can optionally include that the program element comprises a Bayesian program element.

[0305] In Example 6, the subject matter of any of Examples 1-2 can optionally include each individual Bayesian program unit having a different deep neural network (DNN) model based on the applied physical interaction data.

[0306] Example 7 is a method for providing an active artificial intelligence agent, comprising: automatically obtaining physical interaction data from a data collection module using a training framework without manual interaction; storing the physical interaction data in at least one database; and automatically training different sets of machine learning program units using the training framework with the physical interaction data to simulate physical interactions using each individual program unit with a different model based on the applied physical interaction data.

[0307] In Example 8, the subject matter of Example 7 can optionally include training the master program unit by jointly approximating and modeling the behavior of the entire set of each individual program unit.

[0308] In Example 9, the subject matter of any of Examples 7-8 can optionally include applying the input to the master program unit to generate the predicted physical interaction based on the training of the individual program units and the master program unit.

[0309] In Example 10, the subject matter of any of Examples 7-9 can optionally include the predicted physical interactions functioning like a biologically active AI agent for robotic applications.

[0310] In Example 11, the subject matter of any of Examples 7-10 can optionally include that the program element comprises a Bayesian program element.

[0311] In Example 12, the subject matter of any of Examples 7-11 can optionally include each individual Bayesian program unit having a different deep neural network (DNN) model based on the applied physical interaction data.

[0312] Example 13 is an apparatus comprising: a unit for automatically obtaining physical interaction data from a data collection module using a training framework without manual interaction; a unit for storing the physical interaction data in at least one database; and a unit for automatically training different sets of machine learning program units using the training framework with the physical interaction data to simulate physical interactions using each individual program unit having a different model based on the applied physical interaction data.

[0313] In Example 14, the subject matter of Example 13 can optionally include means for training the master program unit by jointly approximating and modeling the behavior of the entire set of each individual program unit.

[0314] In Example 15, the subject matter of any of Examples 13-14 can optionally include means for applying input to the master program unit to generate predicted physical interactions based on training of the individual program units and the master program unit.

[0315] In Example 16, the subject matter of any of Examples 13-15 can optionally include the predicted physical interactions functioning like a biologically active AI agent for robotic applications.

[0316] In Example 17, the subject matter of any of Examples 13-16 can optionally include that the program element comprises a Bayesian program element.

[0317] In Example 18, the subject matter of any of Examples 13-17 can optionally include each individual Bayesian program unit having a different deep neural network (DNN) model based on the applied physical interaction data.

[0318] Example 19 is a system comprising: a memory for storing instructions and physical interaction data; and multiple cores for executing instructions to perform the following operations: automatically obtain physical interaction data from a data collection module without manual interaction, store the physical interaction data in the memory, and automatically train different sets of machine learning program units to simulate physical interactions using each individual program unit with a different model based on the applied physical interaction data.

[0319] In Example 20, the subject matter of Example 19 can optionally include the plurality of cores being used to train the master program unit by jointly approximating and modeling the behavior of the entire set of each individual program unit.

[0320] In Example 21, the subject matter of any of Examples 19-20 can optionally include a plurality of cores for applying inputs including visual inputs to the master program unit to generate predicted physical interactions based on training of the individual program units and the master program unit.

[0321] References to "one embodiment," "an embodiment," "example embodiment," "various embodiments," etc., indicate that the embodiment(s) so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, some embodiments may have some, all, or none of the features described for other embodiments.

[0322] The foregoing description and drawings are to be regarded as illustrative rather than restrictive. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. An apparatus for providing an active artificial intelligence (AI) agent, comprising: at least one database for storing physical interaction data; as well as a computing cluster coupled to the at least one database, the computing cluster being used to: automatically obtain physical interaction data from a data collection module without manual interaction, wherein weak annotations are first automatically generated based on clustering and then refined during training without manual interaction; store the physical interaction data in the at least one database; automatically train different sets of machine learning program units to simulate different physical interactions using each individual program unit having a different model based on the applied physical interaction data; train a master program unit by jointly approximating and modeling the behavior of the entire set of each individual program unit; and apply input including visual input to the master program unit to generate predicted physical interactions based on the training of the individual program units and the master program unit, Wherein, the main program unit is a main Bayesian program unit, And wherein physical interaction data corresponding to the different physical interactions are stored in the at least one database, and the data collection module is associated with different models of the individual program units.

2. The device according to claim 1, wherein: The predicted physical interactions function like biological active AI agents for robotic applications.

3. The device according to claim 1, wherein: The machine learning program unit includes a Bayesian program unit.

4. The device as claimed in claim 3, wherein: Each of the Bayesian program units has a different deep neural network (DNN) model based on the applied physical interaction data.

5. A method for providing an active artificial intelligence agent, comprising: The physical interaction data is automatically obtained from the data collection module using a training framework without manual interaction, where weak annotations are first automatically generated based on clustering and then refined during training without manual interaction; storing the physical interaction data in at least one database; automatically training different sets of machine learning program units using the training framework with the physical interaction data to simulate different physical interactions using each individual program unit having a different model based on the applied physical interaction data; training a master program unit by jointly approximating and modeling the behavior of the entire collection of each individual program unit; and applying inputs including visual inputs to the master programming unit to generate predicted physical interactions based on training of the individual programming units and the master programming unit, Wherein, the main program unit is a main Bayesian program unit, And wherein physical interaction data corresponding to the different physical interactions are stored in the at least one database, and the data collection module is associated with different models of the individual program units.

6. The method of claim 5, wherein: The predicted physical interactions function like biological active AI agents for robotic applications.

7. The method of claim 6, wherein: The machine learning program unit includes a Bayesian program unit.

8. The method of claim 7, wherein: Each of the Bayesian program units has a different deep neural network (DNN) model based on the applied physical interaction data.

9. An apparatus comprising: a unit for automatically obtaining physical interaction data from a data collection module using a training framework without manual interaction, wherein weak annotations are first automatically generated based on clustering and then refined during training without manual interaction; means for storing said physical interaction data in at least one database; for automatically training different sets of machine learning program units using the training framework with the physical interaction data to simulate different physical interaction units using each individual program unit having a different model based on the applied physical interaction data; means for training a master program unit by jointly approximating and modeling the behavior of the entire collection of each individual program unit; and means for applying inputs including visual inputs to the master programming unit to generate predicted physical interactions based on training of the individual programming units and the master programming unit, Wherein, the main program unit is a main Bayesian program unit, And wherein physical interaction data corresponding to the different physical interactions are stored in the at least one database, and the data collection module is associated with different models of the individual program units.

10. The device of claim 9, wherein: The predicted physical interactions function like biological active AI agents for robotic applications.

11. The device of claim 10, wherein: The machine learning program unit includes a Bayesian program unit.

12. The device of claim 11, wherein: Each of the Bayesian program units has a different deep neural network (DNN) model based on the applied physical interaction data.

13. A system comprising: Memory, which is used to store instructions and physical interaction data; as well as a plurality of cores for executing the instructions to: automatically obtain physical interaction data from a data collection module without manual interaction, wherein weak annotations are first automatically generated based on clustering and then refined during training without manual interaction; store the physical interaction data in the memory; automatically train different sets of machine learning program units to simulate different physical interactions with each individual program unit having a different model based on the applied physical interaction data; train a master program unit by jointly approximating and modeling the behavior of the entire set of each individual program unit; and apply inputs including visual inputs to the master program unit to generate predicted physical interactions based on the training of the individual program units and the master program unit, Wherein, the main program unit is a main Bayesian program unit, And wherein physical interaction data corresponding to the different physical interactions are stored in the memory, and the data collection module is associated with different models of the individual program units.

14. A machine-readable medium having instructions stored thereon, which, when executed by a machine, cause the machine to perform the method of any one of claims 5 to 8.

15. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 5 to 8.

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