Semiconductor device with integrated backside power grid and related integrated circuit and manufacturing method

Abstract

An embodiment of the present invention relates to a semiconductor device with an integrated backside power grid and a related integrated circuit and manufacturing method thereof, wherein the semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive track, and a conductive structure. The dielectric region is located on the substrate. The plurality of conductive regions are located on the dielectric region. The first conductive track is located in the dielectric region and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate the substrate and is formed below the first conductive track. The conductive structure is electrically connected to the first conductive track.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device with integrated backside power grid and a related integrated circuit and manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size (e.g., the smallest component or line that can be built using a process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0003] An embodiment of the present invention relates to a semiconductor device, comprising: a substrate; a dielectric region located on the substrate; a plurality of conductive regions located on the dielectric region; a first conductive track located in the dielectric region, the first conductive track being electrically connected to a first conductive region of the plurality of conductive regions; and a conductive structure penetrating the substrate and formed below the first conductive track, the conductive structure being electrically connected to the first conductive track.

[0004] An embodiment of the present invention relates to an integrated circuit, which includes: a substrate; a dielectric region located on the substrate; a first fin field effect transistor, which includes a first source region, a first gate region and a first drain region located on the dielectric region; a conductive track located in the dielectric region, the conductive track being electrically connected to a first terminal region selected from among the first source region, the first gate region and the first drain region; and a conductive structure that penetrates the substrate and is formed below the conductive track, the conductive structure being electrically connected to the conductive track.

[0005] One embodiment of the present invention relates to a method for forming a non-planar semiconductor device, which includes: forming a fin-like structure protruding from the front side of a substrate of the non-planar semiconductor device; forming a dielectric region on the front side of the substrate, wherein the dielectric region includes a conductive track buried in the dielectric region and parallel to the fin-like structure; forming a first opening in the dielectric region to expose the conductive track; forming a plurality of conductive regions on the dielectric region, wherein one of the plurality of conductive regions contacts the conductive track through the first opening; etching the substrate from the back side of the substrate to form a second opening to expose the conductive track; and filling a first conductive material into the second opening to form a through-substrate via in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A An isometric view of an exemplary semiconductor device according to some embodiments is shown.

[0008] Figure 1B An isometric view is shown of a first configuration and arrangement of dielectric regions within an exemplary semiconductor device in accordance with some embodiments.

[0009] Figure 1C An isometric view is shown of a second configuration and arrangement of dielectric regions within an exemplary semiconductor device in accordance with some embodiments.

[0010] Figure 2A and 2B Isometric views of a first exemplary integrated circuit and a second exemplary integrated circuit are respectively depicted, according to some embodiments.

[0011] Figure 3 is an isometric view of a partially fabricated semiconductor structure according to some embodiments.

[0012] Figure 4 is an isometric view of a partially fabricated semiconductor structure after forming a gap filler in the opening and partially removing a seed layer structure in accordance with some embodiments.

[0013] Figure 5 is an isometric view of a partially fabricated semiconductor structure after forming conductive tracks and interlayer dielectric filler, according to some embodiments.

[0014] Figure 6 is an isometric view of a partially fabricated semiconductor structure after etching back the ILD layer and forming a polysilicon gate over the fin, according to some embodiments.

[0015] Figure 7 is an isometric view of the partially fabricated semiconductor structure after partially etching opening trenches in the ILD to expose portions of the conductive tracks, according to some embodiments.

[0016] Figure 8 is an isometric view of a partially fabricated semiconductor structure after forming source / drain terminals, according to some embodiments.

[0017] Fig. 9 is an isometric view of a partially fabricated semiconductor structure after forming shallow trench isolation structures in accordance with some embodiments.

[0018] Fig.10is an isometric view of a partially fabricated semiconductor structure after a gate replacement procedure in accordance with some embodiments.

[0019] Fig.11 is an isometric view of a partially fabricated semiconductor structure after forming metal source / drain contacts, according to some embodiments.

[0020] Fig.12 is an isometric view of a partially fabricated semiconductor structure after depositing metal gate material and forming source / drain contacts, according to some embodiments.

[0021] Fig.13 is an isometric view of a partially fabricated semiconductor structure including BEOL metal conductive lines and self-aligned vias after deposition of metal gate material(s) and formation of source / drain contacts, according to some embodiments.

[0022] Fig.14 is an isometric view of a partially fabricated semiconductor structure after forming BEOL metal conductors and self-aligned vias, according to some embodiments.

[0023] Fig.15 is an isometric view of a partially fabricated semiconductor structure after integration of a backside power grid, according to some embodiments.

[0024] Fig.16 is a flow chart of an exemplary method for forming a non-planar semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for implementing the different features of the provided theme. The following describes the specific examples of components and arrangements to simplify this disclosure. Of course, these are only examples and are not intended to be limiting. For example, the first component in the following description is formed above or on the second component and may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not directly contact. In addition, this disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or component to another element or components as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0027] The present disclosure describes exemplary semiconductor devices (e.g., fin field effect transistors (finFETs)) having one or more conductive tracks that may be located on a semiconductor substrate and electrically connected to one or more conductive structures penetrating the semiconductor substrate, and describes exemplary methods for manufacturing these semiconductor devices. In some scenarios, the one or more conductive tracks may be electrically connected to source, gate, and / or drain regions of these semiconductor devices, and the one or more conductive tracks may be used to connect the source, gate, and / or drain regions of these semiconductor devices to one or more power grids located below the semiconductor substrate through the one or more conductive structures. In some scenarios, one or more first metal wires, each extending in a first direction, may be located above and electrically connected to the source, gate, and / or drain regions of these semiconductor devices, and one or more second metal wires, each extending in a second direction different from the first direction, may be located above the one or more first metal wires and electrically connected to the one or more first metal wires through one or more conductive through vias (e.g., one or more self-aligned vias).

[0028] Figure 1A An isometric view of an exemplary semiconductor device according to one embodiment of the present disclosure is shown. Figure 1A In the embodiment shown in FIG. 1 , the semiconductor device 100 includes a substrate structure layer 101 , a transistor structure layer 103 , a backside structure layer 105 , and a conductive interconnect structure layer 107 , which are placed on top of each other.

[0029] In the present embodiment, the substrate structure layer 101 includes a substrate 102 and a conductive structure 118, wherein the conductive structure 118 penetrates the substrate 102 to provide an electrical connection between a first side and a second side (which is opposite to the first side) of the substrate 102. For illustration purposes, the first side of the substrate 102 on which the transistor structure layer 103 is formed is referred to herein as the front side of the substrate 102 or the front side of the semiconductor device 100; the second side of the substrate 102 on which the backside structure layer 105 is placed is referred to herein as the back side of the substrate 102 or the back side of the semiconductor device 100.

[0030] As will be described in more detail below, a portion of the substrate 102 may be removed during fabrication through a patterning process (e.g., dry etching or wet etching) to expose the transistor structure layer 103. Thereafter, a conductive material may fill the portion of the substrate 102 to form a conductive structure 118. In some embodiments, the conductive structure 118 may include a conductive through-substrate via (TSV), such as a through-silicon via (TSV), and / or a trench-type through-substrate via (e.g., a through-silicon trench (TST)).

[0031] exist Figure 1A In the embodiment illustrated in , a transistor structure layer 103 disposed on a substrate structure layer 101 includes a fin structure 104, a plurality of conductive regions, a dielectric region 112, and a plurality of conductive rails 114 and 116. In some scenarios, the conductive region may include a plurality of terminal regions, such as a source region 106, a gate region 108, and a drain region 110. The fin structure 104, the source region 106, the gate region 108, and the drain region 110 may be configured to form a fin field effect transistor (finFET). However, those skilled in the relevant art will recognize that, without departing from the spirit and scope of the present disclosure, a finFET may include other regions, such as a dielectric region (or isolation region) 120 to provide some examples. In addition, as Figure 1A The configuration and arrangement of the fin structure 104, source region 106, gate region 108, and drain region 110 shown in the figure are for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements of the fin structure 104, source region 106, gate region 108, and drain region 110 are possible without departing from the spirit and scope of the present disclosure.

[0032] For illustrative purposes, the following description describes the semiconductor device 100 according to finFETs. Those skilled in the relevant art will recognize that the semiconductor device 100 can be other non-planar semiconductor devices as well as planar semiconductor devices without departing from the spirit and scope of the present disclosure.

[0033] like Figure 1A As shown in FIG. 1 , a fin structure 104, a source region 106, a gate region 108, a drain region 110, a dielectric region 112 (also referred to as an interlayer dielectric (ILD) region), and conductive tracks 114 and 116 are located on a substrate 102. The fin structure 104 protrudes from the substrate 102 and the dielectric region 112 and passes through the gate region 108 between the source region 106 and the drain region 110. Figure 1A The finFET shown in FIG. 1 includes one fin structure 104 , but persons skilled in the relevant art will recognize that a finFET may include more than one fin structure without departing from the spirit and scope of the present disclosure.

[0034] The source region 106, the gate region 108, and the drain region 110 are located on the dielectric region 112, wherein the fin structure 104 traverses through the dielectric region 112 onto the semiconductor substrate 102. Figure 1A Not shown, but as will be appreciated by those skilled in the relevant art, other dielectric regions may be located between the semiconductor substrate 102 and the dielectric region 112 without departing from the spirit and scope of the present disclosure.

[0035] Conductive tracks 114 and 116 are located within dielectric region 112 and traverse semiconductor substrate 102 between source region 106 and drain region 110. Conductive track 114 faces a first sidewall of fin structure 104, and conductive track 116 faces a second sidewall of fin structure 104. In some scenarios, conductive tracks 114 and 116 are positioned parallel to fin structure 104. However, one skilled in the relevant art will recognize that conductive tracks 114 and 116 may be positioned perpendicular to fin structure 104 without departing from the spirit and scope of the present disclosure. In such scenarios, conductive tracks 114 and 116 traverse through fin structure 104. Additionally, the number of conductive tracks may vary depending on the application without departing from the spirit and scope of the present disclosure. For example, in some scenarios, semiconductor device 100 may have one or more than two conductive tracks.

[0036] In some embodiments, dielectric region 112 may be arranged to isolate source region 106, gate region 108, and / or drain region 110 from conductive rails 114 / 116 to prevent electrical connection between source region 106, gate region 108, and / or drain region 110 and conductive rails 114 / 116. Figure 1B , which illustrates an isometric view of a first configuration of dielectric regions within an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. Figure 1B The conductive track 114.1 and the dielectric region 112.1 shown in FIG. 1 may represent the conductive track 114.1 and the dielectric region 112.1 as described above. Figure 1A An exemplary embodiment of the conductive tracks 114 / 116 and the dielectric region 112 described in FIG. Figure 1B The conductive area 105.1 shown in FIG. Figure 1A 106, gate region 108 and / or drain region 110 as described in the exemplary embodiments of the present invention. Figure 1B The substrate 102.1 and the conductive structure 118.1 shown in FIG. Figure 1A An exemplary embodiment of the substrate 102 and the conductive structure 118 described in Figure 1B In the exemplary embodiment depicted in , the dielectric region 112 . 1 is arranged to prevent electrical connection between the conductive track 114 . 1 and the conductive region 105 . 1 .

[0037] In some embodiments, Figure 1AThe source region 106, the gate region 108 and / or the drain region 110 shown in FIG. 1 may be electrically connected to the conductive rails 114 / 116 to provide electrical connections between the source region 106, the gate region 108 and / or the drain region 110 and the conductive rails 114 / 116. Figure 1C , which illustrates an isometric view of a second configuration of dielectric regions within an exemplary semiconductor device according to an exemplary embodiment of the present disclosure. Figure 1C The conductive track 114.2 and the dielectric region 112.2 shown in FIG. Figure 1A 1 and 12. Figure 1C The conductive area 105.2 shown in FIG. Figure 1A 106, gate region 108 and / or drain region 110 as described in the exemplary embodiments of FIG. Figure 1C The substrate 102.2 and the conductive structure 118.2 shown in FIG. 1 may represent the structure of the substrate 102.2 and the conductive structure 118.2 as described above. Figure 1A An exemplary embodiment of the substrate 102 and the conductive structure 118 described in Figure 1C In the exemplary embodiment depicted in FIG, the conductive track 114.2 may be electrically connected to the conductive region 105.2 to provide an electrical connection between the conductive track 114.2 and the conductive region 105.2. The conductive track 114.2 is sufficiently exposed within the dielectric region 112.2 to electrically connect to the conductive region 105.2 to provide an electrical connection.

[0038] As will be described in more detail below, a portion of the dielectric region 112.2 may be removed during fabrication by a patterning process (such as dry etching or wet etching to provide some examples) to expose that portion of the dielectric region 112.2. Thereafter, the conductive region 105.2 may be deposited onto that portion of the dielectric region 112.2 by a deposition in which a material is grown, coated, or otherwise transferred. In an exemplary embodiment, as shown in FIG. Figure 1C The height of the conductive region 105.2 (labeled as H2) shown in FIG. 1 may be greater than Figure 1B 1 (labeled H1). In the exemplary embodiment, this difference in height between conductive region 105.1 and conductive region 105.2 results from removing enough of dielectric region 112.2 to expose conductive track 114.2 to allow electrical connection between conductive track 114.2 and conductive region 105.2.

[0039] Reference again Figure 1A, at least one of the conductive tracks 114 and 116 may be electrically and / or mechanically connected to other conductive tracks of one or more other finFETs to form an interconnected network of conductive tracks. The interconnected network of conductive tracks may be used to electrically connect various gate, source, and / or drain regions of these finFETs to form one or more integrated circuits. As will be appreciated by those skilled in the relevant art, these integrated circuits may include basic logic gates (e.g., AND gates, OR gates, XOR gates, XNOR gates, or NOT gates to provide some examples) as well as other more complex logic circuits without departing from the spirit and scope of the present disclosure. The interconnected network of conductive tracks allows these electrical connections between the various gate, source, and / or drain regions of these finFETs to be made without traversing through conventional metal layers that may conventionally be used to route signals. Thus, the interconnected network of conductive tracks reduces the area required to form one or more integrated circuits when compared to using conventional metal layers to form these electrical connections between the various source and / or drain regions of these finFETs.

[0040] In some embodiments, a portion of the substrate 102 may be removed during fabrication through a patterning process (e.g., dry etching or wet etching to provide some examples) to expose the conductive tracks 114 and 116. Thereafter, a conductive material may fill the portion of the substrate 102 to form a conductive structure 118. Since the conductive tracks 114 / 116 have sufficient length (e.g., along a direction parallel to the fin structure 104), the conductive structure 118 may be easily aligned with the conductive tracks 114 / 116. In some embodiments, the conductive structure 118 may also be formed under the fin structure 104 so that the fin structure 104 contacts the conductive structure 118.

[0041] exist Figure 1A 1 , a backside structure layer 105 disposed below the substrate structure layer 101 includes a conductor 122. The conductor 122 is located on the backside of the substrate 102 and is electrically connected to the conductive structure 118. In some embodiments, the conductive structure 118 in the substrate structure layer 101 below the conductive tracks 114 and 116 formed in the transistor structure layer 103 may be electrically connected to at least one of the conductive tracks 114 and 116 to provide an electrical connection between the front side and the back side of the substrate 102. Thus, the conductive structure 118 may provide an electrical connection between the conductor 122 located on the backside of the substrate 102 and the conductive tracks 114 and 116 located on the front side of the substrate 102. In some embodiments, the conductor 122 may be a power grid conductor arranged to transmit power for the semiconductor device 100. Thus, the semiconductor device 100 may be powered by a backside power supply, thereby saving a certain amount of routing resources used on the front side of the semiconductor device 100.

[0042] exist Figure 1A1 , the conductive interconnect structure layer 107 may include a back-end-of-line (BEOL) interconnect structure formed on the front side of the semiconductor device 100. The conductive interconnect structure layer 107 may include a plurality of metal wires 124, 126, and 128 and a plurality of dielectric layers 125, 127, and 130. The metal wires 124 and 126 are located in the dielectric region (or isolation region) 120 and extend in a first direction, and the metal wire 128 is located in the dielectric layer 130 and extends in a second direction different from the first direction. By way of example and not limitation, the first direction in which the metal wire 124 extends may be parallel to the fin structure 104, and may be perpendicular to the second direction in which the metal wire 128 extends. However, those skilled in the relevant art will recognize that the metal wire 124 may extend in a direction perpendicular to the fin structure 104 without departing from the spirit and scope of the present disclosure.

[0043] Dielectric layers 125 and 127 are formed on metal wires 124 and 126, respectively. In some scenarios, a conductive through via 132 may be formed in dielectric layer 125 and aligned with metal wire 124 to provide an electrical connection between metal wire 128 and metal wire 124. By way of example and not limitation, metal wire 124 may be formed by depositing (several) conductive materials into a first trench of dielectric region 120, and dielectric layer 125 may be deposited over metal wire 124 in the first trench. Next, dielectric layer 130 is deposited over dielectric region 120 and dielectric layer 125, and a second trench is created by etching dielectric layer 130. The second trench exposes a portion of dielectric layer 125 and a portion of dielectric region 120.

[0044] Since the dielectric layer 125 and the dielectric region 120 may have different etching selectivities, the exposed portion of the dielectric region 120 will not be etched when etching the exposed portion of the dielectric layer 125. This means that the exposed portion of the dielectric layer 125 may be selectively etched. Therefore, when the exposed portion of the dielectric layer 125 is selectively etched to expose a portion of the metal wire 124, the resulting via is self-aligned over the portion of the metal wire 124 due to the first trench and the second trench. Thereafter, the metal wire 128 and the conductive through via 132 are formed by depositing (several) conductive materials into the resulting self-aligned via and the second trench of the dielectric layer 130. Thus, the conductive through via 132 aligned with the metal wire 124 is positioned on the metal wire 124 and below the metal wire 128 to provide an electrical connection between the metal wire 124 and the metal wire 128. Similarly, a conductive through via may be formed in the dielectric layer 127 and aligned with the metal wire 126 to provide an electrical connection between the metal wire 126 and a metal wire formed above the dielectric layer 127 .

[0045] In some embodiments, the distance between conductive paths within a semiconductor device decreases as the device size shrinks, resulting in an increased risk of dielectric breakdown (e.g., time-dependent dielectric breakdown (TDDB)) within the semiconductor device. For example, consider a case where the distance between metal wire 124 and metal wire 126 is very short due to the shrinking size in semiconductor device 100. When conductive through via 132 is misaligned with metal wire 124 and moves toward metal wire 126, there will be a voltage collapse between conductive through via 132 and metal wire 126 because the distance between conductive through via 132 and metal wire 126 fails to meet the misalignment tolerance. In contrast, since conductive interconnect structure layer 107 may include metal wire(s) and self-aligned via(s), the risk of dielectric breakdown in semiconductor device 100 may be greatly reduced.

[0046] In addition, in Figure 1A 1 , the metal wire 124 is electrically connected to the source region 106 through the conductive through via 134. Thus, the source region 106 is electrically connected to the metal wire 128 through the self-aligned conductive through via 132. In some embodiments, the source region 106 electrically connected to the metal wire 128 may be further electrically connected to a conductive region (e.g., the gate region 108 or the drain region 110) through the conductive track 114 / 116. In some embodiments, the source region 106 electrically connected to the metal wire 128 may be isolated from the conductive track 114 / 116 by the dielectric region 120. However, one skilled in the relevant art will recognize that other conductive regions (e.g., the source region and / or the drain region) may be electrically connected to the BEOL metal wire(s) without departing from the spirit and scope of the present disclosure. For example, in some embodiments, a conductive through via may be formed between the gate region 108 and the metal wire 124 such that the gate region 108 is electrically connected to the metal wire 128 through the conductive through via 132. In other embodiments, a conductive through via 132 may be formed between the drain region 110 and the metal conductive line 124 so that the drain region 110 is electrically connected to the metal conductive line 128 through the conductive through via 132 .

[0047] Figure 2A An isometric view of a first exemplary integrated circuit according to some embodiments of the present disclosure is shown. Figure 2A In the embodiment shown in FIG. 1 , the substrate structure layer 211, the transistor structure layer 213 and the backside structure layer 215 of the integrated circuit 200 may be represented as described above. Figure 1A The embodiments of the substrate structure layer 101, the transistor structure layer 103 and the backside structure layer 105 are described in detail.

[0048] The substrate structure layer 211 includes a substrate 102.3 and a conductive structure 118.3. The substrate 102.3 may represent Figure 1AThe embodiment of the substrate 102 shown in FIG. 1 and the conductive structure 118.3 may represent Figure 1A An embodiment of the conductive structure 118 is shown in FIG.

[0049] Transistor structure layer 213 includes finFET 202, finFET 204, dielectric region 112.3, conductive track 114.3, and conductive track 116.3. FinFETs 202 and 204 may represent the same as described above. Figure 1A Thus, the fin structure 104.3 may represent an exemplary embodiment of a finFET as described in Figure 1A The embodiment of the fin structure 104 shown in FIG. 1; the source region 106.3 of the finFET 202 and the source region 106.4 of the finFET 204 may represent the embodiment of the fin structure 104 shown in FIG. 1; Figure 1A 1. The exemplary embodiment of source region 106 described in FIG. 1; gate region 108.3 of finFET 202 and gate region 108.4 of finFET 204 may represent the exemplary embodiment of source region 106 described in FIG. 1. Figure 1A 108; the drain region 110.3 of the finFET 202 and the drain region 110.4 of the finFET 204 may represent the exemplary embodiment of the gate region 108 described in Figure 1A 2. Drain region 110.3 and drain region 110.4 may be characterized as a common drain region shared between finFET 202 and finFET 204. In addition, dielectric region 112.3 may represent Figure 1A An embodiment of the dielectric region 112 is shown in FIG. Conductive tracks 114.3 and 116.3 may represent Figure 1A An embodiment of conductive tracks 114 and 116 is shown in FIG.

[0050] FinFETs 202 and 204 are located on dielectric region 112.3 within which conductive tracks 114.3 and 116.3 are located. Dielectric region 112.3 may be arranged to allow electrical connection between conductive tracks 114.3 and 116.3 and gate, source, and / or drain regions of finFETs 202 and 204. In some embodiments, dielectric region 112.3 may be arranged to prevent electrical connection between conductive tracks 114.3 and 116.3 and gate, source, and / or drain regions of finFETs 202 and 204.

[0051] In the present embodiment, the conductive tracks 114.3 and 116.3 traverse the length of the semiconductor substrate 102.3 in the horizontal direction between the source regions 106.3 and 106.4. The conductive tracks 114.3 may be as described above in Figure 1C 3 to provide an electrical connection between the source region 106.3 and the conductive track 114.3, and may be electrically connected to the source region 106.3 as described above in Figure 1C 4 to provide an electrical connection between the source region 106.4 and the conductive track 114.3. Thus, the conductive track 114.3 provides an electrical connection between the source region 106.3 and the source region 106.4. However, in Figure 2A In the exemplary embodiment shown in FIG. 1 , the dielectric region 112.3 is arranged to prevent electrical connection between the conductive track 116.3 and the source region 106.4, as described above in Figure 1B In the scenario described, the dielectric region 112.3 effectively isolates the conductive track 116.3 from the source region 106.4 to prevent electrical connection between the conductive track 116.3 and the source region 106.4.

[0052] The back structure layer 215 includes a conductor 122.3 and a conductor 122.4. The conductors 122.3 and 122.4 may represent Figure 1A 102.3. In this embodiment, the conductive tracks 114.3 and 116.3 are electrically connected to the conductor 122.4 through the conductive structure 118.3 penetrating the substrate 102.3. Similarly, the conductive tracks 114.3 and 116.3 can be electrically connected to the conductor 122.4 through the conductive structure 118.3 penetrating the substrate 102.3. Figure 2A 3. In some embodiments, at least one of the conductors 122.3 and 122.4 may be a backside metal pad or a power grid conductor.

[0053] like Figure 2A The structure of integrated circuit 200 shown in FIG. 2 is for exemplary purposes only. Persons skilled in the relevant art will recognize that integrated circuit 200 may include more finFETs arranged in a manner substantially similar to finFET 202 and finFET 204 without departing from the spirit and scope of the present disclosure. Additionally or alternatively, in some embodiments, integrated circuit 200 may further include a BEOL interconnect structure formed above transistor structure layer 213, such as Figure 1A The BEOL interconnect structure in the conductive interconnect structure layer 107 is described in detail.

[0054] Figure 2B An isometric view of a second exemplary integrated circuit according to some embodiments of the present disclosure is shown. Figure 2B In the embodiment shown in FIG. 1 , the substrate structure layer 221, the transistor structure layer 223 and the backside structure layer 225 of the integrated circuit 201 may be represented as described above. Figure 1A The embodiments of the substrate structure layer 101, the transistor structure layer 103 and the backside structure layer 105 are described in detail.

[0055] like Figure 2BAs shown in FIG. 2 , the substrate structure layer 221 includes conductive structures 218.1 to 218.b, where b is an integer greater than 1. The conductive structures 218.1 to 218.b may represent Figure 1A An embodiment of the conductive structure 118 is shown in FIG.

[0056] The transistor structure layer 223 includes finFETs 203.1.1 to 203.mn and one or more conductive tracks 214.1 to 214.a, where n and m are integers greater than 1, and a is a positive integer. The finFETs 203.1.1 to 203.mn may be represented as described above in Figure 1A , and one or more conductive tracks 214.1 to 214.a may represent an exemplary embodiment of a finFET as described in Figure 1A 1 to 214.a. finFETs 203.1.1 to 203.mn are arranged in an array of m rows and n columns. However, other arrangements of finFETs 203.1.1 to 203.mn are possible without departing from the spirit and scope of the present disclosure. In the depicted embodiment, each of the m rows includes one or more conductive rails from one or more conductive rails 214.1 to 214.a.

[0057] Backside structural layer 225 includes conductors 222.1 to 222.b, which may represent Figure 1A 1 to 218.b. In this embodiment, conductive structures 218.1 to 218.b are electrically connected to one or more conductive rails from one or more conductive rails 214.1 to 214.a and are electrically connected to conductors 222.1 to 222.b, respectively.

[0058] Figures 3 to 12 An isometric view of a partially fabricated semiconductor structure according to an exemplary embodiment of the present disclosure is shown, wherein conductive track structures formed in an interlayer dielectric material may be used to provide electrical connections between multiple gate / source / drain terminals of a finFET array and to provide electrical connections between a front-side BEOL interconnect structure and a back-side power grid. The following description may be used to fabricate a semiconductor device (e.g., as described above in Figure 1A finFETs as described in the specification and / or integrated circuits having one or more semiconductor devices, such as those described above in Figure 2A The integrated circuit 200 described in and / or as described above in Figure 2B The integrated circuit 201 described in is provided to provide some examples. US Patent Application Publication Nos. 2005 / 0074960 and 2005 / 0074961, each of which is incorporated herein by reference in its entirety, describe integrating interconnect isolation air gaps into semiconductor structures.

[0059] Figure 3FIG. 3 is an isometric view of a partially fabricated semiconductor structure according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 300 includes a portion of a finFET. Figure 3 As shown, a partially fabricated semiconductor structure 300 includes a substrate 302 , a fin structure 304 , a hard mask 306 , a dielectric spacer 308 , and a seed layer structure 310 .

[0060] exist Figure 3 In the exemplary embodiment illustrated in FIG. 3 , substrate 302 may be a silicon substrate. However, one skilled in the relevant art will recognize that substrate 302 may alternatively be another semiconductor, a compound semiconductor, an alloy semiconductor, or a combination thereof. In an exemplary embodiment, substrate 302 may be a semiconductor on insulator (SOI). In an exemplary embodiment, substrate 302 may be an epitaxial material.

[0061] like Figure 3 As shown in FIG. 3 , the fin structure 304 may include a fin-shaped semiconductor material protruding from the substrate and may be parallel to each other. The fin structure 304 includes an active area in which one or more transistors are formed. The fin structure 304 may include silicon, another element semiconductor, a compound semiconductor, an alloy semiconductor, or a combination thereof. The fin structure 304 may be manufactured using a suitable process including a patterning and etching process. The patterning process may include: forming a photoresist layer overlying a substrate (e.g., on a silicon layer); exposing the photoresist to a pattern; performing a post-exposure baking process; and developing the photoresist to form a mask element including the photoresist. The mask element may then be used to protect areas of the substrate while an etching process forms a recess into the substrate 302, leaving a protruding fin. The recess may be etched using reactive ion etching (RIE) and / or other suitable processes. Many other methods for forming the fin structure 304 on the substrate 302 may be suitable. For example, according to some embodiments, the fin structure 304 may include an epitaxial material.

[0062] The hard mask 306 may be used to pattern the fin structures 304, such as by etching. The hard mask 306 may also be used to protect the fin structures 304 during subsequent processing steps. In an exemplary embodiment, the hard mask 306 is formed on the top surface of the fin structures 304. The hard mask 306 may also be formed between the fin structures 304 and on the top surface of the substrate 302. The hard mask 306 may be made of a dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, titanium oxide, other suitable dielectric materials, and / or combinations thereof. In an exemplary embodiment, the hard mask 306 is not formed as shown in FIG. Figure 3 As shown in FIG. 3 , a top surface of the substrate 302 is formed.

[0063] like Figure 3, the isolation spacers 308 may partially fill the recesses between the fin structures 304 and be formed on the sidewalls of the fin structures 304. In an exemplary embodiment, the isolation spacers 308 may be made of a dielectric material such as, for example, silicon oxide, spin-on glass, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, other suitable insulating materials, and / or combinations thereof. In an exemplary embodiment, the isolation spacers 308 may be formed by blanket depositing an isolation material over the exposed surface and using an anisotropic etching process to remove horizontal portions of the deposited isolation layer. The isolation spacers 308 may be deposited by chemical vapor deposition (CVD), plasma assisted CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable processes, and / or combinations thereof. Other fabrication techniques for the isolation spacers 308 and / or the fin structures 304 are possible. The isolation spacers 308 may include a multi-layer structure, such as, for example, a structure having one or more liner layers. The isolation spacers 308 may also be formed by depositing a reinforcement spacer layer using a multi-step deposition and process to eliminate voids and seams in the spacer material. In an exemplary embodiment, the isolation spacers 308 may be an interlayer dielectric material. In an exemplary embodiment, the isolation spacers 308 are formed directly on the substrate 302 and on the sidewalls of the fin structure 304.

[0064] like Figure 3, a seed layer structure 310 is formed on the sidewalls of the isolation spacers 308. In an exemplary embodiment, the seed layer structure 310 may be formed of a silicon material such as, for example, silicon, a silicon compound, titanium nitride (TiN), tungsten, cobalt, other suitable materials, and / or combinations thereof. In an exemplary embodiment, the seed layer structure 310 may have a different etch selectivity than the isolation spacers 308. In an exemplary embodiment, the seed layer structure 310 is formed directly on the substrate 302 and on the sidewalls of the isolation spacers 308. In an exemplary embodiment, the seed layer structure 310 may be formed by blanket depositing a semiconductor material over the exposed surface; patterning the deposited semiconductor material; and using an anisotropic etching process to remove exposed portions of the deposited seed layer material that are not protected by the photoresist. In an exemplary embodiment, an exemplary patterning process may include: forming a photoresist layer over the exposed surface of the deposited seed layer material; exposing the photoresist to a mask or a shrink mask having a pattern thereon; performing a post-exposure bake process; and developing the photoresist to form a mask layer. In an exemplary embodiment, the mask layer may be a hard mask, such as, for example, a silicon nitride layer, other suitable layers, and / or combinations thereof. Surface areas of the seed layer material not protected by the mask layer are etched using, for example, a reactive ion etching (RIE) process, a wet etching process, other suitable processes, and / or combinations thereof. In an exemplary embodiment, the etch selectivity may be substantially different between the seed layer material and other structures of the partially fabricated semiconductor structure 300 by controlling the etching parameters of the etching process, such as, for example, etchant gas type, gas flow rate, etching temperature, plasma power, chamber pressure, other suitable parameters, and / or combinations thereof. For example, the etching process may be a RIE process using a fluorocarbon gas such as CF4, trifluoromethane (CHF3), octafluoropropane (C3F8), other suitable etching gases, and / or combinations thereof. The etching process may be an anisotropic etching process. Other fabrication techniques for the seed layer structure 310 are possible. The seed layer structure 310 may include a multi-layer structure, such as, for example, a structure having one or more liner layers. The length L of the seed layer structure 310 measured along the length of the fin may vary based on device requirements (e.g., the length of a subsequently formed metal drain channel). Figure 3 Seed layer structures 310 with different lengths L are shown. Figure 3 As shown in FIG. 1 , the top surfaces of the hard mask 306, the isolation spacers 308, and the seed layer structure 310 can be substantially coplanar by performing a suitable planarization process on the top surfaces of these structures. The planarization process can be, for example, a chemical mechanical polishing (CMP) process.

[0065] Figure 44 is an isometric view of a partially fabricated semiconductor structure after forming a gap filler in the opening and partially removing a seed layer structure according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 400 includes a substrate 302, a fin structure 304, a hard mask 306, a dielectric spacer 308, a seed layer structure 410, and a gap filler structure 402.

[0066] like Figure 4 As shown in FIG. 4 , the gap filling structure 402 may be filled as described above in Figure 3 304, between opposing fin structures 304 and seed layer structures 310, between opposing seed layer structures 310, and / or other openings between structures. In an exemplary embodiment, the gap-filling structure 402 may be made of a dielectric material similar to the isolation spacers 308, such as, for example, silicon oxide, spin-on-glass, silicon nitride, silicon carbide, silicon carbon nitride, silicon oxynitride, FSG, low-k dielectric material, other suitable insulating materials, and / or combinations thereof. In an exemplary embodiment, the gap-filling structure 402 may be formed by blanket depositing a gap-filling material over the exposed surface and in the opening; and performing a planarization process to remove excess gap-filling material formed over the top surfaces of the hard mask 306 and the seed layer structure 310 so that the top surface of the partially fabricated semiconductor structure 400 is coplanar. An exemplary planarization process may include a CMP process. The gap filling structure 402 may be deposited by CVD, PECVD, PVD, ALD, other suitable processes, and / or combinations thereof. Other fabrication techniques for the gap filling structure 402 are possible. The gap filling structure 402 may include a multi-layer structure, such as, for example, a structure having one or more liner layers. The gap filling structure 402 may also be formed by using a multi-step deposition and process to deposit an enhanced gap filling layer to eliminate voids and seams in the spacer material.

[0067] After forming the gap fill structure 402, the seed layer structure 310 is etched back to form the seed layer structure 410. The seed layer structure 310 may be etched by any suitable etching process (e.g., a RIE process, a wet etching process, other suitable processes, and / or combinations thereof). In an exemplary embodiment, the etching process may be an anisotropic etching process. In an exemplary embodiment, the etching selectivity may be substantially different between the seed layer material and other structures of the partially fabricated semiconductor structure 400 by controlling the etching parameters of the etching process. The etching process may continue until a nominal thickness of the partially fabricated semiconductor structure 400 is reached. In an exemplary embodiment, the thickness of the seed layer structure 410 may be about 1000 Å. To date (For example, arrive ). In an exemplary embodiment, the seed layer structure 410 may have a thickness of about The thickness of the seed layer structure 410 may be determined by several factors, including, but not limited to, thickness uniformity and effect on conductivity. For example, a reduced seed layer thickness may affect the uniformity of the seed layer thickness, while a greater thickness may affect the overall conductivity of subsequently formed conductive tracks.

[0068] Figure 5 is an isometric view of a partially fabricated semiconductor structure after forming conductive tracks and interlayer dielectric fillers according to an exemplary embodiment of the present disclosure. Figure 5 3 , a partially fabricated semiconductor structure 500 includes a substrate 302, a fin structure 304, a hard mask 306, a dielectric spacer 308, a gap fill structure 402, a seed layer structure 410, a conductive track 502, and a dielectric fill 504. In an exemplary embodiment, the dielectric spacer 308, the gap fill structure 402, and the dielectric fill 504 may be formed of the same material. For the purpose of simplicity, they are combined and illustrated as an interlayer dielectric (ILD) 506 (also referred to as a dielectric region).

[0069] like Figure 5 4 , the conductive track 502 may be formed on the seed layer structure 410. In an exemplary embodiment, the conductive track 502 may be formed of any metallic material or conductive material, such as tungsten, cobalt, copper, aluminum, other suitable materials, and / or combinations thereof. In an exemplary embodiment, the conductive track 502 may be formed using a metal alloy of the materials listed above. The top surface of the conductive track 502 may be a substantially smooth surface. The conductive track 502 may be formed using the seed layer structure 410 as a seed layer in which the growth of the conductive track 502 is started. For example, the conductive track 502 may be formed starting from the top surface of the seed layer structure 410 until a nominal thickness of the conductive track is achieved. In an exemplary embodiment, the growth of the conductive track material may be accomplished using a suitable process, such as CVD, electroplating, electroless plating, other suitable processes, and / or combinations thereof. For example, a tungsten material may be formed using a silicon material as a seed layer. The height of the conductive track 502 may be in a range between about 0.8 to about 1.2 times the gate pitch of a finFET device. In an exemplary embodiment, the width of the conductive track may be in a range of about 0.8 to about 2.2 times the width of the fin structure 304. In an exemplary embodiment, the distance between conductive tracks (i.e., the distance between the centers of adjacent conductive tracks) may be in a range of about 0.8 to about 1.2 times the fin pitch of the fin structure 304. In an exemplary embodiment, each conductive track 502 may have a substantially similar width or height. In an exemplary embodiment, the width or height may vary between each conductive track 502.

[0070] After forming the conductive track 502, a dielectric filler 504 is formed over the conductive track 502 and fills the opening within the gap filling structure 402. In an exemplary embodiment, the dielectric filler 504 may be formed by performing a blanket deposition of a dielectric filler material on the structure until the opening within the gap filling structure 402 is completely filled. A planarization process is then performed to remove excess dielectric filler material and planarize the dielectric filler material until the top surface of the dielectric filler material is coplanar with the hard mask 306. After the planarization process, the dielectric filler material is planarized to form the dielectric filler 504. In an exemplary embodiment, the dielectric filler 504 may be formed using the same material as the dielectric spacers 308 and the gap filling structure 402. For example, the dielectric filler 504 may be formed using silicon oxide, spin-on glass, silicon nitride, silicon carbide, silicon carbon nitride, silicon oxynitride, FSG, low-k dielectric materials, other suitable insulating materials, and / or combinations thereof. In some cases, the dielectric spacers 308 , the gap-fill structures 402 , and the dielectric filler 504 may be formed using the same material, such as illustrated as ILD 506 for simplicity.

[0071] Figure 6 6 is an isometric view of a partially fabricated semiconductor structure after etching back the ILD layer and forming a polysilicon gate over the fin according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 600 includes a substrate 302, a fin structure 304, a hard mask 306, a seed layer structure 410, a conductive track 502, a partially etched ILD 602, and a polysilicon gate structure 604.

[0072] exist Figure 6 In the exemplary embodiment shown in FIG. 1 , the uniform etching from Figure 5 The ILD 506 of the partially fabricated semiconductor structure 500 is removed until a nominal depth is reached. The etching process may be an isotropic etching process, in which the etched thickness of the ILD 506 is uniform across the semiconductor structure. After the etching process, the ILD 506 forms a partially etched ILD 602. After the etching process, a portion of the fin structure 304 may protrude from the top surface of the partially etched ILD 602. The amount of the ILD 506 removed may depend on several factors. First, the protruding portion of the fin structure 304 is used to form an active portion of a finFET device in a subsequent manufacturing step. For example, the protruding portion of the fin structure 304 represents an active portion of a fin used to form a channel and source / drain region of a finFET device. Therefore, a sufficient height of the fin structure 304 may be above the top surface of the partially etched ILD 602. Second, after the etching process, the conductive track 502 should remain below the partially etched ILD 602 ​​without being exposed.

[0073] After forming the partially etched ILD 602, a polysilicon gate structure 604 may be formed on the exposed surface of the fin structure 304, including the top surface and sidewall surfaces not covered by the partially etched ILD 602. In an exemplary embodiment, a portion of the hard mask 306 may be patterned and removed before depositing the polysilicon gate material, so that the polysilicon gate structure 604 may be formed directly on the top surface of the fin structure 304. In an exemplary embodiment, removing the hard mask layer includes performing a wet chemical process using phosphoric acid (H3PO4) that etches silicon nitride. The polysilicon gate structure 604 may be formed by blanket depositing a semiconductor material and performing a patterning and etching process. According to some embodiments, the polysilicon gate structure 604 may include a gate dielectric layer, a gate electrode structure, and / or one or more additional layers. In an exemplary embodiment, the polysilicon gate structure 604 uses polysilicon as a gate electrode structure. In an exemplary embodiment, the polysilicon gate structure 604 uses amorphous silicon as a gate electrode structure. In an exemplary embodiment, the polysilicon gate structure 604 may be a sacrificial gate structure formed, for example, in a gate replacement process used to form a metal gate structure. In an exemplary embodiment, a hard mask ( Figure 6 604. In an exemplary embodiment, the hard mask may be made of a dielectric material such as silicon nitride. In an exemplary embodiment, the polysilicon gate pitch (i.e., the distance between the centers of adjacent polysilicon gate structures 604) may be in a range between about 10 nm to about 300 nm.

[0074] Figure 7 7 is an isometric view of a partially fabricated semiconductor structure after opening a trench in a partially etched ILD to expose a portion of a conductive track according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 700 includes a substrate 302, a fin structure 304, a hard mask 306, a seed layer structure 410, a conductive track 502, a partially etched ILD 602, a polysilicon gate structure 604, and a trench 702 formed in the partially etched ILD 602.

[0075] exist Figure 7, trenches 702 are formed between adjacent polysilicon gate structures 604 and in the partially etched ILD 602. The trenches 702 are used to expose portions of one or more of the conductive rails 502 formed between adjacent polysilicon gate structures 604 so that subsequent structures (e.g., source / drain contacts and / or gate contacts) can make direct electrical contact with the conductive rails 502. The specific conductive rails 502 to be exposed depend on the circuit design and can be one or more of the conductive rails 502. The process for exposing the selected conductive rails 502 can include patterning and removing portions of the partially etched ILD 602 ​​formed over the selected conductive rails 502. In an exemplary embodiment, the entire area of ​​the partially etched ILD 602 ​​surrounded by the opposing adjacent fin structures 304 and the opposing adjacent polysilicon gate structures 604 is etched to expose the underlying conductive rails 502. Exposing the entire region described above maximizes the contact area to the conductive track 502 and thus provides the benefit of minimizing the contact resistance to the conductive track 502. In an exemplary embodiment, only a portion of the region is exposed. Figure 7 604. The conductive track regions 502A and 502B of the conductive track 502 are generally exposed. Patterning and exposing a portion of the region provides the benefit of greater tolerance for photolithographic alignment because it reduces the likelihood of exposing undesired adjacent regions of the partially etched ILD 602 ​​in the event of misalignment. In an exemplary embodiment, the exposed region depends on circuit and device needs and considerations. The patterning process may include: forming a photoresist layer overlying a structure (e.g., on a polysilicon gate structure); exposing the photoresist to a pattern; performing a post-exposure bake process; and developing the photoresist to form a mask element including the photoresist. Due to the small feature size and spacing between adjacent polysilicon gate structures 604, the patterned photoresist sheet may have sufficient mechanical strength to be suspended between adjacent polysilicon gate structures or to overhang as a flange over the edge of a polysilicon gate structure. After forming the patterned photoresist, one or more etching processes may be performed to remove the exposed partially etched ILD 602 ​​to expose selected underlying conductive tracks 502.

[0076] Figure 8 8 is an isometric view of a partially fabricated semiconductor structure after forming source / drain terminals according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 800 includes a substrate 302, a fin structure 304, a seed layer structure 410, a conductive track 502, a partially etched ILD 602, a polysilicon gate structure 604, and an epitaxial source / drain terminal 802.

[0077] exist Figure 8In the exemplary embodiment illustrated in , each finFET includes a pair of source / drain terminals. The source and drain terminals are interchangeable and formed in, on and / or around the fin structure 304. The source or drain terminal is formed on one side of the polysilicon gate structure. In an exemplary embodiment, adjacent finFET devices share a common source / drain terminal. The channel region of the fin structure 304 underlies the respective polysilicon gate structure 604. One or more epitaxial source / drain terminals 802 are directly in contact with and electrically connected to the exposed conductive rails. For example, epitaxial source / drain terminals 802A and 802B of epitaxial source / drain terminals 802 are connected to conductive rail regions 502A and 502B, respectively. Although only epitaxial source / drain terminals 802A and 802B are in Figure 8 602, but other source / drain terminals may also be connected depending on the design and device needs. Since the conductive tracks are formed within the partially etched ILD 602, they can electrically connect multiple source / drain terminals without taking up additional device space.

[0078] like Figure 86, epitaxial source / drain terminals 802 may be formed on an active fin structure of the fin structure 304 that protrudes from a top surface of the partially etched ILD 602. In an exemplary embodiment, the epitaxial source / drain terminals 802 may be epitaxial source / drain terminals formed by growing an epitaxial layer over an exposed surface of the fin 304. In an exemplary embodiment, the hard mask 306 is removed from the top of the fin structure 304 prior to the formation of the epitaxial source / drain terminals 802. In an exemplary embodiment, the fin structure 304 is formed using an epitaxial material such as epitaxial silicon, epitaxial silicon germanium (SiGe), gallium arsenide, other suitable materials, and / or combinations thereof. Growing the epitaxial layer on the exposed surface of the fin structure 304 may include performing a pre-cleaning process to remove native oxide on the surface of the fin structure 304. Next, an epitaxial process is performed to grow the epitaxial layer on the exposed surface of the fin structure 304. In an exemplary embodiment, the epitaxial process is a SiGe epitaxial process performed at a temperature between about 400° C. and about 1000° C. (e.g., between 400° C. and 1000° C.). The epitaxial process is a selective process that grows an epitaxial layer only on the exposed surface of the active fin structure. The epitaxial process may use the exposed surface of the fin structure 304 as a seed layer and the growth process continues until the nominal size and / or structure of the source / drain terminals have been achieved. An in-situ doping process may also be performed during the epitaxial process. In an exemplary embodiment, the epitaxial source / drain terminals 802 are SiGe structures. In an exemplary embodiment, the epitaxial source / drain terminals 802 may be silicon structures. In an exemplary embodiment, the thickness of the epitaxial source / drain terminals 802 is between about 10 nm and about 20 nm (e.g., between 10 nm and 20 nm). In an exemplary embodiment, during the epitaxial process, the epitaxial source / drain terminals 802 are doped with p-type or n-type dopants. For example, during the epitaxial process, the epitaxial source / drain terminals 802 may be doped with boron (B). The epitaxial source / drain terminals 802 may also take different shapes depending on various factors such as, for example, epitaxial process conditions, the crystallographic orientation of the active fin structure, and / or other suitable factors. In an exemplary embodiment, the shape of the epitaxial source / drain terminals 802 using epitaxial material has a generally diamond-shaped cross-section. In an exemplary embodiment, the top surface of the epitaxial source / drain terminals 802 may be recessed below the top surface of the polysilicon gate structure 604, such as Figure 8 In an exemplary embodiment, the top surface of the epitaxial source / drain terminal 802 may be substantially coplanar with the top surface of the polysilicon gate structure 604 .

[0079] Fig. 9900 is an isometric view of a partially fabricated semiconductor structure after forming a shallow trench isolation structure according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 900 includes a substrate 302, a fin structure 304, a seed layer structure 410, a conductive track 502, a partially etched ILD 602, a polysilicon gate structure 604, and a shallow trench isolation (STI) structure 902.

[0080] like Fig. 9 As shown in FIG. 1 , the STI structure 902 may be deposited on the Figure 8 8. The STI structure 902 is formed by depositing an insulating dielectric material to fill the opening, followed by a planarization process (e.g., a CMP process). The STI structure 902 may be deposited by CVD, PECVD, PVD, ALD, other suitable processes, and / or combinations thereof. Other fabrication techniques for the STI structure 902 are possible. The STI structure 902 may include a multi-layer structure, such as, for example, a structure having one or more liner layers. The STI structure 902 may also be formed by depositing an enhanced gap fill layer using a multi-step deposition and process to eliminate voids and seams in the dielectric material. After the planarization process, the top surfaces of the polysilicon gate structure 604 and the STI structure 902 are coplanar.

[0081] Fig.10 is an isometric view of a partially fabricated semiconductor structure after a gate replacement process according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 1000 includes a substrate 302, a fin structure 304, a seed layer structure 410, a conductive track 502, a partially etched ILD 602, an STI structure 902, and a metal gate structure 1002.

[0082] As mentioned above Figure 6 Although the polysilicon gate structure 604 is described as using polysilicon or amorphous silicon, the polysilicon gate structure 604 may be a sacrificial gate structure formed, for example, in a replacement gate process for forming a metal gate structure. For example, the polysilicon gate structure 604 may be replaced by a metal gate structure 1002 (also referred to as a gate region), such as Fig.10. The metal gate structure 1002 may further include barrier layer(s), gate dielectric layer(s), working function layer(s), fill metal layer(s), and / or other suitable materials for the metal gate structure. In an exemplary embodiment, the metal gate structure 1002 may include a capping layer, an etch stop layer, and / or other suitable materials. The gate replacement process may be a self-aligned gate replacement process in which alignment is not required. For example, the gate replacement process may begin by removing the polysilicon gate structure 604 through an etching process such as, for example, a dry etching process, a wet etching process, other suitable processes, and / or combinations thereof. The removal of the polysilicon gate structure 604 leaves an opening in the partially fabricated semiconductor structure 1000. A conductive material for forming the metal gate structure 1002 may then be blanket deposited over the opening. A subsequent planarization process may then be used to make the top surfaces of the STI structure 902 and the metal gate structure 1002 coplanar. After the planarization process, the metal gate material is deposited to form the metal gate structure 1002. The gate replacement process is a self-aligned process because the deposited metal gate material is formed in the opening without the need for alignment.

[0083] Fig.11 1 is an isometric view of a partially fabricated semiconductor structure after forming metal source / drain contacts according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 1100 includes a substrate 302, a fin structure 304, a seed layer structure 410, a conductive track 502, a partially etched ILD 602, a metal gate structure 1002, an etched STI structure 1102, and source / drain contacts 1104.

[0084] exist Fig.11, the source / drain contacts 1104 may be metal contacts formed directly on the epitaxial source / drain terminals 802 and used to provide electrical connections to the epitaxial source / drain terminals 802. A patterning and etching process may be used to form openings in the STI structures 902 for deposition of source / drain contact material. In an exemplary embodiment, the STI material may be removed from between opposing metal gate structures 1002 to expose the underlying epitaxial source / drain terminals 802. In an exemplary embodiment, the STI material may remain between adjacent fin structures 304 to provide electrical isolation. The etched STI structure 1102 is formed by patterning and etching the STI material to expose the underlying epitaxial source / drain terminals 802. In an exemplary embodiment, the source / drain contacts 1104 are formed by blanket deposition using an ALD process, a CVD process, a PVD process, or a combination thereof. In an exemplary embodiment, the epitaxial source / drain contacts 1104 may be made of a metal such as, for example, cobalt (Co), tungsten (W), copper (Cu), nickel (Ni), ruthenium (Ru), or other suitable materials. In an exemplary embodiment, a planarization process (e.g., a CMP process) is performed to remove excess source / drain contact material of the source / drain contacts 1104 formed above the top surfaces of the STI structures 902 and the metal gate structure 1002. The source / drain contacts 1104 may be formed after the planarization process, and the top surfaces of the source / drain contacts 1104, the etched STI structures 1102, and the metal gate structure 1002 are coplanar. In an exemplary embodiment, the source / drain contacts 1104 may further include a barrier layer to prevent material from the source / drain contacts 1104 from diffusing into the etched STI structures 1102.

[0085] In an exemplary embodiment, forming the source / drain contact 1104 may further include forming a silicide layer between the source / drain contact 1104 and the epitaxial source / drain terminal 802. In an exemplary embodiment, an etching process is performed to recess the top surface of the epitaxial source / drain terminal 802 to form a flat surface of the source / drain contact. In an exemplary embodiment, recessing the epitaxial source / drain terminal 802 increases the contact area between the source / drain contact 1104 and the epitaxial source / drain terminal 802, which may reduce contact resistance. In an exemplary embodiment, forming the silicide layer is performed by a silicide process, the silicide process including: depositing a metal layer, thereby causing the metal to react with the epitaxial layer or the active fin structure; and removing the unreacted metal layer. In an exemplary embodiment, the silicide layer may include cobalt silicide (CoSix), nickel silicide (NiSix), other suitable silicide layers, and / or combinations thereof.

[0086] In some embodiments, conductive track structures formed in an interlayer dielectric material may be used to provide electrical connections between multiple gate structures of a finFET array. Fig.12 is an isometric view of a partially fabricated semiconductor structure after deposition of metal gate material and formation of source / drain contacts according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 1200 includes Figures 3 to 9 For example, the partially fabricated semiconductor structure 1200 includes a structure similar to Figures 3 to 9 The substrate 1202, the fin structure 1204, the partially removed seed layer structure 1206, the conductive track 1208, the partially etched ILD 1210, and the STI structure 1214 of their respective structures in the embodiment. Fig. 9 The partially fabricated semiconductor structure 1300 is then formed by removing the polysilicon gate structure 604. In an exemplary embodiment, the removal process may be a self-aligned removal process in which a patterning process is not required. For example, the removal process may cause the polysilicon gate material to have a higher etch selectivity than other exposed structures, so that no mask material is required to shield the other exposed structures. In an exemplary embodiment, the exposed structures other than the polysilicon gate structure may be covered to provide further protection from the removal process.

[0087] After the removal process (complete removal of the polysilicon gate material), the underlying fin structure 1204 and the partially etched ILD 1210 are exposed, and the conductive track 1208 remains under the partially etched ILD 1210. The operation may be similar to Figure 6 Next, trenches are formed in the selective openings in which the polysilicon gate material has been removed, and the formed trenches are used to expose portions of one or more conductive rails 1208 so that subsequent structures (e.g., gate electrodes) can make direct electrical contact with the one or more conductive rails 1208. In an exemplary embodiment, the trench formation process for exposing selected conductive rails 1208 can be similar to that described above with reference to Figure 7 The groove formation procedure described in Fig.12 As shown in FIG. 1 , portions of conductive tracks 1208A and 1208B are exposed and directly connected to metal gate structure 1216. In an exemplary embodiment, the deposition of conductive material and the formation of metal gate structure 1216 may be similar to that described above with reference to FIG. Fig.10 The formation of the metal gate structure 1002 is described. In exemplary embodiments, other formation processes may be used. Because the conductive track is formed within the ILD layer, it can electrically connect multiple metal gate structures without taking up additional device space.

[0088] exist Fig.12 In the exemplary embodiment shown in FIG. Fig.11Forming source / drain contacts 1104 as described, a patterning and etching process may be used to form openings in the STI structures 1214 for deposition of source / drain contact material. Next, source / drain contacts 1218 may be formed directly on the epitaxial source / drain terminals to form source / drain regions. In an exemplary embodiment, portions of the STI material may be removed from between opposing metal gate structures 1216 to expose underlying epitaxial source / drain terminals. In an exemplary embodiment, the STI material remains between adjacent fins to provide electrical isolation.

[0089] Figures 13 to 15 is an isometric view of a partially fabricated semiconductor structure integrating a self-aligned via structure and a backside power grid with the partially fabricated semiconductor structure 1200 according to an exemplary embodiment of the present disclosure. Persons skilled in the relevant art(s) will recognize that the integration scheme may be applied to semiconductor structures, such as the partially fabricated semiconductor structure 1100 to provide some examples, without departing from the spirit and scope of the present disclosure.

[0090] Fig.13 is an isometric view of a partially fabricated semiconductor structure including BEOL metal lines and self-aligned vias after deposition of metal gate material(s) and formation of source / drain contacts according to an exemplary embodiment of the present disclosure. The partially fabricated semiconductor structure 1300 includes Fig.12 The substrate 1202, fin structure 1204, partially removed seed layer structure 1206, conductive track 1208, partially etched ILD 1210, STI structure 1214, metal gate structure 1216 and source / drain contacts 1218 described in the specification further include a dielectric layer structure 1320, metal wires 1324 each extending in a first direction, a dielectric layer 1326 formed on the metal wires 1324, metal wires 1328 each extending in a second direction different from the first direction, and a dielectric layer structure 1330.

[0091] exist Fig.13 In the exemplary embodiment illustrated in FIG. 1 , a dielectric layer structure 1320 is formed on the STI structure 1214, the metal gate structure 1216, and the source / drain contacts 1218. A metal wire 1324 may be formed by etching the dielectric layer structure 1320 to create a first trench and depositing (several) conductive materials into the first trench, and a dielectric layer 1326 may be deposited over the metal wire 1324 to fill the first trench. Then, a dielectric layer structure 1330 may be formed on the dielectric layer structure 1320 and the dielectric layer 1326.

[0092] By etching the dielectric layer structure 1330 to create a second trench (which exposes a portion of the dielectric layer structure 1320 and a portion of the dielectric layer 1326) and etching the exposed portion of the dielectric layer 1326 to expose the metal wire 1324, a conductive through via V1 can be created and arranged to electrically connect the metal wire 1324 with the metal wire 1328 after the conductive material(s) are filled into the second trench. In the present embodiment, the conductive through via V1 (also referred to as a self-aligned via) can be created based on the difference in etching selectivity between the dielectric layer structure 1320 and the dielectric layer 1326. By way of example but not limitation, after creating the second trench in the dielectric layer structure 1330 to expose a portion of the dielectric layer structure 1320 and a portion of the dielectric layer 1326, the exposed portion of the dielectric layer 1326 can be selectively etched to expose a portion of the metal wire 1324, while the exposed portion of the dielectric layer structure 1320 will not be etched. Thus, the resulting via is generated on and aligned with the exposed portion of the metal conductive line 1324. After the conductive material(s) are filled into the second trench, a conductive through via V1 and a corresponding metal conductive line 1328 connected to the conductive through via V1 are formed accordingly. In some embodiments, a conductive through via V2 and a corresponding metal conductive line 1328 are formed in a similar manner.

[0093] Thus, the source / drain region including the source / drain contacts 1218 can be electrically connected to the metal wire 1328 through the conductive through vias V0 and V1. In some embodiments, a conductive through via can be generated between the metal wire 1324 and the gate region including the metal gate structure 1216, so that the gate region can be electrically connected to the metal wire 1328 through the conductive through via formed between the metal wire 1324 and the gate region and the conductive through via V1.

[0094] Fig.14 14 is an isometric view of a partially fabricated semiconductor structure after forming BEOL metal wires and self-aligned vias according to an exemplary embodiment of the present disclosure. The difference between the partially fabricated semiconductor structure 1400 and the partially fabricated semiconductor structure 1300 is that the partially fabricated semiconductor structure 1400 includes a conductive structure 1404, which may include a number of conductive through-substrate vias (e.g., through-silicon vias (TSVs)) and / or trench-type through-substrate vias (e.g., through-silicon trenches (TSTs)) penetrating the substrate 1402. In some embodiments, the conductive structure 1404 may be formed by etching the substrate 1402 from the back side of the substrate 1402 to create openings to expose one or more conductive tracks 1208, and filling the openings with conductive material (s) into the openings. In some embodiments, the exposed one or more conductive tracks 1208 may contact the source / drain regions (s) and / or the gate regions (s).

[0095] By way of example and not limitation, first, a photoresist is formed on the back side of the substrate 1402. A photomask is used to expose portions of the photoresist. Next, depending on whether a negative or positive photoresist is used, the exposed or unexposed portions of the photoresist are removed to expose portions of the substrate 1402. Next, an etching process is performed to remove the exposed portions of the substrate 1402. In some embodiments, the etching process includes a RIE process using a fluorocarbon gas (e.g., CF4, CHF3, C3F8), other suitable etching gases, and / or combinations thereof, but the disclosure is not limited thereto. The exposed portions of the substrate 1402 are etched from the back side to expose one or more conductive tracks 1208. Thereafter, the remaining photoresist is removed. In some embodiments, a plasma ashing or wet belt process is used to remove the remaining photoresist. In some embodiments, the plasma ashing process is followed by a wet dip in a sulfuric acid (H2SO4) solution to clean the back side of the substrate 1402 and remove the remaining photoresist.

[0096] After removing the remaining photoresist, deep trench structures or deep via structures with openings are formed from the back side of the substrate 1402 to expose the one or more conductive tracks 1208 on the front side of the substrate 1402. Then, conductive material(s) (e.g., Cu, Al, Ti, Ta, W, Nb, Mo, TiNiC, TaN, Ti / W, or Ti / TiN), any other known conductive or semiconductive materials, or combinations thereof are filled into the openings to form the conductive structures 1404. Since the openings of the deep trench / via structures have sufficient cross-sectional areas exposed to the front side of the substrate 1402, it is easy to couple the filled conductive material(s) to the one or more conductive tracks 1208.

[0097] In some embodiments, the bottom surfaces of the substrate 1402 and the conductive structure 1404 may be made substantially coplanar by performing a suitable planarization process on the bottom surfaces of these structures. The planarization process may be, for example, a CMP process. Additionally or alternatively, the thickness of the substrate 1402 may be less than Fig.13 In some embodiments, a grinding process (such as a CMP process or other suitable process) may be used to grind the substrate 1302. Fig.13 1302 to form the substrate 1402 before forming the conductive structure 1404. In these embodiments, after grinding the substrate 1402 to reduce its thickness, the ground substrate 1402 is etched from the back side to create opening(s) to expose the one or more conductive tracks 1208.

[0098] Fig.151 is an isometric view of a partially fabricated semiconductor structure after integration of a backside power grid according to an exemplary embodiment of the present disclosure. The difference between the partially fabricated semiconductor structure 1500 and the partially fabricated semiconductor structure 1400 is that the partially fabricated semiconductor structure 1500 includes metal pads 1522, power grid conductors 1524, and isolation structures 1526. Each metal pad 1522 may be located between the substrate 1402 and the corresponding power grid conductor 1524 to provide an electrical connection between the power grid conductor 1524 and the conductive structure 1404 in the substrate 1402. In some embodiments, the metal pads 1522 and the power grid conductors 1524 may be part of the power grid. In some embodiments, the power grid conductors 1524 may be directly connected to the conductive structure 1404.

[0099] The metal pad 1522 may be formed using a photolithography and etching process. For example, after forming the conductive structure 1404, a photoresist may be formed over the back side of the substrate 1402. A photomask is used to expose portions of the photoresist. Next, depending on whether a negative or positive photoresist is used, the exposed or unexposed portions of the photoresist are removed to produce (several) openings exposed to the conductive structure 1404. Next, (several) conductive materials (e.g., Cu, Al, Ti, Ta, W, Nb, Mo, TiNiC, TaN, Ti / W, or Ti / TiN), any other known conductive or semiconductive materials, or combinations thereof are filled into the (several) openings to form the metal pad 1522. Thereafter, the remaining photoresist is removed. In some embodiments, a plasma ashing or wet tape process is used to remove the remaining photoresist. In some embodiments, the plasma ashing process is followed by a wet dip in a sulfuric acid (H2SO4) solution to clean the back side of the substrate 1402 and remove the remaining photoresist.

[0100] It should be noted that the structure of the power grid conductor 1524 is for illustrative purposes only and is not intended to limit the scope of the present disclosure. In some embodiments, the power grid conductor 1524 may be arranged in different directions according to design requirements. For example, the structure of the power grid conductor 1524 may include a parallel power rail structure to reduce IR (voltage) drop, wherein one of the power grid conductors 1524 (e.g., a lower power grid conductor) may be placed parallel to another of the power grid conductors 1524 (e.g., an upper power grid conductor placed above the lower power grid conductor).

[0101] By integrating a conductive structure penetrating a semiconductor substrate and a conductive rail structure in a dielectric region on the front side of the semiconductor structure into a semiconductor chip (or integrated circuit), one or more power grids can be placed on the back side of the semiconductor substrate to provide power to the circuit elements on the front side through the conductive structure (e.g., TSV and / or TST) and the conductive rail structure. In other words, since the conductive rail structure can be used for intra-cell connection (e.g., electrical connection between at least two conductive regions of (several) gate regions, (several) drain regions, and (several) source regions), the circuit elements on the front side can be powered by one or more back-side power grids instead of front-side power lines, thereby saving routing resources on the front side. For example, one or more metal wires originally used as front-side power lines can be used in other applications. In addition, since the conductive rail structure can be used for intra-cell connection, the conductive structure does not need to be deep enough to contact the conductive region on the front side, and the conductive region does not need to have a convex shape for connecting the conductive structure.

[0102] By further integrating self-aligned via structures for connecting BEOL metal wires on the first side, the upper metal wires / layers can be self-aligned with the lower metal wires / layers to reduce misalignment and dielectric breakdown (e.g., time-dependent dielectric breakdown (TDDB)) on the front side of the semiconductor device / chip (or integrated circuit). The interconnected network of conductive tracks and conductive structures can reduce the area relative to the area required to form one or more integrated circuits and also save the amount of routing resources used on the front side of the semiconductor chip.

[0103] Fig.16 is a flow chart of an exemplary method for forming a non-planar semiconductor device according to an exemplary embodiment of the present disclosure. Other operations in method 1600 may be performed and the operations of method 1600 may be performed in a different order and / or varied.

[0104] At operation 1602, a fin structure is formed and protrudes from a front side of a substrate of a non-planar semiconductor device. Figure 3 As depicted in FIG. 3 , a fin structure 304 is formed and protrudes from the front side of the substrate 302 .

[0105] At operation 1604, a dielectric region is formed on the front side of the substrate, wherein the dielectric region includes a conductive track buried in the dielectric region and parallel to the fin structure. Figure 5 As depicted in FIG. 3 , an ILD 506 is formed on the substrate 302 , and one or more conductive rails 502 are buried within the ILD 506 and parallel to the fin structure 304 .

[0106] At operation 1606, a first opening is formed in the dielectric region to expose the conductive track. Figure 7As described in FIG. 5 , trench 702 is formed in a partially etched ILD 602 ​​to expose a portion of one or more of the conductive rails 502 formed between adjacent polysilicon gate structures 604. In another example, as Fig.12 , trenches are formed in the partially etched ILD 1210 to expose portions of one or more of the conductive rails 1208 (eg, conductive rails 1208A and 1208B).

[0107] At operation 1608, a plurality of conductive regions are formed on the dielectric region, wherein a first conductive region of the plurality of conductive regions contacts the conductive track through the first opening. Figure 7 and 8 , epitaxial source / drain terminals 802 are formed on the partially etched ILD 602, and epitaxial source / drain terminals 802A and 802B of epitaxial source / drain terminals 802 are connected to conductive rail regions 502A and 502B, respectively. Fig.12 As depicted in FIG. 1 , gate structure 1216 is formed on partially etched ILD 1210 and is arranged to connect to conductive rails 1208A and 1208B, respectively.

[0108] At operation 1610, the substrate is etched from the back side of the substrate to form a second opening to expose the conductive track. Fig.14 14, the substrate 1402 is etched from the back side to expose one or more conductive tracks 1208. In some embodiments, before etching the substrate 1402 from the back side, the thickness of the substrate 1402 may be reduced (eg, by wafer grinding) to facilitate the etching process.

[0109] At operation 1612, a first conductive material is filled into the second opening to form a through-substrate via in the substrate. Fig.14 As described in , (several) conductive materials are filled into (several) openings to form through-substrate vias penetrating the substrate 1402 .

[0110] In some embodiments, after forming one or more through-substrate vias in the substrate, a power grid conductor may be connected to the back side of the substrate to integrate a back-side power scheme into a non-planar semiconductor device. Additionally or alternatively, a metal pad may be formed on the back side of the substrate to electrically connect the power grid conductor to the through-substrate vias. For example, Fig.15, one or more power grid conductors 1524 of the power grid can be connected to the conductive structure 1404 (e.g., TSV and / or TST). In some embodiments, since the conductive structure 1404 (e.g., TSV and / or TST) can be electrically connected to one or more conductive rails 1208 (which are electrically connected to one or more conductive regions (e.g., source, gate, and / or drain regions)), the one or more power grid conductors 1524 can be electrically connected to one or more conductive regions on the front side of the substrate 1402.

[0111] In some embodiments, method 1600 may include (several) operations for forming metal wires and self-aligned vias on the front side of the substrate, such as the following operations: forming a dielectric layer on multiple conductive regions, the dielectric layer including a first metal wire extending in a first direction, the first metal wire buried in the dielectric layer and electrically connected to one of the multiple conductive regions; forming a groove in the dielectric layer to expose the first metal wire, the groove extending in a second direction different from the first direction; and depositing a second conductive material into the groove to form a conductive through via and a second metal wire, wherein the first metal wire is electrically connected to the second metal wire through the conductive through via.

[0112] For example, Fig.13 As described in , a dielectric layer (including dielectric layer structure 1320 and dielectric layer 1326) can be formed on metal gate structure 1216 and source / drain contacts 1218 (multiple conductive regions), wherein one or more metal wires 1324 are buried in the dielectric layer and extend in a first direction. One or more metal wires 1324 can be electrically connected to (several) conductive regions. Fig.13 In the exemplary embodiment illustrated in FIG. 1 , the metal wire 1324 may be electrically connected to the gate region including the metal gate structure 1216 through the conductive through via V0. Then, a trench may be formed in the dielectric layer to expose the metal wire 1324, wherein the trench extends in a second direction different from the first direction, so that the metal wire 1324 and the dielectric layer structure 1320 are exposed. (Several) conductive structures may be deposited into the trench to form a conductive through via and a metal wire, wherein the metal wire 1324 is electrically connected to the formed metal wire through the conductive through via. For example, in FIG. Fig.13 In the exemplary embodiment shown in FIG. 1 , one metal conductive line 1324 is electrically connected to one metal conductive line 1328 through a conductive through via V1 , and another metal conductive line 1324 may be electrically connected to another metal conductive line 1328 through a conductive through via V2 .

[0113] Some embodiments described herein may include a semiconductor device including a substrate, a dielectric region, a plurality of conductive regions, a first conductive track, and a conductive structure. The dielectric region is located on the substrate. The plurality of conductive regions are located on the dielectric region. The first conductive track is located within the dielectric region and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate the substrate and is formed below the first conductive track. The conductive structure is electrically connected to the first conductive track.

[0114] Some embodiments described herein may include an integrated circuit comprising a substrate, a dielectric region, a first fin field effect transistor, a conductive track, and a conductive structure. The dielectric region is located on the substrate. The first fin field effect transistor includes a first source region, a first gate region, and a first drain region located on the dielectric region. The conductive track is located in the dielectric region and is electrically connected to a first terminal region selected from among the first source region, the first gate region, and the first drain region. The conductive structure is arranged to penetrate the substrate and is formed below the conductive track. The conductive structure is electrically connected to the conductive track.

[0115] Some embodiments described herein may include a method for forming a non-planar semiconductor device, comprising: forming a fin-like structure protruding from a front side of a substrate of the non-planar semiconductor device; and forming a dielectric region on the front side of the substrate. The dielectric region includes a conductive track buried in the dielectric region and parallel to the fin-like structure. The method may further include: forming a first opening in the dielectric region to expose the conductive track; forming a plurality of conductive regions on the dielectric region, wherein one of the plurality of conductive regions contacts the conductive track through the first opening. The method may further include: etching the substrate from a back side of the substrate to form a second opening to expose the conductive track; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other programs and structures for implementing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0117] Explanation of symbols

[0118] 100 Semiconductor devices

[0119] 101 substrate structure layer

[0120] 102 Substrate

[0121] 102.1 Substrate

[0122] 102.2 Substrate

[0123] 102.3 Substrate

[0124] 103 Transistor structure layer

[0125] 104 Fin structure

[0126] 104.3 Fin structure

[0127] 105 back structure layer

[0128] 105.1 Conductive Area

[0129] 105.2 Conductive Area

[0130] 106 Source region

[0131] 106.3 Source Region

[0132] 106.4 Source Region

[0133] 107 Conductive interconnect structure layer

[0134] 108 Gate region

[0135] 108.3 Gate region

[0136] 108.4 Gate region

[0137] 110 Drain region

[0138] 110.3 Drain Region

[0139] 110.4 Drain region

[0140] 112 Dielectric region

[0141] 112.1 Dielectric Region

[0142] 112.2 Dielectric Region

[0143] 112.3 Dielectric Region

[0144] 114 Conductor rail

[0145] 114.1 Conductor rails

[0146] 114.2 Conductor rails

[0147] 114.3 Conductor rails

[0148] 116 Conductor rail

[0149] 116.3 Conductor rail

[0150] 118 Conductive structure

[0151] 118.1 Conductive structure

[0152] 118.2 Conductive structures

[0153] 118.3 Conductive structures

[0154] 120 Dielectric region / isolation region

[0155] 122 Conductor

[0156] 122.3 Conductors

[0157] 122.4 Conductors

[0158] 124 Metal wire

[0159] 125 Dielectric layer

[0160] 126 Metal wire

[0161] 127 Dielectric layer

[0162] 128 Metal wire

[0163] 130 Dielectric layer

[0164] 132 Conductive penetration path

[0165] 134 Conductive penetration path

[0166] 200 Integrated Circuits

[0167] 201 Integrated Circuits

[0168] 202 Fin Field Effect Transistor (finFET)

[0169] 203.1.1-203.mn FinFET

[0170] 204 FinFET

[0171] 211 substrate structure layer

[0172] 213 Transistor structure layer

[0173] 214.1-214.a Conductor rails

[0174] 215 back structure layer

[0175] 218.1-218.b Conductive structures

[0176] 222.1-222.b Conductors

[0177] 221 substrate structure layer

[0178] 223 Transistor structure layer

[0179] 225 back structure layer

[0180] 300 Partially manufactured semiconductor structures

[0181] 302 substrate

[0182] 304 Fin Structure

[0183] 306 Hard Mask

[0184] 308 Dielectric Spacer

[0185] 310 Seed layer structure

[0186] 400 Partially manufactured semiconductor structures

[0187] 402 Gap Filling Structure

[0188] 410 Seed layer structure

[0189] 500 Partially manufactured semiconductor structures

[0190] 502 Conductor rail

[0191] 502A Conductor rail area

[0192] 502B Conductor rail area

[0193] 504 Dielectric Filler

[0194] 506 Interlayer Dielectric (ILD)

[0195] 600 Partially manufactured semiconductor structures

[0196] 602 Partially Etched Interlayer Dielectric (ILD)

[0197] 604 Polysilicon Gate Structure

[0198] 700 Partially manufactured semiconductor structures

[0199] 702 Groove

[0200] 800 Partially manufactured semiconductor structures

[0201] 802 Epitaxial Source / Drain Terminals

[0202] 802A Epitaxial Source / Drain Terminals

[0203] 802B Epitaxial Source / Drain Terminals

[0204] 900 Partially manufactured semiconductor structures

[0205] 902 Shallow Trench Isolation (STI) Structure

[0206] 1000 Partially manufactured semiconductor structures

[0207] 1002 Metal Gate Structure

[0208] 1100 Partially manufactured semiconductor structures

[0209] 1102 Etched shallow trench isolation (STI) structure

[0210] 1104 Source / Drain Contacts

[0211] 1200 Partially manufactured semiconductor structures

[0212] 1202 Substrate

[0213] 1204 Fin Structure

[0214] 1206 Structure after partial removal of seed layer

[0215] 1208 Conductor rail

[0216] 1208A Conductor Rail

[0217] 1208B Conductor Rail

[0218] 1210 Partially etched interlayer dielectric (ILD)

[0219] 1214 Shallow Trench Isolation (STI) Structure

[0220] 1216 Metal Gate Structure

[0221] 1218 Source / Drain Contacts

[0222] 1300 Partially manufactured semiconductor structures

[0223] 1320 Dielectric layer structure

[0224] 1324 Metal Wire

[0225] 1326 Dielectric layer

[0226] 1328 Metal Wire

[0227] 1330 Dielectric layer structure

[0228] 1400 Partially manufactured semiconductor structures

[0229] 1402 Substrate

[0230] 1404 Conductive structure

[0231] 1500 Partially manufactured semiconductor structures

[0232] 1522 Metal pad

[0233] 1524 Power Grid Conductor

[0234] 1526 Isolation Structure

[0235] 1600 Methods

[0236] 1602 Operation

[0237] 1604 Operation

[0238] 1606 Operation

[0239] 1608 Operations

[0240] 1610 Operation

[0241] 1612 Operation

[0242] H1 Height

[0243] H2 Height

[0244] V0 Conductive penetration path

[0245] V1 Conductive penetration path

[0246] V2 Conductive penetration path

Claims

1. A semiconductor device comprising: substrate; a dielectric region located on the substrate; a plurality of conductive regions located on the dielectric region; a first conductive track located within the dielectric region, the first conductive track electrically connected to a first conductive region of the plurality of conductive regions, wherein the first conductive region contacts a top surface of the first conductive track at a level at which the first conductive region contacts a top surface of the dielectric region; as well as A conductive structure penetrates the substrate and is formed below the first conductive track, the conductive structure being electrically connected to the first conductive track. 2 . The semiconductor device of claim 1 , the conductive structure comprising a conductive through substrate via.

3. The semiconductor device according to claim 1, further comprising: A power grid conductor is located below the substrate, and the power grid conductor is electrically connected to the conductive structure.

4. The semiconductor device according to claim 3, further comprising: A metal pad is located between the substrate and the power grid conductor, the metal pad being configured to electrically connect the power grid conductor to the substrate.

5. The semiconductor device according to claim 1, further comprising: A fin structure protrudes from the substrate and the dielectric region and contacts the conductive structure.

6. The semiconductor device according to claim 5, further comprising: A second conductive track is located within the dielectric region and electrically connected to the conductive structure, wherein the first conductive track faces a first sidewall of the fin structure and the second conductive track faces a second sidewall of the fin structure. 7 . The semiconductor device of claim 5 , wherein the plurality of conductive regions include a source region, a gate region, and a drain region, and the fin structure, the source region, the gate region, and the drain region are configured to form a fin field effect transistor.

8. The semiconductor device according to claim 1, further comprising: A first metal wire electrically connected to a second conductive region among the plurality of conductive regions, the first metal wire extending in a first direction; a second metal conductive line extending in a second direction different from the first direction; as well as A conductive through via is positioned on the first metal wire and below the second metal wire, and the first metal wire is electrically connected to the second metal wire through the conductive through via. 9 . The semiconductor device according to claim 8 , wherein the second conductive region is electrically connected to the first conductive region through the first conductive track or isolated from the first conductive track by the dielectric region.

10. An integrated circuit comprising: substrate; a dielectric region located on the substrate; A first fin field effect transistor including a first source region, a first gate region, and a first drain region located on the dielectric region; a conductive track located within the dielectric region, the conductive track being electrically connected to a first terminal region selected from among the first source region, the first gate region, and the first drain region, wherein the first terminal region electrically connected to the conductive track contacts each of respective portions of the dielectric region located on opposite sides of the conductive track, wherein the first terminal region contacts a top surface of the conductive track at a level at which the first terminal region contacts a top surface of the dielectric region; as well as A conductive structure penetrates the substrate and is formed below the conductive track, the conductive structure being electrically connected to the conductive track. 11 . The integrated circuit of claim 10 , wherein the first FinFET further comprises a fin structure protruding from the substrate and the dielectric region and contacting the conductive structure.

12. The integrated circuit of claim 10, the conductive structure comprising a conductive through substrate via.

13. The integrated circuit of claim 10, further comprising: A power grid conductor is located below the substrate, and the power grid conductor is electrically connected to the conductive structure.

14. The integrated circuit of claim 13, further comprising: A metal pad is located between the substrate and the power grid conductor, the metal pad being configured to electrically connect the power grid conductor to the substrate.

15. The integrated circuit of claim 10, further comprising: a second fin field effect transistor including a second source region, a second gate region, and a second drain region located on the dielectric region; as well as A first metal wire electrically connected to a second conductive region selected from among the first source region, the first gate region, the first drain region, the second source region, the second gate region, and the second drain region, the first metal wire extending in a first direction; a second metal conductive line extending in a second direction different from the first direction; as well as A conductive through via is positioned on the first metal wire and below the second metal wire, and the first metal wire is electrically connected to the second metal wire through the conductive through via.

16. A semiconductor device comprising: substrate; a dielectric region located on the substrate; a fin structure protruding from the substrate and the dielectric region; a first conductive region located on the dielectric region; a conductive track located within the dielectric region, the conductive track facing a sidewall of the fin-like structure, wherein a bottom surface of the conductive track is at a level equal to or higher than a bottom surface of a fin in the fin-like structure, and the first conductive region contacts a top surface of the conductive track at a level at which the first conductive region contacts a top surface of the dielectric region; as well as A conductive structure penetrates the substrate and is formed below the conductive track, the conductive structure being electrically connected to the conductive track.

17. The semiconductor device according to claim 16, further comprising: A power grid conductor is located below the substrate, and the power grid conductor is electrically connected to the conductive rail through the conductive structure.

18. The semiconductor device according to claim 16, wherein The first conductive region is electrically connected to the conductive track.

19. The semiconductor device according to claim 16, further comprising: A second conductive region is located on the dielectric region, and the second conductive region is isolated from the conductive track by the dielectric region. 20 . The semiconductor device of claim 16 , wherein the conductive structure is further formed under the fin structure and electrically connected to the fin structure.

21. A method for forming a non-planar semiconductor device, comprising: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, wherein the dielectric region includes a first conductive track buried within the dielectric region and parallel to the fin structure; etching the dielectric region to form a first opening in the dielectric region to expose the first conductive track and a portion of the dielectric region; depositing a plurality of conductive regions on the dielectric region, wherein a first conductive region of the conductive regions contacts the first conductive track through the first opening and the first conductive region contacts a top surface of the first conductive track at a level at which the first conductive region contacts a top surface of the portion of the dielectric region; etching the substrate from a back side of the substrate to form a second opening to expose the first conductive track; as well as A first conductive material is filled into the second opening to form a through substrate via in the substrate.

22. The method of claim 21, further comprising: A power grid conductor is connected to the back side of the substrate, wherein the power grid conductor is electrically connected to the first conductive rail through the through-substrate via.

23. The method of claim 22, wherein connecting the power grid conductor to the back side of the substrate comprises: forming a metal pad on the back side of the substrate to contact the through substrate via; as well as Connecting the power grid conductor to the metal pad.

24. The method of claim 21, further comprising: The thickness of the substrate is reduced before etching the substrate from the back side of the substrate.

25. The method of claim 21, further comprising: Depositing a dielectric layer on the conductive region, wherein the dielectric layer includes a first metal wire extending in a first direction, and the first metal wire is buried in the dielectric layer and electrically connected to a second conductive region in the conductive region; etching the dielectric layer to form a trench to expose the first metal wire, wherein the trench extends in a second direction different from the first direction; as well as A second conductive material is deposited into the trench to form a conductive through via and a second metal conductive line, wherein the first metal conductive line is electrically connected to the second metal conductive line through the conductive through via.

26. The method of claim 21 , wherein etching the substrate from the back side of the substrate to form the second opening to expose the first conductive track comprises: The second opening is formed to expose a corresponding bottom portion of the first conductive track and a fin in the fin structure.

27. The method of claim 21 , wherein the dielectric region further comprises a second conductive track buried within the dielectric region; the first conductive track and the second conductive track are positioned at opposite sides of the fin structure; etching the substrate from the back side of the substrate to form the second opening to expose the first conductive track comprises: The second opening is formed to expose the first conductive rail, a corresponding bottom portion of the second conductive rail, and a fin in the fin structure.

28. A method for forming a non-planar semiconductor device, comprising: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a seed layer structure on the front side of the substrate, the seed layer structure being parallel to the fin structure; depositing a first conductive track using the seed layer structure as a seed layer; depositing a dielectric material on the first conductive track to form a dielectric region surrounding the first conductive track; etching the dielectric region to expose the first conductive track; depositing a first conductive region on each of the exposed first conductive track and respective portions of the dielectric region located on opposite sides of the exposed first conductive track, wherein the first conductive region contacts a top surface of the first conductive track at a level at which the first conductive region contacts a top surface of the dielectric region; etching the substrate from a back side of the substrate to form a recess to expose the first conductive track; as well as A first conductive material is filled into the recess to form a through substrate via in the substrate.

29. The method of claim 28, further comprising: A power grid conductor is connected to the back side of the substrate, wherein the power grid conductor is electrically connected to the first conductive rail through the through-substrate via.

30. The method of claim 29, wherein connecting the power grid conductor to the back side of the substrate comprises: forming a metal pad on the back side of the substrate to contact the through substrate via; as well as Connecting the power grid conductor to the metal pad.

31. The method of claim 28, further comprising: The thickness of the substrate is reduced before etching the substrate from the back side of the substrate.

32. The method of claim 28, further comprising: depositing a second conductive region on the dielectric region; Depositing a dielectric layer on the second conductive region, wherein the dielectric layer includes a first metal wire extending in a first direction, and the first metal wire is buried in the dielectric layer and electrically connected to the second conductive region; etching the dielectric layer to form a trench to expose the first metal wire, wherein the trench extends in a second direction different from the first direction; as well as A second conductive material is deposited into the trench to form a conductive through via and a second metal conductive line, wherein the first metal conductive line is electrically connected to the second metal conductive line through the conductive through via.

33. The method of claim 28, wherein etching the substrate from the back side of the substrate to form the recess to expose the first conductive track comprises: The substrate is etched to form the recess to expose corresponding bottom portions of the first conductive rails and fins in the fin structure.

34. The method of claim 28, wherein the first conductive track is positioned at a first side of a fin in the fin-like structure, the method further comprising: A second conductive track is deposited on the substrate at a second side of the fin opposite the first side, wherein the recess is arranged to expose the first conductive track, respective bottom portions of the second conductive track, and the fin in the fin-like structure.

35. A method for forming a non-planar semiconductor device, comprising: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a conductive track and an interlayer dielectric on the front side of the substrate, the conductive track buried within the interlayer dielectric and positioned at one side of a fin in the fin structure; etching the interlayer dielectric to form a recess in the dielectric region to expose a top portion of the conductive track; depositing a first conductive region on the dielectric region to contact the conductive track through the recess, wherein the first conductive region contacts a top surface of the conductive track at a level at which the first conductive region contacts a top surface of the dielectric region; etching the substrate from a back side of the substrate to expose respective bottom portions of the conductive rails and the fins; as well as A first conductive material is deposited on the respective bottom portions of the conductive rails and the fins to form a through-substrate via in the substrate.

36. The method of claim 35, further comprising: A power grid conductor is connected to the back side of the substrate, wherein the power grid conductor is electrically connected to the conductive rails through the through-substrate vias.

37. The method of claim 36, wherein connecting the power grid conductor to the back side of the substrate comprises: forming a metal pad on the back side of the substrate to contact the through substrate via; as well as Connecting the power grid conductor to the metal pad.

38. The method of claim 35, further comprising: The thickness of the substrate is reduced before etching the substrate from the back side of the substrate.

39. The method of claim 35, further comprising: depositing a second conductive region on the dielectric region; Depositing a dielectric layer on the second conductive region, wherein the dielectric layer includes a first metal wire extending in a first direction, and the first metal wire is buried in the dielectric layer and electrically connected to the second conductive region; etching the dielectric layer to form a trench to expose the first metal wire, wherein the trench extends in a second direction different from the first direction; as well as A second conductive material is deposited into the trench to form a conductive through via and a second metal conductive line, wherein the first metal conductive line is electrically connected to the second metal conductive line through the conductive through via.

40. The method of claim 39, wherein the first conductive region and the second conductive region each contact different portions of the conductive track.

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