Single-pole double-throw (SPDT) switch and transmit-receive circuit with high linearity

Abstract

A single-pole double-throw switch. In some embodiments, the switch includes a first switch transistor connected between a common terminal of the single-pole double-throw switch and a first switch terminal of the single-pole double-throw switch, a second switch transistor connected between the common terminal of the single-pole double-throw switch and a second switch terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switch transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switch transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 681,040, filed on June 5, 2018, and U.S. Non-Provisional Application No. 16 / 111,139, filed on August 23, 2018, in the U.S. Patent and Trademark Office, entitled “SYSTEM AND METHOD FOR PROVIDING HIGHLY-LINEAR SINGLE-POLE DOUBLE THROW (SPDT) SWITCH,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects according to embodiments of the present disclosure relate to switches and transmit-receive circuits, and more particularly to SPDT switches and transmit-receive circuits having high linearity. Background Art

[0004] Switches for routing RF and mmWave signals (e.g., single-pole double-throw (SPDT) switches) can be fabricated using transistors and used in a variety of applications, including, for example, transmit-receive switches for transceivers. However, in some designs, the performance of such switches may be limited because of linearity loss that may result from insufficient bootstrapping or because of return loss degradation that may result from the presence of parasitic capacitance associated with on-chip coupling capacitors.

[0005] Therefore, there is a need for an improved design for a SPDT switch. Summary of the invention

[0006] According to an embodiment of the present invention, a single-pole double-throw switch is provided, comprising: a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switching terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switching terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and the gate of the second switching transistor.

[0007] In some embodiments, the gate of the first auxiliary transistor is connected to the gate of the second switch transistor.

[0008] In some embodiments, the gate of the second auxiliary transistor is connected to the gate of the first switch transistor.

[0009] In some embodiments, the single-pole double-throw switch further includes a first coupling capacitor connected between the first switch terminal of the single-pole double-throw switch and the first switching transistor.

[0010] In some embodiments, the single-pole double-throw switch further includes a second coupling capacitor connected between the second switch terminal of the single-pole double-throw switch and the second switching transistor.

[0011] In some embodiments: a channel width of the first auxiliary transistor is less than or equal to a channel width of the first switch transistor, and a channel width of the second auxiliary transistor is less than or equal to a channel width of the second switch transistor.

[0012] In some embodiments: a channel width of the first auxiliary transistor is less than or equal to 50% of a channel width of the first switch transistor, and a channel width of the second auxiliary transistor is less than or equal to 50% of a channel width of the second switch transistor.

[0013] In some embodiments: a channel width of the first auxiliary transistor is less than or equal to 35% of a channel width of the first switch transistor, and a channel width of the second auxiliary transistor is less than or equal to 35% of a channel width of the second switch transistor.

[0014] In some embodiments: the first switching transistor is directly connected to the common terminal without an intervening coupling capacitor, and the second switching transistor is directly connected to the common terminal without an intervening coupling capacitor.

[0015] According to an embodiment of the present disclosure, a transmit-receive circuit is provided, comprising: a single-pole double-throw switch having a common terminal, a first switch terminal, and a second switch terminal; a low-noise amplifier having an input connected to the second switch terminal; and a power amplifier having an output connected to the first switch terminal, the single-pole double-throw switch comprising: a first switch transistor connected between the common terminal of the single-pole double-throw switch and the first switch terminal of the single-pole double-throw switch, a second switch transistor connected between the common terminal of the single-pole double-throw switch and the second switch terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and the gate of the first switch transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and the gate of the second switch transistor.

[0016] In some embodiments, the gate of the first auxiliary transistor is connected to the gate of the second switch transistor.

[0017] In some embodiments, the gate of the second auxiliary transistor is connected to the gate of the first switch transistor.

[0018] In some embodiments, the transmit-receive circuit includes a single-pole double-throw switch, which further includes a first coupling capacitor connected between a first switch terminal of the single-pole double-throw switch and the first switching transistor.

[0019] In some embodiments, the transmit-receive circuit includes a single-pole double-throw switch, which further includes a second coupling capacitor connected between a second switch terminal of the single-pole double-throw switch and the second switching transistor.

[0020] In some embodiments: a channel width of the first auxiliary transistor is less than or equal to a channel width of the first switch transistor, and a channel width of the second auxiliary transistor is less than or equal to a channel width of the second switch transistor.

[0021] In some embodiments: a channel width of the first auxiliary transistor is less than or equal to 50% of a channel width of the first switch transistor, and a channel width of the second auxiliary transistor is less than or equal to 50% of a channel width of the second switch transistor.

[0022] In some embodiments: a channel width of the first auxiliary transistor is less than or equal to 35% of a channel width of the first switch transistor, and a channel width of the second auxiliary transistor is less than or equal to 35% of a channel width of the second switch transistor.

[0023] In some embodiments: the first switching transistor is directly connected to the common terminal without an intervening coupling capacitor, and the second switching transistor is directly connected to the common terminal without an intervening coupling capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification and drawings, in which:

[0025] Figure 1A This is a schematic diagram of a SPDT switch;

[0026] Figure 1B This is a schematic diagram of a SPDT switch;

[0027] Figure 2 is a schematic diagram of a SPDT switch according to an embodiment of the present disclosure; and

[0028] Figure 3 is a schematic diagram of a SPDT switch according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of an exemplary embodiment of a SPDT switch with high linearity provided according to the present disclosure, and is not intended to represent the only form in which the present disclosure can be constructed or utilized. This description sets forth the features of the present disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures can be implemented by different embodiments, which are also intended to be encompassed within the scope of the present disclosure. As shown elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0030] refer to Figure 1A In some related art SPDT switch circuits, insufficient bootstrapping may impair the linearity of the circuit. For example, when the first switch transistor 200 of the switch is turned on and the second switch transistor 210 of the switch is turned off, the input signal 105 (input B) present at the first switch terminal (due to the first switch transistor 200 of the switch being turned on) may be present at the common node T, and due to the capacitive coupling between the main terminals (source and drain) of the first switch transistor 200 and the gate of the first switch transistor 200 (through the internal capacitance in the first switch transistor 200, i.e., through the gate-source capacitance of the first switch transistor 200, and through the gate-drain capacitance of the first switch transistor 200), the same signal may also be present at the gate of the first switch transistor 200. As a result, the voltage between the gate and the main terminals is constant (i.e., it does not fluctuate with the signal) and is equal to the DC bias voltage across these terminals. For example, if the gate bias is 1V, and the bias voltages of the main terminals are both 0V, the gate is at a voltage 1V higher than either main terminal (i.e., Vgs=Vgd=1V). Due to capacitive coupling, the AC voltage on all three terminals is the same, and this behavior of the gate voltage following the voltage on the main terminal of the transistor can be referred to as "bootstrapping". It should be understood that in Figure 1A In a circuit of FIG. 1 , the transistors do not have fixed sources and fixed drains; instead, one or the other of the main terminals can act as a drain (and the other can act as a source) at any point in time, depending on the direction of the voltage on the main terminals.

[0031] exist Figure 1AIn the circuit, bootstrapping may not achieve the same effect as with the second switch transistor 210 being turned off, because the signal 110 (input A) at the second switch terminal may be different from the signal at the common node T (as shown, the signal 110 at the second switch terminal is zero, and the signal at the common node T is equal to the signal 105 at the first switch terminal). Due to this difference, the AC signal on the gate of the second switch transistor 210 can be a combination (e.g., a weighted average) of the signals at the two main terminals of the second switch transistor 210 (both of which are coupled to the gate via capacitive coupling), and (unlike the case of the first switch transistor 200), the AC component of the voltage between the gate and the main terminals may therefore not vanish. The non-vanishing voltage between the gate and the main terminals may cause the conductivity of the channel of the second switch transistor 210 to be modulated by the AC signal, resulting in reduced linearity. Reference Figure 1B In some embodiments, a coupling capacitor may be used to enable a bias voltage to be applied to the main terminals of both the first switching transistor 200 and the second switching transistor 210. In such an embodiment, the linearity of the switch may be improved; however, the presence of the coupling capacitor and its associated parasitic capacitance may result in an input return loss (S 11 ) and output return loss (S 22 ) deterioration of both.

[0032] refer to Figure 2 In some embodiments, the circuit for the SPDT switch includes (eg Figure 1A and Figure 1B The circuit further includes a first auxiliary transistor 230 connected between the gate of the first switch transistor 200 and the common terminal 220, a second auxiliary transistor 240 connected between the gate of the second switch transistor 210 and the common terminal 220, a first coupling capacitor 245 and a second coupling capacitor 247. The gate of the first auxiliary transistor 230 is connected to the gate of the second switch transistor 210, and the gate of the second auxiliary transistor 240 is connected to the gate of the first switch transistor 200, as shown.

[0033] The bias voltages of the SPDT switches can each be selected from one of two voltages, which can be referred to as a "low" voltage (e.g., 0V as shown) and a "high" voltage (e.g., 1V as shown). As discussed in further detail below, these bias voltages can be supplied by a control circuit connected to four bias resistors 206, 208, 216, and 218. The respective values ​​of the high voltage and the low voltage can be selected to be any two voltage values, where the high voltage is sufficiently greater than the low voltage so that (i) when the gate of the transistor of the SPDT switch is at a high voltage and the two main terminals of the transistor are at a low voltage, the transistor is turned on, and (ii) when the gate of the transistor of the SPDT switch is at a low voltage and the two main terminals of the transistor are at a high voltage, the transistor is turned off. In addition, in Figure 2 In the embodiment of the present invention, there is no need for a coupling capacitor at the common terminal 220 (which is present in Figure 1B In the embodiment of Figure 2 In the embodiment of the present invention, it is not necessary to maintain different bias voltages at the second main terminals 204 , 214 of the first switching transistor 200 and the second switching transistor 210 .

[0034] In the first state of the SPDT switch, the first switching transistor 200 is turned on and the second switching transistor 210 is turned off (and Figure 2 ), the DC voltage at the gate of the first switching transistor 200 is high (due to the high bias applied to the first gate bias resistor 206 by the control circuit), the DC voltage at the first main terminal 202 of the first switching transistor 200 is low (due to the low bias applied to the first terminal bias resistor 208 by the control circuit), and the DC voltage at the second main terminal 204 of the first switching transistor 200 is low (due to the first switching transistor 200 being turned on). The signal of the first state of the SPDT switch is Figure 2 A first signal 250 (having a non-zero AC component) is present at the first switch terminal 215 , and a second signal 255 (having no AC component) is present at the second switch terminal 225 .

[0035] Since the first switching transistor 200 is turned on, the AC signal 250 present at the first switching terminal 215 is sent to the common terminal 220 through the first switching transistor 200. The DC voltage at the gate of the second switching transistor 210 is low (due to the low bias applied to the second gate bias resistor 216 by the control circuit). Due to the high bias applied to the first gate bias resistor 206 by the control circuit, the DC voltage at the gate of the second auxiliary transistor 240 is high. The DC voltage at the two main terminals of the second auxiliary transistor 240 is low, the DC voltage at the first main terminal 242 of the second auxiliary transistor 240 is low due to the low bias applied to the second gate bias resistor 216 by the control circuit, and the DC voltage at the second main terminal 244 of the second auxiliary transistor 240 is low due to the common terminal 220 being at a low DC voltage. Therefore, the second auxiliary transistor 240 is turned on, and it causes the AC signal at the common terminal 220 (which is substantially equal to the AC signal 250 present at the first switching terminal 215) to appear at the gate of the second switching transistor 210. In the first state, the first auxiliary transistor 230 is turned off.

[0036] It can be seen from the foregoing that in the first state, the second auxiliary transistor 240 solves the above Figure 1A The problem of insufficient bootstrapping described in the context of Figure 2 In the embodiment of FIG. 1 , in the first state, the AC signal 250 is present substantially unattenuated at the gate of the second switch transistor 210. As a result, the operating point of the second switch transistor 210 is consistent, substantially independent of the RF signal swing, and may result in high linearity.

[0037] In the second state, in which the second switch terminal 225 is connected to the common terminal 220 and the first switch terminal 215 is not connected to the common terminal 220, the bias voltage applied by the control circuit is reversed (a high bias is applied to the first terminal bias resistor 208 and the second gate bias resistor 216, and a low bias is applied to the second terminal bias resistor 218 and the first gate bias resistor 206). In the second state, the first switch transistor 200 and the second auxiliary transistor 240 are turned off, and the second switch transistor 210 and the first auxiliary transistor 230 are turned on. In the second state, the first auxiliary transistor 230 performs the function performed by the second auxiliary transistor 240 in the first state (i.e., it connects the common terminal 220 and the gate of the first switch transistor 200), so that the AC signal is the same at the two nodes; therefore, it solves the problem of insufficient bootstrapping, which in some embodiments would result in reduced linearity without the first auxiliary transistor 230.

[0038] refer to Figure 3In some embodiments, the SPDT switch is used as a transmit-receive selector switch in a radio frequency or millimeter wave transceiver. The first switch terminal 215 can be fed by the power amplifier 305, and the second switch terminal 225 can feed the low noise amplifier 315. The common terminal 220 can be connected to the antenna (e.g., through an antenna matching network). In operation, when the transceiver is transmitting, the SPDT switch can be in a first state that allows the signal from the power amplifier 305 to propagate to the antenna, and when the transceiver is receiving, the SPDT switch can be in a second state that allows the signal from the antenna to propagate to the low noise amplifier 315. By disconnecting the corresponding unused signal path in each of the first (transmit) state and the second (receive) state, the SPDT switch can help reduce or eliminate various problems that may occur when both amplifiers are directly connected to the antenna matching network without an intermediate SPDT switch (e.g., instability of the power amplifier 305, noise from the power amplifier 305 degrading the signal received by the low noise amplifier 315, and increased insertion loss and reduced return loss of signals traveling in both directions).

[0039] In some embodiments, according to Figure 2 The SPDT switch of the circuit can perform better than Figure 1A Other similar circuits constructed (e.g., using the same switching transistors and the same (although more) coupling capacitors, and lacking Figure 2 The performance of the auxiliary transistor of the circuit). For example, according to Figure 2 The circuit configuration of the SPDT switch can be compared to the Figure 1A Other similar circuits of the construction have 1-dB-compression points (i.e., better linearity) that are 3 dB (or higher, e.g., 10 dB) higher (e.g., 3 dBm higher). Furthermore, according to Figure 2 The SPDT switch of the circuit configuration shows a better performance than that according to Figure 1A Other similar circuits are constructed to model limitations and for better robustness to process, voltage, and temperature variations.

[0040] The transistor of the SPDT switch can be a field effect transistor as shown, for example, a metal oxide semiconductor field effect transistor (MOSFET). An N-channel MOSFET can be used because an N-channel MOSFET may have a higher majority carrier mobility than a P-channel MOSFET, and because, if the SPDT switch is connected to a source or load referenced to ground (e.g., an antenna referenced to ground), the signals sent by the SPDT switch may be close to ground, and an N-channel MOSFET may transmit these signals better than a P-channel MOSFET. The first auxiliary transistor 230 can be smaller than the first switch transistor 200 (e.g., the first auxiliary transistor 230 can have a channel width between 30% and 50% of the channel width of the first switch transistor 200), or at most equal to the channel width of the first switch transistor 200 (e.g., the first auxiliary transistor 230 can have a channel width between 30% and 100% of the channel width of the first switch transistor 200). Similarly, the second auxiliary transistor 240 may have a channel width between 30% and 100% of the channel width of the second switch transistor 210 .

[0041] As used herein, the two main terminals of a transistor (e.g., the source and drain for a MOSFET, or the collector and emitter for a bipolar transistor) may be referred to as the "main" terminals of the transistor, and the terminal used to control the transistor (e.g., the gate for a MOSFET, or the base for a bipolar transistor) may be referred to as the "control" terminal of the transistor. As used herein, when a connection to a transistor is described in terms used for a two-terminal device, it is a connection to the main terminals of the transistor being described. For example, a transistor "connected between" two nodes of a circuit has a first of the main terminals of the transistor connected to the first of the two nodes and a second of the main terminals of the transistor connected to the second of the two nodes. As another example, when two transistors are said to be connected "in series" (as in the case of a CMOS inverter), the main terminal of one of the two transistors is connected to the main terminal of the other of the two transistors.

[0042] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present invention, the first element, component, region, layer or section discussed herein may be referred to as a second element, component, region, layer or section.

[0043] Spatial relative terms such as "below", "below", "lower", "below", "above", "above", etc. may be used herein to facilitate the description of the relationship between an element or feature and another (multiple) element or (multiple) feature shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, such spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can cover the above and below orientations. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers can also be present.

[0044] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the inventive concept. As used herein, the terms "substantially," "about," and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations of measurements or calculations that would be recognized by those skilled in the art.

[0045] As used herein, the singular forms "one" and "a" are also intended to include plural forms, unless the context clearly states otherwise. It will be further understood that, when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When expressions such as "at least one" are before the element list, the entire element list is modified without modifying the individual elements of the list. In addition, when describing the embodiments of the present invention, the use of "can" refers to "one or more embodiments of the present disclosure". And, the term "exemplary" is intended to represent an example or description. As used herein, the terms "use", "use" and "being used" can be considered to be synonymous with the terms "utilize", "utilize" and "being utilized" respectively.

[0046] It should be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, directly connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0047] Any numerical range quoted herein is intended to include all subranges of the same numerical precision contained in the quoted range. For example, the range of "1.0 to 10.0" is intended to include all subranges between the quoted minimum value 1.0 and the quoted maximum value 10.0 (and including 1.0 and 10.0), that is, a minimum value equal to or greater than 1.0, and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit quoted herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit quoted in this specification is intended to include all higher numerical limits contained therein.

[0048] Although exemplary embodiments of a SPDT switch with high linearity have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that a SPDT switch with high linearity constructed according to the principles of the present disclosure may be embodied in a manner different from that specifically described herein. The present invention is also defined in the following claims and their equivalents.

Claims

1. A single-pole double-throw switch, comprising: a first switching transistor connected between the common terminal of the single-pole double-throw switch and a first switch connection terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switch connection terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and the gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and the gate of the second switching transistor, The gate of the first auxiliary transistor is connected to the gate of the second switch transistor.

2. The single-pole double-throw switch of claim 1, wherein a gate of the second auxiliary transistor is connected to a gate of the first switch transistor.

3. The single-pole double-throw switch of claim 1, further comprising a first coupling capacitor connected between the first switch terminal of the single-pole double-throw switch and the first switching transistor.

4. The single-pole double-throw switch of claim 3, further comprising a second coupling capacitor connected between the second switch terminal of the single-pole double-throw switch and the second switching transistor.

5. The single-pole double-throw switch of claim 1, wherein: The channel width of the first auxiliary transistor is less than or equal to the channel width of the first switch transistor, and A channel width of the second auxiliary transistor is smaller than or equal to a channel width of the second switch transistor.

6. The single-pole double-throw switch of claim 5, wherein: The channel width of the first auxiliary transistor is less than or equal to 50% of the channel width of the first switch transistor, and A channel width of the second auxiliary transistor is less than or equal to 50% of a channel width of the second switch transistor.

7. The single-pole double-throw switch of claim 5, wherein: The channel width of the first auxiliary transistor is less than or equal to 35% of the channel width of the first switch transistor, and A channel width of the second auxiliary transistor is less than or equal to 35% of a channel width of the second switch transistor.

8. The single-pole double-throw switch of claim 1, wherein: The first switching transistor is directly connected to the common terminal without an intermediate coupling capacitor, and The second switching transistor is directly connected to the common terminal without an intermediate coupling capacitor.

9. A transmitting-receiving circuit, comprising: A single-pole double-throw switch having a common terminal, a first switch terminal, and a second switch terminal; a low noise amplifier having an input connected to the second switch terminal, and a power amplifier having an output connected to the first switch terminal, SPDT switches include: a first switching transistor connected between the common terminal of the single-pole double-throw switch and a first switch connection terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switch connection terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and the gate of the first switching transistor, and A second auxiliary transistor is connected between the common terminal of the single-pole double-throw switch and the gate of the second switching transistor.

10. The transmission-reception circuit of claim 9, wherein a gate of the first auxiliary transistor is connected to a gate of the second switching transistor.

11. The transmission-reception circuit of claim 10, wherein a gate of the second auxiliary transistor is connected to a gate of the first switching transistor.

12. The transmit-receive circuit of claim 9, further comprising a first coupling capacitor connected between the first switch terminal of the single-pole double-throw switch and the first switching transistor.

13. The transmit-receive circuit of claim 12, further comprising a second coupling capacitor connected between the second switch terminal of the single-pole double-throw switch and the second switching transistor.

14. The transmit-receive circuit of claim 9, wherein: The channel width of the first auxiliary transistor is at most as large as the channel width of the first switching transistor, and The channel width of the second auxiliary transistor is at most as large as the channel width of the second switching transistor.

15. The transmit-receive circuit of claim 14, wherein: The channel width of the first auxiliary transistor is at most 50% of the channel width of the first switching transistor, and The channel width of the second auxiliary transistor is at most 50% of the channel width of the second switching transistor.

16. The transmit-receive circuit of claim 15, wherein: The channel width of the first auxiliary transistor is at most 35% of the channel width of the first switching transistor, and The channel width of the second auxiliary transistor is at most 35% of the channel width of the second switching transistor.

17. The transmit-receive circuit of claim 9, wherein: The first switching transistor is directly connected to the common terminal without an intermediate coupling capacitor, and The second switching transistor is directly connected to the common terminal without an intermediate coupling capacitor.

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