Semiconductor package, stacked package device and manufacturing method thereof

Abstract

A semiconductor package can be provided, comprising: a packaging substrate; a semiconductor chip on a first surface of the packaging substrate; a connecting substrate on the packaging substrate, spaced apart from the semiconductor chip and surrounding the semiconductor chip, the connecting substrate comprising a plurality of conductive connecting structures penetrating the connecting substrate; a plurality of first connecting elements between the semiconductor chip and the packaging substrate, electrically connecting the semiconductor chip to the packaging substrate; a plurality of second connecting elements between the connecting substrate and the packaging substrate, electrically connecting the connecting substrate to the packaging substrate; a mold layer encapsulating the semiconductor chip and the connecting substrate; and an upper redistribution pattern on the mold layer and the semiconductor chip, and electrically connected to corresponding conductive connecting structures among the plurality of conductive connecting structures.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2018-0066046 filed in the Korean Intellectual Property Office on June 8, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor packages, package-on-package devices and / or methods of manufacturing the same. Background Art

[0004] In the case where an integrated circuit (IC) chip is provided in the form of a semiconductor package, the IC chip can be easily used as a part of an electronic product. Generally, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, and the semiconductor chip is mounted on the PCB and electrically connected to the PCB through bonding wires or bumps. With the development of the semiconductor industry, many studies are being conducted to improve the reliability and durability of such semiconductor packages. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a highly reliable semiconductor package, a stacked package device including the semiconductor package, and / or a method of manufacturing the same.

[0006] According to an example embodiment of the present invention, a semiconductor package may include: a first packaging substrate; a first semiconductor chip on a first surface of the first packaging substrate; a plurality of first connecting elements between the first semiconductor chip and the first packaging substrate, the plurality of first connecting elements electrically connecting the first semiconductor chip to the first packaging substrate; a connecting substrate on the first packaging substrate, the connecting substrate being spaced apart from the first semiconductor chip and surrounding the first semiconductor chip, the connecting substrate including: two or more insulating layers stacked in sequence, and a plurality of conductive structures, each of the plurality of conductive structures including at least two or more connecting channel portions, and two or more connecting conductive pattern portions electrically connected to each other, the two or more connecting channel portions Respectively penetrating corresponding insulating layers among the two or more insulating layers, the two or more connecting conductive pattern portions are respectively located on corresponding insulating layers among the two or more insulating layers; a plurality of second connecting elements, between the connecting substrate and the first packaging substrate, the plurality of second connecting elements electrically connecting the connecting substrate to the first packaging substrate; a mold layer, encapsulating the first semiconductor chip and the connecting substrate; and an upper redistribution pattern, on the mold layer and the first semiconductor chip, the upper redistribution pattern comprising a redistribution channel portion and a redistribution conductive pattern portion, the redistribution channel portion penetrating the mold layer and electrically connected to corresponding conductive structures among the multiple conductive structures, the redistribution conductive pattern portion being located on the mold layer and connected to the redistribution channel portion.

[0007] According to an example embodiment of the present invention, a semiconductor package may include: a packaging substrate; a semiconductor chip on a first surface of the packaging substrate; a connection substrate on the packaging substrate, the connection substrate being spaced apart from the semiconductor chip and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating the connection substrate; a plurality of first connection elements between the semiconductor chip and the packaging substrate, the plurality of first connection elements electrically connecting the semiconductor chip to the packaging substrate; a plurality of second connection elements between the connection substrate and the packaging substrate, the plurality of second connection elements electrically connecting the connection substrate to the packaging substrate; a mold layer encapsulating the semiconductor chip and the connection substrate; and an upper redistribution pattern on the mold layer and the semiconductor chip, the upper redistribution pattern being electrically connected to corresponding conductive connection structures among the plurality of conductive connection structures.

[0008] According to an example embodiment of the present inventive concept, a semiconductor package may include a first semiconductor unit package and a second semiconductor unit package. The first semiconductor unit package may include: a first package substrate; a first semiconductor chip on a first surface of the first package substrate; a connection substrate on the first package substrate, the connection substrate is spaced apart from the first semiconductor chip and surrounds the first semiconductor chip, the connection substrate includes a plurality of conductive connection structures penetrating the connection substrate; a plurality of first connection elements between the first semiconductor chip and the first package substrate, the plurality of first connection elements electrically connecting the first semiconductor chip to the first package substrate; a plurality of second connection elements between the connection substrate and the first package substrate, the plurality of second connection elements electrically connecting the connection substrate to the first package substrate; a mold layer encapsulating the first semiconductor chip and the connection substrate; and an upper redistribution pattern on the mold layer and the first semiconductor chip, the upper redistribution pattern electrically connected to corresponding conductive connection structures among the plurality of conductive connection structures. The second semiconductor unit package may be electrically connected to the upper redistribution pattern of the first semiconductor unit package, and may include a second package substrate, and a second semiconductor chip on the first surface of the second package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments described herein.

[0010] Figure 1 is a plan view illustrating a semiconductor package according to an example embodiment of the inventive concept.

[0011] Figure 2 is along Figure 1 A cross-sectional view taken along line II-II'.

[0012] Figure 3 is a cross-sectional view illustrating a stacked package device according to example embodiments of the inventive concepts.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N , Fig.4O and Figure 4P is a sequence showing the manufacturing Figure 2 A cross-sectional view of a semiconductor packaging process.

[0014] Figure 5 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0015] Figure 6 is a cross-sectional view illustrating a stacked package device according to example embodiments of the inventive concepts.

[0016] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E is a sequence showing the manufacturing Figure 5 A cross-sectional view of a semiconductor packaging process.

[0017] Figure 8 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0018] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0019] Fig.10 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0020] Fig.11 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0021] Fig.12 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0022] Fig.13 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0023] Fig.14 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0024] Fig.15 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0025] Fig.16 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0026] Fig.17 is a cross-sectional view illustrating a stacked package device according to example embodiments of the inventive concepts.

[0027] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not to scale and may not accurately reflect the precise structure or performance characteristics of any given example embodiment, and should not be interpreted as defining or limiting the range of values ​​or properties contained in the example embodiments. For example, for clarity, the relative thickness and positioning of molecules, layers, regions and / or structural elements may be reduced or enlarged. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0028] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown.

[0029] Figure 1 is a plan view illustrating a semiconductor package according to an example embodiment of the inventive concept. Figure 2 is along Figure 1 A cross-sectional view taken along line II-II'.

[0030] refer to Figure 1 and Figure 2 , the semiconductor package 100 according to the present example embodiment may include a package substrate 90. The semiconductor chip 40 may be mounted on the package substrate 90, and the first connection element 64a is inserted between the semiconductor chip 40 and the package substrate 90. The connection substrate 25 may be provided on the package substrate 90 to surround the semiconductor chip 40. The connection substrate 25 may be spaced apart from the semiconductor chip 40 and surround the semiconductor chip 40. The second connection element 64b may be inserted between the connection substrate 25 and the package substrate 90 to electrically connect the package substrate 90 to the connection substrate 25. The connection substrate 25 and the semiconductor chip 40 may be covered with a mold layer 50.

[0031] The package substrate 90 may include a substrate body 80, a substrate upper conductive pattern 82, a substrate upper passivation layer 84, a substrate lower conductive pattern 86, and a substrate lower passivation layer 88. The substrate body 80 may be formed of or include at least one of a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), a composite material (e.g., prepreg) (in which a reinforcing element (e.g., glass fiber and / or inorganic filler) is pre-impregnated with a thermoplastic and / or thermosetting resin matrix), or a photocurable resin, but the inventive concept is not limited thereto. The substrate body 80 may include a substrate top surface 80a and a substrate bottom surface 80b facing each other. The substrate upper conductive pattern 82 may be disposed on the substrate top surface 80a. The substrate upper conductive pattern 82 and the substrate top surface 80a may be covered with a substrate upper passivation layer 84. The substrate lower conductive pattern 86 may be disposed on the substrate bottom surface 80b. The substrate lower conductive pattern 86 and the substrate bottom surface 80b may be covered with a substrate lower passivation layer 88. The substrate upper conductive pattern 82 and the substrate lower conductive pattern 86 may be formed of or include at least one of aluminum, copper, gold, or titanium nitride, and may have a single-layer structure or a multilayer structure. Although not shown, a plurality of substrate penetration electrodes may be provided to penetrate the substrate body 80 and may be used to electrically connect the substrate upper conductive pattern 82 to the substrate lower conductive pattern 86. At least one of the substrate upper passivation layer 84 and the substrate lower passivation layer 88 may be a photosensitive solder resist (PSR) layer. The photosensitive solder resist may include a photosensitive polymer. The photosensitive polymer may include at least one of a photosensitive polyimide (PSPI), a polybenzoxazole (PBO), a phenol polymer, or a benzocyclobutene polymer (BCB). The photosensitive solder resist may also include an inorganic filler. The package substrate 90 may be a printed circuit board (PCB).

[0032] The semiconductor chip 40 may include at least one of the following: a system large-scale integration (LSI) chip, a logic circuit chip, an image sensor chip (e.g., a CMOS imaging sensor (CIS)), a memory chip (e.g., a flash memory, a DRAM, a SRAM, an EEPROM, a PRAM, an MRAM, a ReRAM, a high bandwidth memory (HBM), or a hybrid memory cube (HMC)), or a micro-electromechanical system (MEMS) device. The semiconductor chip 40 may include a chip main part 41, a chip conductive pad 42 disposed on the bottom surface of the chip main part 41, and a chip passivation layer 44 covering the bottom surface of the chip main part 41. The chip main part 41 may include a semiconductor substrate, a transistor formed on the semiconductor substrate, an interlayer insulating layer covering the semiconductor substrate and the transistor, and an interconnection line disposed between the interlayer insulating layers. The chip conductive pad 42 may be disposed on the topmost interlayer insulating layer in the interlayer insulating layer, and may be electrically connected to an internal interconnection line disposed in the chip main part 41. The chip conductive pattern 42 may be formed of or include at least one of aluminum, copper, gold, tin, or titanium nitride, and may have a single-layer structure or a multi-layer structure. The chip passivation layer 44 may cover the topmost interlayer insulating layer in the interlayer insulating layer. The chip passivation layer 44 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), or polyimide, and may have a single-layer structure or a multi-layer structure.

[0033] refer to Figure 1 and Figure 2, the connection substrate 25 may be spaced apart from the semiconductor chip 40, and may include or define a rectangular cavity structure surrounding the semiconductor chip 40. The connection substrate 25 may include a first connection insulating layer 20a and a second connection insulating layer 20b stacked in sequence. Each of the first connection insulating layer 20a and the second connection insulating layer 20b may be formed of or include an insulating material. The insulating material may include a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or a composite resin (e.g., prepreg, Ajinomoto laminated film (ABF), and bismaleimide triazine (BT)), wherein the thermosetting resin and / or the thermoplastic resin is impregnated with an inorganic filler in a core material such as glass fiber (e.g., glass cloth or glass fabric). In some example embodiments, a photoimageable dielectric (PID) resin may be used as the insulating material. The connection substrate 25 may include a first connection conductive pattern 11a, a second connection conductive pattern 11b, and a third connection conductive pattern 11c, and a first connection channel 13a and a second connection channel 13b. The first connection conductive pattern 11a may be disposed in the first connection insulating layer 20a to be adjacent to the bottom surface of the first connection insulating layer 20a. In some example embodiments, the bottom surface of the first connection insulating layer 20a may be coplanar with the bottom surface of the first connection conductive pattern 11a. The bottom surface of the first connection conductive pattern 11a may be exposed to the outside. One of the first connection through holes 13a and one of the second connection conductive patterns 11b may be connected to each other to form a single body structure (interchangeably referred to as a single integrated structure). The first connection channel 13a may be formed to penetrate the first connection insulating layer 20a and contact the first connection conductive pattern 11a. The second connection conductive pattern 11b may be inserted between the first connection insulating layer 20a and the second connection insulating layer 20b. One of the second connection channels 13b and one of the third connection conductive patterns 11c may be connected to each other to form a single body structure. The second connection channel 13b may penetrate the second connection insulating layer 20b and contact the second connection conductive pattern 11b. The third connection conductive pattern 11c may be inserted between the second connection insulating layer 20b and the mold layer 50. The connection substrate 25 may also be referred to as a connection member. The connection substrate 25 may be a printed circuit board formed with a cavity 25s.

[0034] The connection substrate 25 may include a plurality of conductive connection structures penetrating therein. The connection substrate 25 may be disposed on the package substrate 90 to be spaced apart from and surround the semiconductor chip 40 from the semiconductor chip 40. In some example embodiments, the connection substrate 25 may include two or more insulating layers 20a and 20b stacked in sequence, and a plurality of conductive structures, each of the plurality of conductive structures including at least two or more connection channel portions 13a and 13b, and two or more connection conductive pattern portions 11a, 11b, and 11c electrically connected to each other, the two or more connection channel portions respectively penetrating the corresponding insulating layers in the two or more insulating layers 20a and 20b, the two or more connection conductive pattern portions 11a, 11b, and 11c respectively on the corresponding insulating layers in the two or more insulating layers 20a and 20b. The lowest connection conductive pattern portion of the two or more connection conductive pattern portions 11a, 11b, and 11c may be exposed through the lowest insulating layer in the two or more insulating layers 20a and 20b. The lowermost connection conductive pattern portion of the two or more connection conductive pattern portions 11a, 11b, and 11c may be electrically connected to the package substrate 90 via corresponding second connection elements of the plurality of second connection elements 64b. A bottom surface of the lowermost connection conductive pattern portion of the two or more connection conductive pattern portions 11a, 11b, and 11c may be coplanar with a bottom surface of a lowermost insulation layer of the two or more insulation layers 20a and 20b.

[0035] The mold layer 50 may encapsulate the semiconductor chip 40 and the connection substrate 25. The mold layer 50 may include a mold bottom surface 50 b adjacent to the package substrate 90 and a mold top surface 50 a facing the mold bottom surface 50 b. The mold layer 50 may be formed of or include an insulating resin (e.g., epoxy molding compound (EMC)). The mold layer 50 may also include a filler distributed in the insulating resin. For example, the filler may be formed of or include silicon oxide (SiO 2). The mold layer 50 may fill the space between the semiconductor chip 40 and the connection substrate 25. The mold layer 50 may contact the side surface of the cavity 25s. The mold bottom surface 50b may be substantially coplanar with the bottom surface of the first connection insulating layer 20a of the connection substrate 25. The mold bottom surface 50b may be coplanar with the bottom surface of the chip passivation layer 44. The mold bottom surface 50b, the bottom surface of the chip passivation layer 44, and the bottom surface of the first connection insulating layer 20a may be covered with a lower insulating layer 62. The lower insulating layer 62 may be disposed between the semiconductor chip 40 and the underfill layer 92 and between the connection substrate 25 and the underfill layer 92. A plurality of first connection elements 64a and a plurality of second connection elements 64b penetrate the lower insulating layer 62 and the underfill layer 92. For example, the lower insulating layer 62 may be formed of or include the following items: a thermosetting resin or an epoxy resin. For example, the lower insulating layer 62 may be formed of or include an Ajinomoto build-up film (ABF). The mold bottom surface 50 b may be spaced apart from the package substrate 90 .

[0036] A plurality of second connection elements 64b may be between the connection substrate 25 and the package substrate 90, and electrically connect the connection substrate 25 to the package substrate 90. Each of the first connection element 64a and the second connection element 64b may include at least one of a solder ball, a conductive bump, or a conductive column. The first connection element 64a and the second connection element 64b may be formed of or include at least one of: tin, lead, copper, aluminum, or gold. The first connection element 64a may penetrate the lower insulating layer 62, the chip passivation layer 44, and the substrate upper passivation layer 84, and may be used to electrically connect the chip conductive pad 42 to some of the substrate upper conductive patterns 82 (e.g., corresponding substrate upper conductive patterns 82). The second connection element 64b may penetrate the lower insulating layer 62 and the substrate upper passivation layer 84, and may be used to electrically connect the first connection conductive pattern 11a to some of the substrate upper conductive patterns 82 (e.g., corresponding substrate upper conductive patterns 82).

[0037] The distance between the first connection elements 64a or the distance between the second connection elements 64b may be in the range of 100 μm to 200 μm. The first connection elements 64a or the second connection elements 64b may have a height in the range of 50 μm to 100 μm.

[0038] The bottom filling layer 92 may be inserted between the lower insulating layer 62 and the package substrate 90. The bottom filling layer 92 may be disposed between the package substrate 90 and the semiconductor chip 40 and between the package substrate 90 and the connection substrate 25. The bottom filling layer 92 may include at least one of a thermosetting resin or a photocurable resin. In some example embodiments, the bottom filling layer 92 may also include at least one of an organic filler or an inorganic filler. The bottom filling layer 92 may fill the space between the first connection element 64a and the second connection element 64b. The distance between the semiconductor chip 40 and the package substrate 90 may be in the range of 50 μm to 100 μm.

[0039] In some example embodiments, each or all of the lower insulating layer 62, the mold layer 50, the bottom filling layer 92, and the substrate body 80 may be formed of or include at least one of the following: a thermosetting resin or an epoxy resin. However, the content and / or type of the thermosetting resin and / or epoxy resin contained therein may vary. The mold layer 50, the bottom filling layer 92, and the substrate body 80 may also include fillers. However, the size or type of the fillers contained therein may vary.

[0040] The first upper insulating layer 52 may be disposed on the mold top surface 50a. The redistribution pattern 56 may be disposed on the first upper insulating layer 52. The redistribution channel 54 may penetrate the first upper insulating layer 52 and the mold layer 50, and may be used to electrically connect the redistribution pattern 56 to the third connection conductive pattern 11c. One of the redistribution patterns 56 and the corresponding redistribution channel in the redistribution channel 54 may be connected to each other to form a single body structure. The redistribution pattern 56 may constitute a redistribution layer. The redistribution pattern 56 may be covered with a second upper insulating layer 58. The first upper insulating layer 52 and the second upper insulating layer 58 may independently include at least one of a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), ABF, or a photoimageable dielectric (PID) resin. The second upper insulating layer 58 may have an opening 58h that exposes some of the redistribution patterns 56.

[0041] In other words, the upper redistribution pattern may be disposed on the mold layer 50 and the semiconductor chip 40, and may include a redistribution channel portion 54 and a redistribution conductive pattern portion 56. The redistribution channel portion 54 may penetrate the mold layer 50 and be electrically connected to a corresponding conductive structure among the plurality of conductive structures. The redistribution conductive pattern portion 56 may be on the mold layer 50 and connected to the redistribution channel portion 54.

[0042] For example, the second upper insulating layer 58 may be formed of or include the same material as the lower insulating layer 62. For example, the lower insulating layer 62 and the second upper insulating layer 58 may be formed of or include ABF. The first upper insulating layer 52 may be formed of or include PID resin.

[0043] The external terminal (or alternatively, the external connection terminal) 94 can be attached to the substrate lower conductive pattern 86 of the package substrate 90. The external terminal 94 can be a solder ball. The external terminal 94 can be formed of or include the following items: tin and lead. In this example embodiment, the semiconductor package 100 can have an improved fan-out wafer level packaging (FOWLP) structure. The spacing between the plurality of second connection elements 64b can be smaller than the spacing between the external terminals 94.

[0044] In the semiconductor package 100 according to the present example embodiment, the semiconductor chip 40 may be electrically connected to the connection substrate 25 through the package substrate 90, without providing an additional multi-layer redistribution structure under the semiconductor chip 40. Since a process of forming a multi-layer redistribution structure in a preliminary structure including the semiconductor chip 40, the connection substrate 25, and the mold layer 50 may be omitted by using the package substrate 90, the entire process time may be reduced and / or the manufacturing yield may be improved.

[0045] Figure 3 is a cross-sectional view illustrating a stacked package device according to example embodiments of the inventive concepts.

[0046] refer to Figure 3 In the stack package device 200 according to the present example embodiment, the second semiconductor package 180 may be mounted on the first semiconductor package 100. The first semiconductor package 100 may have the same Figure 1 and Figure 2 The semiconductor package 100 is described to have the same or substantially similar structure.

[0047] The second semiconductor package 180 may include a second package substrate 130, a second semiconductor chip 150, and a second mold layer 160, the second semiconductor chip 150 may be attached to the second package substrate 130 by an adhesive layer 140 interposed between the second semiconductor chip 150 and the second package substrate 130, and the second mold layer 160 is provided to cover the second semiconductor chip 150 and the second package substrate 130. The second semiconductor package 180 may be provided on the upper redistribution pattern 56, and may be electrically connected to the redistribution conductive pattern portion of the upper redistribution pattern 56. The second package substrate 130 may include a second substrate body 120, a second substrate upper conductive pattern 126, a second substrate upper passivation layer 128, a second substrate lower conductive pattern 122, and a second substrate lower passivation layer 124. The second chip conductive pads 152 may be provided on the second semiconductor chip 150. The second chip conductive pads 152 may be connected to some of the second substrate upper conductive patterns 126 by wires 165. The second semiconductor chip 150 may include at least one of the following: a system large-scale integration (LSI) chip, a logic circuit chip, an image sensor chip (e.g., a CMOS imaging sensor (CIS)), a memory chip (e.g., flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, ReRAM, high bandwidth memory (HBM), or hybrid memory cube (HMC)), or a micro-electromechanical system (MEMS) device.

[0048] The first semiconductor package 100 may be electrically connected to the second semiconductor package 180 through a package connection element 170. Each of the package connection elements 170 may be or include at least one of a solder ball, a conductive bump, or a conductive column. The package connection element 170 may be formed of or include at least one of: tin or lead. The package connection element 170 may connect the second substrate lower conductive pattern 122 to the redistribution pattern 56 exposed through the opening 58h of the second upper insulating layer 58. The spacing between the plurality of second connection elements 64b may be smaller than the spacing between the package connection elements 170.

[0049] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N , Fig.4O and Figure 4P is a sequence showing the manufacturing Figure 2A cross-sectional view of a semiconductor packaging process.

[0050] refer to Figure 4A , a first sacrificial substrate 10 may be prepared. The first sacrificial substrate 10 may be, for example, a tape. A deposition process and an etching process may be performed to form a first connection conductive pattern 11a on the first sacrificial substrate 10. A first connection insulating layer 20a may be formed on the first sacrificial substrate 10 together with the first connection conductive pattern 11a. In some example embodiments, a mechanical drilling process and / or a laser drilling process may be performed to remove some portions of the first connection insulating layer 20a to form a first connection through hole, through which the first connection conductive pattern 11a is exposed. A conductive layer may be formed on the first connection insulating layer 20a to fill the first connection through hole, and the conductive layer may be patterned to form a first connection channel 13a and a second connection conductive pattern 11b. A second connection insulating layer 20b may be formed on the first connection insulating layer 20a. In some example embodiments, a mechanical drilling process and / or a laser drilling process may be performed to remove a portion of the second connection insulating layer 20b to form a second connection through hole, through which the second connection conductive pattern 11b is exposed. A conductive layer may be formed on the second connection insulating layer 20b to fill the second connection through hole, and then the conductive layer may be patterned to form a second connection channel 13b and a third connection conductive pattern 11c. The first connection conductive pattern 11a, the second connection conductive pattern 11b, and the third connection conductive pattern 11c and the first connection channel 13a and the second connection channel 13b may be formed in the edge region of the first connection insulating layer 20a and the second connection insulating layer 20b. Each of the first connection insulating layer 20a and the second connection insulating layer 20b may be formed of an insulating material or include an insulating material. The insulating material may include a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or a composite resin (e.g., prepreg, ABF, or bismaleimide triazine (BT)), wherein the thermosetting resin or the thermoplastic resin and the inorganic filler are pre-impregnated with a glass fiber material (e.g., glass fiber, glass cloth, or glass fabric). In some example embodiments, the insulating material may include a PID resin.

[0051] refer to Figure 4B and Figure 4C The first sacrificial substrate 10 may be removed to expose the bottom surfaces of the first connection insulating layer 20a and the first connection conductive pattern 11a. The central areas of the first connection insulating layer 20a and the second connection insulating layer 20b may be removed by, for example, a mechanical drilling process and / or a laser drilling process, so that the connection substrate 25 includes a cavity 25s.

[0052] refer to Figure 4D, a second sacrificial substrate 30 may be prepared. The second sacrificial substrate 30 may be, for example, a single-sided tape. The connection substrate 25 having the cavity 25s may be attached to the second sacrificial substrate 30. Here, the bottom surfaces of the first connection conductive pattern 11a and the first connection insulating layer 20a may contact the second sacrificial substrate 30.

[0053] refer to Figure 4E , the semiconductor chip 40 may be attached to the second sacrificial substrate 30. The semiconductor chip 40 may be inserted into the cavity 25s of the connection substrate 25. The semiconductor chip 40 may include a chip main portion 41, a chip conductive pad 42, and a chip passivation layer 44. The chip passivation layer 44 may contact the second sacrificial substrate 30.

[0054] refer to Figure 4F , a mold layer 50 may be formed on the second sacrificial substrate 30 to cover the connection substrate 25 and the semiconductor chip 40. The mold layer 50 may fill the space between the connection substrate 25 and the first semiconductor chip 40. The mold layer 50 may include a mold top surface 50a and a mold bottom surface 50b. The mold layer 50 may be formed of an insulating resin (e.g., epoxy molding compound (EMC)) in which a filler is contained or dispersed. The mold bottom surface 50b may contact the second sacrificial substrate 30. Hereinafter, a structure including the semiconductor chip 40, the connection substrate 25, and the mold layer 50 is referred to as a preliminary structure 51.

[0055] refer to Figure 4F and Figure 4G , the second sacrificial substrate 30 can be removed from the preliminary structure 51 to expose the mold bottom surface 50b, the first connection insulating layer 20a and the chip passivation layer 44. Thereafter, the preliminary structure 51 can be attached to the first carrier substrate 59, wherein the lower insulating layer 62 is interposed between the preliminary structure 51 and the first carrier substrate 59. The lower insulating layer 62 can be formed of or include at least one of the following: a thermosetting resin or ABF. The lower insulating layer 62 can be used as an adhesive layer. Subsequently, the lower insulating layer 62 can be heated and hardened.

[0056] refer to Figure 4H , a first upper insulating layer 52 may be formed on the mold top surface 50a. The first upper insulating layer 52 may be formed of or include at least one of the following: a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), ABF, or PID resin. Redistribution vias may be formed in the first upper insulating layer 52 and the mold layer 50 using, for example, a laser drilling process to expose the third connection conductive pattern 11c. A conductive layer may be formed on the first upper insulating layer 52, and then the conductive layer may be patterned to form a redistribution channel 54 filling the redistribution via, and a redistribution pattern 56.

[0057] refer to Fig. 4I , the first carrier substrate 59 can be detached or removed from the lower insulating layer 62 using, for example, a physical force applied at an interface between the first carrier substrate 59 and the lower insulating layer 62. The second carrier substrate 60 can be attached to the redistribution pattern 56 by inserting a second upper insulating layer 58 between the second carrier substrate 60 and the redistribution pattern 56. The second upper insulating layer 58 can be formed of or include at least one of a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), ABF, or PID resin. The second upper insulating layer 58 can be used not only as an adhesive layer but also as a passivation layer covering the redistribution pattern 56. Subsequently, the second upper insulating layer 58 can be heated and hardened.

[0058] refer to Figure 4J , Fig. 4I The preliminary structure 51 can be inverted (e.g., can be turned upside down). Next, the lower insulating layer 62 can be patterned using, for example, a laser drilling process to form an opening, through which the first connection conductive pattern 11a and the chip conductive pad 42 are exposed. The first connection element 64a and the second connection element 64b can be bonded to the chip conductive pad 42 and the first connection conductive pattern 11a, respectively. During the bonding process, the opening defined by the lower insulating layer 62 can be used to guide the first connection element 64a and the second connection element 64b. Therefore, bridging between adjacent connection elements in the first connection element 64a and the second connection element 64b can be alleviated or prevented. Each of the first connection element 64a and the second connection element 64b can be formed by at least one of the following or include at least one of the following: a solder ball, a conductive bump, or a conductive column. The first connection element 64a and the second connection element 64b can be formed by at least one of the following or include at least one of the following: tin, lead, copper, aluminum, or gold.

[0059] refer to Figure 4K and Figure 4L , the protective layer 66 may cover the first connection element 64a and the second connection element 64b. The protective layer 66 may be, for example, a single-sided tape. The protective layer 66 may prevent the first connection element 64a and the second connection element 64b from being damaged in subsequent processes. After forming the protective layer 66, the second carrier substrate 60 may be separated from the second upper insulating layer 58 to expose the second upper insulating layer 58.

[0060] refer to Figure 4M , Figure 4L The preliminary structure 51 may be inverted (eg, may be turned upside down). Thereafter, the second upper insulating layer 58 may be patterned using, for example, a laser drilling process to form openings 58h through which the redistribution patterns 56 are exposed.

[0061] refer to Figure 4N and Fig.4O , the protective layer 66 may be removed to expose the lower insulating layer 62 and the first and second connecting elements 64a and 64b. A package substrate 90 may be prepared. The package substrate 90 may include a substrate body 80, a substrate upper conductive pattern 82, a substrate upper passivation layer 84, a substrate lower conductive pattern 86, and a substrate lower passivation layer 88. Figure 4N The preliminary structure 51 may be placed on a package substrate 90 and may be heated to bond the first connection element 64 a and the second connection element 64 b to the substrate upper conductive pattern 82 .

[0062] refer to Figure 4P , an underfill layer 92 may be formed between the lower insulating layer 62 and the package substrate 90. Figure 2 , the external terminal 94 (eg, solder ball) may be bonded to the substrate lower conductive pattern 86. Thereafter, a singulation process and a sorting process may be performed. Thus, the semiconductor package 100 may be manufactured to have Figure 2 structure.

[0063] In the manufacturing methods according to some example embodiments of the inventive concepts, the package substrate 90 may be used to connect the semiconductor chip 40 to the connection substrate 25 without providing an additional multi-layer redistribution structure under the semiconductor chip 40. Because when forming the semiconductor package 100, the process of forming the multi-layer redistribution structure in the preliminary structure including the semiconductor chip 40, the connection substrate 25, and the mold layer 50 may be omitted by using the package substrate 90, and the package substrate 90 may be manufactured and provided separately, the entire process time may be reduced and / or the manufacturing yield may be improved.

[0064] Figure 5 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0065] refer to Figure 5 In the semiconductor package 100a according to the present exemplary embodiment, the first lower insulating layer 62a may be disposed below the mold bottom surface 50b. The second lower insulating layer 74 may be disposed below the first lower insulating layer 62a. The second lower insulating layer 74 may be disposed between the first lower insulating layer 62a and the bottom filling layer 92. The first lower insulating layer 62a may be formed of, for example, ABF or include, for example, ABF. The second lower insulating layer 74 may be formed of, for example, at least one of the following or include, for example, at least one of the following: a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), ABF, or a PID resin.

[0066] The lower redistribution patterns 70a and 70b may be inserted between the first lower insulation layer 62a and the second lower insulation layer 74. The lower redistribution patterns 70a and 70b may include a first lower redistribution pattern 70a and a second lower redistribution pattern 70b. The first lower redistribution pattern 70a may penetrate the first lower insulation layer 62a and contact the chip conductive pad 42. The second lower redistribution pattern 70b may penetrate the first lower insulation layer 62a and contact the first connection conductive pattern 11a. The first lower redistribution pattern 70a and the second lower redistribution pattern 70b may constitute a single-layer lower redistribution layer. Some of the first lower redistribution pattern 70a and the second lower redistribution pattern 70b may be connected to each other.

[0067] In other words, the first lower redistribution pattern 70a may include a redistribution conductive pattern portion, and a redistribution channel portion connected to the redistribution conductive pattern portion. The redistribution conductive pattern portion of the first lower redistribution pattern 70a may be disposed between the first lower insulating layer 62a and the second lower insulating layer 74, and contact a corresponding first connection element among the plurality of first connection elements 64a. The redistribution channel portion of the first lower redistribution pattern 70a may penetrate the first lower insulating layer 62a, and electrically connect the redistribution conductive pattern portion of the first lower redistribution pattern 70a to the semiconductor chip 40. The second lower redistribution pattern 70b may include a redistribution conductive pattern portion, and a redistribution channel portion connected to the redistribution conductive pattern portion. The redistribution conductive pattern portion of the second lower redistribution pattern 70b may be disposed between the first lower insulating layer 62a and the second lower insulating layer 74, and contact a corresponding second connection element among the plurality of second connection elements 64b. The redistribution via portions of the second lower redistribution patterns 70 b may penetrate the first lower insulation layer 62 a and electrically connect the redistribution conductive pattern portions of the second lower redistribution patterns 70 b to corresponding conductive structures of the plurality of conductive structures of the connection substrate 25 .

[0068] The first connection element 64a may penetrate the second lower insulating layer 74 and contact the first lower redistribution pattern 70a. The second connection element 64b may penetrate the second lower insulating layer 74 and contact the second lower redistribution pattern 70b. The bottom fill layer 92 may be inserted between the second lower insulating layer 74 and the package substrate 90. The upper redistribution pattern 56a may be inserted between the first upper insulating layer 52 and the second upper insulating layer 58. The second upper insulating layer 58 may include an opening 58h, and the upper redistribution pattern 56a is exposed through the opening 58h. In addition to the aforementioned structural features, Figure 5 The semiconductor package may be configured to have Figure 2 The structural features are the same or substantially similar.

[0069] exist Figure 5In the semiconductor package 100a, the semiconductor chip 40 and the connection substrate 25 can be electrically connected to each other through the first lower redistribution pattern 70a and the second lower redistribution pattern 70b constituting the single-layer lower redistribution layer. In addition, the semiconductor chip 40 and the connection substrate 25 can also be electrically connected to each other through the package substrate 90. Because the single-layer lower redistribution layer is used Figure 5 The semiconductor package 100a is formed so that the number of layers constituting the package substrate 90 can be reduced. According to the present exemplary embodiment, the semiconductor package 100a includes: the package substrate 90, which includes a plurality of lower redistribution layers and can be used as a multi-layer redistribution structure. Therefore, without forming a multi-layer redistribution structure in the preliminary structure including the semiconductor chip 40, the connection substrate 25 and the mold layer 50, the total process time can be reduced and the manufacturing yield can be improved.

[0070] Figure 6 is a cross-sectional view illustrating a stacked package device according to example embodiments of the inventive concepts.

[0071] refer to Figure 6 In the stack package device 200a according to the present example embodiment, the second semiconductor package 180 may be mounted on the first semiconductor package 100a. The first semiconductor package 100a may have the same Figure 5 The semiconductor package 100 a described above has the same or substantially similar structure.

[0072] The second semiconductor package 180 may have a Figure 3 The first semiconductor package 100a may be electrically connected to the second semiconductor package 180 through a package connection element 170. The package connection element 170 may connect the second substrate lower conductive pattern 122 to the upper redistribution pattern 56a exposed through the opening 58h of the second upper insulating layer 58.

[0073] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E is a sequence showing the manufacturing Figure 5 A cross-sectional view of a semiconductor packaging process.

[0074] refer to Fig. 7A , Fig. 4I The preliminary structure 51 may be inverted (e.g., may be turned upside down), and then the first lower insulating layer 62a may be patterned to form a through hole, through which the first connection conductive pattern 11a is exposed. A conductive layer may be formed on the first lower insulating layer 62a to fill the through hole, and the conductive layer may be patterned to form lower redistribution patterns 70a and 70b.

[0075] refer to Figure 7B and Figure 7C The second lower insulating layer 74 may cover the lower redistribution patterns 70a and 70b and the first lower insulating layer 62a. The second lower insulating layer 74 may be patterned to form lower openings 74h exposing the lower redistribution patterns 70a and 70b.

[0076] refer to Fig.7D The first and second connection elements 64a and 64b may be bonded to the lower redistribution patterns 70a and 70b, respectively. The protection layer 66 may be formed to cover the first and second connection elements 64a and 64b and the second lower insulating layer 74. The protection layer 66 may be, for example, a single-sided tape.

[0077] refer to Fig.7D and Fig. 7E , the second carrier substrate 60 can be detached from the second upper insulating layer 58. Thereafter, the preliminary structure 51 can be inverted (eg, can be turned upside down) so that the mold top surface 50a faces upward, and then the second upper insulating layer 58 can be patterned to form an upper opening 58h exposing the upper redistribution pattern 56. Fig.4O , Figure 4P and Figure 2 The subsequent steps are performed in the same or substantially similar manner as described.

[0078] Figure 8 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0079] refer to Figure 8 In the semiconductor package 100b according to the present exemplary embodiment, the first connection conductive pattern 11a may be thicker than the second connection conductive pattern 11b and the third connection conductive pattern 11c. In addition to the aforementioned structural features, Figure 8 The semiconductor package may be configured to have Figure 2 The same or substantially similar structural features can be manufactured as follows Figure 8 First, as Figure 4A As shown, the first connection conductive pattern 11a may be formed to be thicker than the second connection conductive pattern 11b and the third connection conductive pattern 11c. Then, the following may be performed: Figures 4B to 4P The subsequent process shown in FIG. Figure 8 The semiconductor package 100b is shown.

[0080] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0081] refer to Fig. 9 In the semiconductor package 100c according to the present example embodiment, the bottom surface of the first connection conductive pattern 11a may be higher than the bottom surface of the first connection insulating layer 20a. A portion of the second connection element 64b may extend into the first connection insulating layer 20a. The mold bottom surface 50b may be substantially coplanar with the bottom surface of the first connection insulating layer 20a. Fig. 9 The thickness of the chip passivation layer 44 may be less than Figure 2 . A portion of the mold layer 50 may extend into the space between the chip passivation layer 44 and the lower insulating layer 62. In some example embodiments, a portion of the mold layer 50 may extend to cover the bottom surface of the semiconductor chip 40. The thickness of the lower insulating layer 62 may vary with position. For example, the thickness of the lower insulating layer 62 below the first connection insulating layer 20a may be less than the thickness of the lower insulating layer 62 between the chip conductive pads 42. In addition to the aforementioned structural features, Fig. 9 The semiconductor package may be configured to have Figure 2 The structural features are the same or substantially similar.

[0082] It can be manufactured as follows Fig. 9 The semiconductor package 100c is as follows. Figure 4A As shown, the first connection conductive pattern 11a may be formed to be thicker than the second connection conductive pattern 11b and the third connection conductive pattern 11c. Then, a portion of the first connection conductive pattern 11a may be etched to reduce the thickness of the first connection conductive pattern 11a, as shown in FIG. Figure 4B Afterwards, you can execute Figure 4C to Figure 4P The subsequent process shown in FIG. Fig. 9 A semiconductor package 100c is shown.

[0083] Fig.10 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0084] refer to Fig.10 In the semiconductor package 100d according to the present exemplary embodiment, at least one of the second connection conductive pattern 11b and the third connection conductive pattern 11c may be provided to serve as an internal interconnection line. For example, at least one of the second connection conductive pattern 11b and the third connection conductive pattern 11c may extend in a specific direction. Therefore, a high degree of freedom in constructing a routing structure or an internal interconnection structure may be achieved.

[0085] Fig.11 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0086] refer to Fig.11In the semiconductor package 100e according to the present example embodiment, the package substrate 90a may be provided to have a multilayer PCB structure. For example, the package substrate 90a may include an intermediate substrate body 80m, an upper substrate body 83 provided on a substrate top surface 80a of the intermediate substrate body 80m, and a lower substrate body 87 provided on a substrate bottom surface 80b of the intermediate substrate body 80m. The top surface of the upper substrate body 83 may be covered with a substrate upper passivation layer 84. The bottom surface of the lower substrate body 87 may be covered with a substrate lower passivation layer 88. The first substrate upper conductive pattern 81 may be provided between the intermediate substrate body 80m and the upper substrate body 83. The second substrate upper conductive pattern 82a may be provided between the upper substrate body 83 and the substrate upper passivation layer 84. The first substrate lower conductive pattern 85 may be provided between the intermediate substrate body 80m and the lower substrate body 87. The second substrate lower conductive pattern 86a may be provided between the lower substrate body 87 and the substrate lower passivation layer 88. Each of the middle substrate body 80m, the upper substrate body 83, and the lower substrate body 87 may be formed of or include at least one of a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), a composite material (e.g., prepreg) (in which a reinforcing element (e.g., glass fiber and / or inorganic filler) is pre-impregnated with a thermoplastic and / or thermosetting resin matrix), or a photocurable resin, but the inventive concept is not limited thereto. In addition to the aforementioned structural features, Fig.11 The semiconductor package may be configured to have Fig. 9 The structural features are the same or substantially similar.

[0087] Fig.12 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0088] refer to Fig.12 In the semiconductor package 100f according to the present exemplary embodiment, each of the first connecting elements 64a may include a first conductive pillar 61a and a first conductive bump 63a. The first conductive pillar 61a may contact the chip conductive pad 42. The first conductive pillar 61a may be formed of or include copper. The first conductive bump 63a may be inserted between the first conductive pillar 61a and the corresponding substrate upper conductive pattern 82 in the substrate upper conductive pattern 82. The first conductive bump 63a may be formed of or include at least one of the following: tin or lead. In addition to the aforementioned structural features, Fig.12 The semiconductor package may be configured to have Fig. 9 The structural features are the same or substantially similar.

[0089] Fig.13 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0090] refer to Fig.13 In the semiconductor package 100g according to the present exemplary embodiment, each of the second connecting elements 64b may include a second conductive pillar 61b and a second conductive bump 63b. The second conductive pillar 61b may contact the first connecting conductive pattern 11a. The second conductive pillar 61b may be formed of or include copper. The second conductive bump 63b may be inserted between the second conductive pillar 61b and the corresponding substrate upper conductive pattern 82 in the substrate upper conductive pattern 82. The second conductive bump 63b may be formed of or include at least one of the following: tin or lead. In addition to the aforementioned structural features, Fig.13 The semiconductor package may be configured to have Fig.12 The structural features are the same or substantially similar.

[0091] Fig.14 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0092] refer to Fig.14 In the semiconductor package 100h according to the present exemplary embodiment, each of the first connecting elements 64a may include a first conductive pillar 61a and a first conductive bump 63a, and each of the second connecting elements 64b may include a second conductive pillar 61b and a second conductive bump 63b. The first conductive pillar 61a may contact one of the substrate upper conductive patterns 82, and the second conductive pillar 61b may contact another of the substrate upper conductive patterns 82. The first conductive bump 63a may be inserted between the first conductive pillar 61a and the chip conductive pad 42. The second conductive bump 63b may be inserted between the second conductive pillar 61b and the first connecting conductive pattern 11a. In addition to the aforementioned structural features, Fig.14 The semiconductor package may be configured to have Fig.13 The structural features are the same or substantially similar.

[0093] Fig.15 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0094] refer to Fig.15In the semiconductor package 100i according to the present example embodiment, two semiconductor chips 40a and 40b may be mounted on a package substrate 90 to be placed in a cavity 25s of a connection substrate 25. The semiconductor chips 40a and 40b may include a first semiconductor chip 40a and a second semiconductor chip 40b. The first semiconductor chip 40a and the second semiconductor chip 40b may be of the same or different types. The first semiconductor chip 40a may be spaced apart from the second semiconductor chip 40b. The mold layer 50 may fill the space between the first semiconductor chip 40a and the second semiconductor chip 40b. In addition to the aforementioned structural features, Fig.15 The semiconductor package may be configured to have Fig. 9 The structural features are the same or substantially similar.

[0095] Fig.16 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0096] refer to Fig.16 , except that the lower insulating layer 62 is not present, the semiconductor package 100j according to the present example embodiment may have the same Figure 2 For example, in the semiconductor package 100 j , the under-fill layer 92 may directly contact the first connection insulating layer 20 a , the mold layer 50 , and the chip passivation layer 44 .

[0097] The semiconductor package 100j may be manufactured as follows. According to an example embodiment, the first carrier substrate 59 may be attached to the semiconductor chip 40, the connection substrate 25, and the mold layer 50 without Figure 4G The lower insulating layer 62 shown in FIG. 1 may then be subjected to subsequent processing in the manner described above to produce Fig.16 According to another exemplary embodiment, the semiconductor package 100j may be omitted. Figure 4G The process shown in FIG. 1 and the second sacrificial substrate 30 (instead of the first carrier substrate 59 ) may be used in subsequent steps, such as Figure 4F In this case, the lower insulating layer 62 may not be formed, and thus the underfill layer 92 may directly contact the first connection insulating layer 20 a , the mold layer 50 , and the chip passivation layer 44 .

[0098] Fig.17 is a cross-sectional view illustrating a stacked package device according to example embodiments of the inventive concepts.

[0099] refer to Fig.17 ,and Figure 3Compared with the structure of the embodiment of the present invention, the stacked package device 200b according to the present example embodiment may be configured to further include an insertion substrate 230, which is inserted between the first semiconductor package 100 and the second semiconductor package 180. The insertion substrate 230 may include an insertion body 220, an insertion upper conductive pattern 226, an insertion lower conductive pattern 222, an insertion upper passivation layer 228, and an insertion lower passivation layer 224. The insertion body 220 may be a part of a silicon wafer. The first semiconductor package 100 and the insertion substrate 230 may be connected to each other through a first package connection element 270. The second semiconductor package 180 and the insertion substrate 230 may be connected to each other through a second package connection element 170a. The redistribution conductive pattern portion of the upper redistribution pattern 56 may be connected to the insertion substrate via a plurality of first package connection elements 270, and the second package substrate may be connected to the insertion substrate 230 via a plurality of second package connection elements 170a. The first thermal boundary layer 281 may be inserted between the first semiconductor package 100 and the insertion substrate 230. The second thermal boundary layer 283 may be inserted between the second semiconductor package 180 and the insert substrate 230. Each of the first thermal boundary layer 281 and the second thermal boundary layer 283 may include thermal grease or thermal epoxy, and at least one of the first thermal boundary layer 281 and the second thermal boundary layer 283 may include metal solid particles. The first thermal boundary layer 281 and the second thermal boundary layer 283 may be configured to transfer or dissipate heat generated from the first semiconductor package 100 to the second semiconductor package 180 in an improved manner. Therefore, the heat dissipation characteristics of the stacked package device 200b may be improved. In addition to the aforementioned structural features, Fig.17 The semiconductor package may be configured to have Figure 3 The structural features are the same or substantially similar.

[0100] exist Fig.17 , the first semiconductor package 100 is shown as having Figure 2 However, according to some example embodiments, the first semiconductor package 100 may be configured to have the same structure as the semiconductor package 100 of FIG. Figure 5 and Figures 8 to 16 The semiconductor packages shown in FIG. 1 and FIG. 2 may be identical or substantially similar in structure to one of the semiconductor packages shown in FIG. Figure 3 and Figure 6 The first semiconductor package 100 in each stacked package device can be used Figure 2 , Figure 5 and Figures 8 to 16 is replaced by one of the semiconductor packages shown in FIG.

[0101] In semiconductor packages, stacked package devices and / or methods of manufacturing the same according to some example embodiments of the present invention, a package substrate may be used to replace a multi-layer redistribution structure beneath a semiconductor chip, thereby reducing overall process time and / or improving manufacturing yield.

[0102] While some example embodiments of the present inventive concept have been particularly shown and described, those skilled in the art will understand that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first packaging substrate; a first semiconductor chip on a first surface of the first packaging substrate; a plurality of first connection elements, between the first semiconductor chip and the first packaging substrate, the plurality of first connection elements electrically connecting the first semiconductor chip to the first packaging substrate; A connection substrate, on the first packaging substrate, the connection substrate is spaced apart from the first semiconductor chip and surrounds the first semiconductor chip, the connection substrate comprising: Two or more insulating layers stacked sequentially; and A plurality of conductive structures, each of the plurality of conductive structures at least comprising two or more connection channel portions and two or more connection conductive pattern portions electrically connected to each other, the two or more connection channel portions respectively penetrating corresponding insulating layers among the two or more insulating layers, and the two or more connection conductive pattern portions respectively being on corresponding insulating layers among the two or more insulating layers; a plurality of second connection elements, between the connection substrate and the first packaging substrate, the plurality of second connection elements electrically connecting the connection substrate to the first packaging substrate; a mold layer encapsulating the first semiconductor chip and the connection substrate; and an upper redistribution pattern, on the mold layer and the first semiconductor chip, the upper redistribution pattern comprising a redistribution channel portion and a redistribution conductive pattern portion, the redistribution channel portion penetrating the mold layer and electrically connected to corresponding conductive structures among the plurality of conductive structures, the redistribution conductive pattern portion being on the mold layer and connected to the redistribution channel portion.

2. The semiconductor package according to claim 1, wherein The first packaging substrate further includes a plurality of external connection terminals on a second surface of the first packaging substrate opposite to the first surface of the first packaging substrate, and a pitch between the plurality of second connection elements is smaller than a pitch between the plurality of external connection terminals.

3. The semiconductor package according to claim 1, wherein: The lowest connection conductive pattern portion among the two or more connection conductive pattern portions is exposed by the lowest insulation layer among the two or more insulation layers, and the lowest connection conductive pattern portion among the two or more connection conductive pattern portions is electrically connected to the first packaging substrate via corresponding second connection elements among the plurality of second connection elements.

4. The semiconductor package according to claim 3, wherein: A bottom surface of a lowermost connection conductive pattern portion of the two or more connection conductive pattern portions is coplanar with a bottom surface of a lowermost insulation layer of the two or more insulation layers.

5. The semiconductor package according to claim 3, wherein: A bottom surface of a lowermost connection conductive pattern portion of the two or more connection conductive pattern portions is higher than a bottom surface of a lowermost insulation layer of the two or more insulation layers.

6. The semiconductor package according to claim 1, further comprising: An underfill layer is provided between the first packaging substrate and the first semiconductor chip and between the first packaging substrate and the connection substrate.

7. The semiconductor package according to claim 6, further comprising: A first lower insulating layer is between the first semiconductor chip and the under-fill layer and between the connection substrate and the under-fill layer.

8. The semiconductor package according to claim 7, wherein: The plurality of first connection elements and the plurality of second connection elements penetrate the first lower insulating layer and the under-fill layer.

9. The semiconductor package according to claim 7, further comprising: The second lower insulating layer is between the first lower insulating layer and the underfill layer.

10. The semiconductor package according to claim 9, further comprising: a first lower redistribution pattern, comprising a first redistribution conductive pattern portion and a first redistribution channel portion connected to the first redistribution conductive pattern portion, the first redistribution conductive pattern portion being between the first lower insulating layer and the second lower insulating layer and contacting a corresponding first connecting element of the plurality of first connecting elements, the first redistribution channel portion penetrating the first lower insulating layer and electrically connecting the first redistribution conductive pattern portion to the first semiconductor chip; as well as a second lower redistribution pattern, comprising a second redistribution conductive pattern portion and a second redistribution channel portion connected to the second redistribution conductive pattern portion, the second redistribution conductive pattern portion being between the first lower insulating layer and the second lower insulating layer and in contact with corresponding second connecting elements among the plurality of second connecting elements, the second redistribution channel portion penetrating the first lower insulating layer and electrically connecting the second redistribution conductive pattern portion to corresponding conductive structures among the plurality of conductive structures of the connection substrate.

11. The semiconductor package according to claim 1, further comprising: An upper insulating layer is on the mold layer, a redistribution channel portion of the upper redistribution pattern penetrates the upper insulating layer and the mold layer, and the redistribution conductive pattern portion is on the upper insulating layer.

12. The semiconductor package according to claim 1, wherein The plurality of first connection elements and the plurality of second connection elements include at least one of solder balls, conductive bumps, or conductive pillars.

13. The semiconductor package according to claim 1, wherein The plurality of first connection elements or the plurality of second connection elements include a stacked structure of conductive bumps and conductive pillars.

14. The semiconductor package according to claim 1, further comprising: An additional semiconductor package includes a second package substrate, and a second semiconductor chip on the second package substrate, the second package substrate being on the upper redistribution pattern and electrically connected to a redistribution conductive pattern portion of the upper redistribution pattern.

15. The semiconductor package according to claim 14, further comprising: an insert substrate, between the upper redistribution pattern and the second packaging substrate, the insert substrate comprising a plurality of first packaging connection elements on the bottom surface of the insert substrate, and a plurality of second packaging connection elements on the top surface of the insert substrate, a redistribution conductive pattern portion of the upper redistribution pattern being connected to the insert substrate via the plurality of first packaging connection elements, and the second packaging substrate being connected to the insert substrate via the plurality of second packaging connection elements.

16. A semiconductor package, comprising: Package substrate; A semiconductor chip is disposed on the first surface of the packaging substrate; a connection substrate, on the packaging substrate, the connection substrate being spaced apart from the semiconductor chip and surrounding the semiconductor chip, the connection substrate comprising a plurality of conductive connection structures penetrating the connection substrate; a plurality of first connection elements between the semiconductor chip and the packaging substrate, the plurality of first connection elements electrically connecting the semiconductor chip to the packaging substrate; a plurality of second connection elements, between the connection substrate and the packaging substrate, the plurality of second connection elements electrically connecting the connection substrate to the packaging substrate; A mold layer encapsulating the semiconductor chip and the connection substrate; as well as An upper redistribution pattern is provided on the mold layer and the semiconductor chip, the upper redistribution pattern being electrically connected to corresponding conductive connection structures among the plurality of conductive connection structures.

17. The semiconductor package according to claim 16, wherein: The package substrate further includes a plurality of external connection terminals on a second surface of the package substrate opposite to the first surface of the package substrate, and a pitch between the plurality of second connection elements is smaller than a pitch between the plurality of external connection terminals.

18. The semiconductor package according to claim 16, wherein: The connection substrate includes two or more insulating layers stacked sequentially.

19. The semiconductor package according to claim 18, wherein: The multiple conductive connection structures include: two or more channel portions, respectively penetrating the two or more insulating layers; and two or more conductive pattern portions, extending horizontally from the ends of corresponding channel portions in the two or more channel portions, and the two or more conductive pattern portions are respectively arranged on corresponding insulating layers in the two or more insulating layers.

20. The semiconductor package according to claim 18, wherein The bottom surfaces of the plurality of conductive connection structures are coplanar with a bottom surface of a lowermost insulating layer of the two or more insulating layers.

21. A semiconductor package, comprising: A first semiconductor unit package, comprising: a first packaging substrate; a first semiconductor chip on a first surface of the first packaging substrate; a connection substrate, on the first packaging substrate, the connection substrate being spaced apart from the first semiconductor chip and surrounding the first semiconductor chip, the connection substrate comprising a plurality of conductive connection structures penetrating the connection substrate; a plurality of first connection elements, between the first semiconductor chip and the first packaging substrate, the plurality of first connection elements electrically connecting the first semiconductor chip to the first packaging substrate; a plurality of second connection elements, between the connection substrate and the first packaging substrate, the plurality of second connection elements electrically connecting the connection substrate to the first packaging substrate; a mold layer encapsulating the first semiconductor chip and the connection substrate; and an upper redistribution pattern, on the mold layer and the first semiconductor chip, the upper redistribution pattern being electrically connected to corresponding conductive connection structures among the plurality of conductive connection structures; and A second semiconductor unit package is electrically connected to the upper redistribution pattern of the first semiconductor unit package, the second semiconductor unit package comprising: a second packaging substrate; and The second semiconductor chip is on the first surface of the second packaging substrate.

22. The semiconductor package according to claim 21, wherein The first packaging substrate further includes a plurality of external connection terminals on a second surface of the first packaging substrate opposite to the first surface of the first packaging substrate, and a pitch between the plurality of second connection elements is smaller than a pitch between the plurality of external connection terminals.

23. The semiconductor package according to claim 21, further comprising: A plurality of package connection elements are provided between the first semiconductor unit package and the second semiconductor unit package, the plurality of package connection elements electrically connecting the first semiconductor unit package to the second semiconductor unit package.

24. The semiconductor package according to claim 21, further comprising: An insertion substrate, between the first semiconductor unit package and the second semiconductor unit package, the insertion substrate comprising a plurality of first insertion connection elements on the bottom surface of the insertion substrate, and a plurality of second insertion connection elements on the top surface of the insertion substrate, the first semiconductor unit package being connected to the insertion substrate via the plurality of first insertion connection elements, and the second semiconductor unit package being connected to the insertion substrate via the plurality of second insertion connection elements.

25. The semiconductor package according to claim 24, further comprising: a first thermal boundary layer between the first semiconductor unit package and the interposer substrate for dissipating heat from the first semiconductor chip; as well as A second thermal boundary layer is provided between the second semiconductor unit package and the interposer substrate for dissipating heat from the second semiconductor chip.

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