Solid-state imaging element, imaging device, and control method of solid-state imaging element

Abstract

The present invention relates to a solid-state imaging element, an imaging device, and a control method for a solid-state imaging element. In a solid-state imaging element that detects address events, the image quality of image data is improved. The solid-state imaging element includes a photodiode, a pixel signal generating unit, and a detecting unit. In the solid-state imaging element, the photodiode generates electrons and holes by photoelectric conversion. The pixel signal generating unit generates a pixel signal of a voltage corresponding to the amount of one of the electrons and holes. The detecting unit detects whether the amount of change of the other of the electrons and holes exceeds a predetermined threshold value, and outputs a detection signal.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging element, an imaging device, and a control method of the solid-state imaging element. More specifically, the present invention relates to a solid-state imaging element, an imaging device, and a control method of the solid-state imaging element for detecting whether a change in brightness exceeds a threshold value. Background Art

[0002] For a long time, a synchronous solid-state imaging element that captures image data synchronously with a synchronization signal such as a vertical synchronization signal has been used in an imaging device and the like. In this general synchronous solid-state imaging element, image data can only be obtained in each cycle of the synchronization signal (for example, 1 / 60 second). Therefore, in fields related to transportation, robots, etc., it is difficult to cope with situations that require higher-speed processing. Therefore, an asynchronous solid-state imaging element is proposed that detects in real time for each pixel address whether the change in the brightness of the pixel exceeds a specified threshold as an address event (for example, refer to patent document 1). In this way, a solid-state imaging element that detects address events for each pixel is called a DVS (Dynamic Vision Sensor).

[0003] Prior art literature

[0004] Patent Document 1: Japanese Patent Application No. 2016-533140

[0005] In the above-mentioned asynchronous solid-state imaging element (i.e., DVS), image data can be generated and output at a very high speed compared to a synchronous solid-state imaging element. In addition, in the asynchronous DVS, it is also possible to further add a pixel circuit in a synchronous solid-state imaging element that shares a photodiode with the asynchronous circuit, and further generate image data with a higher quality than the synchronous type. However, in solid-state imaging elements provided with asynchronous and synchronous circuits that share a photodiode, there is a problem that it is difficult to improve the quality of image data. This is because when a photodiode generates and transmits electrons, a portion of the electrons are transmitted to the asynchronous circuit, and the remaining electrons are transmitted to the synchronous circuit, and the number of electrons transmitted to each circuit is reduced compared to the case where only one of these circuits is provided. If the area of ​​the photodiode is increased, the amount of charge can be increased to improve the image quality, but the mounting area will increase, so it is not preferred. Summary of the invention

[0006] The present invention has been made in view of such circumstances, and an object of the present invention is to improve the quality of image data in a solid-state imaging element that detects address events.

[0007] The present invention is made to eliminate the above-mentioned problems. In the first aspect, a solid-state imaging element and a control method thereof are provided. The solid-state imaging element comprises: a photodiode that generates electrons and holes by photoelectric conversion; a pixel signal generating unit that generates a pixel signal of a voltage corresponding to the amount of one of the electrons and the holes; and a detection unit that detects whether the amount of change of the other of the electrons and the holes exceeds a predetermined threshold value and outputs a detection signal. Thus, the following functions are achieved: a pixel signal is generated from one of the electrons and the holes, and an address event is detected from the other.

[0008] In the first aspect, the pixel signal generating unit may generate the pixel signal of a voltage corresponding to the amount of the electrons, and the detecting unit may detect whether the amount of change in the holes exceeds the threshold value. This may achieve the following effects: pixel signals are generated from electrons, and address events are detected from holes.

[0009] Furthermore, in the first aspect, a portion of the pixel signal generating unit and the photodiode may be disposed on a predetermined light receiving chip, and the remaining portion of the pixel signal generating unit and the detecting unit may be disposed on a predetermined circuit chip. This has the effect of reducing the circuit scale of each of the light receiving chip and the circuit chip.

[0010] Furthermore, in the first aspect, the pixel signal generating unit may include: a pixel circuit for generating the pixel signal; and a comparison circuit for comparing the pixel signal with a predetermined reference signal, wherein a portion of the comparison circuit, the photodiode, and the pixel circuit are disposed on the light receiving chip, and the remaining portion of the comparison circuit and the detection unit are disposed on the circuit chip. This achieves the following effect: the circuit scale of each of the light receiving chip and the circuit chip is reduced.

[0011] Furthermore, in the first aspect, the pixel signal generating unit may include: a pixel circuit for generating the pixel signal; a comparison circuit for comparing the pixel signal with a predetermined reference signal, the photodiode and the pixel circuit are arranged on the light receiving chip, and the comparison circuit and the detection unit are arranged on the circuit chip. This has the effect of reducing the circuit scale of each of the light receiving chip and the circuit chip.

[0012] In the first aspect, a driving unit may be further provided to drive the pixel signal generating unit to generate the pixel signal when the detecting unit detects that the change amount exceeds the threshold value. This allows only the pixel signal of the pixel where the address event has occurred to be read out.

[0013] In addition, in the first aspect, the solid-state imaging element may include: a column processing unit that performs predetermined signal processing on the pixel signal and outputs the pixel signal; and a control circuit that controls the column processing unit to output the pixel signal when the change amount exceeds the threshold value during a predetermined exposure period. This achieves the following effect: only the pixel signal of the pixel that has generated an address event during the exposure period is output.

[0014] In addition, in the first aspect, the photodiode, the pixel signal generating unit, and the detecting unit may be respectively arranged in a plurality of pixels, and the pixel signal generating unit may include: a pixel circuit for generating the analog pixel signal; and an analog-to-digital converter for converting the pixel signal into a digital signal and outputting the digital signal. Thus, the pixel signal is converted into a digital signal for each pixel.

[0015] In addition, in the first aspect, an analog-to-digital converter may be further provided to convert the analog pixel signal into a digital signal, the photodiode, the pixel signal generating unit, and the detecting unit may be respectively arranged at a plurality of pixels, and the pixel signal generating unit may generate the analog pixel signal and output it to the analog-to-digital converter. Thus, the pixel signal may be converted into a digital signal outside the pixel.

[0016] In addition, in the first aspect, the pixel signal generating section may include: a charge storage section that stores charges of one of the electrons and the holes; a floating diffusion layer that stores the charges and converts them into the voltage corresponding to the amount of the charges; a first transfer transistor that transfers the charges from the photodiode to the charge storage section; and a second transfer transistor that transfers the charges from the charge storage section to the floating diffusion layer. Thus, the following functions are achieved: the transfer of charges to the charge storage section and the transfer of charges to the floating diffusion layer are performed in sequence.

[0017] In addition, in the first aspect, the detection unit may include: a conversion unit that converts the photocurrent formed by the other of the electrons and the holes into a voltage; a subtractor that obtains the change amount of the voltage by subtraction; and a comparator that compares the change amount with the threshold value and outputs the comparison result as the detection signal. Thus, the following functions are achieved: the photocurrent is converted into a voltage, and the address event is detected by comparing the change amount with the threshold value.

[0018] In the first aspect, the detection unit may further include a buffer, and output the voltage signal from the conversion unit to the subtractor, thereby improving the driving capability of the circuit after the buffer.

[0019] In the first aspect, the converter may include a plurality of loop circuits, each of which is composed of a pair of transistors connected in a loop. This improves the conversion gain of the converter.

[0020] In the first aspect, the conversion unit may include: a pair of transistors connected in a ring shape; and a capacitor connected to each gate of the pair of transistors. This can improve the stability of the conversion unit.

[0021] In addition, the second aspect of the present invention provides an imaging device, comprising: a photodiode that generates electrons and holes by photoelectric conversion; a pixel signal generating unit that generates a pixel signal of a voltage corresponding to the amount of one of the electrons and the holes; a detection unit that detects whether the amount of change of the other of the electrons and the holes exceeds a predetermined threshold value and outputs a detection signal; and a digital signal processing unit that performs predetermined processing on the detection signal and the pixel signal. Thus, the following functions are played: processing the pixel signal generated from the electrons and the detection signal generated from the holes.

[0022] According to the present invention, in a solid-state imaging element for detecting address events, it is possible to achieve an excellent effect of improving the quality of image data. In addition, the effects described here are not limiting, and may be any effect described in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a block diagram showing a configuration example of an imaging device according to the first embodiment of the present invention.

[0024] Figure 2 This is a block diagram showing a configuration example of a solid-state imaging element according to the first embodiment of the present invention.

[0025] Figure 3 This is a block diagram showing a configuration example of a pixel array unit according to the first embodiment of the present invention.

[0026] Figure 4 This is a block diagram showing a configuration example of a pixel according to the first embodiment of the present invention.

[0027] Figure 5 It is an example of a cross-sectional view showing a photodiode according to the first embodiment of the present invention and a comparative example.

[0028] Figure 6 This is a block diagram showing a configuration example of a pixel signal generating unit according to the first embodiment of the present invention.

[0029] Figure 7This is a block diagram showing a configuration example of an address event detection unit according to the first embodiment of the present invention.

[0030] Figure 8 This is a circuit diagram showing a configuration example of a pixel according to the first embodiment of the present invention.

[0031] Fig. 9 This is a flowchart showing an example of the imaging process according to the first embodiment of the present invention.

[0032] Fig.10 This is a flowchart showing an example of AER (Address Event Representation) processing according to the first embodiment of the present invention.

[0033] Fig.11 It is a diagram showing an example of a stacked structure according to a second embodiment of the present invention.

[0034] Fig.12 This is a circuit diagram showing a configuration example of a pixel according to the second embodiment of the present invention.

[0035] Fig.13 This is a circuit diagram showing a configuration example of a pixel according to a modification example of the second embodiment of the present invention.

[0036] Fig.14 This is a timing chart showing an example of a pixel driving method according to the third embodiment of the present invention.

[0037] Fig.15 This is a timing chart showing an example of a pixel driving method according to a first modification of the third embodiment of the present invention.

[0038] Fig.16 This is a block diagram showing a configuration example of a solid-state imaging element according to a second modification of the third embodiment of the present invention.

[0039] Fig.17 This is a block diagram showing a configuration example of a pixel according to a second modification example of the third embodiment of the present invention.

[0040] Fig.18 This is a circuit diagram showing a configuration example of a pixel according to the fourth embodiment of the present invention.

[0041] Fig.19 This is a circuit diagram showing a configuration example of an address event detection unit according to the fifth embodiment of the present invention.

[0042] Fig. 20 This is a circuit diagram showing a configuration example of a logarithmic conversion unit according to the sixth embodiment of the present invention.

[0043] Fig.21 This is a circuit diagram showing a configuration example of a logarithmic conversion unit according to the seventh embodiment of the present invention.

[0044] Fig. 22 This is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0045] Fig.23 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0046] Description of reference numerals:

[0047] 100: camera device; 110: optical unit; 120: DSP circuit; 130: display unit; 140: operation unit; 150: bus; 160: frame memory; 170: storage unit; 180: power supply unit; 200: solid-state imaging element; 201: light receiving chip; 202: circuit chip; 211: DAC; 212: drive circuit; 213: X arbitrator; 215: control circuit; 216: Y arbitrator; 230: time code generation unit; 240: pixel array unit; 241: time code transmission unit; 250: column processing unit; 260: column ADC; 300: pixel; 305: photodiode; 306: N layer; 307: P layer; 310: pixel signal generation unit; 311: load MOS circuit; 320: ADC; 321: comparison circuit; 330: image Element circuit; 331: discharge transistor; 332, 337: transfer transistor; 333: reset transistor; 334: floating diffusion layer; 335: amplifier transistor; 336: selection transistor; 338: analog memory; 340: differential input circuit; 341, 342, 411, 412, 414, 415: PMOS transistors; 343~345, 413, 451, 452: NMOS transistors; 350: voltage conversion circuit; 360: positive feedback circuit; 370: data storage unit; 400: address event detection unit; 410: logarithmic conversion unit; 416, 421, 423: capacitor; 420: subtractor; 422: amplifier; 424: switch; 430: comparator; 440: AER logic circuit; 450: buffer; 12031: camera unit. DETAILED DESCRIPTION

[0048] Hereinafter, a method for implementing the present invention (hereinafter referred to as an embodiment) will be described. The description will be made in the following order.

[0049] 1. First Embodiment (Example of Generating Pixel Signals from Electrons and Detection Signals from Holes)

[0050] 2. Second Embodiment (Example of Generating Pixel Signals from Electrons and Detection Signals from Holes in a Solid-State Image Sensor with a Laminated Structure)

[0051] 3. Third Embodiment (Example of Generating Pixel Signals from Electrons in a Pixel Generating Detection Signals from Holes)

[0052] 4. Fourth Embodiment (Example of Generating Pixel Signals by Transferring Electrons to Analog Memory and Generating Detection Signals from Holes)

[0053] 5. Fifth Embodiment (Example of Providing a Buffer to Generate Pixel Signals from Electrons and Detection Signals from Holes)

[0054] 6. Sixth Embodiment (Example in which the cyclic circuit is set to two stages and pixel signals are generated from electrons and detection signals are generated from holes)

[0055] 7. Seventh Embodiment (Example of Adding Capacitors to Generate Pixel Signals from Electrons and Detection Signals from Holes)

[0056] 8. Application examples to mobile objects

[0057] <1. First embodiment>

[0058] [Configuration Example of Imaging Device]

[0059] Figure 1 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present invention. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. Furthermore, the imaging device 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As the imaging device 100, for example, in addition to digital cameras such as digital still cameras, a smartphone, a personal computer, a car camera, etc. having an imaging function are also assumed.

[0060] The optical unit 110 collects light from the subject and guides it to the solid-state imaging element 200. The solid-state imaging element 200 generates image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC. Here, the vertical synchronization signal VSYNC is a periodic signal of a predetermined frequency indicating the time of imaging. The solid-state imaging element 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.

[0061] The DSP circuit 120 performs predetermined signal processing on the image data from the solid-state imaging element 200. The DSP circuit 120 outputs the processed image data to the frame memory 160 and the like via the bus 150. The DSP circuit 120 is an example of a digital signal processing unit described in the claims.

[0062] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (ElectroLuminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal according to a user's operation.

[0063] The bus 150 is a common path for the optical section 110 , the solid-state imaging element 200 , the DSP circuit 120 , the display section 130 , the operation section 140 , the frame memory 160 , the storage section 170 , and the power supply section 180 to exchange data with each other.

[0064] The frame memory 160 stores image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display unit 130, and the like.

[0065] [Configuration Example of Solid-State Image Sensor]

[0066] Figure 2 1 is a block diagram showing an example of a configuration of a solid-state imaging element 200 according to the first embodiment of the present invention. The solid-state imaging element 200 includes a DAC (Digital to Analog Converter) 211, a driving circuit 212, an X arbitrator 213, a time code generating unit 230, a pixel array unit 240, a column processing unit 250, a control circuit 215, and a Y arbitrator 216. These circuits are configured on a single semiconductor chip, for example. In addition, a plurality of pixels are arranged in a two-dimensional grid in the pixel array unit 240. Hereinafter, a set of pixels arranged along a predetermined direction in the pixel array unit 240 is referred to as a "row", and a set of pixels arranged along a direction perpendicular to the row is referred to as a "column".

[0067] The DAC 211 generates an analog reference signal that changes in a ramp shape by DA (Digital to Analog) conversion and supplies the reference signal to the pixel array unit 240 .

[0068] The driving circuit 212 drives the pixels in the pixel array section 240 in synchronization with the vertical synchronization signal VSYNC.

[0069] The pixels in the pixel array unit 240 generate pixel signals respectively. In addition to generating pixel signals, the pixels also generate detection signals of address events. Here, address events include on events and off events, and the detection signals include 1-bit detection results of on events and 1-bit detection results of off events. An on event means that the change in brightness exceeds a prescribed upper threshold. On the other hand, an off event means that the change in brightness is lower than a prescribed lower threshold. In addition, the pixel detects both on events and off events, but may detect only one side.

[0070] The pixel supplies the pixel signal to the column processing unit 250. When detecting an address event, the pixel performs a request and a response transmission and reception (hereinafter referred to as "handshake") with the Y arbitrator 216 in order to output the detection signal of the address event externally. Next, the pixel performs a handshake with the X arbitrator 213.

[0071] The X arbitrator 213 arbitrates requests from each column and returns a response to the corresponding column based on the arbitration result.

[0072] The time code generation unit 230 generates a time code. The time code indicates a time during a period in which the reference signal changes in a ramp shape. The time code generation unit 230 supplies the generated time code to the pixel array unit 240 .

[0073] The column processing unit 250 performs signal processing such as correlated double sampling (CDS) processing on the pixel signal, and supplies the processed pixel signal to the DSP circuit 120 .

[0074] The Y arbitrator 216 arbitrates requests from each row and returns a response to the corresponding row based on the arbitration result.

[0075] Based on the requested arbitration result, the control circuit 215 outputs the detection signal of the address event to the DSP circuit 120. The detection signal of the address event for each pixel is arranged in a two-dimensional grid, thereby generating image data.

[0076] Hereinafter, the image data composed of the pixel signal output from the column processing unit 250 is referred to as "normal image data", and the image data composed of the detection signal of the address event is referred to as "AER image data". The data size of the pixel signal is larger than that of the detection signal, for example, 15 bits. Therefore, the normal image data has a higher image quality than the AER image data.

[0077] Normal image data and AER image data are used for various purposes. For example, if the camera device 100 is a vehicle-mounted camera, normal image data is displayed on a monitor, etc., for visual confirmation by the driver. On the other hand, AER image data is used in ASAS (Advanced Driver Assistance System) and the like to detect people and obstacles.

[0078] Furthermore, the solid-state imaging element 200 normally outputs all pixel signals of image data, but as described later, it may output only pixel signals of pixels for which address events have been generated.

[0079] [Configuration Example of Pixel Array Section]

[0080] Figure 31 is a block diagram showing a configuration example of the pixel array unit 240 according to the first embodiment of the present invention. The pixel array unit 240 includes a plurality of time code transmission units 241 and a plurality of pixels 300. The time code transmission unit 241 is arranged for each time code generation unit 230. The pixels 300 are arranged in a two-dimensional grid.

[0081] The timing code transmission section 241 transmits the timing code from the corresponding timing code generation section 230. The timing code transmission section 241 transmits the timing code from the corresponding timing code generation section 230 to the pixel 300, and further transmits the timing code from the pixel 300 to the column processing section 250 as a digital pixel signal.

[0082] [Pixel Configuration Example]

[0083] Figure 4 1 is a block diagram showing a configuration example of a pixel 300 according to the first embodiment of the present invention. The pixel 300 includes a photodiode 305, a pixel signal generating unit 310, and an address event detecting unit 400. In addition, one of the anode and the cathode of the photodiode 305 is connected to the pixel signal generating unit 310, and the other is connected to the address event detecting unit 400. For example, the cathode of the photodiode 305 is connected to the pixel signal generating unit 310, and the anode is connected to the address event detecting unit 400.

[0084] The pixel signal generating unit 310 generates a pixel signal having a voltage corresponding to the amount of charge from the photodiode 305. The pixel signal generating unit 310 converts the analog pixel signal into a digital signal (ie, a time code) and supplies the digital signal to the time code transmitting unit 241.

[0085] The address event detection unit 400 detects whether the amount of change in charge from the photodiode 305 exceeds a predetermined threshold value (i.e., an address event is generated) and generates a detection signal. When the address event is detected, the address event detection unit 400 performs handshakes with the X arbitrator 213 and the Y arbitrator 216. The address event detection unit 400 is an example of a detection unit described in the claims.

[0086] Figure 5 1 is an example of a cross-sectional view of the photodiode 305 according to the first embodiment of the present invention and a comparative example. a in the figure is an example of a cross-sectional view of the photodiode 305 according to the first embodiment, and b in the figure is an example of a cross-sectional view of the photodiode 305 according to the comparative example.

[0087] As shown in a in the figure, the photodiode 305 is composed of, for example, an N layer 306 and a P layer 307. The N layer 306 is connected to the pixel signal generating unit 310 via a cathode electrode. On the other hand, the P layer 307 is connected to the address event detecting unit 400 via an anode electrode.

[0088] The photodiode 305 generates electrons and holes through photoelectric conversion. The higher the brightness, the more electrons are generated. In addition, the number of holes generated is the same as the number of electrons. In the same figure, "e-" represents electrons, and "h + ” represents a hole. Among these charges, electrons are output to the pixel signal generating section 310 , and holes are output to the address event detecting section 400 .

[0089] On the other hand, as shown in b in the figure, in the comparative example, both the pixel signal generating unit 310 and the address event detecting unit 400 are connected to the cathode, and the anode is grounded. In this comparative example, a part of the electrons are output to the pixel signal generating unit 310, and the remaining electrons are output to the address event detecting unit 400. In addition, the holes are discharged to the ground terminal. In this way, in the configuration of the comparative example, among the electrons and the holes, only the electrons are used for the generation of the pixel signal and the detection of the address event, and the holes are not used for the generation of the pixel signal and the detection of the address event and are discharged.

[0090] In contrast, in the pixel 300 of the first embodiment, electrons are used to generate pixel signals, and holes are used to detect address events. Therefore, compared with the comparative example using only electrons, the level of the pixel signal becomes higher at the same brightness, and the detection accuracy of the address event is improved. As a result, the image quality of the normal image data and the AER image data is improved. In particular, the image quality in a dark place with low brightness can be improved.

[0091] In addition, the pixel signal and detection signal generated from electrons generally have less noise than those generated from holes. Therefore, by supplying electrons to the pixel signal generating unit 310 through the photodiode 305, the signal quality of the pixel signal can be improved. On the other hand, since holes are supplied to the address event detecting unit 400, although the noise of the detection signal increases, the detection signal of the address event is only 2 bits per pixel, and the increase in the noise has less impact than the pixel signal.

[0092] Furthermore, the cathode of the photodiode 305 is connected to the pixel signal generating unit 310 , and the anode is connected to the address event detecting unit 400 . However, the cathode may be connected to the address event detecting unit 400 , and the anode may be connected to the pixel signal generating unit 310 .

[0093] [Configuration Example of Pixel Signal Generating Unit]

[0094] Figure 61 is a block diagram showing a configuration example of a pixel signal generating unit 310 according to the first embodiment of the present invention. The pixel signal generating unit 310 includes an ADC (Analog-to-Digital Converter) 320 and a pixel circuit 330. In addition, the ADC 320 includes a comparison circuit 321 and a data storage unit 370. Furthermore, the comparison circuit 321 includes a differential input circuit 340, a voltage conversion circuit 350, and a positive feedback circuit 360.

[0095] The pixel circuit 330 generates a reset level or a signal level as a pixel signal SIG according to the control of the driving circuit 212. Here, the reset level is a voltage when the floating diffusion layer is initialized after the exposure starts, and the signal level is a voltage corresponding to the exposure amount when the exposure ends. The pixel circuit 330 supplies the reset level and the signal level to the differential input circuit 340 in sequence.

[0096] ADC320 converts the pixel signal SIG (reset level or signal level) into a digital signal AD (Analog-to-Digital). The data after the reset level is AD-converted is referred to as "P-phase data" below. In addition, the data after the signal level is AD-converted is referred to as "D-phase data" below.

[0097] The differential input circuit 340 in the ADC 320 compares the reference signal REF from the DAC 211 with the pixel signal SIG from the pixel circuit 330. The differential input circuit 340 supplies a comparison result signal indicating the comparison result to the voltage conversion circuit 350.

[0098] The voltage conversion circuit 350 converts the voltage of the comparison result signal from the differential input circuit 340 and outputs it to the positive feedback circuit 360 .

[0099] The positive feedback circuit 360 adds a part of the output to the input (comparison result signal), and outputs the result to the data storage unit 370 as the output signal VCO.

[0100] The data storage unit 370 stores the time code when the output signal VCO is inverted. The data storage unit 370 outputs the time code corresponding to the reset level as P-phase data and the time code corresponding to the signal level as D-phase data according to the control of the drive circuit 212.

[0101] [Configuration Example of Address Event Detection Unit]

[0102] Figure 7 1 is a block diagram showing a configuration example of the address event detection unit 400 according to the first embodiment of the present invention. The address event detection unit 400 includes a logarithmic conversion unit 410 , a subtractor 420 , a comparator 430 , and an AER logic circuit 440 .

[0103] The logarithmic converter 410 logarithmically converts the photocurrent composed of charges (holes, etc.) generated by the photodiode 305 into a voltage. The logarithmic converter 410 supplies the converted voltage signal to the subtractor 420. The logarithmic converter 410 is an example of a converter described in the claims.

[0104] The subtractor 420 obtains the amount of change of the voltage signal by subtracting, and supplies a differential signal indicating the amount of change to the comparator 430. The differential signal is initialized by the reset signal xrst.

[0105] The comparator 430 compares the differential signal from the subtractor 420 with the upper threshold value Vbon and the lower threshold value Vboff, respectively. The comparator 430 outputs the comparison result of the differential signal with the upper threshold value Vbon as the detection result VCH of the on event to the AER logic circuit 440. In addition, the comparator 430 outputs the comparison result of the differential signal with the lower threshold value Vboff as the detection result VCL of the off event to the AER logic circuit 440.

[0106] The AER logic circuit 440 performs handshake based on the detection signal composed of the detection results VCH and VCL. When an address event occurs, the AER logic circuit 440 performs handshake with the Y arbiter 216. Next, the AER logic circuit 440 performs handshake with the X arbiter 213, and resets the subtractor 420 through the reset signal xrst when a response is received.

[0107] Figure 8 3 is a circuit diagram showing a configuration example of a pixel 300 according to the first embodiment of the present invention. The pixel signal generating unit 310 includes a pixel circuit 330, a load MOS circuit 311, a comparison circuit 321, and a data storage unit 370. In addition, the pixel circuit 330 includes a discharge transistor 331, a transfer transistor 332, a reset transistor 333, a floating diffusion layer 334, an amplifier transistor 335, and a selection transistor 336. As the discharge transistor 331, the transfer transistor 332, the reset transistor 333, the amplifier transistor 335, and the selection transistor 336, for example, an NMOS (N-type Metal Oxide Semiconductor) transistor is used. In addition, the discharge transistor 331 and the transfer transistor 332 are connected to the cathode of the photodiode 305.

[0108] The discharge transistor 331 discharges the charges (electrons, etc.) of the photodiode 305 according to the drive signal OFG from the drive circuit 212 .

[0109] The transfer transistor 332 transfers charges from the photodiode 305 to the floating diffusion layer 334 according to a transfer signal TRG from the drive circuit 212 .

[0110] The reset transistor 333 initializes the amount of charge in the floating diffusion layer 334 according to the reset signal RST from the drive circuit 212 .

[0111] The floating diffusion layer 334 accumulates the transferred charges and generates a voltage corresponding to the amount of the charges. The amplifier transistor 335 amplifies the voltage of the floating diffusion layer 334 .

[0112] The selection transistor 336 supplies the amplified voltage signal as the pixel signal SIG to the comparison circuit 321 in accordance with the selection signal SEL from the drive circuit 212 .

[0113] The load MOS circuit 311 is inserted between the source of the selection transistor 336 and the ground terminal.

[0114] The driving circuit 212 initializes the floating diffusion layer 334 for all pixels by the reset signal RST when exposure starts, and transfers the charge by the transfer signal TRG when exposure ends, in synchronization with the vertical synchronization signal VSYNC. In other words, a global shutter system is used. In addition, the driving circuit 212 selects rows in sequence by the selection signal SEL and outputs pixel signals.

[0115] In addition, the address event detection unit 400 includes a logarithmic conversion unit 410, a subtractor 420, a comparator 430, and an AER logic circuit 440. The logarithmic conversion unit 410 includes PMOS (P-type Metal Oxide Semiconductor) transistors 411 and 412 and an NMOS transistor 413. The subtractor 420 includes capacitors 421 and 423, an amplifier 422, and a switch 424.

[0116] In the logarithmic conversion unit 410, the source of the PMOS transistor 411 is connected to the anode of the photodiode 305, and the drain is grounded. In addition, the PMOS transistor 412 and the NMOS transistor 413 are connected in series between the power supply terminal and the ground terminal, and the gate of the PMOS transistor 412 is connected to the anode of the photodiode 305. In addition, the gate of the PMOS transistor 411 is connected to the connection point of the PMOS transistor 412 and the NMOS transistor 413, and the gate of the NMOS transistor 413 is connected to the power supply terminal. The photocurrent from the photodiode 305 is converted into a voltage signal in a logarithmic manner by these ring-connected PMOS transistors 411 and 412, and output from the connection point of the PMOS transistor 412 and the NMOS transistor 413.

[0117] In the subtractor 420, one end of the capacitor 421 is connected to the output terminal of the logarithmic converter 410, and the other end is connected to the input terminal of the amplifier 422. The capacitor 423 is connected in parallel to the amplifier 422. The switch 424 opens and closes the path connecting the two ends of the capacitor 423 according to the reset signal xrst.

[0118] The amplifier 422 amplifies the voltage signal input via the capacitor 421 . The amplifier 422 outputs the amplified signal to the comparator 430 .

[0119] When the switch 424 is turned on, a voltage signal V is input to the logarithmic conversion unit 410 side of the capacitor 421. init , and the opposite side becomes the virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacitance of capacitor 421 is set to C1, the potential Q accumulated in capacitor 421 is init It is expressed by the following equation: On the other hand, since both ends of the capacitor 423 are short-circuited, the accumulated charge is zero.

[0120] Q init =C1×V init ……Formula 1

[0121] Next, the switch 424 is turned off, and the voltage change on the input side of the capacitor 421 becomes V after In the case of after It is expressed by the following formula.

[0122] Q after =C1×V after ……Formula 2

[0123] On the other hand, when the output voltage is Vout, the charge Q2 accumulated in the capacitor 423 is expressed by the following equation.

[0124] Q2=-C2×Vout……Equation 3

[0125] At this time, since the total charge amount of the capacitors 421 and 423 does not change, the following equation holds.

[0126] Q init =Q after +Q2……Formula 4

[0127] When equations 1 to 3 are substituted into equation 4 and transformed, the following equation can be obtained.

[0128] Vout=-(C1 / C2)×(V after -V init )……Formula 5

[0129] Formula 5 represents the subtraction action of the voltage signal, and the gain of the subtraction result becomes C1 / C2. Normally, since it is desired to maximize the gain, it is preferred to design C1 to be larger and C2 to be smaller. On the other hand, if C2 is too small, the KTC noise increases and the noise characteristics may deteriorate. Therefore, the capacitance reduction of C2 is limited to a range that allows noise. In addition, since an address event detection unit 400 including a subtractor 420 is mounted for each pixel, there are area limitations on capacitors C1 and C2. Taking these factors into consideration, for example, C1 is set to a value of 20 to 200 femtofarads (fF), and C2 is set to a value of 1 to 20 femtofarads (fF).

[0130] [Operation Example of Solid-State Image Sensor]

[0131] Fig. 9 This is a flowchart showing an example of the image capture process according to the first embodiment of the present invention. This image capture process is started when, for example, an application for capturing normal image data is executed.

[0132] The solid-state imaging element 200 determines whether it is the rising moment of VSYNC (step S911). If it is the rising moment of VSYNC (step S911: Yes), the pixels in the solid-state imaging element 200 convert the reset level into P-phase data just before the end of exposure (step S912). Then, the pixel transfers the charge to the FD at the end of exposure (step S913) and converts the signal level into D-phase data (step S914). Then, the solid-state imaging element 200 performs CDS processing (step S915). Before the rising moment of VSYNC (step S911: No), or after step S915, the solid-state imaging element 200 repeatedly performs the steps after step S911.

[0133] Fig.10 This is a flowchart showing an example of the AER process according to the first embodiment of the present invention. The AER process is started when, for example, an application program for AER is executed.

[0134] The pixel 300 in the solid-state imaging element 200 determines whether the amount of change in brightness exceeds the upper threshold value (step S921). When the amount of change is below the upper threshold value (step S921: No), the pixel 300 determines whether the amount of change in brightness is below the lower threshold value (step S922). When the amount of change is below the lower threshold value (step S922: Yes), the pixel 300 detects a disconnection event (step S923). On the other hand, when the amount of change exceeds the upper threshold value (step S921: Yes), the pixel 300 detects a connection event (step S924).

[0135] After step S923 or S924, the pixel 300 transmits the detection result of the address event by handshake (step S925), and repeatedly executes the steps after step S921. In addition, when the change amount is greater than the lower limit threshold (step S922: No), the pixel 300 repeatedly executes the steps after step S921.

[0136] As described above, according to the first embodiment of the present invention, the pixel signal generating unit 310 generates pixel signals from electrons and the address event detecting unit 400 detects address events from holes, thereby improving the image quality of image data compared to the case of using only electrons.

[0137] <2. Second Embodiment>

[0138] In the first embodiment described above, the pixel 300 is arranged on a single semiconductor chip, but as the number of pixels increases, the circuit scale of the semiconductor chip is likely to increase. The solid-state imaging element 200 of the second embodiment is different from the first embodiment in that the circuits in the pixel 300 are dispersedly arranged on a plurality of stacked chips.

[0139] Fig.11 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to the first embodiment of the present invention. The solid-state imaging element 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection portion such as a through hole. In addition to the through hole, connection can also be performed by Cu-Cu bonding or bumps.

[0140] Fig.12 1 is a circuit diagram showing a configuration example of a pixel 300 according to a second embodiment of the present invention. In the pixel 300 according to the second embodiment, the pixel circuit 330 does not include an amplifier transistor 335 and a selection transistor 336, and the voltage signal of the floating diffusion layer 334 is directly input as a pixel signal SIG to a differential input circuit 340 in a comparison circuit 321.

[0141] Furthermore, the differential input circuit 340 includes PMOS transistors 341 and 342 , and NMOS transistors 343 to 345 .

[0142] The PMOS transistor 341 and the NMOS transistor 343 are connected in series between a power supply terminal and a drain of the NMOS transistor 345. The PMOS transistor 342 and the NMOS transistor 344 are connected in series between a power supply terminal and a drain of the NMOS transistor 345.

[0143] The gate of the PMOS transistor 342 is connected to the gate of the PMOS transistor 341 and the drain of the PMOS transistor 342. The pixel signal SIG from the pixel circuit 330 is input to the gate of the NMOS transistor 343, and the reference signal REF from the DAC 211 is input to the gate of the NMOS transistor 344. The connection point between the PMOS transistor 341 and the NMOS transistor 343 is connected to the voltage conversion circuit 350.

[0144] In the above circuit configuration, the pixel circuit 330 and the NMOS transistors 343 to 345 in the differential input circuit 340 are arranged in the light receiving chip 201. In addition, the PMOS transistors 341 and 342 in the differential input circuit 340 and the subsequent circuits and the address event detection unit 400 are arranged in the circuit chip 202. The DAC 211, the drive circuit 212, the X arbitrator 213, the time code generation unit 230, the column processing unit 250, the control circuit 215, and the Y arbitrator 216 in the solid-state imaging element 200 are arranged in the circuit chip 202.

[0145] Furthermore, although the circuits and elements in the solid-state imaging element 200 are dispersedly arranged in two chips (the light receiving chip 201 and the circuit chip 202 ), they may be dispersedly arranged in three or more stacked chips.

[0146] As described above, in the second embodiment of the present invention, since the circuits in the solid-state imaging element 200 are dispersedly arranged in the light receiving chip 201 and the circuit chip 202, the circuit scale of each chip can be reduced compared to the case where the circuits are arranged in a single chip.

[0147] [Modifications]

[0148] In the above-mentioned second embodiment, the pixel circuit 330 and the NMOS transistors 343 to 345 in the comparison circuit 321 are arranged in the light receiving chip 201, but the larger the number of pixels, the larger the circuit scale of the light receiving chip 201 is likely to be. The solid-state imaging element 200 of the modified example of the second embodiment is different from the second embodiment in that the pixel circuit 330 is arranged in the light receiving chip 201, and the entire comparison circuit 321 is arranged in the circuit chip 202.

[0149] Fig.13 1 is a circuit diagram showing a configuration example of a pixel 300 according to a modification of the second embodiment of the present invention. In the modification of the second embodiment, the pixel circuit 330 includes an amplifying transistor 335 and a selecting transistor 336 similarly to the first embodiment.

[0150] In addition, the pixel circuit 330 and the load MOS circuit 311 are arranged in the light receiving chip 201 , and the comparison circuit 321 and the like other than these are arranged in the circuit chip 202 .

[0151] Thus, in the modification of the second embodiment of the present invention, the pixel circuit 330 is arranged in the light receiving chip 201 and the entire comparison circuit 321 is arranged in the circuit chip 202. Therefore, the circuit scale of the light receiving chip 201 can be reduced compared with the second embodiment.

[0152] <3. Third embodiment>

[0153] In the first embodiment described above, the pixel signals of all pixels are read out in synchronization with the vertical synchronization signal VSYNC, but as the number of pixels increases, the circuit scale may increase and the power consumption may increase. The solid-state imaging element 200 of the third embodiment is different from the first embodiment in that only the pixel signals of the pixels where the address event occurs are read out.

[0154] Fig.14 1 is a timing diagram showing an example of a driving method of the pixel 300 according to the third embodiment of the present invention. The control circuit 215 supplies a detection signal of an address event to the driving circuit 212. The vertical synchronization signal VSYNC is not input to the solid-state imaging element 200. In addition, the driving circuit 212 drives only the pixel in which the address event has occurred among all the pixels to generate a pixel signal. Then, only the pixel signal of the pixel in which the address event has occurred is read out.

[0155] For example, it is assumed that at time T1, the control circuit 215 outputs a detection signal of a certain pixel 300. The drive circuit 212 supplies a reset signal RST to the pixel 300 to start exposure. Then, at time T2 just before the end of exposure, the comparator circuit 321 outputs an output signal VCO to start AD conversion (in other words, readout) of the reset level.

[0156] The drive circuit 212 supplies the transfer signal TRG at time T3 when exposure ends, and immediately thereafter, at time T4, the comparator circuit 321 outputs the output signal VCO, and AD conversion (reading) of the signal level is started.

[0157] Furthermore, the solid-state imaging element 200 reads out the pixel signal of one pixel when an address event occurs, but it is also possible to read out the pixel signals of a plurality of pixels. For example, the pixel array unit 240 is divided into pixel blocks of a certain size each consisting of a plurality of pixels, and when an address event occurs in a certain pixel block, it is sufficient to read out the pixel signals of the plurality of pixels in the block.

[0158] Thus, according to the third embodiment of the present invention, since the solid-state imaging element 200 reads out only the pixel signals of the pixels in which the address event has occurred among all the pixels, the power consumption of the solid-state imaging element 200 can be reduced compared to the case where all the pixels are read out. In addition, the reading speed can be increased compared to the case where all the pixels are read out.

[0159] [First Modification]

[0160] In the third embodiment, only the pixel in which the address event has occurred among all the pixels is exposed and read out. However, if the exposure timing is different for each pixel, the output timing of the pixel signal will vary for each pixel. The solid-state imaging element 200 of the first variation of the third embodiment is different from the third embodiment in that all the pixels are exposed and only the pixel signal of the pixel in which the address event has occurred is output.

[0161] Fig.15 2 is a timing chart showing an example of a method for driving the pixel 300 according to the first modification of the third embodiment of the present invention. The driving circuit 212 simultaneously exposes all pixels in synchronization with the vertical synchronization signal VSYNC. In other words, a global shutter system is used.

[0162] For example, the driver circuit 212 supplies reset signals RSTn such as RST1, RST2, and RST3 to all pixels at the time T10 when exposure starts. RSTn (n is an integer) is supplied to the pixel Pn. Then, at the time T20 when exposure ends, the driver circuit 212 supplies the transfer signal TRGn to all pixels. Thus, all pixels are exposed at the same time.

[0163] Then, during the exposure period from time T10 to time T20 , the drive circuit 212 controls the column processing unit 250 to output a pixel signal for the pixel for which the address event is detected.

[0164] For example, at time T11 and T12, the detection signals of pixels P1 and P2 are output by the control circuit 215, and the detection signal of pixel P3 is not output. In this case, the drive circuit 212 causes the column processing unit 250 to output the pixel signals of pixels P1 and P2 at time T21 immediately after the exposure ends. Thus, the output timing of pixels P1 and P2 can be made consistent with the timing synchronized with the vertical synchronization signal VSYNC.

[0165] As described above, according to the first variation of the third embodiment of the present invention, the drive circuit 212 exposes all pixels and outputs pixel signals only for pixels where address events have occurred. Therefore, the output timings of the pixel signals of these pixels can be made consistent.

[0166] [Second Modification]

[0167] In the third embodiment described above, ADC 320 is provided for each pixel, and AD conversion (in other words, reading) is performed only on the pixel signal of the pixel where the address event has occurred. However, in the configuration in which ADC 320 is configured for each pixel, the circuit scale of the pixel 300 becomes larger. The solid-state imaging element 200 involved in the second variation of the third embodiment is different from the third embodiment in that ADC is configured for each column.

[0168] Fig.16 This is a block diagram showing a configuration example of a solid-state imaging element 200 according to a second variation of the third embodiment of the present invention. The solid-state imaging element 200 according to the second variation of the third embodiment is different from the third embodiment in that a column ADC 260 is provided instead of the column processing unit 250. In the column ADC 260, an ADC is provided for each column.

[0169] Furthermore, in the second modification of the third embodiment, the control circuit 215 controls the column ADC 260 to perform AD conversion only on the pixel signal from the column in which the address event is detected.

[0170] Fig.17 1 is a block diagram showing a configuration example of a pixel 300 according to a second variant of the third embodiment of the present invention. The second variant of the third embodiment is different from the third embodiment in that the pixel 300 is not provided with an ADC 320. The pixel circuit 330 supplies an analog pixel signal to the column ADC 260 via a vertical signal line VSL wired for each column.

[0171] As described above, in the second modification of the third embodiment of the present invention, the ADC is arranged for each column, and thus the circuit scale of the pixel 300 can be reduced compared to the case where the ADC is arranged for each pixel.

[0172] <4. Fourth embodiment>

[0173] In the first embodiment described above, the pixel signal is AD-converted after the exposure of the pixel 300 is completed, but the next exposure cannot be started during the AD conversion due to noise generated by the initialization of the photodiode 305. The pixel 300 of the fourth embodiment is different from the first embodiment in that the exposure can be started during the AD conversion by adding an analog memory and a transfer transistor.

[0174] Fig.18 : is a circuit diagram showing a configuration example of a pixel 300 according to a fourth embodiment of the present invention. The pixel 300 according to the fourth embodiment differs from the pixel 300 according to the first embodiment in that it further includes a transfer transistor 337 and an analog memory 338. As the transfer transistor 337, for example, an NMOS transistor is used.

[0175] The transfer transistor 337 transfers charge from the photodiode 305 to the analog memory 338 according to the transfer signal TRX from the drive circuit 212. The transfer transistor 337 is an example of a first transfer transistor described in the claims, and the transfer transistor 332 is an example of a second transfer transistor described in the claims.

[0176] The analog memory 338 accumulates charges. The analog memory 338 is also established in terms of wiring capacitance in principle, but in order to transfer charges to the floating diffusion layer 334, it is preferable to use an embedded type fully depletable capacitor. The analog memory 338 is an example of a charge storage unit described in the claims.

[0177] When the exposure period ends, the driving circuit 212 transfers the charge from the photodiode 305 to the analog memory 338 by the transfer signal TRX, and initializes the floating diffusion layer 334 by the reset signal RST. The ADC 320 starts AD conversion at the reset level.

[0178] When AD conversion of the reset level is completed, the driver circuit 212 transfers the charge from the analog memory 338 to the floating diffusion layer 334 through the transfer signal TRG. The ADC 320 starts AD conversion of the signal level.

[0179] As described above, since the charge of the photodiode 305 is transferred to the analog memory 338 before AD conversion, the drive circuit 212 can start the next exposure by the drive signal OFG during AD conversion.

[0180] As described above, according to the fourth embodiment of the present invention, when the exposure period ends, the transfer transistor 337 transfers the charge from the photodiode 305 to the analog memory 338 , so that the next exposure can be started during AD conversion.

[0181] <5. Fifth embodiment>

[0182] In the first embodiment described above, the logarithmic converter 410 supplies the voltage signal to the subtractor 420. However, in this configuration, the driving force of the circuits after the subtractor 420 may be insufficient. The address event detector 400 of the fifth embodiment is different from the first embodiment in that a buffer 450 is provided to increase the driving force.

[0183] Fig.19 1 is a circuit diagram showing a configuration example of an address event detection unit 400 according to a fifth embodiment of the present invention. The address event detection unit 400 according to the fifth embodiment is different from the first embodiment in that a buffer 450 is further provided.

[0184] The buffer 450 outputs the voltage signal from the logarithmic conversion unit 410 to the subtractor 420. The buffer 450 includes NMOS transistors 451 and 452. These transistors are connected in series between the power supply terminal and the ground terminal. In addition, the gate of the NMOS transistor 451 is connected to the logarithmic conversion unit 410, and the connection point of the NMOS transistors 451 and 452 is connected to the subtractor 420. The gate of the NMOS transistor 452 is connected to the power supply terminal.

[0185] The buffer 450 can improve the driving force of the subsequent stage after the subtractor 420. In addition, the buffer 450 can ensure isolation of noise accompanying the switching operation of the subsequent stage.

[0186] As described above, in the fifth embodiment of the present invention, since the buffer 450 is arranged before the subtractor 420 , the driving force of the circuits after the subtractor 420 can be improved.

[0187] <6. Sixth embodiment>

[0188] In the first embodiment described above, only one loop circuit composed of PMOS transistors 411 and 412 is configured in the logarithmic converter 410. However, when there is only one loop circuit, the conversion gain when converting current into voltage may be insufficient. The logarithmic converter 410 of the sixth embodiment is different from the first embodiment in that a two-stage loop circuit is provided.

[0189] Fig. 20 1 is a circuit diagram showing a configuration example of a logarithmic converter 410 according to a sixth embodiment of the present invention. The logarithmic converter 410 of the sixth embodiment is different from the first embodiment in that PMOS transistors 414 and 415 are further provided.

[0190] The PMOS transistors 411 and 414 are connected in series between the photodiode 305 and the ground terminal, and the PMOS transistors 412 and 415 are connected in series with the NMOS transistor 413 between the power supply terminal and the ground terminal. In addition, the gate of the PMOS transistor 411 is connected to the connection point of the PMOS transistors 412 and 415, and the gate of the PMOS transistor 414 is connected to the connection point of the PMOS transistor 415 and the NMOS transistor 413.

[0191] On the other hand, the gate of the PMOS transistor 412 is connected to the connection point between the photodiode 305 and the PMOS transistor 411. The gate of the PMOS transistor 415 is connected to the connection point between the PMOS transistors 411 and 414. In addition, the connection point between the PMOS transistor 415 and the NMOS transistor 413 is connected to the subtractor 420.

[0192] As described above, since the ring circuit composed of the PMOS transistors 411 and 412 and the ring circuit composed of the PMOS transistors 414 and 415 are connected in two stages, the conversion gain is doubled compared to the case of only one stage of the ring circuit.

[0193] As described above, in the sixth embodiment of the present invention, a two-stage loop circuit is provided in the logarithmic converter 410 , so that the conversion gain can be increased compared to the case where only a one-stage loop circuit is provided.

[0194] <7. Seventh embodiment>

[0195] In the first embodiment described above, the PMOS transistors 411 and 412 are connected in a loop in the logarithmic converter 410, but the loop circuit is a negative feedback circuit, and the voltage signal may oscillate under certain conditions. The logarithmic converter 410 of the seventh embodiment is different from the first embodiment in that stability can be improved by adding a capacitor.

[0196] Fig.21 1 is a circuit diagram showing a configuration example of a logarithmic converter 410 according to a seventh embodiment of the present invention. The logarithmic converter 410 of the seventh embodiment is different from the first embodiment in that a capacitor 416 is further provided.

[0197] One end of the capacitor 416 is connected to the gate of the PMOS transistor 412, and the other end is connected to the gate of the PMOS transistor 411. The phase delay of the voltage signal can be compensated by the capacitor 416. For example, in addition to the capacitor, a capacitance element such as a wiring capacitance and a transistor can also be used as the capacitor 416.

[0198] Here, when the capacitor 416 is not provided, the transfer function of the loop circuit formed by the PMOS transistors 411 and 412 is expressed by the following equation.

[0199]

Formula 1

[0200]

[0201] In the above formula, g m is the mutual conductance of the PMOS transistor 411, G m represents the mutual conductance of the PMOS transistor 412. R0 is the output resistance of the loop circuit, and s is a complex number. pd is the capacitance on the source side of the PMOS transistor 411, and C0 is the gate capacitance of the PMOS transistor 411. The unit of mutual conductance is, for example, Siemens (S), and the unit of resistance is, for example, Ohm (Ω). In addition, the unit of capacitance is, for example, Farad (F).

[0202] In contrast, the transfer function of the open loop gain of the loop circuit provided with the capacitor 416 is considered, assuming that the capacitance value of the capacitor is C C It is smaller than the parasitic capacitance added to the output terminal and is expressed by the following equation.

[0203]

Formula 2

[0204]

[0205] In addition, in C C The following relationship holds between C0 and . This relationship is a proper process in design.

[0206] C C <<C0……Formula 8

[0207] According to formula 7, by adding capacitors, m / C C The position of this zero point is related to g m Therefore, considering the pole (i.e., g m / C PD +C C The relationship between the poles) is C Designed to be a capacitance value C C With C pd +C C The capacitance value C C Preferably in C pd / 3 to C pd / 2.

[0208] As described above, in the seventh embodiment of the present invention, the capacitor 416 is added to the loop circuit, so that the phase delay of the voltage signal can be compensated. As a result, the stability of the logarithmic conversion unit 410 can be improved.

[0209] <8. Application examples to mobile objects>

[0210] The technology of the present invention (the present technology) can be applied to various products. For example, the technology of the present invention can be implemented as a device mounted on any mobile body such as an automobile, an electric car, a hybrid electric car, a two-wheeled motor vehicle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0211] Fig. 22 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology of the present invention can be applied.

[0212] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig. 22 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0213] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor for generating a vehicle drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0214] The body system control unit 12020 controls the actions of various devices equipped on the body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, taillights, brake lights, indicator lights, or fog lights. In this case, radio waves or signals of various switches sent from a mobile device that replaces the key can be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals and controls the door lock device, power window device, and lights of the vehicle.

[0215] The vehicle exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to a camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image outside the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 may also perform object detection processing or distance detection processing of a person, a vehicle, an obstacle, a sign, or text on the road surface based on the received image.

[0216] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0217] The in-vehicle information detection unit 12040 detects information in the vehicle. For example, a driver state detection unit 12041 for detecting the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera for photographing the driver. The in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, and can also determine whether the driver is dozing off.

[0218] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output a control instruction to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control, and the coordinated control is aimed at realizing the functions of ASAS (Advanced Driver Assistance System) including vehicle collision avoidance or impact mitigation, following driving based on vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning or vehicle deviation warning.

[0219] In addition, the microcomputer 12051 can control the driving force generating device, steering mechanism or braking device based on the information about the vehicle surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for the purpose of automatic driving that allows the vehicle to travel autonomously without relying on the driver's operation.

[0220] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030, and perform coordinated control for the purpose of anti-glare, such as switching the high beam to the low beam.

[0221] The audio and video output unit 12052 can send an output signal of at least one of audio and video to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. Fig. 22 In the example of FIG. 1 , as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0222] Fig.23 This is a diagram showing an example of the installation position of the camera unit 12031.

[0223] exist Fig.23 In the figure, as the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104, and 12105.

[0224] The camera units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front bumper, side mirrors, rear bumper, trunk door, and upper portion of the front windshield in the vehicle 12100. The camera unit 12101 provided on the front bumper and the camera unit 12105 provided on the upper portion of the front windshield in the vehicle are mainly used to obtain images in front of the vehicle 12100. The camera units 12102 and 12103 provided on the side mirrors are mainly used to obtain images on the side of the vehicle 12100. The camera unit 12104 provided on the rear bumper or trunk door is mainly used to obtain images on the rear of the vehicle 12100. The camera unit 12105 provided on the upper portion of the front windshield in the vehicle is mainly used to detect the vehicle in front or pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0225] In addition, Fig.23 1 shows an example of the photographing range of the camera units 12101 to 12104. The photographing range 12111 indicates the photographing range of the camera unit 12101 provided at the front bumper, the photographing ranges 12112 and 12113 indicate the photographing ranges of the camera units 12102 and 12103 provided at the side mirrors, respectively, and the photographing range 12114 indicates the photographing range of the camera unit 12104 provided at the rear bumper or the trunk door. For example, the image data photographed by the camera units 12101 to 12104 are overlapped, thereby obtaining a bird's-eye view image of the vehicle 12100 observed from above.

[0226] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 1210 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for detecting phase differences.

[0227] For example, the microcomputer 12051 obtains the distance to each solid object within the shooting range 12111 to 12114 and the time change of the distance (relative speed to the vehicle 12100) based on the distance information obtained by the camera units 12101 to 12104, thereby extracting the closest solid object on the driving path of the vehicle 12100 and the solid object traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 as the leading vehicle. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be ensured in advance in front of the leading vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, coordinated control for the purpose of autonomous driving that is independent of the driver's operation can be performed.

[0228] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, etc. and other three-dimensional objects based on the distance information obtained by the camera units 12101 to 12104, and extract them for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually confirmed by the driver of the vehicle 12100 and obstacles that are difficult to visually confirm. Then, the microcomputer 12051 determines the collision risk indicating the degree of danger of collision with each obstacle. When the collision risk is greater than the set value and there is a possibility of collision, an alarm is output to the driver via the audio speaker 12061 and the display unit 12062, or forced deceleration or evasive steering is performed via the drive system control unit 12010, thereby performing driving assistance for avoiding collision.

[0229] At least one of the camera units 12101 to 12104 may also be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether there are pedestrians in the camera images of the camera units 12101 to 12104. For example, the identification of pedestrians is performed by extracting feature points in the camera images of the camera units 12101 to 12104, which are infrared cameras, and performing a pattern matching process on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that there are pedestrians in the camera images of the camera units 12101 to 12104, when a pedestrian is identified, the sound and image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed overlapping the identified pedestrian. In addition, the sound and image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian is displayed at a desired position.

[0230] An example of a vehicle control system to which the technology of the present invention can be applied is described above. The technology of the present invention can be applied to the camera unit 12031 in the configuration described above. Specifically, the camera device 100 can be applied to the camera unit 12031. By applying the technology of the present invention to the camera unit 12031, the image quality can be improved, and a captured image that is easier to view can be obtained, which can reduce the fatigue of the driver.

[0231] In addition, the above-mentioned embodiment represents an example for concretizing the present invention, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention-specific matters in the claims and the matters in the embodiment of the present invention marked with the same name have a corresponding relationship. However, the present invention is not limited to the embodiment, and can be concretized by variously modifying the embodiment within the scope of the present invention.

[0232] In addition, the processing steps described in the above embodiments can be understood as a method having such a series of steps, and can also be understood as a program for causing a computer to execute such a series of steps or even a recording medium storing such a program. As such a recording medium, for example, a CD (Compact Disc), an MD (Mini Disc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray Disc (Blu-ray (registered trademark) Disc), etc. can be used.

[0233] In addition, the effects described in this specification are merely illustrative and not limiting, and other effects may also be present.

[0234] Furthermore, the present invention can adopt the following structures.

[0235] (1) A solid-state imaging device comprising:

[0236] Photodiodes generate electrons and holes through photoelectric conversion;

[0237] a pixel signal generating unit that generates a pixel signal having a voltage corresponding to an amount of one of the electrons and the holes; and

[0238] The detection unit detects whether a change amount of the other of the electrons and the holes exceeds a predetermined threshold value, and outputs a detection signal.

[0239] (2) In the solid-state imaging element described in (1),

[0240] The pixel signal generating unit generates the pixel signal having a voltage corresponding to the amount of the electrons.

[0241] The detection unit detects whether the amount of change in the cavitation exceeds the threshold value.

[0242] (3) In the solid-state imaging device described in (1) or (2),

[0243] A portion of the pixel signal generating unit and the photodiode are arranged on a predetermined light receiving chip.

[0244] The remaining part of the pixel signal generating unit and the detecting unit are arranged on a predetermined circuit chip.

[0245] (4) In the solid-state imaging element described in (3),

[0246] The pixel signal generating unit comprises:

[0247] A pixel circuit that generates the pixel signal; and

[0248] A comparison circuit compares the pixel signal with a predetermined reference signal.

[0249] A part of the comparison circuit, the photodiode and the pixel circuit are arranged on the light receiving chip.

[0250] The remaining part of the comparison circuit and the detection unit are configured on the circuit chip.

[0251] (5) In the solid-state imaging element described in (3),

[0252] The pixel signal generating unit comprises:

[0253] A pixel circuit, generating the pixel signal;

[0254] A comparison circuit compares the pixel signal with a predetermined reference signal.

[0255] The photodiode and the pixel circuit are arranged on the light receiving chip.

[0256] The comparison circuit and the detection unit are disposed on the circuit chip.

[0257] (6) In the solid-state imaging device described in any one of (1) to (5),

[0258] The device further includes a driving unit configured to drive the pixel signal generating unit to generate the pixel signal when the detecting unit detects that the amount of change exceeds the threshold value.

[0259] (7) In the solid-state imaging device described in any one of (1) to (5),

[0260] The solid-state imaging element comprises:

[0261] a column processing unit that performs predetermined signal processing on the pixel signal and outputs the pixel signal; and

[0262] The control circuit controls the column processing unit to output the pixel signal when detecting that the change amount exceeds the threshold value within a predetermined exposure period.

[0263] (8) In the solid-state imaging device described in any one of (1) to (7),

[0264] The photodiode, the pixel signal generating unit, and the detecting unit are respectively arranged in a plurality of pixels.

[0265] The pixel signal generating unit comprises:

[0266] A pixel circuit, generating an analog pixel signal; and

[0267] The analog-to-digital converter converts the pixel signal into a digital signal and outputs the digital signal.

[0268] (9) In the solid-state imaging device described in any one of (1) to (7),

[0269] It also includes an analog-to-digital converter to convert the analog pixel signal into a digital signal.

[0270] The photodiode, the pixel signal generating unit, and the detecting unit are respectively arranged in a plurality of pixels.

[0271] The pixel signal generating unit generates the analog pixel signal and outputs the analog pixel signal to the analog-to-digital converter.

[0272] (10) In the solid-state imaging device described in any one of (1) to (9),

[0273] The pixel signal generating unit comprises:

[0274] a charge storage unit for storing charges of one of the electrons and the holes;

[0275] a floating diffusion layer that accumulates the charges and converts them into the voltage corresponding to the amount of the charges;

[0276] a first transfer transistor that transfers the charge from the photodiode to a charge storage unit; and

[0277] The second transfer transistor transfers the charge from the charge storage unit to the floating diffusion layer.

[0278] (11) In the solid-state imaging device described in any one of (1) to (11),

[0279] The detection unit comprises:

[0280] a conversion unit that converts a photocurrent composed of the other of the electrons and the holes into a voltage;

[0281] a subtractor for obtaining a change in the voltage by subtraction; and

[0282] The comparator compares the change amount with the threshold value and outputs the comparison result as the detection signal.

[0283] (12) In the solid-state imaging element described in (11),

[0284] The detection unit further includes a buffer, and outputs the voltage signal from the conversion unit to the subtractor.

[0285] (13) In the solid-state imaging element described in (11) or (12),

[0286] The conversion unit includes a multi-stage ring circuit.

[0287] The multi-stage ring circuits are each composed of a pair of transistors connected in a ring shape.

[0288] (14) In the solid-state imaging element described in (11) or (12),

[0289] The conversion unit comprises:

[0290] a pair of transistors connected in a ring; and

[0291] A capacitor is connected to each gate of the pair of transistors.

[0292] (15) A camera device comprising:

[0293] Photodiodes generate electrons and holes through photoelectric conversion;

[0294] a pixel signal generating unit that generates a pixel signal having a voltage corresponding to an amount of one of the electrons and the holes;

[0295] a detection unit that detects whether a change amount of the other of the electrons and the holes exceeds a predetermined threshold value and outputs a detection signal; and

[0296] The digital signal processing unit performs predetermined processing on the detection signal and the pixel signal.

[0297] (16) A method for controlling a solid-state imaging element, comprising:

[0298] a pixel signal generating step of generating a pixel signal having a voltage corresponding to the amount of one of electrons and holes generated by photoelectric conversion; and

[0299] The detection step detects whether the change amount of the other of the electrons and the holes exceeds a predetermined threshold value, and outputs a detection signal.

Claims

1. A solid-state imaging element, characterized in that: have: Photodiodes generate electrons and holes through photoelectric conversion; a pixel signal generating unit that generates a pixel signal having a voltage corresponding to an amount of one of the electrons and the holes; as well as The detection unit detects whether a change amount of the other of the electrons and the holes exceeds a predetermined threshold value, and outputs a detection signal.

2. The solid-state imaging element according to claim 1, wherein The pixel signal generating unit generates the pixel signal having a voltage corresponding to the amount of the electrons. The detection unit detects whether the amount of change in the cavitation exceeds the threshold value.

3. The solid-state imaging element according to claim 1, wherein A portion of the pixel signal generating unit and the photodiode are arranged on a predetermined light receiving chip. The remaining part of the pixel signal generating unit and the detecting unit are arranged on a predetermined circuit chip.

4. The solid-state imaging element according to claim 3, wherein: The pixel signal generating unit comprises: A pixel circuit that generates the pixel signal; and A comparison circuit compares the pixel signal with a predetermined reference signal. A part of the comparison circuit, the photodiode and the pixel circuit are arranged on the light receiving chip. The remaining part of the comparison circuit and the detection unit are configured on the circuit chip.

5. The solid-state imaging element according to claim 3, wherein The pixel signal generating unit comprises: A pixel circuit, generating the pixel signal; A comparison circuit compares the pixel signal with a predetermined reference signal. The photodiode and the pixel circuit are arranged on the light receiving chip. The comparison circuit and the detection unit are disposed on the circuit chip.

6. The solid-state imaging element according to claim 1, wherein The device further includes a driving unit configured to drive the pixel signal generating unit to generate the pixel signal when the detecting unit detects that the amount of change exceeds the threshold value.

7. The solid-state imaging element according to claim 1, wherein The solid-state imaging element comprises: A column processing unit, performing a predetermined signal processing on the pixel signal and outputting the pixel signal; as well as The control circuit controls the column processing unit to output the pixel signal when detecting that the change amount exceeds the threshold value within a predetermined exposure period.

8. The solid-state imaging element according to claim 1, wherein The photodiode, the pixel signal generating unit, and the detecting unit are respectively arranged in a plurality of pixels. The pixel signal generating unit comprises: A pixel circuit, generating an analog pixel signal; and The analog-to-digital converter converts the pixel signal into a digital signal and outputs the digital signal.

9. The solid-state imaging device according to claim 1, wherein It also includes an analog-to-digital converter to convert the analog pixel signal into a digital signal. The photodiode, the pixel signal generating unit, and the detecting unit are respectively arranged in a plurality of pixels. The pixel signal generating unit generates the analog pixel signal and outputs the analog pixel signal to the analog-to-digital converter.

10. The solid-state imaging element according to claim 1, wherein The pixel signal generating unit comprises: a charge storage unit for storing charges of one of the electrons and the holes; a floating diffusion layer that accumulates the charges and converts them into the voltage corresponding to the amount of the charges; a first transfer transistor for transferring the charge from the photodiode to the charge storage unit; as well as The second transfer transistor transfers the charge from the charge storage unit to the floating diffusion layer.

11. The solid-state imaging element according to claim 1, wherein The detection unit comprises: a conversion unit that converts a photocurrent composed of the other of the electrons and the holes into a voltage; A subtractor, for obtaining a change in the voltage by subtraction operation; as well as The comparator compares the change amount with the threshold value and outputs the comparison result as the detection signal.

12. The solid-state imaging element according to claim 11, wherein The detection unit further includes a buffer, and outputs the voltage signal from the conversion unit to the subtractor.

13. The solid-state imaging element according to claim 11, wherein The conversion unit includes a multi-stage ring circuit. The multi-stage ring circuits are each composed of a pair of transistors connected in a ring shape.

14. The solid-state imaging element according to claim 11, wherein The conversion unit comprises: a pair of transistors connected in a ring; and A capacitor is connected to each gate of the pair of transistors.

15. A camera device, characterized in that: have: Photodiodes generate electrons and holes through photoelectric conversion; a pixel signal generating unit that generates a pixel signal having a voltage corresponding to an amount of one of the electrons and the holes; a detection unit that detects whether a change amount of the other of the electrons and the holes exceeds a predetermined threshold value and outputs a detection signal; as well as The digital signal processing unit performs predetermined processing on the detection signal and the pixel signal.

16. A method for controlling a solid-state imaging element, characterized in that: have: a pixel signal generating step of generating a pixel signal having a voltage corresponding to the amount of one of electrons and holes generated by photoelectric conversion; and The detection step detects whether the change amount of the other of the electrons and the holes exceeds a predetermined threshold value, and outputs a detection signal.

Images