Power management device for storage devices

Abstract

A power management device for a storage device is provided. The disclosed storage device includes: a control unit, an NVM chip, an interface, and a power management unit; the power management unit receives a first power input from the interface, supplies power to the control unit through a first power supply channel, and supplies power to the NVM chip through a second power supply channel.

Description

Technical Field

[0001] This application relates to storage devices, and more specifically, to power management devices for storage devices. Background Technology

[0002] Figure 1 A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), and RRAM (Resistive Random Access Memory) are common types of NVM.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] Storage devices also include power management devices for providing power to the various components of the storage device. Power supply circuits for storage devices are illustrated in Chinese patent applications 201210258780.0 and 201510347811.3 as examples of power management devices. Figure 2 A power management device as an integrated circuit was demonstrated. Figure 2 The power management integrated circuit shown receives external power on its Vin pin and provides, for example, 3.3V, power through its SW pin. It receives feedback signals regarding the supply voltage through its FB pin to adaptively adjust the output voltage of the SW pin, stabilizing the output voltage at a specified value (e.g., 3.3V). Figure 2 The PG signal of the integrated power management circuitry shown indicates whether the current power supply is normal.

[0008] Figure 3 Another power management integrated circuit was demonstrated. Figure 3The power integrated circuit on display receives external power on its Vin pin, which includes multiple power outputs (Vout1 and Vout2). Taking one power output, Vout1, as an example, the power management integrated circuit provides power through its LX1 pin, and receives feedback signals on the supply voltage provided to the LX1 pin through the FB1 pin to adaptively adjust the output voltage of the LX1 pin. Figure 3 The power management integrated circuit shown also includes a controller (not shown) that can be programmed to execute various programs to control GPIO pins (general purpose input / output pins) and to control the on / off state and timing of various power outputs. Figure 3 The power management integrated circuit on display also includes one or more digital-to-analog converters (DACs) / analog-to-digital converters (ADCs). The controller uses these DACs to acquire or monitor external signals, such as acquiring the voltage / current value on the Vin pin to calculate power, or acquiring ambient temperature. The controller also communicates with external devices via interfaces such as UART and I2C. Summary of the Invention

[0009] Power management devices need to continue to evolve with improvements in storage devices to provide more reliable power supply, higher power efficiency, and richer functionality.

[0010] According to a first aspect of this application, a first storage device according to the first aspect of this application is provided, comprising: a control unit, an NVM chip, an interface, and a power management unit; the power management unit obtains a first power input from the interface and provides power to the control unit through a first power supply channel, and provides power to the NVM chip through a second power supply channel; the storage device further comprises a voltage feedback circuit; the voltage feedback circuit receives an adaptive voltage adjustment signal provided by the control unit and provides a voltage feedback signal to the first power supply channel; the power management unit adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

[0011] According to the first storage device of the first aspect of this application, a second storage device according to the first aspect of this application is provided, wherein when the adaptive voltage regulation signal indicates that the control unit supports the adaptive voltage regulation function, the power management unit reduces the voltage of the power supplied to the control unit through the first power supply channel; and when the adaptive voltage regulation signal indicates that the control unit does not support the adaptive voltage regulation function, the power management unit does not reduce the voltage of the power supplied to the control unit through the first power supply channel.

[0012] According to the first or second storage device of the first aspect of this application, a third storage device according to the first aspect of this application is provided, wherein the power management component provides power to the I / O interface of the NVM chip and the I / O interface of the control component through a third channel.

[0013] According to one of the first to third storage devices of the first aspect of this application, a fourth storage device according to the first aspect of this application is provided, further comprising a DRAM component; the power management component provides power to the DRAM component through a fourth power supply channel.

[0014] According to the fourth storage device of the first aspect of this application, a fifth storage device according to the first aspect of this application is provided, wherein the power management component provides power to the I / O interface of the DRAM component and the I / O interface of the control component coupled to the DRAM component through a fifth power supply channel.

[0015] According to one of the first to fifth storage devices according to the first aspect of this application, a sixth storage device according to the first aspect of this application is provided, further comprising a backup power supply; the power management component provides power for charging to the backup power supply through a sixth power supply channel.

[0016] According to one of the first to sixth storage devices of the first aspect of this application, a seventh storage device according to the first aspect of this application is provided, which further includes a voltage conversion circuit that converts a first power input into a second power output, and a power management component obtains the first power input and the second power output.

[0017] According to one of the first to sixth storage devices of the first aspect of this application, an eighth storage device according to the first aspect of this application is provided, wherein the power management component also receives a second power input from the interface.

[0018] According to one of the first to eighth storage devices of the first aspect of this application, a ninth storage device according to the first aspect of this application is provided, wherein when the adaptive voltage regulation signal indicates that the control unit supports the adaptive voltage regulation function, the voltage feedback circuit outputs a first voltage feedback signal to the power management unit; when the adaptive voltage regulation signal indicates that the control unit does not support the adaptive voltage regulation function, the voltage feedback circuit outputs a second voltage feedback signal to the power management unit; and wherein the voltage of the first voltage feedback signal is lower than that of the second voltage feedback signal.

[0019] According to the ninth storage device of the first aspect of this application, a tenth storage device according to the first aspect of this application is provided, wherein the voltage feedback circuit includes a first resistor and a second resistor connected in series, the first resistor and the second resistor being subjected to the voltage output of a first power supply channel; the connection point of the first resistor and the second resistor connected in series provides a voltage feedback signal to the power management component, and also provides a voltage to a switch and a third resistor connected in series.

[0020] According to the tenth storage device of the first aspect of this application, an eleventh storage device according to the first aspect of this application is provided, wherein the series-connected switch and the third resistor are connected in parallel with the second resistor.

[0021] According to one of the first to eleventh storage devices of the first aspect of this application, a twelfth storage device according to the first aspect of this application is provided, wherein a power management unit provides a first power input in response to the interface of the storage device, first provides a valid reset signal to the control unit, then sequentially supplies power to the control unit and the NVM chip, and subsequently provides an invalid reset signal to the control unit.

[0022] According to the twelfth storage device of the first aspect of this application, a thirteenth storage device according to the first aspect of this application is provided, wherein the power management component supplies power to a backup power supply before supplying power to the control component.

[0023] According to one of the first to thirteenth storage devices according to the first aspect of this application, a fourteenth storage device according to the first aspect of this application is provided, wherein the power management component provides an effective interrupt signal to the control component in response to the disappearance of a first power input provided by the interface of the storage device.

[0024] According to a second aspect of this application, a first storage device according to the second aspect of this application is provided, comprising: a control unit, an NVM chip, an interface, and a power management unit; the power management unit obtains a first power input from the storage interface and provides power to the control unit through a first power supply channel, and provides power to the NVM chip through a second power supply channel; the power management unit also provides a reset signal and one or more interrupt signals to the control unit; the first communication interface of the power management unit is also coupled to the communication interface of the control unit.

[0025] According to the first storage device of the second aspect of this application, a second storage device according to the second aspect of this application is provided, further comprising a debug interface connector; a reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

[0026] According to the second storage device of the second aspect of this application, a third storage device according to the second aspect of this application is provided, wherein when the debugging interface connector of the storage device is coupled to a debugging device, the debugging device acquires a reset signal and one or more interrupt signals provided by the power management component, and the communication interface of the debugging device is also coupled to the communication interface of the power management component.

[0027] According to the second or third storage device of the second aspect of this application, a fourth storage device according to the second aspect of this application is provided, wherein...

[0028] The communication interface of the power management component is coupled to the communication interface of the control component via a switch; the control terminal of the switch is coupled to the debug interface connector; when the debug interface connector of the storage device is coupled to the debug device, the debug device is coupled to the control terminal of the switch via the debug interface connector to disconnect the coupling between the communication interface of the power management component and the communication interface of the control component.

[0029] According to one of the first to fourth storage devices of the second aspect of this application, a fifth storage device according to the second aspect of this application is provided, wherein an adaptive voltage regulation signal provided by the control component is coupled to the debug interface connector.

[0030] According to the fifth storage device of the second aspect of this application, a sixth storage device according to the second aspect of this application is provided, wherein when the debugging interface connector of the storage device is coupled to a debugging device, the debugging device acquires an adaptive voltage regulation signal provided by the control component.

[0031] According to one of the first to sixth storage devices of the second aspect of this application, a seventh storage device according to the second aspect of this application is provided, wherein the second communication interface of the control component is coupled to the debug interface connector; when the debug interface connector of the storage device is coupled to a debug device, the second communication interface of the debug device communicates with the second communication interface of the control component.

[0032] According to the first storage device of the second aspect of this application, an eighth storage device according to the second aspect of this application is provided, further comprising a debugging device; a reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debugging device; the communication interface of the power management component is also coupled to the debugging device.

[0033] According to the eighth storage device of the second aspect of this application, a ninth storage device according to the second aspect of this application is provided, wherein the communication interface of the power management component is coupled to the communication interface of the control component via a switch; the control terminal of the switch is coupled to the debugging device; the debugging device controls the switch to disconnect the coupling between the communication interface of the power management component and the communication interface of the control component.

[0034] According to the eighth or ninth storage device of the second aspect of this application, a tenth storage device according to the second aspect of this application is provided, wherein an adaptive voltage regulation signal provided by the control component is coupled to the debugging device.

[0035] According to one of the eighth to tenth storage devices of the second aspect of this application, an eleventh storage device according to the second aspect of this application is provided, further comprising a debug interface connector; a second communication interface of the debug device is coupled to the debug interface connector; and a second communication interface of the control component is coupled to the storage interface.

[0036] According to one of the first to eleventh storage devices of the second aspect of this application, a twelfth storage device according to the second aspect of this application is provided, wherein the storage interface further includes a pin for SMBUS; the pin for SMBUS is coupled to a second communication interface of the power management component; the power management component responds to an SMBUS access request to the storage device through the second communication interface.

[0037] According to the twelfth storage device of the second aspect of this application, a thirteenth storage device according to the second aspect of this application is provided, further comprising debugging equipment; wherein the power management component obtains first information from the control component through its first communication interface; the power management component provides the first information through a second communication interface in response to an SMBUS access request to the storage device.

[0038] According to the twelfth or thirteenth storage device of the second aspect of this application, a fourteenth storage device according to the second aspect of this application is provided, which also includes a debugging device; it also includes a second non-volatile memory; the second non-volatile memory is coupled to the pin for SMB, and the second non-volatile memory also responds to SMBUS access requests to the storage device.

[0039] According to the thirteenth or fourteenth storage device of the second aspect of this application, a fifteenth storage device according to the second aspect of this application is provided, wherein a third communication interface of the control unit is coupled to the pin for SMB, and the control unit also responds to SMBUS access requests to the storage device through the third communication interface.

[0040] According to a third aspect of this application, a first storage device according to the third aspect of this application is provided, comprising: a control unit, an NVM chip, an interface, and a power management unit; the power management unit obtains a first power input from the interface, provides power to the control unit through a first power supply channel, and provides power to the NVM chip through a second power supply channel.

[0041] According to the first storage device of the third aspect of this application, a second storage device according to the third aspect of this application is provided, further comprising a voltage feedback circuit; the voltage feedback circuit receives an adaptive voltage adjustment signal provided by a control unit and provides a voltage feedback signal to a first power supply channel; the power management unit adjusts the voltage of the power supplied by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

[0042] A second storage device according to a third aspect of this application is provided, and a third storage device according to a third aspect of this application is provided, wherein when the adaptive voltage regulation signal indicates that the control unit supports the adaptive voltage regulation function, the power management unit reduces the voltage of the power supplied to the control unit through the first power supply channel; and when the adaptive voltage regulation signal indicates that the control unit does not support the adaptive voltage regulation function, the power management unit does not reduce the voltage of the power supplied to the control unit through the first power supply channel.

[0043] According to one of the first to third storage devices of the third aspect of this application, a fourth storage device according to the third aspect of this application is provided, wherein the power management component provides power to the I / O interface of the NVM chip and the I / O interface of the control component through a third channel.

[0044] According to one of the first to fourth storage devices according to the third aspect of this application, a fifth storage device according to the third aspect of this application is provided, further comprising a DRAM component; the power management component provides power to the DRAM component through a fourth power supply channel.

[0045] According to the fifth storage device of the third aspect of this application, a sixth storage device according to the third aspect of this application is provided, wherein the power management component provides power to the I / O interface of the DRAM component and the I / O interface of the control component coupled to the DRAM component through a fifth power supply channel.

[0046] According to one of the first to sixth storage devices of the third aspect of this application, a seventh storage device according to the third aspect of this application is provided, further comprising a backup power supply; the power management component provides power for charging to the backup power supply through a sixth power supply channel.

[0047] According to one of the first to seventh storage devices of the third aspect of this application, an eighth storage device according to the third aspect of this application is provided, which further includes a voltage conversion circuit that converts a first power input into a second power output, and a power management component obtains the first power input and the second power output.

[0048] According to one of the first to seventh storage devices of the third aspect of this application, a ninth storage device according to the third aspect of this application is provided, wherein the power management component also receives a second power input from the interface.

[0049] According to the second storage device of the third aspect of this application, a tenth storage device according to the third aspect of this application is provided, wherein when the adaptive voltage regulation signal indicates that the control unit supports the adaptive voltage regulation function, the voltage feedback circuit outputs a first voltage feedback signal to the power management unit; when the adaptive voltage regulation signal indicates that the control unit does not support the adaptive voltage regulation function, the voltage feedback circuit outputs a second voltage feedback signal to the power management unit; and wherein the voltage of the first voltage feedback signal is lower than that of the second voltage feedback signal.

[0050] According to the tenth storage device of the third aspect of this application, an eleventh storage device according to the third aspect of this application is provided, wherein the voltage feedback circuit includes a first resistor and a second resistor connected in series, the first resistor and the second resistor being subjected to a voltage output from a first power supply channel; the connection point of the first resistor and the second resistor connected in series provides a voltage feedback signal to the power management component, and also provides a voltage to the switch and the third resistor connected in series.

[0051] According to the eleventh storage device of the third aspect of this application, a twelfth storage device according to the third aspect of this application is provided, wherein the series switch and the third resistor are connected in parallel with the second resistor.

[0052] According to one of the first to twelfth storage devices of the third aspect of this application, a thirteenth storage device according to the third aspect of this application is provided, wherein the power management unit provides a first power input in response to the interface of the storage device, first provides a valid reset signal to the control unit, then sequentially supplies power to the control unit and the NVM chip, and subsequently provides an invalid reset signal to the control unit.

[0053] According to the thirteenth storage device of the third aspect of this application, a fourteenth storage device according to the third aspect of this application is provided, wherein the power management component supplies power to a backup power supply before supplying power to the control component.

[0054] According to one of the first to fourteenth storage devices according to the third aspect of this application, a fifteenth storage device according to the third aspect of this application is provided, wherein the power management component provides an effective interrupt signal to the control component in response to the disappearance of a first power input provided by the interface of the storage device.

[0055] According to one of the first to fifteenth storage devices of the third aspect of this application, a sixteenth storage device according to the third aspect of this application is provided, wherein the power management component further provides a reset signal and one or more interrupt signals to the control component; the first communication interface of the power management component is also coupled to the communication interface of the control component.

[0056] According to the sixteenth storage device of the third aspect of this application, a seventeenth storage device according to the third aspect of this application is provided, further comprising a debug interface connector; a reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

[0057] According to the seventeenth storage device of the third aspect of this application, an eighteenth storage device according to the third aspect of this application is provided, wherein when the debugging interface connector of the storage device is coupled to a debugging device, the debugging device acquires a reset signal and one or more interrupt signals provided by the power management component, and the communication interface of the debugging device is also coupled to the communication interface of the power management component.

[0058] According to the seventeenth or eighteenth storage device of the third aspect of this application, a nineteenth storage device according to the third aspect of this application is provided, wherein the communication interface of the power management component is coupled to the communication interface of the control component via a switch; the control terminal of the switch is coupled to the debug interface connector; when the debug interface connector of the storage device is coupled to a debug device, the debug device is coupled to the control terminal of the switch via the debug interface connector to disconnect the coupling between the communication interface of the power management component and the communication interface of the control component.

[0059] According to one of the sixteenth to nineteenth storage devices according to the third aspect of this application, a twentieth storage device according to the third aspect of this application is provided, wherein an adaptive voltage regulation signal provided by the control component is coupled to the debug interface connector.

[0060] According to the twentieth storage device of the third aspect of this application, a twenty-first storage device according to the third aspect of this application is provided, wherein when the debugging interface connector of the storage device is coupled to a debugging device, the debugging device acquires an adaptive voltage regulation signal provided by the control component.

[0061] According to one of the sixteenth to twenty-first storage devices of the third aspect of this application, a twenty-second storage device according to the third aspect of this application is provided, wherein the second communication interface of the control component is coupled to the debug interface connector; when the debug interface connector of the storage device is coupled to a debug device, the second communication interface of the debug device communicates with the second communication interface of the control component.

[0062] According to the sixteenth storage device of the third aspect of this application, a twenty-third storage device according to the third aspect of this application is provided, further comprising a debugging device; a reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debugging device; the communication interface of the power management component is also coupled to the debugging device.

[0063] According to the twenty-third storage device of the third aspect of this application, a twenty-fourth storage device according to the third aspect of this application is provided, wherein the communication interface of the power management component is coupled to the communication interface of the control component via a switch; the control terminal of the switch is coupled to the debugging device; and the debugging device controls the switch to disconnect the coupling between the communication interface of the power management component and the communication interface of the control component.

[0064] According to the twenty-third or twenty-fourth storage device of the third aspect of this application, a twenty-fifth storage device according to the third aspect of this application is provided, wherein an adaptive voltage regulation signal provided by the control component is coupled to the debugging device.

[0065] According to one of the twenty-second to twenty-fifth storage devices of the third aspect of this application, a twenty-sixth storage device according to the third aspect of this application is provided, further comprising a debug interface connector; a second communication interface of the debug device is coupled to the debug interface connector; and a second communication interface of the control component is coupled to the storage interface.

[0066] According to one of the first to twenty-sixth storage devices of the third aspect of this application, a twenty-seventh storage device according to the third aspect of this application is provided, wherein the storage interface further includes a pin for SMBUS; the pin for SMBUS is coupled to a second communication interface of the power management component; the power management component responds to an SMBUS access request to the storage device through the second communication interface.

[0067] According to the twenty-seventh storage device of the third aspect of this application, a twenty-eighth storage device according to the third aspect of this application is provided, wherein the power management component obtains first information from the control component through its first communication interface; the power management component responds to an SMBUS access request to the storage device and provides the first information through a second communication interface.

[0068] According to the twenty-seventh or twenty-eighth storage device of the third aspect of this application, a twenty-ninth storage device according to the third aspect of this application is provided, further comprising a second non-volatile memory; the second non-volatile memory is coupled to the pin for SMB, and the second non-volatile memory also responds to SMBUS access requests to the storage device.

[0069] According to one of the twenty-seventh to twenty-ninth storage devices of the third aspect of this application, a third type of storage device according to the third aspect of this application is provided, wherein a third communication interface of the control unit is coupled to the pin for SMB, and the control unit also responds to SMBUS access requests to the storage device through the third communication interface. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0071] Figure 1 A schematic diagram of a solid-state storage device in the prior art provided in this application;

[0072] Figure 2 A power management device as an integrated circuit was demonstrated;

[0073] Figure 3 Another power management integrated circuit was demonstrated;

[0074] Figure 4 A schematic diagram of a storage device according to an embodiment of this application is shown;

[0075] Figure 5 A schematic diagram of a storage device according to yet another embodiment of this application is shown;

[0076] Figure 6A This application demonstrates the power-on sequence provided by the power management integrated circuit according to an embodiment of the present application;

[0077] Figure 6B This application demonstrates a power-down sequence provided by a power management integrated circuit according to an embodiment of the present application;

[0078] Figure 7 A schematic diagram of a storage device according to another embodiment of this application is shown;

[0079] Figure 8 A schematic diagram of a storage device according to another embodiment of this application is shown; and

[0080] Figure 9 A schematic diagram of a storage device according to yet another embodiment of this application is shown. Detailed Implementation

[0081] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0082] Figure 4 A schematic diagram of a storage device according to an embodiment of this application is shown. A power management integrated circuit 410 is arranged in the storage device. The power management integrated circuit 410 is used to power various components of the storage device (control unit 104, one or more NVM chips 105, one or more DRAMs 110, etc., see also...). Figure 1 It provides electricity.

[0083] The power management integrated circuit 410 includes multiple power input pins (Vin1 and Vin2) and multiple power supply channels (CH1, CH2, ... CH6) for output power. For example, the power input pin (Vin2) is coupled to interface 103 to obtain power from interface 103 for supplying power to the storage device. Figure 3 In this example, the power supplied from interface 103 is 12V. The power supplied from interface 103 is coupled to the power input pin Vin via switch 420. The Vin2_EN pin of the power management integrated circuit 410 is connected to the control terminal of switch 420 to control the opening or closing of switch 420. Optionally, the power supplied from interface 103 may also be converted to other voltage values ​​via a transformer circuit and coupled to the power input pin Vin2. Again, optionally, interface 103 provides two or more power sources, each coupled to a power input pin of the power management integrated circuit. Again, as an example, when the storage device uses the U.2 standard interface 103, the power management integrated circuit 410 obtains a single 12V power from interface 103; when the storage device uses the M.2 standard interface 103, the power management integrated circuit 410 obtains a single 3.3V power from interface 103.

[0084] Each component of the storage device (control unit 104, NVM chip 105, DRAM 110, etc.) requires one or more power supplies. The NVM chip 105 needs to be supplied with power for the memory cell array (denoted as V1), power for the I / O interface (denoted as Vp), and optionally additional power (denoted as Vpp). The DRAM 110 needs to be supplied with power for the memory cell array (denoted as V1), power for the I / O interface (denoted as Vp), and optionally additional power (denoted as Vpp). The control unit 104 needs to be supplied with power for the core circuitry (denoted as VDD), power for the I / O interface coupling the NVM chip 105, power for the I / O interface coupling the DRAM 110, and optionally power for its GPIO pins.

[0085] The power supply channels of the power management integrated circuit 410 are configured with output voltage specifications, for example, through programming, and coupled to the power supply pins of their respective components. See also Figure 4 Power supply channel CH1 of the power management integrated circuit 410 provides power (VDD) to the control unit 104 for the core circuitry. Power supply channel CH2 provides power to the I / O interface of DRAM 110, and also provides power to the I / O interface of control unit 104 coupled to DRAM 110, thus ensuring that the I / O interface of DRAM 110 and the I / O interface of control unit 104 coupled to DRAM 110 use the same power specifications. Power supply channel CH4 provides power to the I / O interface of one or more NVM chips 105, and also provides power to the I / O interface of control unit 104 coupled to NVM chips 105, thus ensuring that the I / O interface of NVM chips 105 and the I / O interface of control unit 104 coupled to NVM chips 105 use the same power specifications. Power supply channel CH3 provides power to the control unit for its GPIO pins. Power supply channel CH5 provides power to DRAM 110 for the core circuitry. Power supply channel CH6 provides power to NVM chip 105 for the core circuitry. Optionally, the power management integrated circuit 410 also includes additional power supply channels for providing power to charge, for example, a backup power supply for a storage device. Understandably, the coupling method between the power supply channels of the power management circuit 410 and the components of the storage device can be varied; for example, power supply channel CH1 can be used to provide power to the control unit for its GPIO pins, while power supply channel CH2 can be used to provide power (VDD) to the control unit 104 for its core circuitry.

[0086] The power management integrated circuit 410 also includes a controller (not shown). The controller runs a program and can be programmed.

[0087] The power management integrated circuit 410 also includes an I2C interface, a serial port, and one or more GPIO pins (INT0, INT1, Reset) coupled to, for example, the control unit 104. The control unit 104 configures the power management integrated circuit 410 via, for example, the I2C interface. The controller of the power management integrated circuit obtains configuration information provided by the control unit 104 from the I2C interface and sets the output power specifications (voltage and / or current values, etc.) for each power supply channel, as well as controlling the on / off state and timing of each power supply channel. The power management integrated circuit 410 also provides a reset signal and one or more interrupt signals to the control unit 104 via the GPIO interface to indicate the power status to the control unit 104. For example, after obtaining power from interface 103, the power management integrated circuit 410, upon meeting specified conditions (e.g., power stabilization for a specified time, providing power to each component of the storage device through each power supply channel for a specified time), provides a valid signal to the control unit 104 via the Reset pin to instruct the control unit 104 to reset. Optionally, after recognizing a power supply interruption from interface 103, the power management integrated circuit 410 provides a specified signal to the control unit 104 via the INT0 / INT1 pin after a specified condition is met (e.g., a specified time of power interruption, or the output voltage of the backup power supply drops below a specified level), to indicate to the control unit 104 the event of power failure.

[0088] Optionally, the power management integrated circuit 410 also includes one or more digital-to-analog converters / analog-to-digital converters, through which the controller acquires or monitors external signals, such as acquiring the voltage / current value on the Vin pin to calculate power, or acquiring the ambient temperature, etc.

[0089] Figure 5 A schematic diagram of a storage device according to yet another embodiment of this application is shown. Figure 5 The power management integrated circuit 410 in the embodiment also identifies whether the control unit 104 supports AVS (Adaptive Voltage Scaling) and adjusts the power supplied to the control unit 104 accordingly.

[0090] See Figure 5The power supply channel CH1 of the power management integrated circuit 410 is used to provide power (VDD) for the core circuitry of the control unit 104. Optionally, the pin CH1 SW of the power supply channel CH1 is coupled to an inductor 510, and the other end of the inductor 510 serves as the output of the power supply channel CH1, coupled to the power input of the control unit. The inductor 510 protects the power supply channel pin CH1 SW from excessive current fluctuations. The output of the power supply channel CH1 (denoted as Vout) is also coupled to ground through a series resistor 520 and a resistor 522. The point where the series resistors 520 and 522 are connected is coupled to the pin CH1 FB of the power supply channel CH1 to provide voltage feedback to the power supply channel CH1. The point where the series resistors 520 and 522 are connected is also coupled to ground through a series resistor 524 and a switch 530. When the switch 530 is closed, resistors 524 and 522 are connected in parallel, and then connected in series with resistor 520. When switch 530 is open, resistor 524 is disconnected from the circuit, leaving only resistors 522 and 520 connected. The AVS-enabled control unit 104 provides an AVE_EN signal, which is coupled to the control terminal of switch 530. Thus, when the AVS_EN signal is valid, switch 530 is closed, and when the AVS_EN signal is invalid or absent, switch 530 is open. Resistors 520, 522, 524, and switch 530 constitute a voltage feedback circuit used to provide a voltage feedback signal to the power management integrated circuit 410.

[0091] Compared to control units that do not support AVS, control unit 104 can accept a lower supply voltage, thereby reducing power consumption. For example, if control unit 104 supports AVS, upon receiving a reset signal (RESET), it first outputs a low-level AVS_EN signal, followed by a high-level AVS_EN signal. In response to the low-level AVS_EN signal, switch 530 opens, and the point where series resistors 520 and 522 are connected has a voltage value V1, which is provided as a feedback signal to pin CH 1FB. Based on the feedback voltage value V1 at pin CH 1FB, the power management integrated circuit 410 stabilizes the output voltage of pin CH 1SW at Vo1. In response to the high-level AVS_EN signal, switch 530 closes, and the point where series resistors 520 and 522 are connected has a voltage value V2, which tends to decrease relative to voltage value V1. As a feedback signal provided to pin CH1FB, the power management integrated circuit 410 stabilizes the output voltage of pin CH1SW at Vo2 based on the feedback voltage value V2 of pin CH1FB, where the output voltage Vo2 is less than the output voltage Vo1. If the control unit 104 coupled to the power management integrated circuit 410 does not support the AVS function, the AVS_EN signal provided to switch 530 remains low, keeping switch 530 open, thus stabilizing the output voltage of pin CH1SW at Vo1 without changing it. Therefore, based on... Figure 5 The circuit of the embodiment can be used in both control components 104 that support AVS function and control components 104 that do not support AVS function, so that the storage device does not need to adopt different circuit designs depending on whether the control component 104 supports AVS function during the manufacturing process, thus saving design and production costs.

[0092] In another example, control unit 104 outputs a high-level AVS_EN signal (rather than a low-level-then-high transition signal) when the AVS function is supported, and outputs a low-level AVS_EN signal when the AVS function is not supported. Such control unit 104 is also applicable to… Figure 5 The circuit shown.

[0093] In another example, the AVS_EN signal output by control unit 104 is independent of the reset signal. Such control unit 104 is also suitable for... Figure 5 The circuit shown.

[0094] In another embodiment according to this application, the AVS_EN signal provided by the control unit 104 is coupled to one of the GPIO pins of the power management integrated circuit 410. The controller of the power management integrated circuit 410 acquires the level of the GPIO pin coupled to the AVS_EN signal to identify whether the control unit 104 supports the AVS function, and outputs a relatively high voltage on the power supply channel CH1 when the control unit 104 does not support the AVS function, and outputs a relatively low voltage on the power supply channel CH1 when the control unit 104 supports the AVS function.

[0095] Figure 6A The power-on sequence provided by the power management integrated circuit according to an embodiment of this application is shown.

[0096] In response to power-on (the power input pin Vin of the power management integrated circuit 410 receives power), according to Figure 6A The power-on sequence shown demonstrates how the power management integrated circuit 410 supplies power to the external circuitry through its respective power supply channels in a sequential order, and how the GPIO pins provide designated signals in a sequential order. See also... Figure 6A At time 1, the power input pin Vin1 receives 12V power, and at the same time, the power management integrated circuit 410 sets the pin INT0 (GPIO) to the specified level. Figure 6A The power management integrated circuit 410 sets the Reset (GPIO) pin to a specified level (high level) to indicate to the control unit 104 that the power supply is normal (although the control unit 104 has not yet started at this time, this setting avoids the control unit 104 from thinking that the power supply is in an abnormal state after it starts). Figure 6A (At time 2, the power input pin Vin2 receives 5V power). Next, the power management integrated circuit 410 activates the power supply channels according to a preferred timing sequence. At time 3, the power supply channel charging the backup power supply is activated first (see...). Figure 5Charging the backup power supply consumes a significant amount of power; therefore, a separate power supply channel CH7 is activated to prevent excessive power fluctuations in a short period from adversely affecting the host coupled to the storage device. Subsequently, at time 4, power is supplied to the core circuitry of the control unit 104 (power supply channel CH1 is activated). The control unit 104 requires some time for initialization; supplying power to the control unit 104 earlier shortens the startup time of the storage device. Next, at time 5, power is supplied to the GPIO pins of the control unit 104 to enable it to operate some peripheral components. Next, at time 6, power is supplied to the memory cell array of DRAM 110 and NVM chip 105 via power supply channels CH5 and CH6. Then, at time 7, power is supplied to the I / O interfaces of DRAM 110 and NVM chip 105 via power supply channels CH2 and CH4. Power is also supplied to the I / O interfaces of NVM chip 105 / DRAM 110 via power supply channels CH2 and CH4 to the control unit 104. At this point, DRAM 110 and NVM chip 105 are operational, and the control unit 104 can access them. At time 8, the power management integrated circuit 410 provides a reset signal to the control unit 104, causing the control unit 104 to begin, for example, loading the firmware stored in NVM chip 105. At this point, the power management integrated circuit 410 has begun supplying power to all major components of the storage device, and each major component is functioning normally.

[0097] Optionally, the power management integrated circuit 410 uses different power-on sequences to power the various components of the storage device to ensure a smooth power demand during the power-on process and that sufficient power has been provided when the components are started up or need to be used.

[0098] Figure 6B The power-down sequence provided by the power management integrated circuit according to an embodiment of this application is shown. Figure 6B The power-down sequence provided by the power management integrated circuit 410 was also demonstrated. When a storage device is powered down, a series of operations need to be performed to shut down the various parts of the storage device and save the necessary information.

[0099] See Figure 6BAt time 1, the host coupled to the storage device stops supplying 12V power to the power input pin Vin1. For example, the power management integrated circuit 410 identifies whether the 12V power supplied by the host is stored based on the voltage level of the power input pin Vin1. In response to identifying that the host has stopped supplying 12V power, the power management integrated circuit 410 indicates a host power supply abnormality signal to the control unit 104 via the INT0 (GPIO) pin. Subsequently, the power management integrated circuit 410 maintains power to the main components of the storage device for a period of time, waiting for the control unit to save necessary information and prepare for power failure. For example, during this time, power supply is maintained by the storage device's backup power supply. Alternatively, during this time, power supply is maintained using the 5V power supplied by the host.

[0100] Subsequently, at time 2, the power management integrated circuit 410 cuts off the power supply channel (CH7) to the backup power supply to prevent the backup power supply from absorbing the remaining power available from the power management circuit 410 due to the power loss of the backup power supply.

[0101] Subsequently, at time 3, the power management integrated circuit 410 cuts off the power supply channel (CH3) to the GPIO pins of the control unit 104, at which point the control unit 104 can no longer use the GPIO.

[0102] Subsequently, at time 4, the power supply channels (CH4 and CH6) to the memory cell array and IO interface of the NVM chip 105 are cut off, and the control unit 104 can no longer access the NVM chip 105.

[0103] Subsequently, at time 5, the power supply channels (CH2 and CH5) to the DRAM memory cell array and I / O interface are cut off, as is the power supply channel (CH1) to the core circuit of the control unit 104. At this point, neither the control unit 104 nor the DRAM 110 will work.

[0104] Subsequently, at time 6, the 5V power supplied by the host disappeared, and the power management integrated circuit 410 no longer guaranteed that the reset signal provided by the GPIO pin was invalid.

[0105] pass Figure 6B The power-down sequence shown indicates that during the power-down process, the storage device gradually cuts off one or more power supply channels to reduce power consumption and uses the remaining power to ensure that the control unit 104 completes the necessary operations required for power-down.

[0106] Figure 7 A schematic diagram of a storage device according to another embodiment of this application is shown. Figure 7The embodiment provides the storage device with the ability to debug the power management integrated circuit 410. Since the power management integrated circuit 410 includes a controller and a program running in the controller, it needs to be effectively debugged during the program process, and the coordination between the power management integrated circuit 410 and the control unit 104 also needs to be debugged during the operation of the storage device to ensure that each component operates normally.

[0107] See Figure 7 The storage device also includes a debug interface 710. As an example, the debug interface 710 includes one or more pins for debugging. In one example, the debug interface 710 is integrated into interface 103, and the debug pins are connected via interface 103, which is connected to the storage device. Figure 7 In the example shown, debug interface 710 is independent of interface 103. The storage device is debugged by additionally connecting a debug device to debug interface 710. Furthermore, because the debug device is external to the storage device and not part of it, the manufacturing cost of the storage device is reduced. Debug devices include, for example, microcontrollers (MCUs).

[0108] The power management integrated circuit 410 provides an I2C interface to the control unit 104, and one or more GPIO pins (INT0, INT1, and Reset) are coupled to the debug interface 710. When the debug interface 710 of the storage device is not connected to a debug device, the I2C interface and one or more GPIO pins (INT0, INT1, and Reset) of the power management integrated circuit 410 only sense the presence of the control unit 104 and communicate with it, thus allowing the storage device to function normally even without a debug device connection. When the debug interface 710 of the storage device is connected to a debug device, the debug device provides information to the I2C interface of the power management integrated circuit 410 through the debug interface 710, and the debug device obtains input from one or more GPIO pins (INT0, INT1, and Reset), thereby enabling debugging of the power management integrated circuit 410 and the storage device.

[0109] Continue reading Figure 7The I2C interface of control unit 104 is coupled to the I2C interface of power management integrated circuit 410 via switch 720. Under normal conditions, switch 720 is on, allowing control unit 104 to provide information to power management integrated circuit 410 via the I2C interface. The control terminal of the switch is also coupled to debug interface 710. When debug equipment is coupled to the control terminal of switch 720 via debug interface, the debug equipment can disconnect switch 720 via, for example, a GPIO pin (Debug_EN). The debug equipment's I2C interface is then coupled to the I2C interface of power management integrated circuit 410 via debug interface 710, allowing the debug equipment to exchange information with power management integrated circuit 410 via the I2C interface. The GPIO pins of the debug equipment are also coupled to the GPIO pins (INT0, INT1, and Reset) of power management integrated circuit 410 via debug interface 710, enabling the debug equipment to obtain the values ​​of key signals (INT0, INT1, and Reset) generated by power management integrated circuit 410 and the times at which these signals occurred.

[0110] Optionally, the debug device closes switch 720 via, for example, a GPIO pin (Debug_EN), thereby allowing the control unit 104 to provide information to the power management integrated circuit 410 via the I2C interface during debugging. The debug device also acquires the information provided by the control unit 104 via the I2C interface to identify whether the behavior of the control unit 104 and the power management integrated circuit 410 is as expected.

[0111] Optionally, one or more GPIO pins (AVS_EN, GPIO, etc.) of the control unit 104 are also coupled to the debug interface 710. The debug device couples these GPIO pins of the control unit 104 through the debug interface 710 to exchange information with the control unit 104. For example, the debug device obtains the AVS_EN signal output by the control unit 104 through the debug interface 710 and obtains the voltage output by the power supply channel CH1 through the I2C interface of the power management integrated circuit 410 to identify whether the power management integrated circuit 410 correctly responds to the AVS signal provided by the control unit 104.

[0112] Optionally, the debugging device can also obtain the time when the power management integrated circuit 410 receives power from the host through the input pin Vin of the power management integrated circuit 410, and obtain the signals output by the power management integrated circuit 410 through the GPIO pins (INT0, INT1 and Reset), as well as the timing and voltage value of each power supply channel supplying power to each component of the storage device, thereby identifying whether the operation of the power management integrated circuit 410 is as expected.

[0113] Optionally, the debugging device may also include other interfaces such as a UART interface and a JTAG interface, which are coupled to the control unit 104 through the debugging interface 710 to communicate with the control unit 104, for example, to obtain information output by the control unit 104 on these interfaces, and / or to provide debugging commands to the control unit 104 through these interfaces.

[0114] Debugging equipment is particularly useful in debugging the power-on and power-off sequences of the power management integrated circuit 410. To facilitate debugging, the power management integrated circuit 410 acquires the voltage / current values ​​of its power input pins and power output pins of each power supply channel, as well as, for example, the time it takes for the power input interface to receive stable power and the time it takes for each power supply channel to output stable power, and stores these values ​​in its own registers. The debugging equipment obtains the values ​​of the power management integrated circuit 410's registers through an I2C interface or other interfaces such as UART / JTAG, thereby understanding the behavior of the power management integrated circuit 410 during the power-on and power-off processes. For example, the debugging equipment can determine, through the debugging interface, the time when the power input pins of the power management integrated circuit 410 are supplied with 12V, the subsequent time and voltage values ​​of power output on each power supply channel, and the signal and timing of the GPIO pins (INT0, INT1, and Reset), thereby determining whether the power-on process meets expectations. The debugging equipment also knows the timing of the 12V voltage message on the power input pin of the power management integrated circuit 410 through the debugging interface, as well as the timing of the power output message on each power supply channel, and the signal and timing of the output of the GPIO pins (INT0, INT1 and Reset), thereby determining whether the power-down process is as expected.

[0115] In an optional implementation, to debug the power-on and / or power-off process, the debugging device is also connected to interface 103 and provides, for example, 12V power to the power management integrated circuit 410 through interface 103. This allows the debugging device to control and monitor the entire power-on / power-off process. The debugging device also selects the preferred configuration provided to the power management integrated circuit 410 through repeated power-on / power-off processes. For example, the debugging device sets the specifications and timing of the output voltage of each power supply channel of the power management integrated circuit through the I2C interface, provides 12V power to the power management integrated circuit 410 through interface 103, and monitors whether the output of each power supply channel and GPIO pin of the power management integrated circuit 410 meets expectations. If the expectations are not met, the debugging device changes the configuration of the power management integrated circuit 410 through the I2C interface, and again provides 12V power to the power management integrated circuit 410 through interface 103, monitoring whether the behavior of the power management integrated circuit 410 receiving 12V power through interface 103 meets expectations. This method completes the debugging of the power management integrated circuit 410 and shortens the debugging time.

[0116] As another example, the debugging equipment actively cuts off the 12V power supplied to the power management integrated circuit 410 through interface 103, and observes through the debugging interface whether the power management integrated circuit 410 generates the expected INT0, INT1, and other signals at the appropriate time through the GPIO pins, and whether the backup power supply and the output voltage of each power supply channel remain effective for a specified time after the power supply to the power input pin Vin of the power management integrated circuit 410 is cut off. If the output of the power management integrated circuit 410 does not meet expectations, the debugging component changes the configuration of the power management integrated circuit 410 through the I2C interface, and again supplies and cuts off the 12V power to the power management integrated circuit 410 through interface 103, and monitors whether the behavior of the power management integrated circuit 410 through interface 103 meets expectations.

[0117] Figure 8 A schematic diagram of a storage device according to another embodiment of this application is shown. According to embodiment 8, the storage device is provided with the ability to debug the power management integrated circuit 410.

[0118] Different from Figure 7 The illustrated embodiments are based on Figure 8In this embodiment, the storage device includes a debugging device. The debugging device is coupled to the I2C interface of the power management integrated circuit 410 and one or more GPIO pins (INT0, INT1, and Reset). When the storage device is operating, the debugging device continuously acquires the status of each power input pin, each power supply channel, and each GPIO of the power management integrated circuit 410 to identify whether the behavior of the power management integrated circuit 410 is as expected.

[0119] according to Figure 8 Optionally, the embodiment also includes a debug interface independent of interface 103. The debug device's UART or JTAG interface is coupled to the debug interface, allowing access to the debug device via the debug interface when the storage device is connected to an external computer or debug computer, thereby obtaining the operating states of the power management integrated circuit 410 and control unit 104 through the debug device. The debug computer also modifies the behavior of the debug device through the debug interface.

[0120] Continue reading Figure 8 Optionally, interface 103 also includes pins coupled to the UART / JTAG interface of control unit 104. In addition to connecting to the UART / JTAG interface of the debugging device via the debugging interface, the debugging computer also couples to the UART / JTAG interface of control unit 104 via interface 103. Thus, the debugging computer communicates with control unit 104 via interface 103 and with the debugging device via the debugging interface, enabling simultaneous debugging of control unit 104 and power management integrated circuit 410.

[0121] Figure 9 A schematic diagram of a storage device according to yet another embodiment of this application is shown. The storage device provides an SMBUS interface, through which a host accesses the storage device outside the storage interface, for example, to obtain configuration information of the storage device. A portion of the pins of interface 103 of the storage device are used to provide the SMBUS interface. Figure 9 In the illustrated embodiment, the storage device includes an EEPROM (Electrically Erasable Programmable Memory). The EEPROM, control unit 104, and / or power management integrated circuit 410 are coupled to an SMBUS. The host reads information from the EEPROM, control unit 104, and / or power management integrated circuit 410 by accessing the SMBUS.

[0122] In one example, the EEPROM stores the configuration information of the storage device. The host reads the configuration information from the EEPROM via SMBUS. Optionally, for some dynamic information, such as the temperature information of the storage device, the control unit or power management integrated circuit 410 writes this dynamic information into the EEPROM, enabling the host to read this dynamic information from the EEPROM via SMBUS.

[0123] In yet another example, the host reads configuration information from the EEPROM via SMBUS, and reads dynamic information from the control unit and / or power management integrated circuit 410 via SMBUS.

[0124] In yet another example, control unit 104 is coupled to the SMBUS of interface 103, while power management integrated circuit 410 is not coupled to the SMBUS of interface 103. Control unit 104 obtains dynamic information such as temperature and capacitor health status collected by power management integrated circuit 410 via I2C interface and responds to host access via SMBUS. Optionally, the host also accesses EERPOM via the SMBUS of interface 103.

[0125] In another example, the power management integrated circuit 410 is coupled to the SMBUS of interface 103, while the control unit 104 is not coupled to the SMBUS of interface 103. The control unit 104 provides information such as temperature to the power management integrated circuit 410 via an I2C interface, and the host obtains this dynamic information by accessing the power management integrated circuit 410 via the SMBUS. Optionally, the host also accesses EERPOM via the SMBUS of interface 103 to obtain other configuration information.

[0126] Although the examples referred to in the present invention are described, they are for illustrative purposes only and not for limiting the scope of this application. Changes, additions and / or deletions to the implementation may be made without departing from the scope of this application.

[0127] Those skilled in the art who benefit from the teachings presented in the above description and associated drawings will recognize many modifications and other embodiments of the present application described herein. Therefore, it should be understood that the present application is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in its general and descriptive sense and not for limiting purposes.

Claims

1. A storage device, comprising: Control components, NVM chip, DRAM components, interfaces, and power management components; The power management unit receives a first power input from the interface and supplies power to the control unit through a first power supply channel. Power is supplied to the NVM chip through a second power supply channel; Power is supplied to the I / O interface of the NVM chip and the I / O interface of the control unit through a third power supply channel; It also includes a voltage feedback circuit; the voltage feedback circuit provides a voltage feedback signal to the power management unit, and the power management unit identifies whether the control unit supports adaptive voltage regulation function based on the voltage feedback signal; the power management unit responds to the interface of the storage device by providing a first power input, first provides a valid reset signal to the control unit, then supplies power to the control unit and the NVM chip in sequence, and then provides an invalid reset signal to the control unit. During the power-down process, one or more of the first, second, and third power supply channels are gradually disconnected.

2. The storage device according to claim 1, wherein the voltage feedback circuit receives an adaptive voltage adjustment signal provided by the control unit and provides a voltage feedback signal to the first power supply channel; The power management unit adjusts the voltage of the power supplied by the first power supply channel based on the voltage feedback signal received from the first power supply channel.

3. The storage device according to claim 2, wherein When the adaptive voltage regulation signal indicates that the control unit supports the adaptive voltage regulation function, the power management unit reduces the voltage of the power supplied to the control unit through the first power supply channel; and When the adaptive voltage regulation signal indicates that the control unit does not support the adaptive voltage regulation function, the power management unit will not reduce the voltage of the power supplied to the control unit through the first power supply channel.

4. The storage device of claim 3, further comprising a DRAM component; the power management component provides power to the DRAM component via a fourth power supply channel.

5. The storage device of claim 4, wherein the power management component provides power to the I / O interface of the DRAM component and the I / O interface of the control component coupled to the DRAM component via a fifth power supply channel.

6. The storage device according to claim 5 further includes a backup power supply; The power management component provides charging power to the backup power supply through a sixth power supply channel.

7. The storage device according to claim 6 further includes a voltage conversion circuit, the voltage conversion circuit converting the first power input into a second power output, and the power management unit obtaining the first power input and the second power output.

8. The storage device of claim 7, wherein the power management component further receives a second power input from the interface.

9. The storage device according to claim 8, wherein the voltage feedback circuit outputs a first voltage feedback signal to the power management unit; when the adaptive voltage regulation signal indicates that the control unit does not support the adaptive voltage regulation function, the voltage feedback circuit outputs a second voltage feedback signal to the power management unit; and wherein the voltage of the first voltage feedback signal is lower than that of the second voltage feedback signal.

10. The storage device of claim 9, wherein the voltage feedback circuit includes a first resistor and a second resistor connected in series, the first resistor and the second resistor being subjected to a voltage output from a first power supply channel; the connection point of the first resistor and the second resistor connected in series provides a voltage feedback signal to the power management component and also provides a voltage to a switch and a third resistor connected in series.

11. The storage device of claim 10, wherein the series-connected switch and the third resistor are connected in parallel with the second resistor.

12. The storage device of claim 11, wherein the power management unit supplies power to a backup power supply before supplying power to the control unit.

13. The storage device of claim 12, wherein the power management component provides a valid interrupt signal to the control component in response to the disappearance of a first power input provided by the interface of the storage device.

14. The storage device according to any one of claims 1-13, The power management component also provides the control component with a reset signal and one or more interrupt signals; The first communication interface of the power management component is also coupled to the communication interface of the control component.

15. The storage device of claim 14, further comprising a debug interface connector; The reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector. The first communication interface of the power management component is also coupled to the debug interface connector.

16. The storage device of claim 15, wherein when the debug interface connector of the storage device is coupled to the debug device, the debug device acquires a reset signal and one or more interrupt signals provided by the power management component, and the communication interface of the debug device is also coupled to the communication interface of the power management component.

17. The storage device according to claim 15, wherein The communication interface of the power management component is coupled to the communication interface of the control component via a switch; The control terminal of the switch is coupled to the debugging interface connector; When the debugging interface connector of the storage device is coupled to the debugging device, the debugging device is coupled to the control terminal of the switch through the debugging interface connector to disconnect the communication interface of the power management component from the communication interface of the control component.

18. The storage device of claim 17, wherein the adaptive voltage regulation signal provided by the control component is coupled to the debug interface connector.

19. The storage device of claim 18, wherein when the debugging interface connector of the storage device is coupled to the debugging device, the debugging device acquires the adaptive voltage adjustment signal provided by the control component.

20. The storage device of claim 19, wherein the second communication interface of the control component is coupled to the debug interface connector; when the debug interface connector of the storage device is coupled to a debug device, the second communication interface of the debug device communicates with the second communication interface of the control component.

21. The storage device according to claim 20, further comprising debugging equipment; The reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debugging device; the communication interface of the power management component is also coupled to the debugging device.

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