Capacitor bank structure, semiconductor package structure and manufacturing method thereof

Abstract

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer, and a plurality of first pillars. The capacitors are disposed side-by-side. Each of the capacitors has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes, and sidewalls of the second electrodes, and has a first surface corresponding to the first surfaces of the capacitors and a second surface corresponding to the second surfaces of the capacitors. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 688,927, filed June 22, 2018, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a capacitor bank structure and a semiconductor package structure including at least one capacitor, and a method of manufacturing the same. BACKGROUND

[0004] As microelectronic technology advances, the size of semiconductor devices will become smaller and smaller, which will make the operating voltage of the overall electronic system lower and lower, and the stability of voltage variation will be an important issue. To achieve the stability of voltage variation, more electronic devices (e.g., decoupling capacitors) should be integrated at the power supply of the electronic system. In addition to providing a more stable power output to the electronic system, the decoupling capacitors can effectively reduce the noise of the electronic devices coupled to the power supply; in turn, indirectly reducing the noise of the electronic devices to other electronic devices, and suppressing undesirable radiation. That is, when the power supply of the electronic system is turned off, voltage surges can be effectively suppressed; and when the power supply of the electronic system is turned on, voltage drops can also be suppressed. SUMMARY

[0005] In some embodiments, a capacitor bank structure includes a plurality of capacitors, a protective material, a first dielectric layer, and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protective material covers sidewalls of the capacitors, the first electrodes, and the second electrodes, and has a first surface corresponding to the first surfaces of the capacitors and a second surface corresponding to the second surfaces of the capacitors. The first dielectric layer is disposed on the first surface of the protective material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

[0006] In some embodiments, a semiconductor package structure includes a conductive structure, a semiconductor device, at least one capacitor, an encapsulant, and a plurality of external pillars. The conductive structure has a top surface and a bottom surface opposite the top surface. The semiconductor device is electrically connected to the top surface of the conductive structure. The capacitor is disposed between the semiconductor device and the top surface of the conductive structure. The capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof for electrical connection to the conductive structure and a plurality of second electrodes disposed adjacent to the second surface thereof for electrical connection to the semiconductor device. The encapsulant covers the semiconductor device and the conductive structure. The external pillars are disposed around the semiconductor device and extend through the encapsulant.

[0007] In some embodiments, a method for manufacturing a semiconductor package structure includes: (a) providing at least one capacitor, an encapsulant, and a plurality of external pillars on a semiconductor device, wherein the capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof and a plurality of second electrodes disposed adjacent to the second surface thereof for electrical connection to the semiconductor device; the encapsulant covers the semiconductor device; and the external pillars extend through the encapsulant; and (b) forming a conductive structure on the at least one capacitor, the encapsulant, and the external pillars, wherein the first electrodes of the capacitor are electrically connected to the conductive structure, and the at least one capacitor is disposed between the semiconductor device and the conductive structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] Aspects of some embodiments of the present application are readily understood when considered in conjunction with the following detailed description and accompanying drawings, in which:

[0009] Figure 1 A cross-sectional view illustrating a capacitor bank structure according to some embodiments of the present application is described.

[0010] Figure 2 A cross-sectional view illustrating a capacitor bank structure according to some embodiments of the present application is described.

[0011] Figure 3 A cross-sectional view illustrating a capacitor bank structure according to some embodiments of the present application is described.

[0012] Figure 4 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present application is described.

[0013] Figure 5 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present application is described.

[0014] Figure 6A cross-sectional view of a semiconductor package structure according to some embodiments of the application is illustrated.

[0015] Figure 7 A cross-sectional view of a semiconductor package structure according to some embodiments of the application is illustrated.

[0016] Figure 8 A cross-sectional view of a semiconductor package structure according to some embodiments of the application is illustrated.

[0017] Figure 9 A cross-sectional view of a semiconductor package structure according to some embodiments of the application is illustrated.

[0018] Figure 10 A cross-sectional view of a semiconductor package structure according to some embodiments of the application is illustrated.

[0019] Figure 11 A cross-sectional view of a semiconductor package structure according to some embodiments of the application is illustrated.

[0020] Figure 12 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0021] Figure 13 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0022] Figure 14 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0023] Figure 15 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0024] Figure 16 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0025] Figure 17 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0026] Figure 18 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0027] Figure 19 An example of one or more stages of a method for manufacturing a capacitor bank structure according to some embodiments of the application is illustrated.

[0028] Figure 20 Illustrate one or more stages of an example of a method for fabricating a capacitor bank structure according to some embodiments of the application.

[0029] Figure 21 Illustrate one or more stages of an example of a method for fabricating a capacitor bank structure according to some embodiments of the application.

[0030] Figure 22 Illustrate one or more stages of an example of a method for fabricating a capacitor bank structure according to some embodiments of the application.

[0031] Figure 23 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0032] Figure 24 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0033] Figure 25 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0034] Figure 26 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0035] Figure 27 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0036] Figure 28 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0037] Figure 29 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0038] Figure 30 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0039] Figure 31 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0040] Figure 32 Illustrate one or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the application.

[0041] Figure 33 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0042] Figure 34 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0043] Figure 35 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0044] Figure 36 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0045] Figure 37 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0046] Figure 38 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0047] Figure 39 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0048] Figure 40 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0049] Figure 41 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0050] Figure 42 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0051] Figure 43 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0052] Figure 44 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0053] Figure 45 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0054] Figure 46 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0055] Figure 47 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0056] Figure 48 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0057] Figure 49 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0058] Figure 50 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0059] Figure 51 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0060] Figure 52 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0061] Figure 53 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0062] Figure 54 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0063] Figure 55 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0064] Figure 56 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated.

[0065] Figure 57 An example of one or more stages of a method for fabricating a semiconductor package structure in accordance with some embodiments of the application is illustrated. DETAILED DESCRIPTION

[0066] Common reference numbers are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of the present application will be readily understood by the detailed description in conjunction with the accompanying drawings.

[0067] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the application. These are, of course, merely examples and are in no way limiting of the application. For example, in the following description, a reference to first feature being on or on top of a second feature can include embodiments where the first feature is formed or arranged directly in contact with the second feature, and can also include embodiments where additional features can be formed or arranged between the first feature and the second feature such that the first feature and the second feature can not be directly in contact. Additionally, the present application can refer to reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0068] In comparative packaging structures, a capacitor such as a decoupling capacitor can be placed as close as possible to the semiconductor die or hot spot in order to increase its effectiveness. That is, the capacitor can be mounted on a side of the semiconductor die, on a land of the substrate, or embedded in the substrate. These three types are described as follows. In a first type, a capacitor mounted on the side of the semiconductor die is called a "die side capacitor (DSC)." The capacitor and the semiconductor die are mounted side by side to the substrate. While the DSC is easy to package, the disadvantage is that the current path is too long and too much area is wasted. In a second type, a capacitor embedded inside the substrate is called an "embedded capacitor (ECC)." While the ECC has better performance than the DSC, the thickness of the substrate to accommodate the ECC is relatively large. Furthermore, the assembly cost of the ECC can be relatively high. In a third type, a capacitor mounted on a land pad of the bottom surface of the substrate is called a "land side capacitor (LSC)." While the LSC does not have the thickness and cost issues compared to the ECC, the LSC reduces the number of solder balls. Furthermore, the LSC increases the size of the solder balls.

[0069] At least some embodiments of the present application provide a semiconductor packaging structure that includes at least one capacitor disposed between a semiconductor device and a conductive structure. As a result, the decoupling loop is shortened, and the ball planting area of the bottom surface of the conductive structure is increased.

[0070] Figure 1A cross-sectional view of a capacitor bank structure 1 according to some embodiments of the present disclosure is illustrated. The capacitor bank structure 1 can include one or more capacitors 12, a protection material 13 (e.g., including a first protection material 13a and a second protection material 13b), a first dielectric layer 14, a plurality of first pillars 15, a plurality of conductive pads 16, a second dielectric layer 17, a third dielectric layer 18, a plurality of second pillars 19, and a plurality of conductive pillars 11.

[0071] The capacitors 12 are disposed side-by-side. The capacitors 12 can be double-sided decoupling capacitors or single-sided decoupling capacitors. As shown in FIG. 1, the capacitors 12 are double-sided decoupling capacitors. Figure 1 As shown in FIG. 2, each of the capacitors 12 is a double-sided decoupling capacitor and has a first surface 121 and a second surface 122 opposite to the first surface 121, and includes a plurality of first electrodes 123 and a plurality of second electrodes 124. The first electrodes 123 are disposed adjacent to the first surface 121 of the capacitor 12 for external connection, and the second electrodes 124 are disposed adjacent to the second surface 122 of the capacitor 12 for external connection. That is, both sides (e.g., the first surface 121 and the second surface 122) of the capacitor 12 can be used for electrical connection. In addition, the first surface 121 is electrically connected to the second surface 122. Thus, the first electrodes 123 on the first surface 121 can be electrically connected to the second electrodes 124 on the second surface 122. It is noted that the number of the first electrodes 123 can be equal to or different from the number of the second electrodes 124. In addition, each of the first electrodes 123 has a first surface 1231 and a sidewall 1233, and each of the second electrodes 124 has a sidewall 1243. The thickness of each of the capacitors 12 can be less than 50 pm, or less than 30 pm.

[0072] The conductive pads 16 are electrically connected to the second electrodes 124 of the capacitors 12. In some embodiments, the conductive pads 16 can be copper layers, which can further include at least one surface finishing layer (e.g., a nickel (Ni) layer 161 and a gold (Au) layer 162). The Au layer 162 of the surface finishing layer of the conductive pads 16 is connected or bonded to the second electrodes 124 of the capacitors 12 by a solder layer 125. As shown in FIG. 3, each of the conductive pads 16 has a second surface 164 and a sidewall 163. Figure 1

[0073] The protection material 13 covers the capacitors 12, the sidewalls 1233 of the first electrodes 123, the sidewalls 1243 of the second electrodes 124, and the sidewalls 163 of the conductive pads 16. As shown in FIG. 4, the protection material 13 includes the first protection material 13a and the second protection material 13b. The first protection material 13a covers the capacitors 12, the sidewalls 1233 of the first electrodes 123, the sidewalls 1243 of the second electrodes 124, and the sidewalls 163 of the conductive pads 16. The second protection material 13b covers the first protection material 13a. Figure 1 ​As shown, protective material 13 may be located between the first dielectric layer 14 and the second dielectric layer 17. Protective material 13 also has a first surface 131 corresponding to a first surface 121 of capacitor 12 and a second surface 132 corresponding to a second surface 122 of capacitor 12. The first surface 131 of protective material 13 may contact the first dielectric layer 14, and the second surface 132 of protective material 13 may contact the second dielectric layer 17. In some embodiments, protective material 13 may include an underfill and / or a molding compound. Figure 1 As shown, the protective material 13 may comprise a first protective material 13a and a second protective material 13b. The first protective material 13a covers the sidewalls 1243 of the capacitor 12 and the second electrode 124, as well as the sidewalls 163 of the conductive pad 16. The second protective material 13b covers the sidewalls 1233 of the first protective material 13b and the first electrode 123. The material of the first protective material 13a may be the same as or different from the material of the second protective material 13b. In some embodiments, the material of the first protective material 13a may be an underfill, and the material of the second protective material 13b may be a molding compound 13b. The first protective material 13a may have a first surface 131a and a second surface 132a opposite to the first surface 131a. The first surface 131a of the first protective material 13a may be substantially coplanar with the first surface 121 of the capacitor 12. The second protective material 13b may have a first surface 131b and a second surface 132b opposite to the first surface 131b. A portion of the second protective material 13b is disposed between the first surface 131a of the first protective material 13a and the first dielectric layer 14. The first surface 131b of the second protective material 13b is the first surface 131 of the protective material 13. The second surface 132b of the second protective material 13b and the second surface 132a of the first protective material 13a constitute the second surface 132 of the protective material 13.

[0074] Conductive supports 11 are positioned around the capacitor 12 and extend through the protective material 13. For example... Figure 1 As shown, conductive struts 11 are disposed around the capacitor 12 and the first protective material 13a of the protective material 13, and extend through the second protective material 13b of the protective material 13. Conductive struts 11 may be disposed between the first dielectric layer 14 and the third dielectric layer 18, and extend through the second dielectric layer 17. Each of the conductive struts 11 has a first surface 111 and a second surface 112 opposite to the first surface 111. Figure 1 As shown, the first surface 1231 of the first electrode 123, the first surface 111 of the conductive pillar 11 and the first surface 131 of the protective material 13 are substantially coplanar with each other.

[0075] A first dielectric layer 14 (e.g., a passivation layer) is disposed on the first surface 131 of the protective material 13 and defines a plurality of openings 141 to expose the first electrodes 123 and the conductive pillars 11. The first dielectric layer 14 can include or be formed of a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy resin or a polyimide (PI) including a photoinitiator, or a combination of two or more of these. First pillars 15 are disposed in the openings 141 of the first dielectric layer 14 and protrude from the first dielectric layer 14. Thus, the first pillars 15 contact the first surfaces 1231 of the first electrodes 123 and the first surfaces 111 of the conductive pillars 11.

[0076] A second dielectric layer 17 (e.g., a passivation layer) is disposed on the second surface 132 of the protective material 13 and covers the sidewalls 163 of the conductive pads 16 and the sidewalls of the conductive pillars 11. The second dielectric layer 17 has a first surface 171 and a second surface 172 opposite the first surface 171. As shown, the second surfaces 164 of the conductive pads 16, the second surfaces 112 of the conductive pillars 11, and the second surface 172 of the second dielectric layer 17 are substantially coplanar with each other. The second dielectric layer 17 can include or be formed of a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy resin or a polyimide (PI) including a photoinitiator, or a combination of two or more of these. Figure 1

[0077] A third dielectric layer 18 (e.g., a passivation layer) is disposed on the second dielectric layer 17 and defines a plurality of openings 181 to expose the conductive pads 16 and the conductive pillars 11. The third dielectric layer 18 can include or be formed of a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy resin or a polyimide (PI) including a photoinitiator, or a combination of two or more of these. Second pillars 19 are disposed in the openings 181 of the third dielectric layer 18 and protrude from the third dielectric layer 18. Thus, the second pillars 19 contact the second surfaces 164 of the conductive pads 16 and the second surfaces 112 of the conductive pillars 11. As shown, some of the second pillars 19 can be electrically connected to some of the first pillars 15 through the conductive pads 16, the Ni layer 161, the Au layer 162, the solder layer 125, the second electrodes 124, the capacitors 12, and the first electrodes 123. In addition, some of the second pillars 19 can be electrically connected to some of the first pillars 15 through the conductive pillars 11. Figure 1

[0078] Figure 2 ​​A cross-sectional view of a capacitor bank structure 1a according to some embodiments of the present application is illustrated. Figure 2 The capacitor bank structure 1a can be similar to the capacitor bank structure 1 of Figure 1 the difference being that the electrically conductive pillars 11 are omitted and the protective material 13 can comprise the first protective material 13a or the second protective material 13b alone. As shown in Figure 2 the first surface 131a of the first protective material 13a is the first surface 131 of the protective material 13 and the second surface 132a of the first protective material 13a is the second surface 132 of the protective material 13.

[0079] Figure 3 A cross-sectional view of a capacitor bank structure 1b according to some embodiments of the present application is illustrated. Figure 3 The capacitor bank structure 1b can be similar to the capacitor bank structure 1 of Figure 1 the difference being that the electrically conductive pillars 11 are omitted. As shown in Figure 3 the second surface 132b of the second protective material 13b is disposed on the first surface 131a of the first protective material 13a. The first surface 131b of the second protective material 13b is the first surface 131 of the protective material 13 and the second surface 132a of the first protective material 13a is the second surface 132 of the protective material 13.

[0080] Figure 4 A cross-sectional view of a semiconductor package structure 2 according to some embodiments of the present application is illustrated. The semiconductor package structure 2 comprises an electrically conductive structure 24, a semiconductor device 25, one or more capacitors 12, an encapsulant 26, a plurality of outer pillars 27, a top package 3, a plurality of inner pillars 28, a redistribution circuit structure 29, a wiring structure 4, and a plurality of solder bumps 37.

[0081] The conductive structure 24 may be a substrate or an interposer, and may have a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the conductive structure 24 may include four dielectric layers 243 (e.g., four passivation layers) and four metal circuit layers 244 electrically connected to each other. The semiconductor device 25 may be a semiconductor logic die, such as a central processing unit (CPU), graphics processing unit (GPU), or application processor (AP), and may be electrically connected to the top surface 241 of the conductive structure 24. Figure 4 As shown, the semiconductor device 25 has a first surface 251 and a second surface 252 opposite to the first surface 241. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 via a redistribution circuit structure 29, a capacitor bank structure 1a, and an internal support 28. The second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. The capacitor bank structure 1a may be the same as... Figure 2 The capacitor bank structure 1a may include one or more capacitors 12. Therefore, the capacitor 12 is disposed between the first surface 251 of the semiconductor device 25 and the top surface 241 of the conductive structure 24. A first electrode 123 is electrically connected to the conductive structure 24. A second electrode 124 is electrically connected to the semiconductor device 25 via a solder layer 125, a Ni layer 161, an Au layer 162, a conductive pad 16, a second pillar 19, a conductive pad 281, and a redistribution circuit structure 29. The capacitor 12 is not embedded in the conductive structure 24. The area of ​​the capacitor bank structure 1a, viewed from a top view, is smaller than the area of ​​the semiconductor device 25, viewed from a top view. An internal pillar 28 is disposed outside the capacitor bank structure 1a and electrically connected to the semiconductor device 25 and the conductive structure 24.

[0082] A redistribution circuit structure 29 (e.g., including a first passivation layer 291, a second passivation layer 294, and a redistribution layer (RDL) 293) is disposed between the semiconductor device 25 and the capacitor bank structure 1a (including the capacitor 12). The size of the redistribution circuit structure 29 may be substantially equal to the size of the semiconductor device 25. Internal pillars 28 may stand on the redistribution circuit structure 29. Furthermore, the redistribution layer (RDL) 293 may include a fiducial mark 296. However, in some embodiments, the redistribution circuit structure 29 may be omitted.

[0083] The encapsulant 26 is disposed in a space between the wiring structure 4 and the conductive structure 24 to cover the semiconductor device 25, the capacitor bank structure la (including the capacitors 12), the conductive structure 24, the internal pillar 28, and the redistribution circuit structure 29. The material of the encapsulant 26 can be a molding compound.

[0084] The external pillar 27 is disposed around the semiconductor device 25 and extends through the encapsulant 26 to electrically connect the wiring structure 4 and the conductive structure 24. The wiring structure 4 is disposed between the encapsulant 26 and the top package 3. The wiring structure 4 includes at least one dielectric layer and at least one circuit layer 40. However, in some embodiments, the wiring structure 4 can be omitted.

[0085] The top package 3 is electrically connected to the external pillar 27 and the semiconductor device 25 by the internal solder 35 and the wiring structure 4. In one embodiment, the top package 3 includes a top substrate 30, one or more memory dice 32, and a top encapsulant 34. The memory dice 32 can be Synchronous Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), lower power DDR (LPDDR), or High Bandwidth Memory (HBM). The memory dice 32 are electrically connected to the top substrate 30 by wire bonds. However, the memory dice 32 can be electrically connected to the top substrate 30 by flip chip bonds. The top encapsulant 34 covers the plurality of memory dice 32 and the top substrate 30. Additionally, an intermediate encapsulant 36 can be included in a space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Furthermore, solder bumps 37 are disposed on the second surface 242 of the conductive structure 24 for external connections.

[0086] In the semiconductor package structure 2 described in Figure 4 In the semiconductor package structure 2 described in

[0087] Figure 5A cross-sectional view of a semiconductor package structure 2a according to some embodiments of the present invention is shown. Figure 5 The semiconductor packaging structure 2a can be similar to Figure 4 The semiconductor packaging structure 2 differs from the capacitor bank structure 1a in that it is... Figure 1 The capacitor bank structure 1 is replaced, and the internal support 28 is omitted. For example... Figure 5 As shown, the area of ​​the capacitor bank structure 1a, viewed from top view, is approximately equal to the area of ​​the semiconductor device 25, viewed from top view. Therefore, Figure 4 The internal support 28 is not necessary, and the conductive support 11 of the capacitor bank structure 1 is electrically connected to the redistributed circuit structure 29 (or semiconductor device 25) and the conductive structure 24. Additionally, a bottom filler 38 is formed between the capacitor bank structure 1 and the redistributed circuit structure 29 (or semiconductor device 25) to cover and protect the joint structure between them. The area of ​​the bottom filler 38, viewed from the top view, is approximately equal to the area of ​​the semiconductor device 25, viewed from the top view.

[0088] Figure 6 A cross-sectional view of a semiconductor package structure 2b according to some embodiments of the present invention is shown. Figure 6 The semiconductor packaging structure 2b can be similar to Figure 4semiconductor package structure 2, and the differences are described as follows. The internal pillars 28 are disposed on the first surface 251 of the semiconductor device 25. The middle redistribution structure 43 (including a redistribution layer (RDL) 431) is disposed on the encapsulant 26 to electrically connect the internal pillars 28 and the external pillars 27. The capacitors 12 are disposed on and electrically connected to the redistribution layer (RDL) 431 of the middle redistribution structure 43. Each of the capacitors 12b is a double-sided decoupling capacitor, and has a first surface 121b and a second surface 122b opposite to the first surface 121b, and includes a plurality of first electrodes 123b and a plurality of second electrodes 124b. The first electrodes 123b are disposed adjacent to the first surface 121b of the capacitor 12b for external connection, and the second electrodes 124b are disposed adjacent to the second surface 122b of the capacitor 12b for external connection. That is, both sides (e.g., the first surface 121b and the second surface 122b) of the capacitor 12b can be used for electrical connection. The bottom protection material 42 (e.g., a bottom filler) is disposed on the middle redistribution structure 43 to cover and protect the capacitors 12. It should be noted that the area of the bottom protection material 42 from a top view is greater than the area of the semiconductor device 25 from a top view. The insulating layer 46 is formed or disposed on the middle redistribution structure 43 to cover the bottom protection material 42 and the sidewalls of the first electrodes 123b of the capacitors 12b. The conductive structure 24 is disposed on the insulating layer 46 and electrically connected to the first electrodes 123b of the capacitors 12b. In addition, a plurality of external pillars 27' are disposed around the capacitors 12b and the bottom protection material 42, and electrically connect the middle redistribution structure 43 and the conductive structure 24.

[0089] Figure 7 A cross-sectional view of a semiconductor package structure 2c according to some embodiments of the present application is illustrated. Figure 7 The semiconductor package structure 2c can be similar to the semiconductor package structure 2 Figure 4 except for the location of the capacitors 12c. As shown in Figure 7 The capacitors 12c are embedded in the conductive structure 24. In addition, the thickness of the semiconductor device 25c can be substantially equal to the height of the external pillars 27.

[0090] Figure 8 A cross-sectional view of a semiconductor package structure 2d according to some embodiments of the present application is illustrated. Figure 8 The semiconductor package structure 2d can be similar to the semiconductor package structure 2 Figure 4 except for the location of the capacitors 12d. As shown in Figure 8As shown in FIG. 12, the capacitor 12d is disposed between the conductive structure 24 and the wiring structure 4. The capacitor 12d is disposed around the semiconductor device 25d. That is, the capacitor 12d and the semiconductor device 25d are disposed side by side. The thickness of the semiconductor device 25d, the thickness of the capacitor 12d, and the height of the external post 27 can be substantially equal to each other.

[0091] Figure 9 A cross-sectional view of a semiconductor package structure 2e according to some embodiments of the present application is illustrated. The semiconductor package structure 2e includes a photo die (P-die) 50, an electrical die (E-die) 52, a plurality of capacitors 12e, a plurality of external posts 27, an encapsulant 26, and a plurality of solder bumps 37. The electrical die (E-die) 52, the capacitors 12e, and the external posts 27 are electrically connected to a bottom surface of the photo die (P-die) 50. That is, the electrical die (E-die) 52 and the capacitors 12e are disposed side by side. The external posts 27 are disposed around the electrical die (E-die) 52 and the capacitors 12e. The encapsulant 26 covers the bottom surface of the photo die (P-die) 50, the electrical die (E-die) 52, the capacitors 12e, and the external posts 27. The external posts 27 extend through the encapsulant 26 and are exposed from a bottom surface of the encapsulant 26. The solder bumps 37 are disposed on the bottom surface of the encapsulant 26 and are electrically connected to the external posts 27.

[0092] Figure 10 A cross-sectional view of a semiconductor package structure 2f according to some embodiments of the present application is illustrated. The semiconductor package structure 2f includes a conductive structure 24, a capacitor bank structure 1b, a semiconductor device 54, a memory die 56, an encapsulant 26, and a plurality of solder bumps 37. The capacitor bank structure 1b is disposed on or electrically connected to a first surface 241 of the conductive structure 24. The capacitor bank structure 1b can include a plurality of capacitors 12f, a bridge die 58, a plurality of posts 62, and a protection material 60. The capacitors 12f and the bridge die 58 are disposed side by side and are covered by the protection material 60. The posts 62 extend through the protection material 60. The semiconductor device 54 and the memory die 56 are disposed on the capacitor bank structure 1b and are electrically connected to the capacitors 12f and the bridge die 58. Thus, the capacitor bank structure 1b is disposed between the semiconductor device 54 and the memory die 56 and the conductive structure 24. The semiconductor device 54 is electrically connected to the memory die 56 through the bridge die 58. The encapsulant 26 covers the first surface 241 of the conductive structure 24, the capacitor bank structure 1b, the semiconductor device 54, and the memory die 56. The solder bumps 37 are disposed on a second surface 242 of the conductive structure 24.

[0093] Figure 11 A cross-sectional view of a semiconductor package structure 2g according to some embodiments of the present application is illustrated. Figure 11 The semiconductor package structure 2g can be similar toFigure 10 semiconductor package structure 2f, except for the locations of the capacitor 12g and the bridge die 58. As shown, the bridge die 58 is embedded in the conductive structure 24, and the capacitor 12g is disposed on or electrically connected to a first surface 241 of the conductive structure 24. The encapsulant 26 covers the first surface 241 of the conductive structure 24, the capacitor 12g, the semiconductor device 54, and the memory die 56. Figure 11

[0094] Figures 12 to 22 A method for fabricating a capacitor bank structure according to some embodiments of the present disclosure is described. In some embodiments, the method is used to fabricate the capacitor bank structure 1 shown in Figure 1 Referring to Figure 12 , a first support carrier 20 and a second dielectric layer 17 are provided. The second dielectric layer 17 is disposed on the first support carrier 20 and defines a plurality of openings 171.

[0095] Referring to Figure 13 , a plurality of conductive pads 16 and a plurality of conductive pillars 11 are formed in the openings 171 of the second dielectric layer 17. The conductive pads 16 can include at least one surface finishing layer (e.g., a Ni layer 161 and an Au layer 62) on their end surfaces. As shown in Figure 13 , each of the conductive pads 16 has a second surface 164 and a sidewall 163.

[0096] Referring to Figure 14 , one or more capacitors 12 are electrically connected to the conductive pads 16. The capacitors 12 can be double-sided decoupling capacitors. The capacitors 12 have a first surface 121 and a second surface 122 opposite to the first surface 121, and include a plurality of first electrodes 123 and a plurality of second electrodes 124. The first electrodes 123 are disposed adjacent to the first surface 121 of the capacitors 12, and the second electrodes 124 are disposed adjacent to the second surface 122 of the capacitors 12. The second electrodes 124 of the capacitors 12 are connected to the surface finishing layers (e.g., the Ni layer 161 and the Au layer) of the conductive pads 16 through a solder layer 125. In addition, each of the first electrodes 123 has a first surface 1231 and a sidewall 1233, and each of the second electrodes 124 has a sidewall 1243.

[0097] Referring to Figure 15 and Figure 16 , a protection material 13 (e.g., including a first protection material 13a and a second protection material 13b) is formed to cover the capacitors 12, the sidewalls 1233 of the first electrodes 123, the sidewalls 1243 of the second electrodes 124, and the sidewalls 163 of the conductive pads 16. Referring to Figure 15 , the first protection material 13a is formed to cover the capacitors 12, the sidewalls 1243 of the second electrodes 124, and the sidewalls 163 of the conductive pads 16. Referring to​Figure 16 The second protective material 13b of the protective material 13 is thinned from the first surface 131 to expose the first electrode 123 and the conductive pillar 11. Meanwhile, the first surface 1231 of the first electrode 123, the first surface 111 of the conductive pillar 11, and the first surface 131 of the protective material 13 are substantially coplanar with each other.

[0098] Referring to Figure 17 The first dielectric layer 14 is formed on the first surface 131 of the protective material 13. The first dielectric layer 14 defines a plurality of openings 141 to expose the first electrode 123 and the conductive pillar 11.

[0099] Referring to Figure 18 The first dielectric layer 14 is formed on the first surface 131 of the protective material 13. The first dielectric layer 14 defines a plurality of openings 141 to expose the first electrode 123 and the conductive pillar 11.

[0100] Referring to Figure 19 The first dielectric layer 14 is formed on the first surface 131 of the protective material 13. The first dielectric layer 14 defines a plurality of openings 141 to expose the first electrode 123 and the conductive pillar 11.

[0101] Referring to Figure 20 The second support carrier 22 is attached to the first pillars 15 and the first dielectric layer 14 by the adhesive layer 221. Subsequently, the first support carrier 20 is removed.

[0102] Referring to Figure 21 The third dielectric layer 18 is formed on the second dielectric layer 17. The third dielectric layer 18 defines a plurality of openings 181 to expose the conductive pads 16 and the conductive pillars 11.

[0103] Referring to Figure 22 The second dielectric layer 17 is formed on the first dielectric layer 14. The second dielectric layer 17 defines a plurality of openings 171 to expose the first electrode 123 and the conductive pillar 11. Figure 1 The second pillars 19 contact the conductive pads 16 and the conductive pillars 11, and protrude from the third dielectric layer 18. Subsequently, a singulation process is performed, and the second support carrier 22 and the adhesive layer 221 are removed so as to form a plurality of capacitor bank structures 1 of

[0104] Figures 23 to 36 A method for fabricating a semiconductor package structure according to some embodiments of the present application is described. In some embodiments, the method is used to fabricate the semiconductor package structure 2 shown in Figure 4 Referring to Figure 23A wafer 5 comprising a plurality of semiconductor devices 25 is provided. The semiconductor devices 25 can be logic dies, such as central processing units (CPUs), graphics processing units (GPUs), or application processors (APs), and can have a first surface 251 and a second surface 252 opposite to the first surface 251.

[0105] Referring to Figure 24 A first passivation layer 291 is formed on the first surface 251 of the semiconductor devices 25 (e.g., the first surface of the wafer 5). The first passivation layer 291 defines a plurality of openings 292.

[0106] Referring to Figure 25 A redistribution layer (RDL) 293 is formed in the openings 292 and on the first passivation layer 291. In some embodiments, the redistribution layer (RDL) 293 can include fiducial marks 296.

[0107] Referring to Figure 26 A second passivation layer 294 is formed on the redistribution layer (RDL) 293 and the first passivation layer 291. The second passivation layer 294 defines a plurality of openings 295 to expose portions of the redistribution layer (RDL) 293. Meanwhile, a redistribution structure 29 (comprising the first passivation layer 291, the redistribution layer (RDL) 293, and the second passivation layer 294) is formed.

[0108] Referring to Figure 27 A plurality of conductive pads 281 and a plurality of internal pillars 28 are formed in the openings 295 and on the redistribution layer (RDL) 293. There can be at least one surface finish layer on the end surface of the conductive pads 281.

[0109] Referring to Figure 28 , Figure 2 The capacitor bank structure 1a is attached to the conductive pads 281. In one embodiment, the second pillars 19 of the capacitor bank structure 1a are connected to the surface finish layer of the conductive pads 281. Thus, the capacitors 12 are electrically connected to the semiconductor devices 25. The internal pillars 28 are disposed around the capacitor bank structure 1a (comprising the capacitors 12). It is noted that the fiducial marks 296 of the redistribution layer (RDL) 293 can be used for positioning when the capacitor bank structure 1a is attached to the redistribution structure 29.

[0110] Referring to Figure 29 A singulation process is performed on the wafer 5 to form a plurality of assemblies 5a.

[0111] Referring to Figure 30 A third support carrier 41 (or a first carrier) is provided. Subsequently, a wiring structure 4 (comprising at least one dielectric layer and at least one circuit layer 40) is formed on the third support carrier 41 (or the first carrier). Subsequently, a plurality of external pillars 27 are formed on or attached to the wiring structure 4.

[0112] Referring to Figure 31 The second surface 252 of the semiconductor device 25 of the assembly 5a is attached (or adhered) to the wiring structure 4 on the third support carrier 41 (or first carrier). Meanwhile, the external pillar 27 is disposed around the assembly 5a.

[0113] Referring to Figure 32 The encapsulant 26 is formed to cover the assembly 5a (including the semiconductor device 25, the capacitor 12) and the external pillar 27.

[0114] Referring to Figure 33 The encapsulant 26 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surface of the encapsulant 26, the bottom surface of the external pillar 27, the bottom surface of the internal pillar 28, and the bottom surface of the first pillar 15 are substantially coplanar with each other.

[0115] Referring to Figure 34 The conductive structure 24 is formed or disposed on the encapsulant 26 to electrically connect the external pillar 27, the first pillar 15, and the internal pillar 28. The conductive structure 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the conductive structure 24 can include four dielectric layers 243 (e.g., four passivation layers) and four metal circuit layers 244 electrically connected to each other. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 through the redistribution circuit structure 29, the capacitor bank structure la, and the internal pillar 28. The capacitor 12 is not embedded in the conductive structure 24. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.

[0116] Referring to Figure 35 The fourth support carrier 45 (or second carrier) is attached to the second surface 242 of the conductive structure 24 through the adhesive layer 44. Subsequently, the third support carrier 41 (or first carrier) is removed.

[0117] Referring to Figure 36The top package 3 is electrically connected to the external pillar 27. In one embodiment, the top package 3 is electrically connected to the external pillar 27 and the semiconductor device 25 by the internal solder 35 and the wiring structure 4. In one embodiment, the top package 3 includes a top substrate 30, one or more memory dies 32, and a top encapsulant 34. The memory dies 32 can be synchronous random access memory (SRAM), dynamic random access memory (DRAM), low power DDR (LPDDR), or high bandwidth memory (HBM). The memory dies 32 are electrically connected to the top substrate 30 by wire bonds. However, the memory dies 32 can be electrically connected to the top substrate 30 by flip chip bonding. The top encapsulant 34 covers the plurality of memory dies 32 and the top substrate 30. In addition, the middle encapsulant 36 can be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a singulation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed so as to form a plurality of semiconductor package structures 2 of Figure 4 .

[0118] Figures 37 to 46 A method for fabricating a semiconductor package structure according to some embodiments of the present disclosure is described. In some embodiments, the method is used to fabricate the semiconductor package structure 2a shown in Figure 5 . The initial stages of the illustrated process are the same as or similar to the stages described in Figures 23 to 26 . Figure 37 depicts stages after the stages depicted in Figure 26 .

[0119] Referring to Figure 37 , a plurality of conductive pads 281 are formed in the openings 295 and on the RDL 293. There can be a surface finish layer on the end faces of the conductive pads 281.

[0120] Referring to Figure 38 , Figure 1 the capacitor bank structure 1 is attached to the conductive pads 281. In one embodiment, the second pillar 19 and the conductive pillars 11 of the capacitor bank structure 1 are connected to the surface finish layer of the conductive pads 281. Thus, the capacitors 12 are electrically connected to the semiconductor device 25. Subsequently, the underfill 38 is formed between the space between the capacitor bank structure 1 and the re-distribution circuit structure 29 (or the semiconductor device 25) to cover and protect the bonding structures between the capacitor bank structure 1 and the re-distribution circuit structure 29 (or the semiconductor device 25).

[0121] Referring to Figure 39 , a singulation process is performed on the wafer 5 to form a plurality of assemblies 5b.

[0122] Referring to Figure 40, a third support carrier 41 (or a first carrier) is provided. Subsequently, a wiring structure 4 (including at least one dielectric layer and at least one circuit layer 40) is formed on the third support carrier 41 (or the first carrier). Subsequently, a plurality of external pillars 27 is formed on or attached to the wiring structure 4.

[0123] Referring to Figure 41 , a second surface 252 of the semiconductor device 25 of the assembly 5b is attached (or adhered) to the wiring structure 4 on the third support carrier 41 (or the first carrier). Meanwhile, the external pillars 27 are disposed around the assembly 5b.

[0124] Referring to Figure 42 , an encapsulant 26 is formed to cover the assembly 5b (including the semiconductor device 25, the capacitor 12) and the external pillars 27.

[0125] Referring to Figure 43 , the encapsulant 26 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surface of the encapsulant 26, the bottom surface of the external pillars 27, and the bottom surface of the first pillars 15 are substantially coplanar with each other.

[0126] Referring to Figure 44 , a conductive structure 24 is formed or disposed on the encapsulant 26 to electrically connect the external pillars 27 and the first pillars 15. The conductive structure 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 through the redistribution circuit structure 29 and the capacitor bank structure 1. Subsequently, a plurality of solder bumps 37 is formed on the second surface 242 of the conductive structure 24.

[0127] Referring to Figure 45 , a fourth support carrier 45 (or a second carrier) is attached to the second surface 242 of the conductive structure 24 through an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.

[0128] Referring to Figure 46 , the top package 3 is electrically connected to the external pillars 27. In one embodiment, the top package 3 is electrically connected to the external pillars 27 and the semiconductor device 25 through the internal solder 35 and the wiring structure 4. In addition, an intermediate encapsulant 36 can be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a singulation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed to form a plurality of semiconductor package structures 2a of Figure 5 .

[0129] Figures 47 to 57 A method for manufacturing semiconductor package structures according to some embodiments of the present application is described. In some embodiments, the method is used to manufactureFigure 6 The semiconductor package structure 2b is shown. The initial stages of the illustrated process are the same as or similar to those described above with respect to the semiconductor package structure 2a. Figures 23 to 26 The stages described above with respect to the semiconductor package structure 2a are followed. Figure 47 The stages described above with respect to the semiconductor package structure 2a are followed. Figure 26 The stages described above with respect to the semiconductor package structure 2a are followed.

[0130] Referring to FIG. 27, a plurality of external pillars 27 is formed on the wiring structure 4. Figure 47 Referring to FIG. 28, a second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. The external pillars 27 are disposed around the semiconductor device 25. Subsequently, a plurality of internal pillars 28 is formed on a first surface 251 of the semiconductor device 25. In some embodiments, the internal pillars 28 can be first formed on the first surface 251 of the semiconductor device 25; subsequently, the second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4.

[0131] Figure 48 Referring to FIG. 29, the encapsulant 26 is formed to cover the semiconductor device 25, the wiring structure 4, the internal pillars 28, and the external pillars 27.

[0132] Referring to FIG. 30, the encapsulant 26 is thinned from its bottom surface by, for example, grinding. At the same time, the bottom surface of the encapsulant 26, the bottom surface of the external pillars 27, and the bottom surface of the internal pillars 28 are substantially coplanar with each other. Figure 49 Referring to FIG. 31, an intermediate redistribution structure 43 (including a redistribution layer (RDL) 431) is formed or disposed on the encapsulant 26 to electrically connect the external pillars 27 and the internal pillars 28.

[0133] Figure 50 Referring to FIG. 32, at least one capacitor 12b is disposed on and electrically connected to the intermediate redistribution structure 43. A second electrode 124b of the capacitor 12b is electrically connected to the redistribution layer (RDL) 431 of the intermediate redistribution structure 43. Thus, the capacitor 12b can be electrically connected to the semiconductor device 25 and the external pillars 27. Subsequently, a bottom protection material 42 (e.g., a bottom filler) is formed or disposed on the intermediate redistribution structure 43 to cover and protect the capacitor 12b. It should be noted that the area of the bottom protection material 42, as viewed from the top, is greater than the area of the semiconductor device 25, as viewed from the top. Subsequently, a plurality of external pillars 27' is formed or disposed on the redistribution layer (RDL) 431 of the intermediate redistribution structure 43. The external pillars 27' are disposed around the capacitor 12b and the bottom filler 42.

[0134] Referring to FIG. 33, a plurality of external pillars 27 is formed on the wiring structure 4. Figure 51 Referring to FIG. 34, a second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. The external pillars 27 are disposed around the semiconductor device 25. Subsequently, a plurality of internal pillars 28 is formed on a first surface 251 of the semiconductor device 25. In some embodiments, the internal pillars 28 can be first formed on the first surface 251 of the semiconductor device 25; subsequently, the second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4.

[0135] Figure 52 Referring to FIG. 35, the encapsulant 26 is formed to cover the semiconductor device 25, the wiring structure 4, the internal pillars 28, and the external pillars 27.

[0136] Referring to FIG. 36, the encapsulant 26 is thinned from its bottom surface by, for example, grinding. At the same time, the bottom surface of the encapsulant 26, the bottom surface of the external pillars 27, and the bottom surface of the internal pillars 28 are substantially coplanar with each other. Figure 53 ​​​The insulating layer 46 is formed or disposed on the intermediate redistribution structure 43 to cover the bottom protection material 42, the sidewall of the first electrode 123b of the capacitor 12b, and the external pillar 27'.

[0137] Referring to Figure 54 The insulating layer 46 is thinned from its bottom surface by, for example, grinding. At the same time, the bottom surface of the insulating layer 46, the bottom surface of the first electrode 124b of the capacitor 12b, and the bottom surface of the external pillar 27' are substantially coplanar with each other.

[0138] Referring to Figure 55 The conductive structure 24 is formed or disposed on the insulating layer 46 and electrically connected to the first electrode 123b of the capacitor 12b and the external pillar 27'. In one embodiment, the conductive structure 24 can include four dielectric layers 243 and four metal circuit layers 244. Subsequently, a plurality of solder bumps 37 is formed on the second surface 242 of the conductive structure 24.

[0139] Referring to Figure 56 The fourth support carrier 45 (or second carrier) is attached to the second surface 242 of the conductive structure 24 by the adhesive layer 44. Subsequently, the third support carrier 41 (or first carrier) is removed.

[0140] Referring to Figure 57 The top package 3 is electrically connected to the external pillar 27. In one embodiment, the top package 3 is electrically connected to the external pillar 27 and the semiconductor device 25 by the internal solder 35 and the wiring structure 4. In addition, the intermediate encapsulant 36 can be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a singulation process is performed, and the fourth support carrier 45 (or second carrier) and the adhesive layer 44 are removed to form a plurality of semiconductor package structures 2b. Figure 6

[0141] Unless otherwise stated, spatial descriptions, e.g., "above", "below", "upper", "left", "right", "bottom", "top", "vertical", "horizontal", "side", "higher", "lower", "upper", "on", "under", etc., are indicated with respect to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical embodiments of the structures described herein can be oriented in any direction or manner in space, with the proviso that the advantages of embodiments of the present invention are not vitiated by such an arrangement.

[0142] ​As used herein, the terms “approximately,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered “substantially” the same as or equal to the second numerical value. For example, "generally" vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0143] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is not greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0144] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0145] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to transfer electric current. Conductive materials typically indicate those that exhibit very little or no resistance to current flow. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0146] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0147] While the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing methods and limitations. Other embodiments of the invention may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A capacitor bank structure, comprising: A plurality of capacitors arranged side by side, wherein each of the capacitors comprises a plurality of first electrodes and a plurality of second electrodes opposite to the plurality of first electrodes; Multiple conductive pads are electrically connected to the second electrode; A first protective material covers the sidewalls of the capacitor, the second electrode, and the conductive pad. A second protective material covers the first protective material and the sidewalls of the first electrode, wherein the material of the first protective material is different from the material of the second protective material; A first dielectric layer is disposed on a first surface of the second protective material and defines a plurality of openings to expose the first electrode; as well as Multiple first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

2. The capacitor bank structure according to claim 1, further comprising: A second dielectric layer is disposed on the second surface of the first protective material and the second surface of the second protective material, and covers the sidewall of the conductive pad; A third dielectric layer is disposed on the second dielectric layer and defines a plurality of openings to expose the conductive pad; as well as Multiple second pillars are disposed in the openings of the third dielectric layer and protrude from the third dielectric layer.

3. The capacitor bank structure according to claim 1, wherein the first protective material and the second protective material comprise an underfill or a molding compound.

4. The capacitor bank structure according to claim 1, further comprising a plurality of conductive struts disposed around the capacitor and extending through the second protective material.

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