Soft Error Recovery Latch

Abstract

Embodiments of this disclosure relate to soft error recovery latches. A latch is provided. The latch includes a plurality of memory nodes, including a plurality of data storage nodes configured to store data bits having one of two storage states, and a plurality of complementary data storage nodes configured to store the complement of the data bits. The latch includes a plurality of power supply voltage multi-dependent stages, each corresponding to one of the plurality of memory nodes. Each power supply voltage multi-dependent stage has an output coupled to a memory node and at least two control inputs coupled to at least two other memory nodes, respectively. The power supply voltage multi-dependent stage is configured to cause a change in the state of the data bits stored in the memory node from a first state to a second state in response to a change in the two states of the two data bits stored in the at least two other memory nodes.

Description

Technical Field

[0001] The present disclosure relates to data storage latches, and in particular to data storage latches that are resilient to soft errors occurring in storing data. Background Art

[0002] In some cases, a storage device such as a latch may experience an error that causes one or more stored data bits to change state. For example, as a result of an error, a stored data bit may change state from a logic 0 to a logic 1 or vice versa. Storage errors may occur due to radiation or particle impact, among other reasons. After the error occurs, it propagates through the circuit or system and causes the circuit or system to malfunction or operate in a manner different from its intended purpose.

[0003] In many applications, especially critical ones such as space, automotive or medical applications, the error tolerance is very low. This is because the propagation of errors can have serious adverse consequences. Summary of the invention

[0004] A latch is provided. The latch is soft error resilient and can therefore tolerate errors in one storage bit without adversely affecting the operation of the latch. The latch can recover from a single bit error by exploiting redundancy and dependency.

[0005] As described herein, for each data bit, the latch stores multiple data bits in a corresponding plurality of storage nodes. Some storage nodes store a copy of the data bit, while other storage nodes store the complement of the data bit. The stored data bit can be a logic 0 or a logic 1. For example, if the stored data bit is a logic 0, some storage nodes of the latch store a logic 0, and other storage nodes of the latch store a logic 1 (the complement of logic 0).

[0006] For each storage node, the latch includes one or more multi-dependency levels. The multi-dependency levels link the storage node to two or more other storage nodes of the latch. The multi-dependency levels make the state of a data bit stored in the storage node dependent on the two or more other storage nodes on which it depends. The data in the storage node does change unless the data in the two or more other storage nodes also changes. If the data of only one of the other storage nodes changes, the change is not sufficient to trigger a change in the data of the storage node.

[0007] A change in the data of a storage node occurs when the data in all two or more other storage nodes (on which the storage node depends) changes. If fewer than all other storage nodes change state, the change is not sufficient to trigger a data change. Therefore, latches are resilient to soft errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 shows a schematic diagram of a latch;

[0009] Figure 2 A schematic diagram showing a latch; and

[0010] Figure 3A and 3B A schematic diagram of a trigger is shown. DETAILED DESCRIPTION

[0011] Figure 1 A schematic diagram of a latch 100a is shown. The latch 100a includes a memory stage 101a coupled to a first input stage 102a and a second input stage 104a. The latch 100a is a memory device that stores one or more data bits. The latch 100a includes four data storage nodes: a first data storage node 106a, a second data storage node 106b, a first complementary data storage node 106c, and a second complementary data storage node 106d. The data storage nodes 106a-d are coupled to the first input stage 102a. In the latch 100a, each data storage node 106a-d is coupled to an associated power supply voltage multi-dependency stage 108a-d and an associated reference voltage multi-dependency stage 110a-d.

[0012] Specifically, the latch 100a includes a first power supply voltage multi-dependence stage 108a and a second power supply voltage multi-dependence stage 108b for a first data storage node 106a and a second data storage node 106b, respectively. The latch 100a includes a third power supply voltage multi-dependence stage 108c and a fourth power supply voltage multi-dependence stage 108d for a first complementary data storage node 106c and a second complementary data storage node 106d, respectively. The latch 100a also includes a first reference voltage multi-dependence stage 110a and a second reference voltage multi-dependence stage 110b for the first data storage node 106a and the second data storage node 106b, respectively, and a third reference voltage multi-dependence stage 110c and a fourth reference voltage multi-dependence stage 110d for a third complementary data storage node 106c and a fourth complementary data storage node 106d, respectively.

[0013] The power supply voltage multi-dependent stages 108a, 108b, 108c, 108d selectively couple the data storage nodes 106a, 106b, 106c, 106d, respectively, to a voltage supply node 120. The voltage supply node 120 can provide a power supply voltage (or rail voltage) (V dd) and the like. The power supply voltage may be a voltage level representing a logic 1. The reference voltage multi-dependency stages 110a, 110b, 110c, 110d selectively couple the data storage nodes 106a, 106b, 106c, 106d to the second input stage 104a, respectively. The second input stage 104a selectively couples the reference voltage multi-dependency stages 110a-d to a reference voltage node (not shown) to provide a reference voltage (or ground voltage) for selectively grounding the data storage nodes 106a-d. The reference voltage may be a zero voltage having a voltage level representing a logic 0.

[0014] Each supply voltage multi-dependence stage 108a-d includes two cascaded transistors. The first supply voltage multi-dependence stage 108a, the second supply voltage multi-dependence stage 108b, the third supply voltage multi-dependence stage 108c and the fourth supply voltage multi-dependence stage 108d include first transistors 112a, 112b, 112c, 112d and second transistors 114a, 114b, 114c, 114d, respectively. The first reference voltage multi-dependence stage 110a, the second reference voltage multi-dependence stage 110b, the third reference voltage multi-dependence stage 110c and the fourth reference voltage multi-dependence stage 110d include first transistors 116a, 116b, 116c, 116d and second transistors 118a, 118b, 118c, 118d, respectively.

[0015] In each supply voltage multi-dependent stage 108a-d, a first transistor 112a-d has a drain coupled to a data storage node 106a-d of the stage 108a-d and a source coupled to a drain of a second transistor 114a-d. The first transistor 112a-d has a gate coupled to another data storage node 106a-d. The second transistor 114a-d has a source coupled to a voltage source node 120 and a gate coupled to another data storage node 106a-d different from the data storage node 106a-d to which the gate of the first transistor 112a-d is coupled.

[0016] Although the first transistors 112a-d and the second transistors 114a-d of the supply voltage multi-dependent stages 108a-d are shown as p-channel metal oxide semiconductor field effect transistors (MOSFETs), any other type of transistors may be used. Each supply voltage multi-dependent stage 108a-d may have a data input at the source of the second transistor 114a-d, a first control input and a second control input at the gates of the first transistor 112a-d and the second transistor 114a-d, respectively, and an output at the drain of the first transistor 112a-d. Thus, the supply voltage multi-dependent stage 108a-d provides an output voltage (the output of the stage 108a-d) at the data storage node 106a-d, which depends on the voltage of the gates of the first transistor 112a-d and the second transistor 114a-d (the control input of the stage 108a-d) and the source voltage at the voltage source node 120 (the input of the stage 108a-d).

[0017] In the first power supply voltage multi-dependence stage 108a, the drain of the first transistor 112a is coupled to the first data storage node 106a, the gate of the first transistor 112a is coupled to the second complementary data storage node 106d, and the gate of the second transistor 114a is coupled to the first complementary data storage node 106c. In the second power supply voltage multi-dependence stage 108b, the drain of the first transistor 112b is coupled to the second data storage node 106b, the gate of the first transistor 112b is coupled to the first complementary data storage node 106c, and the gate of the second transistor 114b is coupled to the second complementary data storage node 106d. In the third power supply voltage multi-dependence stage 108c, the drain of the first transistor 112c is coupled to the first complementary data storage node 106c, the gate of the first transistor 112c is coupled to the second data storage node 106b, and the gate of the second transistor 114c is coupled to the first data storage node 106a. In the fourth supply voltage multi-dependent stage 108d, the drain of the first transistor 112d is coupled to the second complementary data storage node 106d, the gate of the first transistor 112d is coupled to the first data storage node 106a, and the gate of the second transistor 114d is coupled to the second data storage node 106b.

[0018] The reference voltage multi-dependent stages 110a - d for the plurality of data storage nodes 106a - d are similarly configured as the corresponding supply voltage multi-dependent stages 108a - d , except that the inputs of the reference voltage multi-dependent stages 110a - d are coupled to the second input stage 104a instead of the voltage supply node 120 .

[0019] Each reference voltage multi-dependent stage 110a-d includes a first transistor 116a-d and a second transistor 118a-d. The first transistor 116a-d has a drain coupled to a data storage node 106a-d and a source coupled to a drain of the second transistor 118a-d. The source of the second transistor is coupled to the second input stage 104a. The gates of the first transistor 116a-d and the second transistor 118a-d are respectively coupled to two data storage nodes 106a-d, which are different from each other and different from the data storage node 106a-d to which the drain of the first transistor 116a-d is coupled.

[0020] The gates of the first transistor 116a and the second transistor 118a of the first reference voltage multi-dependence stage 110a are coupled to the second complementary data storage node 106d and the first complementary data storage node 106c, respectively. The gates of the first transistor 116b and the second transistor 118b of the second reference voltage multi-dependence stage 110b are coupled to the first complementary data storage node 106c and the second complementary data storage node 106d, respectively. The gates of the first transistor 116c and the second transistor 118c of the third reference voltage multi-dependence stage 110c are coupled to the second data storage node 106b and the first data storage node 106a, respectively. The gates of the first transistor 116d and the second transistor 118d of the fourth reference voltage multi-dependence stage 110d are coupled to the first data storage node 106a and the second data storage node 106b, respectively.

[0021] The first data storage node 106a and the second data storage node 106b store duplicate (or identical) data bits (represented as "MA" and "MB", respectively). The first complementary data storage node 106c and the second complementary data storage node 106d store the complements of the data bits stored in the first data storage node 106a and the second data storage node 106b (represented as "MAn" and "MBn", respectively). For example, if MA and MB are logic 1, then MAn and MBn are logic 0, and vice versa.

[0022] The arrangement of supply voltage multi-dependency stages 108a-d and reference voltage multi-dependency stages 110a-d enables data storage nodes 106a-d to be dependent on latch 100a. This dependency ensures that the state of a node 106a-d changes only if the corresponding state of the node on which it depends also changes.

[0023] For example, the state of the first data storage node 106a ("MA") depends on the state of the first complementary data storage node 106c and the second complementary data storage node 106d ("MAn" and "MBn"). When the first data storage node 106a stores a logic 1, the first complementary data storage node 106c and the second complementary data storage node 106d both store a logic 0. In order for the state of the first data storage node 106a to change from a logic 1 to a logic 0, the state of the first complementary data storage node 106c and the second complementary data storage node 106d should change from a logic 0 to a logic 1. The change in the state of one of the complementary data storage nodes 106c, 106d is not sufficient to cause a change in the state of the first data storage node 106a. The increased redundancy reduces the possibility of changing the data stored in the latch due to factors such as radiation or particle impact, and increases the robustness of the latch 100a in handling such events.

[0024] During operation, the first input stage 102a outputs a data bit having a logic 1 state to two data storage nodes 106a-d for storage, such as the first data storage node 106a and the second data storage node 106b or the first complementary data storage node 106c and the second complementary data storage node 106d. The second input stage 104a outputs a data bit having a complementary state (logic 0) to two data storage nodes 106a-d for storage, such as the first data storage node 106a and the second data storage node 106b or the first complementary data storage node 106c and the second complementary data storage node 106d. Thus, for one data bit, the latch stores four bits; two bits have the same state as the data bit and are copies of the data bit, and two bits have complementary states or opposite states.

[0025] After data is stored or fed into the latch 100a by the first input stage 102a and the second input stage 104a, the state of the data storage nodes 106a-d does not change unless the state of the two other data storage nodes changes. For example, initially, the first data storage node 106a (MA) stores a logic 0, wherein the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn) store a complementary logic 1. As a result, the first transistor 112a and the second transistor 114a of the first power supply voltage multi-dependency stage 108a are turned off, and the first data storage node 106a is decoupled from the voltage source node 120. In contrast, the first transistor 116a and the second transistor 118a of the first reference voltage multi-dependency stage 110a are turned on, and the first data storage node 106a is coupled to the second input stage 104a that provides the reference voltage. Coupling the first data storage node 106a to the second input stage 104a causes the data stored in the first data storage node 106a (MA) to remain at a logic 0.

[0026] If one of the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn) changes state from a logic 1 to a logic 0 (e.g., as a result of a soft error), the change is not sufficient to change the state of the first data storage node 106a (MA). If the first complementary data storage node 106c (MAn) changes state from a logic 1 to a logic 0, the second transistor 114a of the first supply voltage multi-dependency stage 108a turns on. However, because the first transistor 112a remains off, the first supply voltage multi-dependency stage 108a is turned off as a whole, and the first data storage node 106a (MA) remains decoupled from the voltage source node 120. The change in state of the first complementary data storage node 106c (MAn) causes the second transistor 118a of the first reference voltage multi-dependency stage 110a to turn off, thereby decoupling the first data storage node 106a (MA) from the second input stage 104a. With the first data storage node 106a (MA) decoupled from the voltage supply node 120 and the second input stage 104a, the first data storage node 106a (MA) maintains its logic state of 1. Soft errors in the state of the first complementary data storage node 106c (MAn) do not affect the stored data of the first data storage node 106a (MA).

[0027] Table 1 shows the dependencies of the first data storage node 106a and the second data storage node 106b (MA, MB) and the first complementary data storage node 106c and the second complementary data storage node 106d (Man, MBn).

[0028] node Dependencies MA MAn、MBn MB MAn、MBn MAn MA, MB MB MA, MB

[0029] Table 1

[0030] The stages 108a-d, 110a-d operate to couple the data storage nodes 106a-d to the voltage source node 120 or the second input stage 104a in the absence of a soft error. When the data storage node 106a-d stores a logic 1, it is coupled to the voltage source node 120, and when the data storage node 106a-d stores a logic 0, it is coupled to the second input stage 104a. When a soft error occurs, the stages 108a-d, 110a-d operate to decouple the data storage nodes 106a-d from both the voltage source node 120 and the second input stage 104a. Once decoupled from the voltage source node 120 and the second input stage 104a, the data storage nodes 106a-d retain their states before the soft error occurs. If the states of the two nodes on which the data storage nodes 106a-d depend change, the stages 108a-d, 110a-d operate to change the states of the data storage nodes 106a-d.

[0031] Figure 2 1 shows a schematic diagram of a latch 100b. The latch 100b includes a memory stage 101a and a first input stage 102b and a second input stage 104b coupled to the memory stage 101a. The latch 100b has a reference Figure 1 The latch 100a described above has a similar structure. However, in Figure 2 In the latch 100b, the data storage nodes 106a-d are coupled to the second input stage 104b instead of the first input stage 102b. The second input stage 104b operates to selectively couple the first data storage node 106a and the second data storage node 106b (SA, SB) or the first complementary data storage node 106c and the second complementary data storage node 106d (San, SBn) to a reference voltage node. Therefore, the first data storage node 106a and the second data storage node 106b or the first complementary data storage node 106c and the second complementary data storage node 106d are set to store logic 0 (or are in a de-asserted or deactivated state).

[0032] When a data storage node 106a-d stores a logic 0, its complementary node 106a-d stores a logic 1, which causes the associated reference voltage multi-dependent stage 110a-d and its transistors 116a-d, 118a-d to turn on. Thus, the input of the reference voltage multi-dependent stage 110a-d (the source of the second transistor 118a-d) is coupled to the reference voltage node 122. The reference voltage node 122 provides a reference voltage or ground voltage to the latch 100b.

[0033] The latch 100b is coupled to the first input stage 102b at the input of the supply voltage multi-dependent stage 108a-d. Specifically, the sources of the second transistors 114a-d of the supply voltage multi-dependent stage 108a-d are coupled to the first input stage 102b. The first input stage 102b selectively provides the supply voltage to the supply voltage multi-dependent stage 108a-d.

[0034] Figure 3A and 3B Schematic diagram of flip-flop 124 is shown. Flip-flop 124 includes master stage 126a and slave stage 126b. Master stage 126a includes data stage 128, first input stage 102a, first latch 100a and second input stage 104a. Slave stage 126b includes first input stage 102b, second latch 100b, second input stage 104b and output stage 130.

[0035] The data stage 128 includes two inverting diodes 132a, 132b arranged back to back, whereby the cathode of the first inverting diode 132a is coupled to the anode of the second inverting diode 132b. The first inverting diode 132a receives the data bit at its anode (denoted as "D") and outputs the complement of the data bit at its cathode (denoted as "DN"). The second inverting diode 132b receives the complement of the data bit at its anode and outputs the data bit at its cathode (denoted as "DB").

[0036] The first input stage 102a of the main stage 126a includes a first data transistor 134a and a second data transistor 134b, a first complementary data transistor 134c and a second complementary data transistor 134d, and a first clock transistor 136a, a second clock transistor 136b, a third clock transistor 136c, and a fourth clock transistor 136d. The data transistors 134a, 134b, 134c, 134d have a cascade arrangement with the clock transistors 136a, 136b, 136c, 136d, respectively. According to the cascade arrangement, the data transistors 134a-d have a source coupled to the voltage source node 120 and a drain coupled to the source of the clock transistors 136a-d. The gates of the clock transistors 136a-d are used to receive a clock signal (denoted as "CP"). The gates of the first data transistor 134a and the second data transistor 134b are coupled to the cathode of the first inverting diode 132a. The gates of the second complementary data transistor 134c and the second complementary data transistor 134d are coupled to the cathode of the second inverting diode 132b.

[0037] The drains of the clock transistors 136a, 136b, 136c, 136d are coupled to the first and second data storage nodes 106a, 106b and the first and second complementary data storage nodes 106c, 106d, respectively.

[0038] The second input stage 104a includes first and second complementary data transistors 138a and 138b, first and second data transistors 138c and 138d, and first and second clock transistors 140a and 140b. The drains of transistors 138a, 138b, 138c, 138d are coupled to the sources of second transistors 118a-d of the reference voltage multi-dependent stages 110a-d, respectively. The sources of transistors 138a, 138b, 138c, 138d are coupled to the reference voltage node 122. The gates of the first and second complementary data transistors 138a and 138b are coupled to the cathode of the first inverting diode 132a. The gates of the first and second data transistors 138c and 138d are coupled to the cathode of the second inverting diode 132b.

[0039] The first clock transistor 140a has a drain coupled to the drain of the first complementary data transistor 138a, a source coupled to the drain of the second data transistor 138d, and a gate for receiving a clock signal ("CP"). The second clock transistor 140a has a drain coupled to the drain of the second complementary data transistor 138b, a source coupled to the drain of the first data transistor 138c, and a gate for receiving a clock signal ("CP").

[0040] In the slave stage 126b of the flip-flop 124, the first input stage 102b includes first, second, third, and fourth master data transistors 142a, 142b, 142c, and 142d and first and second clock transistors 144a, 144b. The sources of the master data transistors 142a-d are coupled to the voltage source node 120. The drains of the master data transistors 142a, 142b, 142c, 142d are coupled to the sources of the second transistors 114a, 114b, 114c, 114d of the power supply voltage multi-dependent stage 108a, 108b, 108c, 108d, respectively. The gates of the master data transistors 142a, 142b, 142c, 142d are coupled to the data storage nodes 106a, 106b, 106c, 106d of the first latch 100a of the master stage 126a, respectively.

[0041] The first clock transistor 144a has a source coupled to the source of the second transistor 114a of the first supply voltage multi-dependence stage 108a, a drain coupled to the source of the second transistor 114d of the fourth supply voltage multi-dependence stage 108d, and a gate for receiving the clock signal (CP). The second clock transistor 144b has a source coupled to the source of the second transistor 114b of the second supply voltage multi-dependence stage 108b, a drain coupled to the source of the second transistor 114c of the third supply voltage multi-dependence stage 108c, and a gate for receiving the clock signal (CP).

[0042] The second input stage 104b of the slave stage 126b includes a first data transistor 146a and a second data transistor 146b, a first complementary data transistor 146c and a second complementary data transistor 146d, and a first clock transistor 148a, a second clock transistor 148b, a third clock transistor 148c, and a fourth clock transistor 148d. The data transistors 146a, 146b, 146c, 146d have a cascade arrangement with the clock transistors 148a, 148b, 148c, 148d, respectively. According to the cascade arrangement, the data transistors 136a-d have a source coupled to the reference voltage node 122 and a drain coupled to the source of the clock transistors 148a-d. The gates of the clock transistors 148a-d are used to receive a clock signal (denoted as "CP"). The drains of the clock transistors 148a, 148b, 148c, 148d are coupled to the first and second data storage nodes 106a, 106b and the first and second complementary data storage nodes 106c, 106d of the second latch 100b, respectively.

[0043] The gate of the first data transistor 146a is coupled to the first complementary data storage node 106c of the first latch 100a of the main stage 126a, the gate of the second data transistor 146b is coupled to the second complementary data storage node 106d of the first latch 100a of the main stage 126a, the gate of the first complementary data transistor 146c is coupled to the second data storage node 106b, and the gate of the second complementary data transistor 146d is coupled to the first data storage node 106a.

[0044] The output stage 130 includes a first transistor 150a, a second transistor 150b, a third transistor 150c, and a fourth transistor 150d having a cascade arrangement. The first transistor 150a has a source coupled to the voltage source node 120, a drain coupled to the source of the second transistor 150b, and a gate coupled to the second complementary data storage node 106d of the second latch 100b. The second transistor 150b has a drain coupled to the output node 152 and a gate coupled to the first complementary data storage node 106c of the second latch 100b. The third transistor 150c has a drain coupled to the output node 152, a source coupled to the drain of the fourth transistor 150d, and a gate coupled to the first complementary data storage node 106c of the second latch 100b. The fourth transistor 150d has a gate coupled to the second complementary data storage node 106d of the second latch 100b and a source coupled to the reference voltage node 122.

[0045] The master latch 126a is a single-phase active low latch. When the clock signal (CP) is low, the first input stage 102a and the second input stage 104a feed data into the first latch 100a. When the clock signal (CP) is low, the clock transistors 136a-d of the first input stage 102a are turned on. Therefore, depending on whether the data bit (D) is a logic 0 or a logic 1, the first data storage node 106a and the second data storage node 106b or the first complementary data storage node 106c and the second complementary data storage node 106d are coupled to the voltage source node 120 to store a logic 1.

[0046] When the data bit (D) is a logic 1, the first data transistor 134a and the second data transistor 134b are turned on, and the logic 1 is passed to the first data storage node 106a and the second data storage node 106b (MA and MB). As described herein, the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn) are dependent on the first data storage node 106a and the second data storage node 106b (MA and MB).

[0047] At the same time, the first data transistor 138c and the second data transistor 138d of the second input stage 104a are turned on, and the first complementary data transistor 138a and the second complementary data transistor 138b are not turned on. Therefore, the reference voltage of the reference voltage node 122 is transferred to the source of the second transistors 118c, 118d, and is transferred to the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn) via the third reference voltage multi-dependency stage 110c and the fourth reference voltage multi-dependency stage 110d, and the first complementary data storage node 106c and the second complementary data storage node 106d are thus converted to store logic 0. When the data bit (D) is logic 0, the first input stage 102a and the second input stage 104a operate in a similar manner to cause logic 0 to be stored in the first data storage node 106a and the second data storage node 106b (MA and MB) and cause logic 1 to be stored in the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn).

[0048] When the clock signal (CP) transitions to logic 0, the first input stage 102a turns off. The second input stage 104a provides a reference voltage at the sources of the second transistors 118a-d of the reference voltage multi-dependent stages 110a-d. The first latch 100a retains the stored data in the data storage nodes 106a-d.

[0049] In slave latch 126b, second input stage 104b is off while clock signal (CP) is low. First input stage 102b provides supply voltage to sources of second transistors 114a-d of supply voltage multi-dependent stages 108a-d. Second latch 102b retains previously stored data in data storage nodes 106a-d.

[0050] When the clock signal (CP) transitions to high, the clock transistors 148a-d become conductive. Depending on the logic state of the data stored in the first data storage node 106a and the second data storage node 106b (MA and MB) and the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn) of the first latch 100a of the master latch 126a, the first data transistor 146a and the second data transistor 146b or the first complementary data transistor 146c and the second complementary data transistor 146d are turned on.

[0051] When the master latch 126a stores a logic 1 in the first data storage node 106a and the second data storage node 106b (MA and MB), the second input stage 104b passes a logic 0 to the first complementary data storage node 106c and the second complementary data storage node 106d (SAn and SBn) of the slave latch 126b. As described herein, the first data storage node 106a and the second data storage node 106b (SA and SB) are dependent on the first complementary data storage node 106c and the second complementary data storage node 106d (SAn and SBn). Therefore, a logic 1 is fed from the first input stage 102b to the first data storage node 106a and the second data storage node 106b (SA and SB).

[0052] Therefore, when the clock signal (CP) becomes high, the data stored in the data storage nodes 106a-d of the master latch 126a is transferred to the data storage node 106a of the slave latch 126b. The slave latch 126b, which is a high-level active latch, stores the data stored in the master latch 126a at the moment when the clock signal (CP) changes from low to high. When the clock signal (CP) changes back to low, the slave latch 126b keeps the data stored when the clock signal (CP) is high.

[0053] The output stage 130 outputs a logic 1 or a logic 0 based on the state of the data stored in the first complementary data storage node 106c and the second complementary data storage node 106d (SAn and SBn). When the complementary data storage nodes 106c, 106d (SAn and SBn) are both logic 0, the output stage 130 outputs a logic 1 at the output node 152. Conversely, when the complementary data storage nodes 106c, 106d (SAn and SBn) are both logic 1, the output stage 130 outputs a logic 0 at the output node 152. If the first complementary data storage node 106c and the second complementary data storage node 106d (SAn and SBn) have different states, the output stage 130 maintains the previous output (i.e., the output provided before the inconsistency between the data states in the first complementary data storage node 106c and the second complementary data storage node 106d (SAn and SBn)).

[0054] The various embodiments described above may be combined to provide additional embodiments. These and other changes may be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. An electronic circuit comprising: The first latch comprises: Multiple storage nodes, including: a plurality of data storage nodes, each data storage node configured to store a data bit having one of two states, the two states comprising a first state and a second state; and a plurality of complementary data storage nodes, each complementary data storage node being configured to store a complement of said data bit; a plurality of first voltage multi-dependence stages, corresponding to the plurality of storage nodes respectively, each of the first voltage multi-dependence stages having an output coupled to a corresponding storage node among the plurality of storage nodes and at least two control inputs coupled to at least two other storage nodes among the plurality of storage nodes respectively, the first voltage multi-dependence stages being configured to cause the state of the data bit stored in the storage node to change from the second state to the first state in response to changes in two states of two data bits respectively stored in the at least two other storage nodes; and A plurality of second voltage multi-dependence stages respectively correspond to the plurality of storage nodes, each second voltage multi-dependence stage having an output coupled to the corresponding storage node among the plurality of storage nodes, and at least two control inputs respectively coupled to the at least two other storage nodes among the plurality of storage nodes, the second voltage multi-dependence stage being configured to cause the state of the data bit stored in the storage node to change from the first state to the second state in response to changes in two states of two data bits respectively stored in the at least two other storage nodes.

2. The electronic circuit of claim 1 , wherein the first voltage multi-dependency stage is configured to avoid causing the state of the data bit stored in the storage node to change from the second state to the first state when only one of the two data bits respectively stored in the at least two other storage nodes changes state, or when neither of the two data bits respectively stored in the at least two other storage nodes changes state.

3. The electronic circuit of claim 1 , wherein the first voltage multi-dependency stage comprises: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conduction terminal; as well as A second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a first voltage node providing a first voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

4. The electronic circuit of claim 1 , wherein the second voltage multi-dependency stage comprises: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conduction terminal; as well as The second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a second voltage node providing a second voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

5. The electronic circuit of claim 1 , wherein the first latch comprises: A first input stage is coupled to the plurality of storage nodes and is configured to: receiving a clock signal having one of two clock states, the two clock states comprising a first clock state and a second clock state; receiving a data signal having a data signal state; in response to the clock signal having the first clock state, setting the data bit and the complement of the data bit based on the data signal state; as well as In response to the clock signal having the second clock state, refraining from setting the data bit and the complement of the data bit.

6. The electronic circuit according to claim 5, comprising: A second latch, coupled to the first latch and comprising a plurality of second latch storage nodes, wherein the second latch is configured as: receiving the clock signal; and In response to the clock signal having the second clock state, the data stored in the plurality of storage nodes are caused to be transferred to the plurality of second latch storage nodes, respectively.

7. A method for a latch, comprising: storing a plurality of data bits in corresponding plurality of storage nodes of the latch, each data bit of the plurality of data bits being stored in a corresponding storage node of the plurality of storage nodes; determining, by a first multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs coupled to at least two other storage nodes of the plurality of storage nodes, respectively, whether two corresponding states of two data bits respectively stored in the at least two other storage nodes are changed; causing a state change of a data bit stored in the storage node in response to determining the two corresponding state changes, wherein each data bit of the plurality of data bits has one of two states, the two states comprising: a first state corresponding to a reference voltage, and a second state corresponding to a power supply voltage, and wherein causing the state change of the data bit stored in the storage node comprises: causing the state of the data bit to change from the first state to the second state; In response to determining that one of the two corresponding states changes or that neither of the two corresponding states changes, avoiding causing the state of the data bit stored in the storage node to change; determining, by a second multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs coupled to two other storage nodes of the plurality of storage nodes, respectively, whether the two corresponding states of the two data bits respectively stored in the two other storage nodes change from the first state to the second state; and In response to determining that the two corresponding states change from the first state to the second state, causing the state of the data bit stored in the storage node to change from the second state to the first state.

8. The method of claim 7, wherein the first multi-dependency level comprises: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conduction terminal; as well as A second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a power supply voltage node providing the power supply voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

9. The method of claim 8, wherein the second multi-dependency level comprises: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to the first storage node of the at least two other storage nodes, and a second conduction terminal; as well as A second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a power supply voltage node providing the power supply voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

10. A latch comprising: Supply voltage node; reference voltage node; A plurality of storage nodes, including a first storage node, a second storage node, and a third storage node; as well as a plurality of supply voltage multi-dependence stages including a first supply voltage multi-dependence stage including a first supply transistor having a first conduction terminal coupled to the first storage node, a control terminal coupled to the second storage node, and a second conduction terminal, and a second supply transistor having a first conduction terminal coupled to the second conduction terminal of the first supply transistor, a control terminal coupled to the third storage node, and a second conduction terminal coupled to the supply voltage node; as well as A plurality of reference voltage multi-dependence stages include a first reference voltage multi-dependence stage, the first reference voltage multi-dependence stage including a first reference transistor and a second reference transistor, the first reference transistor having a first conduction terminal coupled to the first storage node, a control terminal coupled to the second storage node, and a second conduction terminal, the second reference transistor having a first conduction terminal coupled to the second conduction terminal of the first reference transistor, a control terminal coupled to the third storage node, and a second conduction terminal coupled to the reference voltage node. The latch of claim 10 , wherein the plurality of storage nodes includes a fourth storage node. 12 . The latch of claim 11 , wherein the first storage node and the fourth storage node are configured to store a data bit, and the second storage node and the third storage node are configured to store a complement of the data bit.

13. The latch according to claim 11, comprising: The first input stage is configured to selectively couple the first storage node and the fourth storage node, or the second storage node and the third storage node to the power supply voltage node.

14. The latch according to claim 11, comprising: The second input stage is configured to selectively couple the first storage node and the fourth storage node, or the second storage node and the third storage node to the reference voltage node.

15. The latch of claim 13 , wherein the first input stage is configured as: receiving a clock signal and an input data signal; coupling the first storage node and the fourth storage node to the power supply voltage node when the clock signal has a low state and the input data signal has a high state; and When the clock signal has a low state and the input data signal has a low state, the first storage node and the fourth storage node are coupled to the reference voltage node.

16. The latch of claim 15, wherein the first input stage is configured as: When the clock signal transitions to the high state, the first storage node and the fourth storage node are decoupled from the power supply voltage node.

17. An electronic circuit comprising: The first latch comprises: Multiple storage nodes, including: a plurality of data storage nodes, each data storage node configured to store a data bit having one of two states, the two states comprising a first state and a second state; and a plurality of complementary data storage nodes, each complementary data storage node being configured to store a complement of the data bit; and a plurality of first voltage multi-dependence stages, corresponding to the plurality of storage nodes respectively, each first voltage multi-dependence stage having an output coupled to a corresponding storage node among the plurality of storage nodes, and at least two control inputs coupled to at least two other storage nodes among the plurality of storage nodes respectively, the first voltage multi-dependence stage being configured to cause the state of the data bit stored in the storage node to change from the second state to the first state in response to changes in two states of two data bits respectively stored in the at least two other storage nodes, wherein the first voltage multi-dependence stage comprises: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conduction terminal; and A second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a first voltage node providing a first voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

18. An electronic circuit according to claim 17, wherein the first voltage multi-dependence stage is configured to avoid causing the state of the data bit stored in the storage node to change from the second state to the first state when only one of the two data bits respectively stored in the at least two other storage nodes changes state, or when neither of the two data bits respectively stored in the at least two other storage nodes changes state.

19. The electronic circuit of claim 17, wherein the first latch comprises: A first input stage is coupled to the plurality of storage nodes and is configured to: receiving a clock signal having one of two clock states, the two clock states comprising a first clock state and a second clock state; receiving a data signal having a data signal state; in response to the clock signal having the first clock state, setting the data bit and the complement of the data bit based on the data signal state; as well as In response to the clock signal having the second clock state, refraining from setting the data bit and the complement of the data bit.

20. An electronic circuit comprising: The first latch comprises: Multiple storage nodes, including: a plurality of data storage nodes, each data storage node configured to store a data bit having one of two states, the two states comprising a first state and a second state; and a plurality of complementary data storage nodes, each complementary data storage node being configured to store a complement of the data bit; and a plurality of first voltage multi-dependence stages, corresponding to the plurality of storage nodes respectively, each of the first voltage multi-dependence stages having an output coupled to a corresponding storage node among the plurality of storage nodes and at least two control inputs coupled to at least two other storage nodes among the plurality of storage nodes respectively, the first voltage multi-dependence stages being configured to cause the state of the data bit stored in the storage node to change from the second state to the first state in response to changes in two states of two data bits respectively stored in the at least two other storage nodes; and A first input stage is coupled to the plurality of storage nodes and is configured to: receiving a clock signal having one of two clock states, the two clock states comprising a first clock state and a second clock state; receiving a data signal having a data signal state; in response to the clock signal having the first clock state, setting the data bit and the complement of the data bit based on the data signal state; and In response to the clock signal having the second clock state, refraining from setting the data bit and the complement of the data bit.

21. An electronic circuit according to claim 20, wherein the first voltage multi-dependence stage is configured to avoid causing the state of the data bit stored in the storage node to change from the second state to the first state when only one of the two data bits respectively stored in the at least two other storage nodes changes state, or when neither of the two data bits respectively stored in the at least two other storage nodes changes state.

22. The electronic circuit according to claim 20, comprising: A second latch, coupled to the first latch and comprising a plurality of second latch storage nodes, wherein the second latch is configured as: receiving the clock signal; as well as In response to the clock signal having the second clock state, the data stored in the plurality of storage nodes are caused to be transferred to the plurality of second latch storage nodes, respectively.

23. A method for a latch, comprising: storing a plurality of data bits in corresponding plurality of storage nodes of the latch, each data bit of the plurality of data bits being stored in a corresponding storage node of the plurality of storage nodes; determining, by a first multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs coupled to at least two other storage nodes of the plurality of storage nodes, respectively, whether two corresponding states of two data bits respectively stored in the at least two other storage nodes are changed; causing a state change of a data bit stored in the storage node in response to determining the two corresponding state changes, wherein causing the state change of the data bit stored in the storage node comprises: causing the state of the data bit to change from a first state to a second state, and wherein each of the plurality of data bits has one of two states, the two states comprising: a first state corresponding to a reference voltage, and a second state corresponding to a power supply voltage; and In response to determining that one of the two corresponding states changes or that neither of the two corresponding states changes, avoiding causing the state of the data bit stored in the storage node to change, wherein the first multi-dependency level comprises: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conduction terminal; and A second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a power supply voltage node providing the power supply voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

24. The method of claim 23, wherein the latch comprises a second multi-dependency stage, the second multi-dependency stage comprising: a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conduction terminal; as well as A second transistor has a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a power supply voltage node providing the power supply voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

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