A false trigger prevention circuit, method, system, power amplifier circuit, and device

Abstract

The present application relates to the technical field of integrated circuits, and discloses a false trigger prevention circuit, method, system, power amplifier circuit and device, which comprises an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are both connected with the input end of the logic circuit, so that the false trigger problem of the existing N-type power tube caused by glitches is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a false trigger prevention circuit, method, system, power amplifier circuit and device. BACKGROUND

[0002] In use, the existing N-type power tube may appear a glitch phenomenon due to the parasitic effect at the gate, and for the glitch phenomenon, when the N-type power tube gate voltage is 0V and in the off state, if a glitch appears on the gate, the N-type power tube will be turned on, thus causing a false trigger condition and affecting the normal use of the circuit. SUMMARY

[0003] The present application provides a false trigger prevention circuit, method, system, power amplifier circuit and device to solve the problem of false trigger of the existing N-type power tube due to glitch.

[0004] To solve the above technical problems, the present application solves the problems by the following technical solutions:

[0005] A false trigger prevention circuit, comprising an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, the output end of the glitch trigger circuit and the input end of the input circuit are connected with the input end of the logic circuit.

[0006] Optionally, the glitch trigger circuit comprises an inverter and a same-phase delay circuit, the output end of the inverter is connected with the input end of the same-phase delay circuit.

[0007] Optionally, the same-phase delay circuit comprises an even number of inverters, and the even number of inverters are connected in series.

[0008] Optionally, the logic circuit comprises an AND circuit, a buffer current expansion circuit and an NMOS tube, the output end of the AND circuit is connected with the input end of the buffer current expansion circuit, and the output end of the buffer current expansion circuit is connected with the gate of the NMOS tube.

[0009] Optionally, the input circuit comprises an inverting driving circuit, and the inverting driving circuit is used to realize step-by-step strengthening.

[0010] Optionally, the inverting driving circuit comprises an odd number of inverters, and the odd number of inverters are connected in series.

[0011] A power amplifier circuit, comprising the false trigger prevention circuit according to any one of the preceding claims, further comprising an N-type power tube signal input circuit, the output end of the false trigger prevention circuit is connected with the gate of the N-type power tube, and the signal input circuit is connected with the drain of the N-type power tube.

[0012] An apparatus comprising the power amplifier circuit as described above.

[0013] A method for preventing false triggering of a glitch, applied to the false triggering prevention circuit as described in any one of the above, comprising the steps of:

[0014] Obtaining the original amplitude and original width of the glitch, and setting an amplitude threshold and a width threshold;

[0015] Determining whether the glitch reaches the glitch amplitude threshold and the glitch width threshold at the same time, and if so, releasing the gate pull-down of the NMOS tube, otherwise keeping the gate pull-down of the NMOS tube.

[0016] A system for preventing false triggering of a glitch, which performs the method for preventing false triggering of a glitch as described above, comprising a glitch obtaining unit and an analysis and determination unit;

[0017] The glitch obtaining unit is used to obtain the original amplitude and original width of the glitch, and set an amplitude threshold and a width threshold;

[0018] The analysis and determination unit is used to determine whether the glitch reaches the glitch amplitude threshold and the glitch width threshold at the same time, and if so, release the gate pull-down of the NMOS tube, otherwise keep the gate pull-down of the NMOS tube.

[0019] Compared with the prior art, the technical scheme provided by the present application has the following beneficial effects:

[0020] Through the setting of the glitch trigger circuit, the condition for releasing the gate pull-down of the N-type power tube by the glitch is provided, at the same time, the glitch amplitude requirement for glitch triggering is set by the inverter trigger in the glitch trigger circuit, and the glitch width requirement for glitch triggering is set by the same phase delay circuit, and the two are simultaneously satisfied, effectively preventing the glitch on the gate of the N-type power tube from shutting down the pull-down tube, so that the pull-down tube effectively maintains the pull-down capability of the N-type power tube, thereby preventing false triggering of the N-type power tube. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0022] Figure 1 A circuit diagram of a false triggering prevention circuit for the first embodiment;

[0023] Figure 2This is a circuit diagram of a power amplifier circuit proposed in Embodiment 2. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0025] Example 1

[0026] like Figure 1 As shown, an anti-false triggering circuit includes an input circuit, a glitch triggering circuit, and a logic circuit. The output terminal of the input circuit is connected to the input terminal of the glitch triggering circuit. Both the output terminal of the glitch triggering circuit and the input terminal of the input circuit are connected to the input terminal of the logic circuit. Specifically, the input circuit includes an inverting drive circuit used to achieve step-by-step reinforcement. The glitch triggering circuit includes an inverting flip-flop and a non-inverting delay circuit. The output terminal of the inverting flip-flop is connected to the input terminal of the non-inverting delay circuit.

[0027] Specifically, the inverting drive circuit includes an odd number of inverters, which are connected in series. This odd number of inverters is used to achieve inversion. The input terminal of the inverting drive circuit is set to in, and the output terminal is out. When in is "1" and out is "0", the output terminal out is connected to the gate of the N-type power transistor (in...). Figure 1 (Not shown in the text), at this time the output terminal out is "0", and then after passing through the inverting flip-flop and the non-inverting delay circuit, it becomes "1".

[0028] Since the logic circuit includes an AND circuit, a buffer current-boosting circuit, and an NMOS transistor, the output of the AND circuit is connected to the input of the buffer current-boosting circuit. The output of the buffer current-boosting circuit is connected to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to the output out, and the source of the NMOS transistor is grounded. The buffer current-boosting circuit is used to buffer and drive the pull-down transistor. Therefore, when the input in of the AND circuit is "1" and the input of the inverting delay circuit is "1", its output is also "1", and the buffer current-boosting circuit (i.e., the BUF circuit) also outputs "1". Thus, the pull-down transistor mn1 of the NMOS transistor is turned on, which enhances the pull-down of the output out, thereby enhancing the pull-down capability of the gate of the N-type power transistor.

[0029] Furthermore, the in-phase delay circuit includes an even number of inverters, which are connected in series; the BUF circuit includes an even number of inverters, which are connected in series; and the inverting trigger is an inverted Schmitt trigger, which has a hysteresis effect.

[0030] Specifically, when there is a glitch on the output end out, the glitch needs to meet two conditions to remove the pull-down of the output end out by the pull-down tube mn1, the first is that the amplitude of the glitch reaches the trigger point of the inverting Schmitt trigger, and the trigger condition can be set by setting the trigger voltage of the trigger point, and if the trigger voltage is set lower than the amplitude, the glitch will not trigger the inverting Schmitt trigger, that is, the first condition of removing the gate pull-down of the N-type power tube by the pull-down tube mn1 is not met.

[0031] The second condition is the width of the glitch, that is, the width of the pulse, and the comparison of the width of the glitch and the time of the non-inverting delay circuit is realized by the non-inverting delay circuit. Only when the width of the glitch is longer than the time of the non-inverting delay circuit, the gate pull-down of the N-type power tube by the pull-down tube mn1 can be removed. Since the inverting Schmitt trigger and the non-inverting delay circuit are connected in series, only when the above two conditions are met at the same time, the gate pull-down of the N-type power tube by the pull-down tube mn1 can be removed. Otherwise, the pull-down tube mn1 keeps the gate pull-down of the N-type power tube, preventing the false trigger caused by the glitch.

[0032] Embodiment Two

[0033] As Figure 2 described, a power amplifier circuit includes the false trigger prevention circuit of embodiment one, and further includes an N-type power tube signal input circuit, the output end of the false trigger prevention circuit is connected to the gate of the N-type power tube, the signal input circuit is connected to the drain of the N-type power tube, and the source of the N-type power tube is grounded. Specifically, the glitch generated by the N-type power tube is transmitted to the false trigger prevention circuit through point C, and then processed by the gate pull-down condition setting of the false trigger prevention circuit to prevent false triggering. Specifically, it can be a CLASSD power amplifier circuit.

[0034] Embodiment Three

[0035] A device includes the power amplifier circuit of embodiment two, such as an audio device containing the power amplifier circuit. Specifically, it can be a headset, a Bluetooth speaker, etc. In this embodiment, it is not limited in detail.

[0036] Embodiment Four

[0037] A method for preventing glitch false triggering is applied to the false trigger prevention circuit of any one of embodiments one, and includes the following steps: obtaining the original amplitude and original width of the glitch, and setting the amplitude threshold and width threshold; determining whether the glitch meets the glitch amplitude threshold and the glitch width threshold at the same time, if so, removing the gate pull-down of the NMOS tube, otherwise, keeping the gate pull-down of the NMOS tube. Specifically, since the principle of preventing glitch false triggering is described in detail in embodiment one, it is not described in detail in this embodiment.

[0038] Example Five

[0039] A system for preventing false triggering of a glitch, the system performing the method for preventing false triggering of a glitch as described in Example Four, comprising a glitch obtaining unit and an analysis and judgment unit; the glitch obtaining unit is configured to obtain the original amplitude and original width of the glitch, and set an amplitude threshold and a width threshold; the analysis and judgment unit is configured to judge whether the glitch reaches the glitch amplitude threshold and the glitch width threshold at the same time, if yes, the gate pull-down of the NMOS tube is released, otherwise the gate pull-down of the NMOS tube is maintained.

[0040] The above description is only the preferred embodiment of the present application, not any form and substantial limitation of the present application, it should be noted that for ordinary skilled in the art, without departing from the method of the present application, can also make a number of improvements and supplements, these improvements and supplements should also be considered as the protection scope of the present application. For those skilled in the art, without departing from the spirit and scope of the present application, some changes, modifications and equivalent variations made by using the above disclosed technical content, are equivalent embodiments of the present application; at the same time, any equivalent changes, modifications and evolution of the above-mentioned embodiments according to the essential technology of the present application, still belong to the scope of the technical solutions of the present application.

Claims

1. A misfire prevention circuit, characterized by, The input circuit, the glitch trigger circuit and the logic circuit are included, the output end of the input circuit is connected with the input end of the glitch trigger circuit, the output end of the glitch trigger circuit and the input end of the input circuit are connected with the input end of the logic circuit; The glitch trigger circuit includes the inverting Schmitt trigger and the same-phase delay circuit, the output end of the inverting Schmitt trigger is connected with the input end of the same-phase delay circuit; The logic circuit includes the AND circuit, the buffer expansion circuit and the NMOS tube, the output end of the AND circuit is connected with the input end of the buffer expansion circuit, the output end of the buffer expansion circuit is connected with the gate of the NMOS tube; The input circuit includes the inverting driving circuit, and the inverting driving circuit is used for realizing step-by-step strengthening. The trigger voltage of the trigger point of the inverting Schmitt trigger is lower than the set amplitude, and the glitch width is longer than the time of the same-phase delay circuit.

2. A misfire prevention circuit according to claim 1, characterised in that, The same-phase delay circuit includes even number of inverters, and the even number of inverters are connected in series.

3. A misfire prevention circuit according to claim 1, wherein The inverting driving circuit includes odd number of inverters, and the odd number of inverters are connected in series.

4. A power amplifier circuit, characterized by comprising: The power amplifier circuit includes the anti-mis-triggering circuit of any one of claims 1-3, and further includes an N-type power tube signal input circuit, the output end of the anti-mis-triggering circuit is connected with the gate of the N-type power tube, and the signal input circuit is connected with the drain of the N-type power tube.

5. An apparatus, comprising: The device includes the power amplifier circuit of claim 4.

6. A method of preventing false triggering of a hairpin, characterized by, The method for preventing glitch mis-triggering is applied to the anti-mis-triggering circuit of any one of claims 1-3, and includes the following steps: Original amplitude and original width of the glitch are acquired, and amplitude threshold and width threshold are set; It is judged whether the glitch reaches the glitch amplitude threshold and the glitch width threshold at the same time, if yes, the gate pull-down of the NMOS tube is released, otherwise the gate pull-down of the NMOS tube is kept.

7. A system for preventing false triggering of a hairpin, the system comprising: The system executes the method for preventing glitch mis-triggering of claim 6, and includes a glitch acquisition unit and an analysis and judgment unit; The glitch acquisition unit is used for acquiring original amplitude and original width of the glitch, and setting amplitude threshold and width threshold; The analysis and judgment unit is used for judging whether the glitch reaches the glitch amplitude threshold and the glitch width threshold at the same time, if yes, the gate pull-down of the NMOS tube is released, otherwise the gate pull-down of the NMOS tube is kept.

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