Semiconductor chip including bump structure and semiconductor package including semiconductor chip

Abstract

A semiconductor chip includes a semiconductor substrate. An electrode pad is disposed on the semiconductor substrate. The electrode pad includes a low-k material layer. A first protective layer at least partially surrounds the electrode pad. The first protective layer includes a first opening located at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protective layer at least partially surrounds the buffer pad. The second protective layer includes a second opening located at an upper portion thereof. A column layer and a solder layer are sequentially stacked on the buffer pad. The thickness of the buffer pad is greater than the thickness of the electrode pad. The width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than the width of the second opening in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0077321 filed on July 3, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor chip, and more particularly, to a semiconductor chip including a bump structure and a semiconductor package including the semiconductor chip. Background Art

[0004] Electronic devices are becoming smaller and capable of performing more functions. As a result, semiconductor chips used in electronic devices are becoming more highly integrated. Such semiconductor chips may have small connection terminals with fine pitches. In order to package such high-capacity semiconductor chips, a bump structure may be used. The size of the bump structure included in the semiconductor package is also steadily decreasing to accommodate more highly integrated semiconductor chips. Summary of the invention

[0005] A semiconductor chip includes a semiconductor substrate. An electrode pad is disposed on the semiconductor substrate. The electrode pad includes a low-k material layer. A first protective layer at least partially surrounds the electrode pad. The first protective layer includes a first opening located at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protective layer at least partially surrounds the buffer pad. The second protective layer includes a second opening located at an upper portion thereof. A column layer and a solder layer are sequentially stacked on the buffer pad. The thickness of the buffer pad is greater than the thickness of the electrode pad. The width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than the width of the second opening in the first direction.

[0006] A semiconductor chip includes a semiconductor substrate having an interlayer dielectric including a low-k material and an electrode pad arranged on the interlayer dielectric. A protective layer at least partially covers the side surface and the upper surface of the electrode pad. The protective layer includes an internal space, the internal space having a first opening located at the lower part of the internal space and a second opening located at the upper part of the internal space; a buffer pad is arranged in the internal space of the protective layer and is electrically connected to the electrode pad through the first opening. A bump structure (not located in the internal space of the protective layer) is formed above the protective layer and is electrically connected to the buffer pad through the second opening, and the width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than the width of the second opening in the first direction.

[0007] A semiconductor package includes a package substrate having a substrate pad and a semiconductor chip mounted above the package substrate. The semiconductor chip includes an electrode pad, which is arranged on the semiconductor substrate and has a low-k material layer. The first protective layer includes a first opening located at the upper portion of the first protective layer and at least partially surrounds the electrode pad. The buffer pad is electrically connected to the electrode pad. The second protective layer includes a second opening located at the upper portion of the second protective layer and at least partially surrounds the buffer pad. The column layer and the solder layer are sequentially stacked on the buffer pad. The thickness of the buffer pad is greater than the thickness of the electrode pad. The width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than the width of the second opening in the first direction. The solder layer is electrically connected to the substrate pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept;

[0010] Figure 2 is a cross-sectional view of a semiconductor chip according to an exemplary embodiment of the inventive concept;

[0011] Figures 3 to 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor chip according to an exemplary embodiment of the inventive concept;

[0012] Fig.12 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept;

[0013] Fig.13 is a diagram illustrating a thickness of a buffer pad and stress under a bump structure in a semiconductor package according to an exemplary embodiment of the inventive concept; and

[0014] Fig.14 is a block diagram of a structure of a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0015] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0016] Figure 1 is a cross-sectional view of a semiconductor package 1 according to an exemplary embodiment of the inventive concept.

[0017] Reference Figure 1, the semiconductor package 1 may include a semiconductor device 100, a package substrate 300, and a connection structure 200 connecting the semiconductor device 100 to the package substrate 300. The semiconductor package 1 may be a flip chip package in which the semiconductor device 100 is mounted over the package substrate 300 through the connection structure 200 in a face-down manner.

[0018] The semiconductor device 100 and the connection structure 200 may be considered together as a semiconductor chip 10. Specifically, the semiconductor chip 10 may include an electrode pad 210 formed on a semiconductor substrate 110. The electrode pad 210 may be configured to extend the circuit function included in the semiconductor device 100 to the outside. A circuit portion including individual unit elements 150 for performing the circuit function of the semiconductor device 100 may be formed in the semiconductor chip 10 by a semiconductor manufacturing process. For example, the semiconductor device 100 including the semiconductor chip 10 may include transistors, resistors, capacitors, conductive wiring, and / or an insulating layer arranged therebetween.

[0019] Electrode pad 210 may be partially exposed by first protective layer 212 formed on the circuit portion of semiconductor device 100. Electrode pad 210 may be electrically connected to the circuit portion of semiconductor device 100 through upper via 160, and thus the circuit portion of semiconductor device 100 may be electrically connected to package substrate 300.

[0020] According to some exemplary embodiments of the present invention, the semiconductor chip 10 may include a logic chip and / or a memory chip. The logic chip may include, for example, a microprocessor, an analog device, and / or a digital signal processor. In addition, for example, the memory chip may include: a volatile memory chip, such as a dynamic random access memory (DRAM) or a static RAM (SRAM); or a non-volatile memory chip, such as a phase change RAM (PRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM). According to some exemplary embodiments of the present invention, the semiconductor chip 10 may include a high-bandwidth memory device. According to some exemplary embodiments of the present invention, the semiconductor chip 10 may include an interposer and / or a controller.

[0021] The semiconductor chip 10 may include a high bandwidth memory device that does not include a redistribution layer. Compared with other memory devices, a high bandwidth memory device may require a larger portion of the connection structure for signal transmission. Therefore, the formation of the redistribution layer may be accompanied by difficulties in circuit design and semiconductor manufacturing process.

[0022] The package substrate 300 may include a base 310 , an internal connection pad 320 , an insulating layer 330 , an external connection pad 340 , and an external terminal 350 .

[0023] The base 310 may include phenolic resin, epoxy resin and / or polyimide. The internal connection pad 320 may be formed above one side of the base 310, and the package substrate 300 may be electrically connected to the connection structure 200. The insulating layer 330 may be formed above the upper surface of the base 310, and a portion of the upper surface of the internal connection pad 320 may be exposed. The external connection pad 340 may be formed on the other side of the base 310, and the external terminal 350 may be attached to the external connection pad 340. For example, the external terminal 350 may include a solder ball or a solder bump. The external terminal 350 may electrically connect the semiconductor package 1 to an external electronic device.

[0024] According to some exemplary embodiments of the present disclosure, when the package substrate 300 is a printed circuit board (PCB), the base 310 can be formed in a film state by compressing a polymer material to a certain thickness, and the polymer material is, for example, a thermosetting resin, an epoxy resin, or a phenolic resin, such as flame retardant 4 (FR-4), bismaleimide triazine (BT) and / or ajinomoto build-up film (ABF). After applying copper foil to both sides of the base 310, the base 310 can be realized by forming a wiring pattern, which is a transmission path of an electrical signal. In addition, the internal connection pad 320 and the external connection pad 340 can be electrically connected to each other through a through hole passing through the base 310. In addition to the internal connection pad 320 and the external connection pad 340, the solder resist can be completely coated on the lower surface and the upper surface of the base 310 to form a lower protective layer and an upper protective layer.

[0025] According to some exemplary embodiments of the present disclosure, the PCB may be divided into a single-layer PCB having wiring only on a single side of the PCB and a double-layer PCB having wiring on both sides of the PCB. In addition, by using an insulator called a prepreg, the number of copper foil layers that can be formed may be three or more layers. A PCB having multi-layer wiring may be formed by forming three or more wiring layers according to the number of copper foil layers formed. The package substrate 300 of the semiconductor package 1 according to the exemplary embodiments of the present inventive concept is not limited to the structure or material of the PCB.

[0026] The bump structure BS of the semiconductor chip 10 may be attached to the internal connection pad 320 of the package substrate 300, and thus the electrode pad 210 of the semiconductor chip 10 may be electrically connected to the internal connection pad 320. The bump structure BS may include a seed layer 230, a pillar layer 240, and a solder layer 250.

[0027] The underfill 410 may be formed in a space between the semiconductor chip 10 and the package substrate 300. The underfill 410 may surround sidewalls of the connection structures 200 to fill a space between adjacent connection structures 200.

[0028] The molding member 420 may protect the semiconductor chip 10 from external influences (e.g., impact). To perform this function, the molding member 420 may include an epoxy molding compound or resin, etc. In addition, the molding member 420 may be formed by a process such as compression molding, lamination, or screen printing, etc. According to some exemplary embodiments of the inventive concept, the molding member 420 may cover the side surface of the semiconductor chip 10 so that the upper surface of the semiconductor chip 10 may be exposed.

[0029] Figure 2 is a cross-sectional view of a semiconductor chip 10 according to an exemplary embodiment of the inventive concept.

[0030] refer to Figure 2 , a semiconductor chip 10 is shown, wherein a connection structure 200 is arranged over an upper surface of the semiconductor device 100 .

[0031] The semiconductor device 100 and the connection structure 200 may together constitute a semiconductor chip 10 . For ease of explanation, the first direction X and the second direction Y are defined as planes parallel to the upper surface of the semiconductor substrate 110 , and the third direction Z is perpendicular to the upper surface of the semiconductor substrate 110 .

[0032] The semiconductor chip 10 may include: an electrode pad 210 arranged above the semiconductor device 100; a first protective layer 212 at least partially surrounding the electrode pad 210; a buffer pad 220 electrically connected to the electrode pad 210; a second protective layer 222 at least partially surrounding the buffer pad 220; and a bump structure BS arranged above the buffer pad 220.

[0033] The thickness 220T of the buffer pad 220 in the third direction Z may be greater than the thickness 210T of the electrode pad 210 in the third direction Z. According to some exemplary embodiments of the inventive concept, the thickness 220T of the buffer pad 220 may be about 5 to about 10 times the thickness 210T of the electrode pad 210 .

[0034] The width 220W of the buffer pad 220 in the first direction X may be greater than the width 210W of the electrode pad 210 in the first direction. According to some exemplary embodiments of the inventive concept, the width 220W of the buffer pad 220 may be about 1.5 to about 3 times the width 210W of the electrode pad 210 .

[0035] A width 240W of the pillar layer 240 in the first direction X may be greater than a width 210W of the electrode pad 210 in the first direction X, and may be smaller than a width 220W of the buffer pad 220 in the first direction X.

[0036] Therefore, when the buffer pad 220 is thicker and larger than the electrode pad 210 , the buffer pad 220 may relieve stress applied to the electrode pad 210 and the semiconductor device 100 .

[0037] The second opening of the second protective layer 222 may have a width 222W in the first direction X substantially the same as the width 212W of the first opening of the first protective layer 212 in the first direction X. According to an exemplary embodiment of the inventive concept, the second opening width 222W may be smaller than the first opening width 212W.

[0038] The buffer pad 220 may be reinforced, and damage to the upper surface of the buffer pad 220 caused by fluorine (F) gas generated in forming the second opening of the second protective layer 222 when the central portion of the buffer pad 220 is exposed may be minimized.

[0039] In a semiconductor device, an interlayer dielectric may include a low dielectric material. A low dielectric material is a material having a lower dielectric constant than silicon oxide. When an interlayer dielectric is used in a semiconductor device, a semiconductor device with increased insulation capability can be provided with high integration and high speed.

[0040] However, compared with other dielectric materials, the elastic modulus and hardness of low-dielectric materials are relatively low due to their porous film quality, so low-dielectric materials may be susceptible to damage from stress.

[0041] Due to these characteristics, the use of low dielectric materials in semiconductor packages including bump structures may be limited. In particular, the high elastic modulus of the material including the bump structure may diffuse stress to the interlayer dielectric located below the bump structure, thereby possibly causing defects such as cracking and / or delamination of the interlayer dielectric.

[0042] When manufacturing some semiconductor chips, a redistribution layer may be formed above the semiconductor device to separate the bump structure from the interlayer dielectric. However, compared with other memory devices, high-bandwidth memory devices may encounter more connection structures for signal transmission. Therefore, the formation of the redistribution layer may be accompanied by difficulties in circuit design and semiconductor manufacturing processes.

[0043] Therefore, the semiconductor chip 10 according to the exemplary embodiment of the inventive concept may form the buffer pad 220 under the bump structure BS and relieve stress generated in the bump structure BS, and thus may reduce defects such as cracking and / or peeling of the interlayer dielectric 130 including a low dielectric material.

[0044] Finally, the semiconductor chip 10 and the semiconductor package 1 including the semiconductor chip 10 may be increased (see Figure 1 )’s electrical characteristics and reliability.

[0045] Figures 3 to 11 is a cross-sectional view illustrating a method of manufacturing the semiconductor chip 10 according to an exemplary embodiment of the inventive concept.

[0046] Reference Figure 3 , the semiconductor device 100 includes an electrode pad 210 configured to extend an integrated circuit functional structure of an individual unit cell 150 above the semiconductor substrate 110 .

[0047] The semiconductor substrate 110 may include a semiconductor wafer substrate on which a plurality of semiconductor devices 100 arranged in a matrix form are separated from one another by scribe lanes.

[0048] The semiconductor substrate 110 may include, for example, silicon. Alternatively, the semiconductor substrate 110 may include a semiconductor element such as germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and / or indium phosphide (InP). Alternatively, the semiconductor substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate 110 may include a buried oxide layer (BOX). The semiconductor substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities. In addition, the semiconductor substrate 110 may have various device isolation structures, such as a shallow trench isolation (STI) structure.

[0049] A circuit portion including individual unit elements 150 for realizing the integrated circuit function of the semiconductor device 100 may be formed on the semiconductor substrate 110 through a semiconductor manufacturing process. For example, individual unit elements 150 such as transistors, resistors, and capacitors, conductive vias 120, conductive wiring 140, wiring layers such as upper vias 160, and interlayer dielectrics 130 disposed therebetween may be formed on the semiconductor substrate 110.

[0050] According to some exemplary embodiments of the inventive concept, the interlayer dielectric 130 may include a low-k material layer having a lower dielectric constant than silicon oxide. For example, the dielectric material of the interlayer dielectric 130 may be phosphosilicate glass (PSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), plasma enhanced TEOS (PE-TEOS), high density plasma chemical vapor deposition (HDP-CVD) oxide, dielectric materials used in BEOL, ultra-low dielectric materials, etc.

[0051] According to some exemplary embodiments of the inventive concept, the interlayer dielectric 130 may have a structure in which a first interlayer dielectric, a second interlayer dielectric, a third interlayer dielectric, and a fourth interlayer dielectric are sequentially stacked. However, in the present invention, the number of interlayer dielectrics in the interlayer dielectric 130 is not limited thereto.

[0052] The interlayer dielectric 130 may be arranged to at least partially fill the periphery of the wiring layer, such as the conductive via 120 and the conductive wiring 140 including a conductive material. In addition, the interlayer dielectric 130 may be arranged to at least partially fill the periphery of the upper via 160 electrically connected to the electrode pad 210 and in direct contact with the electrode pad 210.

[0053] Electrode pad 210 may be electrically connected to a circuit portion of semiconductor device 100 to perform a function of electrically connecting semiconductor device 100 to an external electronic device. Electrode pad 210 may be electrically connected to conductive via 120 and conductive wiring 140 at the lower portion of semiconductor device 100 through upper via 160 of semiconductor device 100.

[0054] A plurality of electrode pads 210 may be formed over the semiconductor device 100 as a portion for inputting / outputting electrical signals to / from the semiconductor device 100, and may include aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), or a combination thereof. The electrode pads 210 may form a metal (e.g., aluminum (Al)) to a predetermined thickness over the semiconductor device 100, and then may be patterned to manufacture the electrode pads 210 of a desired shape by performing a photolithography process and an etching process.

[0055] Reference Figure 4 , a first protection layer 212 having a first opening 212H may be formed over each of the electrode pad 210 and the semiconductor device 100 .

[0056] After forming a protective layer over both the electrode pad 210 and the semiconductor device 100 , the protective layer is patterned through a photolithography process and an etching process to form a first protective layer 212 including a first opening 212H exposing the center of the electrode pad 210 .

[0057] The first protective layer 212 may include a first opening 212H exposing the center of the electrode pad 210. For example, the first protective layer 212, which is the final protective layer of the circuit portion of the semiconductor device 100, may partially expose the electrode pad 210. The electrode pad 210 may be electrically connected to the circuit portion of the semiconductor device 100 through the upper through hole 160, and may be electrically connected to an external electronic device through the portion of the electrode pad 210 exposed by the first opening 212H. The width 212W of the first opening 212H of the first protective layer 212 in the first direction X may be substantially equal to the degree of exposure of a normal electrode pad.

[0058] The first protective layer 212 may be disposed on the remaining portion of the upper portion of the semiconductor device 100 except for the region where the electrode pad 210 is formed, and the semiconductor device 100 may be insulated in the region except for the electrode pad 210. In addition, the first protective layer 212 may protect the upper surface of the semiconductor device 100 from contamination by external impurities and physical impact, etc. According to some exemplary embodiments of the inventive concept, the first protective layer 212 may include a plurality of material layers.

[0059] The material of the first protection layer 212 may include, for example, silicon oxide, silicon nitride, polyimide, benzocyclobutene, polybenzoxazole, bismaleimide triazine (BT), phenolic resin, epoxy resin, and / or equivalents thereof.

[0060] Reference Figure 5 The spare buffer pad 220P is formed to at least partially surround each of the electrode pad 210 and the first protective layer 212, and the spare buffer pad 220P is formed through the first opening 212H (see Figure 4 ) is electrically connected to the electrode pad 210. In addition, a first mask pattern M1 is formed over the spare buffer pad 220P.

[0061] After forming the backup buffer pad 220P to a predetermined thickness over the electrode pad 210 and the first protective layer 212 through a chemical vapor deposition process or a physical vapor deposition process, a first mask pattern M1 is formed over the backup buffer pad 220P through a photolithography process and a development process.

[0062] The backup buffer pad 220P may include Al, Cu, Ni, or a combination thereof According to some exemplary embodiments of the inventive concept, the backup buffer pad 220P may include the same material as the electrode pad 210 .

[0063] The first mask pattern M1 may cover the entire electrode pad 210 in the first direction X and may have a width M1W covering a portion of the first protective layer 212. The process of forming the first mask pattern M1 includes depositing a photoresist material over the spare buffer pad 220P and patterning the photoresist material by exposure. The patterned photoresist forms the first mask pattern M1. The buffer pad 220 (see FIG. 2 ) to be described later is formed. Figure 6 ) may be defined by the first mask pattern M1.

[0064] Reference Figure 6 , by using the first mask pattern M1 (see Figure 5 ) as an etching mask to etch the spare buffer pad 220P (see Figure 5 ) to form the buffer pad 220, the first mask pattern M1 (see Figure 5 ) is removed. In addition, a second pre-protection layer 222P is formed over the buffer pad 220 and the first protection layer 212. The second pre-protection layer 222P may be formed to completely cover the buffer pad 220.

[0065] A stripping process and / or an ashing process may be performed to remove the first mask pattern M1 (see Figure 5 Thereafter, a second pre-protection layer 222P is formed over the buffer pad 220 and the first protection layer 212 .

[0066] The buffer pad 220 may be formed over the first protective layer 212 and may directly contact and be electrically connected to the electrode pad 210 through the first opening 212H (see Figure 4 ). The buffer pad 220 may include Al, W, Cu, Ni, or a combination thereof. According to some exemplary embodiments of the inventive concept, the buffer pad 220 may include the same material as the electrode pad 210 .

[0067] The thickness 220T of the buffer pad 220 in the third direction Z may be greater than the thickness 210T of the electrode pad 210 in the third direction Z. According to some exemplary embodiments of the inventive concept, the thickness 220T of the buffer pad 220 may be about 5 to about 10 times the thickness 210T of the electrode pad 210 .

[0068] The width 220W of the buffer pad 220 in the first direction X may be greater than the width 210W of the electrode pad 210 in the first direction. According to some exemplary embodiments of the inventive concept, the width 220W of the buffer pad 220 may be about 1.5 to about 3 times the width 210W of the electrode pad 210 .

[0069] Therefore, when the buffer pad 220 is thicker and larger than the electrode pad 210, the buffer pad 220 can relieve stress applied to the electrode pad 210 and the semiconductor device 100. Fig.13 Describe its details.

[0070] The second pre-protection layer 222P may be formed in the remaining portion except for the region where the buffer pad 220 is formed, and thus the semiconductor device 100 may be insulated in the region except for the buffer pad 220. In addition, the second pre-protection layer 222P may protect the buffer pad 220 from contamination by external impurities and physical impact, etc. According to some exemplary embodiments of the inventive concept, the second pre-protection layer 222P may include a plurality of material layers.

[0071] The material of the second pre-protection layer 222P may include, for example, silicon oxide, silicon nitride, polyimide, benzocyclobutene, polybenzoxazole, bismaleimide triazine (BT), phenolic resin, epoxy resin and / or its equivalent. For example, the second pre-protection layer 222P may include the same material as the first protective layer 212. The buffer pad 220 may be arranged in an inner space defined by the protective layer including the second pre-protection layer 222P and the first protective layer 212.

[0072] Reference Figure 7 In the second pre-protection layer 222P (see Figure 6 ) is formed over the second mask pattern M2, and the second pre-protection layer 222P (see Figure 6 ) is etched to form a second protective layer 222.

[0073] Through the photolithography process and the development process, the pre-protection layer 222P (see Figure 6 ) is formed over the second mask pattern M2. The second mask pattern M2 may be formed to expose the second pre-protection layer 222P (see Figure 6 The second pre-protection layer 222P (see Figure 6 ) to expose the central portion of the upper surface of the buffer pad 220.

[0074] The central portion of the buffer pad 220 exposed by the second mask pattern M2 corresponds to a portion directly contacting the pre-seed layer 230P in a subsequent process (see Figure 8). The second opening 222H of the second protective layer 222 in the first direction X may be formed so that the exposed central portion of the buffer pad 220 may be minimized. In some exemplary embodiments of the present inventive concept, the width 222W of the second opening 222H may be substantially equal to the width 212W of the first opening 212H. In exemplary embodiments of the present inventive concept, the width 222W of the second opening 222H may be smaller than the width 212W of the first opening 212H.

[0075] When the exposed central portion of the buffer pad 220 is minimized, the upper surface of the buffer pad 220 may be further protected from fluorine (F) gas generated in the process of etching the second pre-protection layer 222P.

[0076] Reference Figure 8 , after removing the second mask pattern M2 (see Figure 7 ) thereafter, a pre-seed layer 230P is formed over the buffer pad 220 and the second protective layer 222 .

[0077] A stripping process and / or an ashing process may be performed to remove the second mask pattern M2 (see Figure 7 ).

[0078] The pre-seed layer 230P may be formed on the upper surface of the buffer pad 220 and the entire surface of the second protective layer 222 by performing a chemical vapor deposition process or a physical vapor deposition process, and its thickness in the third direction Z ranges from about 100 to about 200 Å. The pre-seed layer 230P may include a metal or alloy of copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), and tin (Sn), or an alloy thereof, and may have a single layer structure or a multi-layer structure.

[0079] The pre-seed layer 230P is used to form the bump structure BS (see Figure 2 ) seeds. For example, when the bump structure BS is formed by an electroplating method, the pre-seed layer 230P may provide a path in which current may flow so that the bump structure BS may be formed over the pre-seed layer 230P. According to an exemplary embodiment of the inventive concept, the bump structure BS may be formed by an electroless plating method.

[0080] The pre-seed layer 230P may conformally completely cover the second opening 222H of the second protective layer 222 (see Figure 6 ).

[0081] The central portion of the buffer pad 220 exposed by the second protective layer 222 corresponds to a portion directly contacting the pre-seed layer 230P.

[0082] refer to Fig. 9, a third mask pattern M3 is formed over the pre-seed layer 230P. The third mask pattern M3 may be formed as a pattern exposing a portion of the pre-seed layer 230P.

[0083] The exposed portion of the pre-seed layer 230P may include a portion in contact with the buffer pad 220. Since the portion exposed by the third mask pattern M3 corresponds to a portion where the pillar layer 240 is formed in a subsequent process (see Fig.10 ) and pre-solder layer 250P (see Fig.10 ), and thus the exposed portion may be formed in plurality to respectively correspond to the plurality of buffer pads 220. The portion exposed by the third mask pattern M3 may be referred to as a ball land.

[0084] Reference Fig.10 A double layer including the pillar layer 240 and the pre-solder layer 250P may be formed over the pre-seed layer 230P on which the third mask pattern M3 is formed. However, the inventive concept is not limited thereto, and alternatively, a single pre-solder layer 250P may be formed.

[0085] The pillar layer 240 may be formed to directly contact the upper surface of the pre-seed layer 230P exposed by the third mask pattern M3. The pillar layer 240 may be formed by electroplating. The electroplating for forming the pillar layer 240 may be referred to as primary electroplating.

[0086] In order to form the pillar layer 240, the semiconductor substrate 110 on which the third mask pattern M3 is formed may be placed in a plating solution to perform primary electroplating. The pillar layer 240 may include, for example, copper (Cu), nickel (Ni), or gold (Au), or an alloy thereof, or may be a double-layer structure including copper (Cu), nickel (Ni), and gold (Au).

[0087] The pillar layer 240 may be formed to fill only the region exposed by the third mask pattern M3 but not completely fill the region exposed by the third mask pattern M3. For example, the thickness of the pillar layer 240 in the third direction Z may be less than the thickness of the third mask pattern M3 in the third direction Z.

[0088] The pre-solder layer 250P may be formed above the pillar layer 240. The upper surface of the pre-solder layer 250P may be substantially flush with the upper surface of the third mask pattern M3, or the upper surface of the pre-solder layer 250P may protrude beyond the upper surface of the third mask pattern M3. The pre-solder layer 250P may be formed by electroplating. The electroplating for forming the pre-solder layer 250P may be referred to as secondary electroplating to distinguish it from the primary electroplating for forming the pillar layer 240.

[0089] In order to form the pre-solder layer 250P, the semiconductor substrate 110 on which the pillar layer 240 is formed may be placed in a plating solution different from that used in the primary plating, and a secondary plating may be performed. The pre-solder layer 250P may include an alloy of tin (Sn) and silver (Ag), and a small amount of copper (Cu), palladium (Pd), bismuth (Bi), and / or antimony (Sb) may be added.

[0090] The width 240W of the pillar layer 240 in the first direction X may be greater than the width 210W of the electrode pad 210 in the first direction X, and may be less than the width 220W of the buffer pad 220 in the first direction X. In addition, as described above, the width 220W of the buffer pad 220 may be greater than the width 210W of the electrode pad 210. For example, the corresponding width may be designed so that the buffer pad 220 may most effectively relieve the stress transmitted through the pillar layer 240.

[0091] Reference Fig.11 , after removing the third mask pattern M3 (see Fig.10 ) after which the pre-seed layer 230P is removed (see Fig.10 ) to form a seed layer 230.

[0092] A stripping process and / or an ashing process may be performed to remove the third mask pattern M3 (see Fig.10 ).

[0093] After removing the third mask pattern M3 (see Fig.10 ) After that, the pre-seed layer 230P exposed to the outside (see Fig.10 ) is wet-etched. When the pre-seed layer 230P is etched by using wet etching (which is isotropic etching) (see Fig.10 ), a bottom fill may be formed in the lower portion of the pillar layer 240.

[0094] When the pre-seed layer 230P (see Fig.10 ) is copper (Cu), the pre-seed layer 230P exposed to the outside can be removed by using ammonia etching. For example, Cu(NH 3 ) 4 Cl 2 、Cu(NH 3 ) 2 Cl, NH 3 and NH 4 Cl alkaline etchant. In the following, it can be 3 and H 2 O is used to clean the chemical substances including CuO obtained as a result of etching.

[0095] Reference again Figure 2 , according to exemplary embodiments of the inventive concept, a reflow process may be performed on the pre-solder layer 250P to form the semiconductor chip 10 .

[0096] The semiconductor substrate 110 is heat-treated to perform a reflow process. The reflow process may be performed at a temperature of about 220° C. to about 260° C. By melting the pre-solder layer 250P using the reflow process, a solder layer 250 may be formed. The pre-solder layer 250P may not collapse after melting, and the solder layer 250 may be formed over the pillar layer 240 by surface tension, and an intermetallic compound may be formed at an interface between the solder layer 250 and the pillar layer 240. The length from the center to the side of the solder layer 250 in the first direction X may be greater than the length from the center to the side of the pillar layer 240 in the first direction X.

[0097] The bump structure BS may include a seed layer 230, a pillar layer 240, and a solder layer 250. The bump structure BS is not limited thereto, and may include only the seed layer 230 and the solder layer 250.

[0098] The type of the bump structure BS may vary depending on the semiconductor package to be manufactured. The bump structure BS may be used as a contact terminal and may be electrically connected to the package substrate 300 (see Figure 1 A plurality of bump structures BS may exist in the semiconductor chip 10, but only one bump structure BS is shown for ease of illustration.

[0099] Fig.12 is a cross-sectional view illustrating a method of manufacturing a semiconductor package 1 including a semiconductor chip 10 according to an embodiment of the inventive concept.

[0100] refer to Fig.12 First, you can refer to Figures 3 to 11 The semiconductor chip 10 may include a plurality of connection structures 200 .

[0101] A flux may be formed over the bump structure BS and / or the internal connection pad 320. The flux may be formed with a small thickness on the surface of the solder layer 250 to prevent oxidation or undesired reaction of the solder layer 250. In some exemplary embodiments of the present inventive concept, the flux may be formed by coating chloride, fluoride, resin, etc.

[0102] Hereinafter, a package substrate 300 on which an internal connection pad 320 over a surface of a base 310 and an insulating layer 330 exposing a portion of the internal connection pad 320 are formed may be provided.

[0103] The semiconductor chip 10 may be mounted over the package substrate 300 by flip chip bonding. The lower surface 110B of the semiconductor substrate 110 may be arranged to face the package substrate 300 so that the solder layer 250 may contact the internal connection pads 320. In some exemplary embodiments of the present inventive concept, the process of adhering the solder layer 250 to the internal connection pads 320 may be performed at a temperature high enough to allow a portion of the solder layer 250 to melt.

[0104] As described above, stress applied to the bump structure BS may be transferred to the lower portion of the bump structure BS during mounting of the semiconductor chip 10 over the package substrate 300. As described above, the buffer pad 220 may relieve stress.

[0105] Reference again Figure 1 , the underfill 410 may at least partially surround the sidewall of the connection structure 200 between the semiconductor chip 10 and the package substrate 300. Hereinafter, a molding member 420 at least partially surrounding the upper surface and the side surface of the semiconductor chip 10 may be formed.

[0106] Afterwards, external connection pads 340 over the surface of the package substrate 300 and external terminals 350 mounted to the external connection pads 340 are formed. However, the process of forming the external connection pads 340 and / or the external terminals 350 may be performed before the process of attaching the semiconductor chip 10.

[0107] Fig.13 is a graph illustrating a thickness of a buffer pad and stress under a bump structure in a semiconductor package according to an exemplary embodiment of the inventive concept.

[0108] Reference Fig.13 , in the semiconductor chip A (e.g., control group) in which no buffer pad was formed over the electrode pad and in the semiconductor chip B (e.g., experimental group) in which a buffer pad was formed over the electrode pad and the thickness of the buffer pad was about 5 times the thickness of the electrode pad, the voltage applied to the interlayer dielectric ( Fig.12 The stress of the peripheral portion of the upper through hole 160).

[0109] At this time, the stress applied to the semiconductor chip A is normalized to 100% and expressed as a relative value of the stress applied to the semiconductor chip B.

[0110] As a result of the measurement, the stress applied to the interlayer dielectric adjacent to the electrode pad in the semiconductor B was measured to be at a level corresponding to 80.2% of the stress applied to the interlayer dielectric adjacent to the electrode pad in the semiconductor A.

[0111] Since the stress relief level of semiconductor chip B is significant enough, in which the buffer pad is formed above the electrode pad with a thickness approximately 5 times that of the electrode pad, stress relief effects of semiconductor B and a semiconductor package including semiconductor chip B can be expected.

[0112] For example, electrical characteristics and reliability of the semiconductor chip 10 and the semiconductor package 1 according to exemplary embodiments of the inventive concepts may be increased.

[0113] Fig.14 is a block diagram of a structure of a semiconductor package 1000 according to an exemplary embodiment of the inventive concept.

[0114] refer to Fig.14 , the semiconductor package 1000 may include a microprocessor 1010, a memory device 1020, an interface 1030, a graphics processing unit 1040, a functional block 1050, and a system bus 1060 that connects the microprocessor 1010, the memory device 1020, the interface 1030, the graphics processing unit 1040, and the functional block 1050 to each other. The semiconductor package 1000 may include both the microprocessor 1010 and the graphics processing unit 1040, or may include only one of them.

[0115] The microprocessor 1010 may include at least one core and an L2 cache. For example, the microprocessor 1010 may include multiple cores. Each of the cores may have the same or different performance. In addition, each of the cores may be activated simultaneously or may be activated individually.

[0116] The memory device 1020 may store the result processed in the functional block 1050 according to the control of the microprocessor 1010. The interface 1030 may exchange information and signals with an external device. The interface 1030 may perform a graphics function. For example, the graphics processing unit 1040 may process a video codec or 3D graphics. The functional block 1050 may perform various functions. For example, when the semiconductor package 1000 is an application processor used in a mobile device, some functional blocks 1050 may perform a communication function. According to an exemplary embodiment of the inventive concept, the semiconductor package 1000 may include the above-mentioned semiconductor package 1.

[0117] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor chip, include: a semiconductor substrate having a low-k material layer formed thereon; An electrode pad is disposed on the semiconductor substrate; A first protective layer at least partially surrounding the electrode pad, the first protective layer comprising a first opening at an upper portion thereof; a buffer pad contacting the electrode pad and the first protective layer, electrically connected to the electrode pad, and configured to relieve stress applied to the electrode pad; A second protection layer at least partially surrounding the buffer pad, the second protection layer comprising a second opening at an upper portion thereof; as well as A pillar layer and a solder layer are sequentially stacked on the buffer pad, Wherein, the thickness of the buffer pad is greater than the thickness of the electrode pad, and The width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than the width of the second opening in the first direction. Wherein, the width of the electrode pad in the first direction is smaller than the width of the buffer pad in the first direction, The width of the column layer in the first direction is smaller than the width of the buffer pad in the first direction, and larger than the width of the electrode pad in the first direction.

2. The semiconductor chip according to claim 1, in, The electrode pad and the buffer pad include the same material.

3. The semiconductor chip according to claim 1, further comprising: include: An interlayer dielectric is disposed below the electrode pad, and the interlayer dielectric includes a unit cell, a wiring layer, and the low-k material layer.

4. The semiconductor chip according to claim 1, in, The center of the electrode pad, the center of the buffer pad, the center of the pillar layer, and the center of the solder layer are aligned in a direction perpendicular to an upper surface of the semiconductor substrate.

5. The semiconductor chip according to claim 1, in, The thickness of the buffer pad is at least 5 times the thickness of the electrode pad.

6. The semiconductor chip according to claim 1, in, The buffer pad is formed over the first protection layer and at least partially fills the first opening and at least partially surrounds the electrode pad, wherein the first protection layer is disposed between the buffer pad and the electrode pad.

7. The semiconductor chip according to claim 1, further comprising: include: a seed layer, disposed below the column layer, wherein the seed layer is formed above the second protection layer and at least partially fills the second opening, and Wherein, an undercut is formed on a side surface of the seed layer.

8. A semiconductor chip, include: A semiconductor substrate comprising an interlayer dielectric and an electrode pad, wherein the interlayer dielectric comprises a low-k material and the electrode pad is arranged on the interlayer dielectric; a protective layer at least partially covering the side surface and the upper surface of the electrode pad, the protective layer comprising an inner space having a first opening located at a lower portion of the inner space and a second opening located at an upper portion of the inner space; a buffer pad disposed in the inner space of the protective layer, electrically connected to the electrode pad through the first opening, and contacting the electrode pad and the protective layer, the buffer pad being configured to relieve stress applied to the electrode pad; as well as a bump structure, which is not located in the inner space of the protective layer, is formed above the protective layer and is electrically connected to the buffer pad through the second opening, Wherein, the thickness of the buffer pad is greater than the thickness of the electrode pad, The width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than the width of the second opening in the first direction. Wherein, the width of the electrode pad in the first direction is smaller than the width of the buffer pad in the first direction, The bump structure includes a stacked structure of a column layer and a solder layer, wherein the width of the column layer in the first direction is smaller than the width of the buffer pad in the first direction and larger than the width of the electrode pad in the first direction.

9. The semiconductor chip according to claim 8, in, The protection layer includes an insulating material, and the electrode pad and the buffer pad include the same conductive material.

10. The semiconductor chip according to claim 8, in, A side surface of the protection layer and a side surface of the buffer pad protrude from a side surface of the bump structure.

11. The semiconductor chip according to claim 8, in, The semiconductor substrate further includes a conductive via surrounded by the interlayer dielectric, wherein an upper surface of the conductive via contacts with a lower surface of the electrode pad.

12. The semiconductor chip according to claim 8, in, The electrode pad and the buffer pad include the same material, and an elastic coefficient of the material of the column layer is greater than an elastic coefficient of the material of the electrode pad and the buffer pad.

13. A semiconductor package, include: A package substrate, including a substrate pad; as well as A semiconductor chip mounted on the packaging substrate; Wherein, the semiconductor chip comprises: An electrode pad is disposed on a semiconductor substrate on which a low-k material layer is formed; a first protective layer, comprising a first opening located at an upper portion of the first protective layer and at least partially surrounding the electrode pad; a buffer pad contacting the electrode pad and the first protective layer, electrically connected to the electrode pad, and configured to relieve stress applied to the electrode pad; A second protection layer, comprising a second opening located at an upper portion of the second protection layer and at least partially surrounding the buffer pad; and A pillar layer and a solder layer are sequentially stacked on the buffer pad, Wherein, the thickness of the buffer pad is greater than the thickness of the electrode pad, wherein a width of the first opening in a first direction parallel to the upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction, and wherein the solder layer is electrically connected to the substrate pad, Among them, the width of the electrode pad in the first direction is smaller than the width of the column layer in the first direction, and the width of the column layer in the first direction is smaller than the width of the buffer pad in the first direction and larger than the width of the electrode pad in the first direction.

14. The semiconductor package according to claim 13, further comprising: include: A bottom fill is provided in the space between the semiconductor chip and the packaging substrate, The bottom filling at least partially surrounds the second protection layer, the pillar layer and the solder layer.

15. The semiconductor package according to claim 13, in, The elastic coefficient of the material of the column layer is greater than the elastic coefficient of the material of the buffer pad.

16. The semiconductor package according to claim 13, in, The semiconductor chip includes a memory chip, wherein the memory chip is a high bandwidth memory device, and the high bandwidth memory device does not include a redistribution layer.

Images