Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method for manufacturing the same are disclosed. The semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer covering a sidewall of the first semiconductor chip and including at least two guide holes, the guide holes exposing the first substrate and spaced apart from each other in the periphery of the first substrate, a second substrate on the first mold layer, a connection terminal between the first substrate and the second substrate and connecting the first substrate and the second substrate to each other, and an alignment structure extending from the bottom surface of the second substrate to each of the at least two guide holes of the first mold layer. The height of the alignment structure is greater than the height of the first mold layer or the first semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0077164, filed on July 3, 2018 with the Korean Intellectual Property Office, and entitled “Semiconductor package and method for manufacturing the same” is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor package and a method of manufacturing the same, and more particularly, to a stacked semiconductor package and a method of manufacturing the same. Background Art

[0004] In one type of semiconductor package, a semiconductor chip is mounted on a printed circuit board, and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. To achieve high integration, there are various stacking methods, such as stacking multiple semiconductor chips on a single substrate or stacking a package on another package. However, precise alignment of these elements can be difficult. Summary of the invention

[0005] According to some example embodiments, a semiconductor package may include: a first semiconductor chip located on a first substrate; a first mold layer located on the first substrate and covering a side wall of the first semiconductor chip, the first mold layer including at least two guide holes, the at least two guide holes exposing the first substrate and spaced apart from each other in a periphery of the first substrate; a second substrate located on the first mold layer; a connecting terminal located between the first substrate and the second substrate, the connecting terminal connecting the first substrate and the second substrate to each other; and an alignment structure extending from a bottom surface of the second substrate to each of the at least two guide holes of the first mold layer, wherein a height of the alignment structure is greater than a height of the first mold layer or the first semiconductor chip.

[0006] According to some example embodiments, a method for manufacturing a semiconductor package may include: providing a first package, the first package including a first semiconductor chip on a first substrate and a first mold layer covering a side wall of the first semiconductor chip on the first substrate, the first mold layer having a connection hole and a guide hole; providing a lower solder ball in the connection hole, the lower solder ball protruding beyond a top surface of the first mold layer; providing a second substrate on the first package, the second substrate having an upper solder ball and an alignment structure on a bottom surface thereof; inserting the alignment structure into the guide hole; connecting the lower solder ball and the upper solder ball to each other; and forming a connection terminal by combining the lower solder ball and the upper solder ball to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A plan view of a first semiconductor package according to some example embodiments is illustrated.

[0009] FIG. 2A to FIG. 2H Cross-sectional views illustrating stages in a method of manufacturing a first semiconductor package according to some example embodiments.

[0010] Figure 3 and Figure 4 Shown Figure 1 Magnified view of part A.

[0011] Figure 5 Shown Figure 2D Magnified view of part B.

[0012] Figure 6 Cross-sectional views illustrating stages in a method of manufacturing a first semiconductor package according to some example embodiments.

[0013] Figure 7 A cross-sectional view of a stacked package according to some example embodiments is illustrated. DETAILED DESCRIPTION

[0014] In this specification, the same reference numerals may denote the same components. A semiconductor package and a method of manufacturing the same according to an embodiment will now be described.

[0015] Figure 1 A plan view showing a first semiconductor package is illustrated according to some example embodiments. FIG. 2A to FIG. 2D According to some example embodiments, Figure 1 A cross-sectional view of the first semiconductor package taken along line II′ is shown. Figure 3 and Figure 4 Shown Figure 1 Magnified view of part A. Figure 5 Shown Figure 2D Magnified view of part B.

[0016] See also Figure 1 and Figure 2A , a first substrate 100 may be provided. The first substrate 100 may be a printed circuit board (PCB) having a circuit pattern. The first substrate 100 may include a redistribution layer.

[0017] The first substrate 100 may include a first pad 110, a second pad 120, and a third pad 130. The first pad 110 and the second pad 120 may be spaced apart from each other along the first direction D1 and the second direction D2 on the top surface of the first substrate 100, and the third pad 130 may be spaced apart from the first pad 110 and the second pad 120 along the third direction D3 on the bottom surface of the first substrate 100. The third pad 130 may be connected to the first pad 110 or the second pad 120 through an internal connection line of the first substrate 100. The first substrate 100 has a dotted line therein, which schematically shows its internal connection line. The second pad 120 may be electrically connected to a ground circuit provided in the first substrate 100. It can be seen from this that the third pad 130 may overlap with the second pad 120 along the third direction D3, for example, completely overlap, but may only partially overlap or not overlap with the first pad 110 along the third direction D3.

[0018] The external terminal 140 may be formed on the bottom surface of the first substrate 100. The external terminal 140 may be, for example, on the third pad 130. The external terminal 140 may be a solder ball. The external terminal 140 may include a conductive material.

[0019] The first semiconductor chip 200 may be mounted on the first substrate 100. The first semiconductor chip 200 may be coupled to the first substrate 100 through a connector 210. For example, the connector 210 may be between the first semiconductor chip 200 and the first substrate 100. The connector 210 may include a solder ball, a solder bump, or a conductive column. The first semiconductor chip 200 may include an integrated circuit. The first semiconductor chip 200 may be a logic chip. For example, the first semiconductor chip 200 may be used as a non-memory chip, such as an application processor.

[0020] The first mold layer 300 may be formed on the top surface of the first substrate 100. The first mold layer 300 may cover the side surface of the first semiconductor chip 200 (e.g., may extend from the top surface of the first substrate 100 along the sidewall of the first semiconductor chip 200), and may have a top surface 300a coplanar with the top surface 200a of the first semiconductor chip 200. The first mold layer 300 may expose the top surface 200a of the first semiconductor chip 200. The first mold layer 300 may fill the space between the first substrate 100 and the first semiconductor chip 200. For example, the first mold layer 300 may be located between the bottom surface of the first semiconductor chip 200 and the top surface of the first substrate 100 to encapsulate the connector 210, for example, completely surrounding its sidewall. The first mold layer 300 may include epoxy molding compound (EMC).

[0021] The first mold layer 300 may include a connection hole 310 and a guide hole 320. For example, the first mold layer 300 may be partially removed to form the connection hole 310 and the guide hole 320. The partial removal of the first mold layer 300 may be achieved by performing a laser drilling process or an etching process. The connection hole 310 may expose the first pad 110 of the first substrate 100, and the guide hole 320 may expose the second pad 120 of the first substrate 100.

[0022] exist Figure 1 In the figure, each guide hole 320 is shown as a circular shape. Alternatively, each guide hole 320 may have a Figure 3 The cross shape shown in FIG. 1 may have various shapes (e.g., polygons such as quadrilaterals or hexagons). In addition, alternatively, as Figure 4 As shown, each guide hole 320 may have a dome-like shape opened toward the outside of the first substrate 100 .

[0023] In a plan view, for example, a D1-D2 plane, the connection hole 310 and the guide hole 320 may be spaced apart from the first semiconductor chip 200. The connection hole 310 may be spaced apart from the guide hole 320. In a plan view, the guide hole 320 may be formed outside the first substrate 100, and the connection hole 310 may be formed farther from the outside of the first substrate 100 than the guide hole 320. For example, the semiconductor chip 200 may be mounted on a central portion of the first substrate 100, the guide hole 320 may be formed outside the first substrate 100, and the connection hole 310 may be formed between the first semiconductor chip 200 and the guide hole 320. Some of the guide holes 320 may span the first semiconductor chip 200 and be spaced apart from the other guide holes.

[0024] like Figure 1 As shown, the guide hole 320 may be on a corner region of the first substrate 100. The corner region may be defined as indicating a portion of the top surface of the first substrate 100 adjacent to an edge at which side surfaces of the first substrate 100 are connected to each other. Figure 1 As shown, each guide hole 320 may overlap with another guide hole 320 along both the first direction D1 and the second direction D2, and may not overlap with any of the connection holes 310 or the first semiconductor chip 200 along the first direction D1 and the second direction D2. Although four guide holes 320 are shown, the guide holes may be arranged differently in the periphery of the first substrate 100. For example: the four guide holes 320 may form a cross pattern; there may be an additional guide hole 320 between each of the four guide holes; or only two guide holes may be located at opposite corners.

[0025] As described below, a connection hole 310 may be provided for receiving a second substrate 500 (see Figure 2B ). A guide hole 320 may be provided to align the second substrate 500 with the first substrate 100 .

[0026] The lower solder ball 410 may be formed in the connection hole 310. The lower solder ball 410 may be coupled to the first pad 110. The lower solder ball 410 may be electrically connected to the first semiconductor chip 200 or the external terminal 140 through the internal circuit of the first substrate 100, and the uppermost end of the lower solder ball 410 may have a level higher than the level of the top surface 300a of the first mold layer 300 along the third direction D3. The upper side surface of the lower solder ball 410 may be exposed by the first mold layer 300. The lower solder ball 410 may include a conductive material, such as tin (Sn), lead (Pb) or silver (Ag). Alternatively, the connection hole 310 may be provided with solder paste instead of the lower solder ball 410.

[0027] See also Figure 1 and Figure 2B , the second substrate 500 may be disposed on the first substrate 100. The second substrate 500 may have a bottom surface facing the first semiconductor chip 200. The second substrate 500 may be an insert substrate. The insert substrate may include, for example, a dielectric resin. The dielectric resin may include a solder resist material, such as photosensitive polyimide.

[0028] The second substrate 500 may include a fourth pad 510, a fifth pad 520, and a sixth pad 530. The fourth pad 510 and the fifth pad 520 may be located on the bottom surface of the second substrate 500, and the sixth pad 530 may be located on the top surface of the second substrate 500. The sixth pad 530 may be connected to the fourth pad 510 or the fifth pad 520 through an internal connection line of the second substrate 500. The second substrate 500 has a dotted line schematically showing its internal connection line therein. The fourth pad 510 may be formed at a position corresponding to the first pad 110, and the fifth pad 520 may be formed at a position corresponding to the second pad 120.

[0029] The upper solder ball 420 may be on the bottom surface of the second substrate 500. The upper solder ball 420 may be coupled to the fourth pad 510. The upper solder ball 420 may include a conductive material, such as Sn, Pb, or Ag. The upper solder ball 420 may be different from the sixth pad 530 in number or arrangement. For example, in a plan view, the upper solder ball 420 may not overlap with the sixth pad 530 along the third direction D3.

[0030] The second substrate 500 may include an alignment structure 540. At least two alignment structures 540 may be provided. The alignment structure 540 may be coupled to the fifth pad 520 of the second substrate 500, respectively. For example, the alignment structure 540 may be coupled to the fifth pad 520 using a welding process or an electroplating process. The alignment structure 540 may include a metal column or a solder bump. The alignment structure 540 may include a material different from that of the upper solder ball 420. For example, the material of the alignment structure 540 may have a higher melting point than that of the material of the upper solder ball 420. An example in which the alignment structure 540 includes a metal column will be discussed below.

[0031] The alignment structure 540 may be formed on a corner region of the second substrate 500. The alignment structure 540 may be spaced apart from the upper solder ball 420. When viewed in a plan view, the alignment structure 540 may be formed on an outer side of the second substrate 500, and the upper solder ball 420 may be formed farther from the outer side of the second substrate 500 than the alignment structure 540. Figure 1 As shown, the alignment structure 540 may be located on a corner region of the second substrate 500 to correspond to the guide hole 320 .

[0032] The alignment structure 540 may have a planar shape that is the same as or similar to that of the guide hole 320. The planar shape of the alignment structure 540 may have a size that is the same as or smaller than that of the guide hole 320 and extend along the third direction D3. Figure 1 In FIG. 5 , each alignment structure 540 is shown as a circular shape. Alternatively, each alignment structure 540 may have a cross shape, such as Figure 3 As shown, or various other shapes (e.g., polygonal shapes such as quadrilaterals or hexagons).

[0033] The bottom end of the alignment structure 540 may be at a level lower than the bottom end of the upper solder ball 420, for example, may extend farther toward the first substrate 100 than the upper solder ball 420 along the third direction D3. Along the third direction D3, the height h1 of each alignment structure 540 may be higher than the height h2 of the upper solder ball 420, and less than the sum of the height h2 of the upper solder ball 420 and the height h3 of the lower solder ball 410 (i.e., before the solder balls melt). The heights h1 and h2 are measured from the bottom surface of the second substrate 500 (i.e., the surface facing the first substrate 100) along the third direction D3, while the heights h3 and h4 are measured from the top surface of the first substrate 100 (i.e., the surface facing the second substrate 500) along the third direction D3. The height h1 of the alignment structure 540 may be greater than the height h4 of the first mold layer 300 or the height of the first semiconductor chip 200. Because, after the solder balls are melted, the alignment structures 540 are in contact with both the bottom surface of the second substrate 500 and the top surface of the first substrate 100, the height h1 of each alignment structure 540 may be the same as the distance between the first substrate 100 and the second substrate 500, for example, the distance between the first substrate 100 and the second substrate 500 may be defined. In this case, the top surface 300a of the first mold layer 300 may be spaced apart from the second substrate 500.

[0034] The alignment structure 540 may have a rounded bottom end. The alignment structure 540 may have a side surface 541, a bottom surface 542, and a corner surface 543. The bottom surface 542 of the alignment structure 540 may be parallel to the top surface of the first substrate 100. The side surface 541 of the alignment structure 540 may be perpendicular to the bottom surface 542 of the alignment structure 540. The corner surface 543 of the alignment structure 540 may be a corner portion where the side surface 541 and the bottom surface 542 intersect. The corner surface 543 of the alignment structure 540 may connect the side surface 541 to the bottom surface 542. The corner surface 543 of the alignment structure 540 may be a rounded surface curved with a curvature. Alternatively, the corner surface 543 of the alignment structure 540 may be a flat surface. In this case, the corner surface 543 may be an inclined surface, such as an inclined surface, relative to the bottom surface 542. In other words, the corner surface 543 is not orthogonal to the side surface 541 or the bottom surface 542.

[0035] In some example embodiments, Figure 2C As shown, an alignment solder cap 545 may be disposed on the bottom surface 542 of each alignment structure 540. For example, the alignment solder cap 545 may be formed by coating a solder material on the bottom surface 542 of the alignment structure 540. The alignment solder cap 545 may include a material different from that of the lower solder ball 410 and the upper solder ball 420. Figure 2B The example shown in .

[0036] See also Figure 1 and Figure 2D As shown, the second substrate 500 can be aligned with the first substrate 100 so that the upper solder ball 420 corresponds to the lower solder ball 410. The anti-warpage member 600 can be placed on the second substrate 500. For example, a weight can be used as the anti-warpage member 600. The anti-warpage member 600 can extend farther than the first substrate 100 and the second substrate 50 in the first direction D1 and the second direction D2. The second substrate 500 and the first substrate 100 can be brought into contact so that the guide hole 320 accommodates the alignment structure 540. Because the alignment structure 540 is provided at a position corresponding to the guide hole 320, when the alignment structure 540 is inserted into the guide hole 320, the first substrate 100 and the second substrate 500 can be aligned with each other. The cooperation of the first substrate 100 and the second substrate 500 can be achieved by applying a physical force to the anti-warpage member 600.

[0037] Depending on circumstances, the alignment structure 540 may be misaligned with the guide hole 320, and then the upper solder ball 420 may be misaligned with the lower solder ball 410. Such misalignment may result from mechanical errors of process equipment or other problems. Figure 5 An example is shown in which the first substrate 100 and the second substrate 500 have a deviation D due to misalignment therebetween. The first substrate 100 and the second substrate 500 can be self-aligned with each other even when the above-mentioned misalignment occurs. For example, the mating of the first substrate 100 and the second substrate 500 can cause the alignment structure 540 to contact a portion of the first mold layer 300 adjacent to the guide hole 320 (or adjacent to the corner edge of the side surface of the guide hole 320).

[0038] In this case, since each alignment structure 540 has a rounded (or inclined) corner surface 543, the alignment structure 540 can be formed by Figure 5 . For example, the second substrate 500 may be moved in the first direction D1 and / or the second direction D2 so that the alignment structure 540 is inserted into the guide hole 320. As a result, the first substrate 100 and the second substrate 500 may be aligned with each other. Because the size of the planar shape of the guide hole 320 is larger than the size of the planar shape of the alignment structure 540, the alignment structure 540 may be easily inserted into the guide hole 320. After the alignment structure 540 is inserted into the guide hole 320, the alignment structure 540 may be spaced apart from the side (e.g., inner wall) of the guide hole 320 by a first distance L1 (see Figure 1 ).

[0039] Return to see Figure 1 and Figure 2D, the second substrate 500 may extend continuously to couple the bottom end of the upper solder ball 420 to the top end of the lower solder ball 410. The bottommost end of the alignment structure 540 may be spaced apart from the top surface of the first substrate 100. The upper solder ball 420 and the lower solder ball 410 may have a circular shape. When the second substrate 500 moves, the upper solder ball 420 may slide on the lower solder ball 410. In this case, the second substrate 500 may move horizontally, for example, in the first direction D1 and / or the second direction D2, to cause misalignment with the first substrate 100. Because the alignment structure 540 inserted into the guide hole 320 maintains the second substrate 500 in its horizontal position, the upper solder ball 420 may not slide on the lower solder ball 410. Therefore, the connection terminal may be formed as desired in a subsequent process (see Figure 2E 430) and improve the reliability of stacked packages.

[0040] See also Figure 1 and Figure 2E , the first substrate 100 and the second substrate 500 may undergo a reflow process to form the connection terminal 430. The reflow process may be performed at a temperature higher than the melting point of the lower solder ball 410 and the upper solder ball 420. For example, the reflow process may be performed at a temperature of about 200° C. to about 250° C. The reflow process may be performed at a temperature lower than the melting point of the first mold layer 300 and the alignment structure 540, that is, the lower solder ball 410 and the upper solder ball 420 have a lower melting point than the first mold layer 300 and the alignment structure 540. The lower solder ball 410 and the upper solder ball 420 may be reflowed to form the connection terminal 430. The connection terminal 430 may be coupled to the first pad 110 and the fourth pad 510.

[0041] When the reflow process is performed, a physical force may be continuously applied to the warpage prevention member 600. When the lower solder ball 410 and the upper solder ball 420 are melted, the second substrate 500 may be continuously lowered. The second substrate 500 may be continuously lowered until the alignment structure 540 contacts the top surface of the first substrate 100. The alignment structure 540 may be coupled and electrically connected to the second pad 120 of the first substrate 100. The alignment structure 540 may be electrically connected to the ground circuit of the first substrate 100 through the second pad 120. Alternatively, the alignment structure 540 may be connected to a circuit provided in the first substrate 100. The alignment structure 540 may not only align the first substrate 100 and the second substrate 500 with each other but also electrically connect them to each other, and the circuit between the first substrate 100 and the second substrate 500 may be freely designed.

[0042] When the connection terminals 430 are cooled to room temperature (eg, about 25°) after the reflow process, the warpage preventing member 600 may be removed. Through the processes discussed above, the first semiconductor package P100 may be manufactured.

[0043] In some example embodiments, when the alignment structure 540 includes a solder bump, a process may be additionally performed to bond the alignment structure 540 to the first substrate 100. Figure 2F As shown, the connection terminal 430 may be formed after the alignment structure 540 is inserted into the guide hole 320. Thereafter, a laser welding process may be performed on the alignment structure 540. Figure 4 As shown, the first mold layer 300 may have a dome-like shape opened toward the outside of the first substrate 100. Each alignment structure 540 may have a first side surface 541a facing the first semiconductor chip 200 and a second side surface 541b opposite to the first side surface 541a. The laser welding process may be performed on the second side surface 541b of the alignment structure 540, which is not covered by the first mold layer 300 and is therefore exposed to the outside of the first substrate 100.

[0044] like Figure 2C As shown, when the alignment structure 540 includes an alignment cap 545 at its bottom end, a process may be additionally performed to couple the alignment structure 540 to the first substrate 100. Figure 2G As shown, after the alignment structure 540 is inserted into the guide hole 320, the alignment solder cap 545 may also be melted when a soldering process is performed to form the connection terminal 430. When the alignment solder cap 545 is cooled to room temperature (e.g., about 25°) after the reflow process, the alignment solder cap 545 may connect the alignment structure 540 to the second solder pad 120.

[0045] See also Figure 1 and Figure 2H , the second semiconductor package P200 may be mounted on the first semiconductor package P100 to form a stacked package. The first semiconductor package P100 may be as shown in FIG. Figure 2E , Figure 2F or Figure 2G The manufactured package discussed. The second semiconductor package P200 may include a third substrate 700, a second semiconductor chip 730, and a second molding layer 750. The third substrate 700 may include a first lower substrate pad 710 on its bottom surface. The second semiconductor chip 730 may be electrically connected to the third substrate 700 by a bonding wire 740. Alternatively, the second semiconductor chip 730 may be flip-chip bonded to the third substrate 700. The second semiconductor chip 730 may be different from the first semiconductor chip 200. The second semiconductor chip 730 may be provided in a single or multiple form. The third substrate 700 may have therein a circuit configured according to the mounting method, type, size, and / or quantity of the second semiconductor chip 730. The second molding layer 750 may be formed on the third substrate 700, covering the second semiconductor chip 730.

[0046] The second substrate 500 and the third substrate 700 may be provided with a coupling terminal 720 coupled to the sixth pad 530 and the first lower substrate pad 710 therebetween. The second substrate 500 may distinguish the coupling terminal 720 from the connection terminal 430 in terms of quantity and arrangement. Therefore, the first semiconductor chip 200 and the second semiconductor chip 730 may be variously changed in terms of quantity, size, mounting method and arrangement. In addition, the circuit may be freely designed in the second substrate 500.

[0047] Figure 6 A cross-sectional view showing a stage in a method of manufacturing a first semiconductor package according to some example embodiments is shown. For ease of description, the following will explain the Figure 1 and FIG. 2A to FIG. 2H Differences to those discussed.

[0048] See also Figure 6 , a plurality of first semiconductor chips 200 may be provided. The first semiconductor chips 200 may be disposed on a first wafer 1000. The first wafer 1000 may be a strip-shaped printed circuit board. A first mold layer 300 may be formed on the first wafer 1000, covering the first semiconductor chips 200. The first mold layer 300 may be formed with reference Figure 2A The first mold layer 300 discussed is substantially the same. For example, the first mold layer 300 may have a connection hole 310 and a guide hole 320.

[0049] The second substrate 500 may be provided in plurality, for example, and may be individually aligned with each first semiconductor chip. Figure 2B The second substrates 500 of the first and second semiconductor chips 200 are substantially the same. For example, each of the second substrates 500 may have an alignment structure 540 on its bottom surface. The second substrate 500 may be disposed on the corresponding first semiconductor chip 200. The alignment structure 540 of the second substrate 500 may be aligned with the corresponding guide hole 320 of the first mold layer 300. The reflow process may form a connection terminal 430 between the first wafer 1000 and the second wafer 5000. Then, depending on the situation, an underfill layer may be formed between the first mold layer 300 and the second substrate 500 and between the first semiconductor chip 200 and the second substrate 500.

[0050] The first wafer 1000, the first mold layer 300, and the underfill layer may be cut along the dotted lines, resulting in a plurality of first semiconductor packages P100' being formed to be separated from each other. Each of the plurality of first semiconductor packages P100' may be separated from each other. Figure 2E The first semiconductor package P100 in FIG.

[0051] Figure 7 2 shows a cross-sectional view of a stacked package according to some example embodiments. Figure 7 , the stack package may include a first semiconductor package P100 and a third semiconductor package P300. The third semiconductor package P300 may be mounted on the first semiconductor package P100.

[0052] The first semiconductor package P100 may include a first substrate 100, a first semiconductor chip 200, and a first mold layer 300. The third semiconductor package P300 may include a fourth substrate 800, a third semiconductor chip 820, and a third mold layer 830. The first substrate 100, the first semiconductor chip 200, and the first mold layer 300 may be connected to the reference Figure 2E Those discussed are substantially the same. Instead, the second substrate 500 may be omitted, and the fourth substrate 800 may include an alignment structure 540 on its bottom surface. In a plan view, the alignment structure 540 may overlap with the guide hole 320 of the first mold layer 300. The alignment structure 540 may extend from the bottom surface of the fourth substrate 800 into the guide hole 320 of the first mold layer 300, and may be coupled to the second pad 120 of the first substrate 100.

[0053] The first substrate 100 may include a connection terminal 430 in the connection hole 310 of the first mold layer 300. The connection terminal 430 may be connected to the first pad 110 of the first substrate 100 and the second lower substrate pad 810 of the fourth substrate 800. When a reflow process is performed to form the connection terminal 430, the alignment structure 540 may prevent the third semiconductor package P300 from shifting. Therefore, the connection terminal 430 may be desirably formed and the reliability of the stacked package may be improved.

[0054] According to some example embodiments, a semiconductor package may use an alignment structure to reduce misalignment that may occur when a second substrate is provided on a first substrate. In addition, when a reflow process is performed to mount the second substrate on the first substrate, the alignment structure may prevent the second substrate from shifting relative to the first substrate. Therefore, the first substrate and the second substrate may be successfully aligned with each other, and proper electrical connection may be achieved. As a result, the reliability of the semiconductor package may be improved.

[0055] In addition, the alignment structure can be used not only to align the first substrate and the second substrate with each other, but also to connect the second substrate to the ground circuit or electrical circuit of the first substrate. Therefore, the alignment structure can electrically connect the first substrate and the second substrate to each other, and a circuit can be freely designed between the first substrate and the second substrate.

[0056] Some example embodiments may provide a semiconductor package having improved structural stability and a method of manufacturing the same. Some example embodiments may provide a semiconductor package having enhanced reliability and a method of manufacturing the same.

[0057] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as would be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip, which is located on a first substrate; a first mold layer located on the first substrate and covering a sidewall of the first semiconductor chip, the first mold layer comprising at least two guide holes, the at least two guide holes exposing the first substrate and spaced apart from each other in a periphery of the first substrate; a second substrate, which is located on the first molding layer; a connection terminal located between the first substrate and the second substrate, the connection terminal connecting the first substrate and the second substrate to each other; as well as an alignment structure extending from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer, Wherein, the height of the alignment structure is greater than the height of the first molding layer or the first semiconductor chip, and The alignment structure has a side surface, a bottom surface, and a corner surface connecting the side surface and the bottom surface to each other, and the corner surface is a rounded surface or a sloped surface.

2. The semiconductor package according to claim 1, wherein: The at least two guide holes are located in a corner region of the first substrate.

3. The semiconductor package according to claim 1, wherein: The alignment structure contacts the first substrate.

4. The semiconductor package according to claim 3, wherein: The alignment structure is connected to a ground circuit of the first substrate.

5. The semiconductor package according to claim 1, wherein: The plane shape of the alignment structure is a circular shape, a polygonal shape or a cross shape.

6. The semiconductor package according to claim 1, wherein: The alignment structure is spaced apart from inner walls of corresponding guide holes of the at least two guide holes.

7. The semiconductor package according to claim 1, wherein: The alignment structures include conductive pillars or solder bumps. 8 . The semiconductor package of claim 1 , further comprising a solder cap on a bottom end of the alignment structure, the solder cap connecting the alignment structure and the first substrate to each other.

9. The semiconductor package according to claim 1, wherein: The alignment structure has a first side surface facing the first semiconductor chip and a second side surface opposite to the first side surface, and The first molding layer exposes a second side surface of the alignment structure. 10 . The semiconductor package of claim 1 , further comprising an electrical connection between the first substrate and the second substrate, wherein a material of the electrical connection has a melting point lower than melting points of the alignment structure and the first mold layer.

11. A method for manufacturing a semiconductor package, the method comprising the steps of: Providing a first package, the first package comprising a first semiconductor chip on a first substrate and a first mold layer covering a side wall of the first semiconductor chip on the first substrate, the first mold layer having a connection hole and a guide hole; providing a lower solder ball in the connection hole, the lower solder ball protruding beyond a top surface of the first molding layer; providing a second substrate on the first package, the second substrate having upper solder balls and an alignment structure on a bottom surface thereof, the alignment structure having a side surface, a bottom surface, and a corner surface connecting the side surface and the bottom surface to each other, and the corner surface is a rounded surface or a sloped surface; inserting the alignment structure into the guide hole; connecting the lower solder ball and the upper solder ball to each other; and A connection terminal is formed by combining the lower solder ball and the upper solder ball with each other.

12. The method according to claim 11, wherein: The melting points of the materials of the upper solder ball and the lower solder ball are lower than the melting points of the alignment structure and the first mold layer.

13. The method according to claim 11, wherein: The lowermost end of the alignment structure is located at a level lower than that of the lowermost end of the upper solder ball.

14. The method according to claim 13, wherein: The height of the alignment structure is greater than a height of the upper solder ball, less than a sum of a height of the upper solder ball and a height of the lower solder ball, and greater than a height of the first semiconductor chip.

15. The method according to claim 11, wherein: An upper side surface of the lower solder ball is exposed by the first mold layer.

16. The method according to claim 11, wherein: After forming the connection terminals, the method further includes coupling the alignment structure to the first substrate.

17. The method according to claim 11, wherein: The alignment structure includes an alignment welding cap at a bottom end thereof, and The step of forming the connection terminal includes connecting the alignment structure and the first substrate to each other using the alignment solder cap.

18. The method according to claim 11, wherein: The guide hole exposes a corner region of the first substrate.

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