GCT chip structure and fabrication method with P-type drift region

Abstract

This invention belongs to the field of power semiconductor devices and discloses a GCT chip structure and fabrication method with a P-type drift region. The GCT chip structure includes a P+ emitter with an anode, an n+ buffer layer attached to the P+ emitter, a P-type drift region attached to the n+ buffer layer, and an n+ emitter. During dynamic and static processes, the P-type drift region withstands the voltage difference between the anode and cathode. This invention ensures that the dynamic avalanche effect is reduced during high-current turn-off, thus providing high-current turn-off capability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor devices, and more specifically, it relates to a GCT chip structure with a P-type drift region and its fabrication method. Background Technology

[0002] The IGCT device is a new generation of current-controlled device developed based on the GTO. From the chip level, the GCT chip adopts transparent anode technology and buffer layer design, which reduces the trigger current level and on-state voltage drop. From the perspective of gate drive circuit and turn-on / turn-off mechanism, the IGCT adopts an integrated drive circuit. By optimizing the circuit layout and package structure, the stray parameters of the commutation circuit are reduced to the nanohenry level, so that the current can be completely transferred from the cathode to the gate in a very short time during the turn-off process, and then the PNP transistor is turned off naturally.

[0003] Reference Figure 1 , Figure 1 This is a schematic diagram of an existing GCT chip structure. Figure 1 As shown, existing GCT chips, during static blocking and dynamic shutdown processes, Figure 1 The J2 junction shown in the diagram handles voltages above kV between the anode and cathode. It's important to note that to ensure high-voltage withstand capability, the n-type drift region is typically fabricated using pristine silicon single crystals to create a low-doping region. In this case, the voltage drop mainly occurs within the n-type drift region shown in the diagram. Furthermore, according to Poisson's equation, the rate of change of the electric field is directly proportional to the doping concentration; that is, a lower doping concentration means that a well-designed structure can withstand higher blocking voltages.

[0004] However, during the high-current turn-off process at the anode, the J2 junction is continuously swept out of electron-hole pairs. The moving charge corresponding to this current increases the doping of the equivalent n-drift region during the dynamic process, which in turn reduces the breakdown voltage under dynamic turn-off conditions, i.e., the "dynamic avalanche effect" occurs. The dynamic avalanche effect may further trigger local current convergence or thermal breakdown, causing the entire chip to fail.

[0005] Therefore, there is an urgent need to develop a GCT chip structure and its fabrication method that overcomes the above-mentioned defects. Summary of the Invention

[0006] To address the aforementioned problems, this invention provides a GCT chip structure with a P-type drift region, comprising a P+ emitter with an anode, an n+ buffer layer attached to the P+ emitter, a P-type drift region attached to the n+ buffer layer, and an n+ emitter. During dynamic and static processes, the P-type drift region withstands the voltage difference between the anode and cathode.

[0007] The GCT chip structure described above also includes a P+ region, which is attached to the P-type drift region and connected to the n+ emitter.

[0008] The GCT chip structure described above also includes a P-base region, which is attached to the P-type drift region and located between the P+ region and the P-type drift region.

[0009] In the above-described GCT chip structure, the P+ region leads out a gate, the n+ emitter leads out a cathode, the connection between the n+ emitter and the P+ region forms a J3 junction, the connection between the P-type drift region and the n+ buffer layer forms a J2 junction, and the connection between the p+ emitter and the n+ buffer layer forms a J1 junction.

[0010] In the aforementioned GCT chip structure, the doping concentration of the P-type drift region is 3 × 10⁻⁶. 12 / cm 3 -4×10 13 / cm 3 .

[0011] In the aforementioned GCT chip structure, the thickness of the P-type drift region ranges from 300μm to 700μm.

[0012] In the aforementioned GCT chip structure, the P-type drift region is made of a P-type silicon wafer.

[0013] In the aforementioned GCT chip structure, the surface doping concentration of the n+ buffer layer is 1×10⁻⁶. 14 / cm 3 -4×10 16 / cm 3 The doping depth of the n+ buffer layer is 60 μm.

[0014] This invention also provides a method for fabricating a GCT chip structure with a P-type drift region, comprising:

[0015] Step S10: Select a P-substrate with specific resistivity and thickness.

[0016] Step S11: Using ion implantation followed by diffusion or deposition, a P+ region, a P-based region, and a P-type drift region are formed on the cathode surface of the P- substrate.

[0017] Step S12: An n+ buffer layer is formed on the anode surface of the P- substrate by diffusion or deposition after ion implantation;

[0018] Step S13: Form a thin layer of high-concentration n-type doped region on the cathode surface using ion implantation or deposition;

[0019] Step S14: A groove shape is formed on the cathode surface of the P- substrate using a dry or wet method, and then advanced by thermal diffusion to form an n+ emitter;

[0020] Step S15: Form a p+ emitter on the n+ buffer layer by diffusion or deposition after ion implantation;

[0021] Step S16: Form contact and patterning of metal electrodes on both sides, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

[0022] The above preparation method, wherein step S10 includes:

[0023] Step S101: Estimate the lowest selectable resistivity;

[0024] Step S102: Obtain the minimum thickness of the P-substrate based on the lowest selectable resistivity;

[0025] Step S103: Select a P-type silicon wafer with a resistivity higher than the minimum selectable value and a thickness higher than the minimum thickness as the P-substrate.

[0026] The advantages of this invention over the prior art are: to ensure that the occurrence of dynamic avalanche effect is reduced during high current turn-off, so as to provide high current turn-off capability.

[0027] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the existing GCT chip structure;

[0030] Figure 2 This is a schematic diagram of the first embodiment of the GCT chip structure of the present invention;

[0031] Figure 3 This is a schematic diagram of the second embodiment of the GCT chip structure of the present invention;

[0032] Figure 4 This is a flowchart of the preparation method of the present invention;

[0033] Figure 5 for Figure 4 Step-by-step flowchart;

[0034] Figure 6 This is a schematic diagram of the electric field intensity distribution of a GCT chip with an n-type drift region in the prior art;

[0035] Figure 7 for Figure 6 A schematic diagram of the electric field intensity distribution during the dynamic voltage establishment process;

[0036] Figure 8 This is a schematic diagram of the electric field intensity distribution of the GCT chip with a P-type drift region according to the present invention;

[0037] Figure 9 for Figure 8 A schematic diagram of the electric field intensity distribution in the first state during the establishment of dynamic voltage;

[0038] Figure 10 for Figure 8 A schematic diagram of the electric field intensity distribution in the second state during the establishment of dynamic voltage. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] The directional terms used in this article, such as up, down, left, right, front, or back, are for reference only when referring to the accompanying drawings. Therefore, the use of directional terms is for illustrative purposes and not to limit this work.

[0041] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0042] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0043] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a first embodiment of the GCT chip structure with a P-type drift region according to the present invention. Figure 2As shown, the GCT chip structure of the present invention includes: a P+ emitter with an anode, an n+ buffer layer attached to the P+ emitter, a P-type drift region attached to the n+ buffer layer, and an n+ emitter. During dynamic turn-off and static blocking processes, the P-type drift region bears the main voltage difference between the anode and cathode.

[0044] The P-type drift region is formed from the original P-type silicon single crystal; specifically, the P-type drift region is P-type doped, with a typical doping concentration of 3 × 10⁻⁶. 12 / cm 3 -4×10 13 / cm 3 The specific value used is related to the corresponding static blocking voltage and dynamic turn-off current density. In this embodiment, during the fabrication of the GCT chip, the doping of the P-type drift region is not achieved using doping processes such as thermal diffusion or ion implantation, but rather by directly using the original P-type silicon single crystal with the corresponding resistivity. Since the doping in other regions does not diffuse into the P-type drift region and the corresponding single crystal region, the doping in this part of the original P-type silicon single crystal is retained, thus forming the P-type drift region.

[0045] It should be noted that, in this embodiment, in order to improve the operability of the edge grinding process during device manufacturing, the depth of the n+ buffer layer may be appropriately increased compared with the traditional structure. The preferred reference range for the depth of the n+ buffer layer is between 30μm and 100μm, and the electric field is required to be cut off within the n+ buffer layer.

[0046] In one embodiment of the present invention, when the design breakdown voltage is 4500V-6500V, preferably, the thickness range of the corresponding P-type drift region is 300μm-700μm.

[0047] Furthermore, the GCT chip structure also includes a P+ region, which is attached to the P-type drift region. The P+ region is connected to the n+ emitter, where the P+ region leads out the gate and the n+ emitter leads out the cathode.

[0048] The GCT chip has a typical asymmetric structure, containing PN junctions. These PN junctions are formed by diffusion of P-type and N-type semiconductors using different doping processes on the same semiconductor substrate. A space charge region, called a PN junction, is formed at the interface between the P-type and N-type semiconductors. To distinguish the different PN junctions, a J3 junction is formed at the connection between the n+ emitter and the P+ region, a J2 junction at the connection between the P-type drift region and the n+ buffer layer, and a J1 junction at the connection between the p+ emitter and the n+ buffer layer. However, this invention is not limited to these specific junctions.

[0049] In one embodiment of the present invention, the surface doping concentration of the n+ buffer layer is 1×10⁻⁶.14 / cm 3 -4×10 16 / cm 3 .

[0050] In one embodiment of the present invention, the doping depth of the n+ buffer layer is 60 μm, and the surface concentration is 1 × 10⁻⁶. 15 / cm 3 .

[0051] It should be noted that the n+ buffer layer is formed by diffusion, so it is not uniformly doped. The structure is generally described by limiting the surface concentration and junction depth. On the other hand, the P-type drift region is determined by the original silicon wafer and is uniformly doped. Only the concentration and thickness need to be limited.

[0052] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a second embodiment of the GCT chip structure with a P-type drift region according to the present invention. Figure 3 The GCT chip structure shown is similar to Figure 2 The GCT chip structures shown are largely the same, so the identical parts will not be described again here. The differences are explained below. In this embodiment, the GCT chip structure also includes a P-base region, which is attached to the P-type drift region and located between the P+ region and the P-type drift region.

[0053] It should be noted that, based on the GCT chip structure of the present invention, when the doping concentration of the P-type drift region is high and the design value of the turn-off current is low, the P-type base region can be omitted, thereby simplifying the GCT chip manufacturing process.

[0054] In one embodiment of the present invention, the GCT chip structure may further include structures such as an anode emitter short circuit and a buffer wave base region. Figure 2 and / or Figure 3 The GCT chip structure shown is used in combination with other chips.

[0055] Please refer to Figure 4 , Figure 4 This is a flowchart of the preparation method of the present invention. Figure 5 for Figure 4 A step-by-step flowchart. For example... Figures 4-5 As shown, the preparation method of the present invention includes the following steps:

[0056] Step S10: Select a P-substrate with specific resistivity and thickness;

[0057] Specifically, when selecting the P-substrate for preparing the P-type drift region, the voltage blocking capability of the device should be considered first, that is, the blocking capability of the device in the absence of anodic current. In order to ensure sufficient voltage blocking capability, in this invention, preferably, the device must be selected as the P-substrate with a P-type silicon wafer that has a higher resistivity and a higher thickness than the minimum selectable resistivity.

[0058] Step S10 includes:

[0059] Step S101: Estimate the minimum selectable resistivity; wherein, in this embodiment, the minimum selectable resistivity is estimated according to the following formula:

[0060]

[0061] Where, N p,drift ε is the resistivity, which is also the doping concentration of the P-based region (according to national standards, there is a one-to-one correspondence between doping concentration and resistivity. When discussing silicon wafer parameters, resistivity is commonly used in the industry, but using doping concentration is essentially the same), U is the design blocking voltage, and ε is... Si is the dielectric constant of silicon;

[0062] Step S102: Obtain the minimum thickness of the P-substrate based on the lowest selectable resistivity; wherein, in this embodiment, the minimum thickness of the P-substrate is obtained according to the following formula:

[0063]

[0064] Among them, w p,drift The minimum thickness of the P-substrate;

[0065] For example, taking a design blocking voltage of 4500V as an example, the required maximum doping concentration in the p-type drift region is 8.7 × 10⁻⁶. 12 cm -3 The corresponding minimum selectable resistivity is approximately 480 Ω·m, with a minimum thickness of 310 μm at this minimum selectable resistivity. Based on this, the lowest permissible resistivity and a suitable thickness of P-type silicon wafer should be selected for fabrication. Typically, the thickness selection, in addition to exceeding the minimum thickness requirement described above to meet the blocking voltage requirement, also needs to consider the influence of the on-state voltage drop. However, since the optimal thickness value usually does not have an analytical solution, simulation tools are needed to assist in the design. Taking a 4500V blocking voltage as an example, the optimal thickness of the P-type drift region under different carrier lifetime conditions is approximately 300 μm-450 μm.

[0066] Step S103: Select a P-type silicon wafer with a resistivity higher than the minimum selectable value and a thickness higher than the minimum selectable value as the P-substrate.

[0067] Step S11: Using ion implantation followed by diffusion or deposition, a P+ region, a P-based region, and a P-type drift region are formed on the cathode surface of the P- substrate.

[0068] Step S12: An n+ buffer layer is formed on the anode surface of the P- substrate by diffusion or deposition after ion implantation;

[0069] Step S13: Form a thin layer of high-concentration n-type doped region on the cathode surface using ion implantation or deposition;

[0070] Step S14: A groove shape is formed on the cathode surface of the P- substrate using a dry or wet method, and then advanced by thermal diffusion to form an n+ emitter;

[0071] Step S15: Form a p+ emitter on the n+ buffer layer by diffusion or deposition after ion implantation;

[0072] Step S16: Form contact and patterning of metal electrodes on both sides, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

[0073] Please refer to Figures 6-7 , Figure 6 This is a schematic diagram of the electric field intensity distribution of a GCT chip with an n-type drift region in the prior art; Figure 7 for Figure 6 A schematic diagram of the electric field intensity distribution during the establishment of dynamic voltage.

[0074] Specifically, such as Figure 6 As shown, according to the Poisson equation:

[0075]

[0076] Where N drift For the corresponding doping concentrations (negative for the n-type drift region and positive for the P-based region), it can be seen that the rate of change of electric field intensity is proportional to the doping concentration. However, during the dynamic voltage establishment process, the distribution of electric field intensity is as follows: Figure 7 As shown, the rate of change of electric field intensity increases in the n-type drift region. This is because, in the presence of anodic current, the moving charge corresponding to the anodic current is positive in both the P-base region and the n-type drift region, which can be equivalent to n-type doping. Therefore, the overall slope of the electric field intensity change increases after the equivalent process. The increase in slope leads to an increase in the peak electric field intensity under the same anodic voltage, thereby enhancing the avalanche effect.

[0077] Please refer to Figures 8-10 , Figure 8 This is a schematic diagram of the electric field intensity distribution of the GCT chip with a P-type drift region according to the present invention; Figure 9 for Figure 8 A schematic diagram of the electric field intensity distribution in the first state during the establishment of dynamic voltage; Figure 10for Figure 8 A schematic diagram of the electric field intensity distribution in the second state during the establishment of dynamic voltage.

[0078] Specifically, such as Figure 8 As shown, the electric field intensity distribution differs in the P-type drift region structure. Under no-current conditions, the peak electric field intensity is located at the boundary between the P-type drift region and the n+ buffer layer. However, during the dynamic voltage establishment process, the electric field intensity distribution changes as follows: Figures 9-10 As shown, in the first state, when there is a certain anode current, but the value of the moving charge corresponding to the anode current is less than the doping concentration, the equivalent n-type doping of the moving charge in the P-type drift region is insufficient to invert the doping type of the P-type drift region. Therefore, reflected in the electric field intensity distribution, the peak value of the electric field intensity is still at the J2 junction formed by the P-type drift region and the n+ buffer layer. However, the slope of the electric field change in the P-type drift region is reduced. In the second state, after the anode current is further increased, the amount of moving charge exceeds the doping concentration in the P-type drift region, and the P-type drift region is inverted to n-type. It can be seen that under the same anode current and anode voltage, the slope of the electric field change in the drift region of the GCT chip with the P-type drift region structure is gentler than that of the GCT chip with the n-type drift region structure, thus effectively alleviating the peak electric field intensity, suppressing the dynamic avalanche process, and improving the current turn-off capability of the device.

[0079] In summary, the GTC chip structure and its design method of the present invention have strong applicability. They not only achieve the on-state voltage drop of existing GCT chip structures, but also possess stronger current turn-off capability, meaning they are less prone to avalanche processes under high current. Furthermore, they eliminate the higher turn-off losses caused by the delayed voltage rise rate during the turn-off process.

[0080] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GCT chip structure, characterized in that, It includes a P+ emitter, an n+ buffer layer, a P-type drift region, and a P+ region; among which, The P-type drift region and P+ region are directly prepared using a uniformly doped, original single-crystal silicon with specific resistivity and thickness as the P-substrate: formed by ion implantation followed by diffusion or deposition diffusion on the cathode surface of the P-substrate. The n+ buffer layer is formed on the anodic surface of the P- substrate by diffusion after ion implantation or by deposition diffusion. The P+ emitter is formed on the n+ buffer layer by ion implantation followed by diffusion or deposition diffusion. The GCT chip structure also includes an n+ emitter, which is formed by ion implantation or deposition on the cathode surface of the P- substrate to form a thin layer of high-concentration n-type doped region. A groove is formed on the cathode surface of the P- substrate by dry or wet method, and then the formation is advanced by thermal diffusion. The metal electrode on the cathode surface of the GCT chip structure is higher than the metal electrode on the gate surface.

2. The GCT chip structure as described in claim 1, characterized in that, It also includes a P+ region, which is attached to the P-type drift region and is connected to the n+ emitter.

3. The GCT chip structure as described in claim 2, characterized in that, It also includes a P-base region, which is attached to the P-type drift region and located between the P+ region and the P-type drift region.

4. The GCT chip structure as described in claim 3, characterized in that, The P+ region leads out a gate, the n+ emitter leads out a cathode, the connection between the n+ emitter and the P+ region forms a J3 junction, the connection between the P-type drift region and the n+ buffer layer forms a J2 junction, and the connection between the p+ emitter and the n+ buffer layer forms a J1 junction.

5. The GCT chip structure as described in any one of claims 1-4, characterized in that, The doping concentration of the P-type drift region is 3 × 10⁻⁶. 12 / cm 3 -4×10 13 / cm 3 .

6. The GCT chip structure as described in any one of claims 1-4, characterized in that, The thickness of the P-type drift region ranges from 300μm to 700μm.

7. The GCT chip structure as described in any one of claims 1-4, characterized in that, The material of the P-type drift region is a P-type silicon wafer.

8. The GCT chip structure as described in claim 2, characterized in that, The surface doping concentration of the n+ buffer layer is 1×10⁻⁶. 14 / cm3-4×10 16 / cm 3 The doping depth of the n+ buffer layer is 60 μm.

9. A method for fabricating a GCT chip structure, applicable to fabricating the GCT chip structure according to any one of claims 1-8, characterized in that, include: Step S10: Select a uniformly doped, original single-crystal silicon with specific resistivity and thickness as the P-substrate; Step S11: Using ion implantation followed by diffusion or deposition, a P+ region, a P-based region, and a P-type drift region are formed on the cathode surface of the P- substrate. Step S12: An n+ buffer layer is formed on the anode surface of the P- substrate by diffusion or deposition after ion implantation; Step S13: Form a thin layer of high-concentration n-type doped region on the cathode surface using ion implantation or deposition; Step S14: A groove shape is formed on the cathode surface of the P- substrate using a dry or wet method, and then advanced by thermal diffusion to form an n+ emitter; Step S15: Form a p+ emitter on the n+ buffer layer by diffusion or deposition after ion implantation; Step S16: Form contact and patterning of metal electrodes on both sides, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

10. The preparation method according to claim 9, characterized in that, Step S10 includes: Step S101: Through The minimum selectable resistivity is estimated, where, The minimum selectable resistivity, which is also the doping concentration in the P-base region, and U is the design blocking voltage. is the dielectric constant of silicon; Step S102: Obtain the minimum thickness of the P-substrate based on the lowest selectable resistivity: , in, The minimum thickness of the P-substrate; Step S103: Select a P-type silicon wafer with a resistivity higher than the minimum selectable value and a thickness higher than the minimum thickness as the P-substrate.

Images