Pulse width filtering circuit and pulse width filtering method for input pulse signal

Abstract

The invention discloses a pulse width filter circuit and a pulse width filter method for an input pulse signal, comprising a signal input terminal, a first control circuit, a second control circuit, a filter circuit and a signal output terminal; when the pulse width of the input pulse signal inputted at the signal input terminal is less than the filter width of the pulse width filter circuit, the filter circuit filters out the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output terminal for output; when the pulse width of the input pulse signal inputted at the signal input terminal is greater than or equal to the filter width of the pulse width filter circuit, the filter circuit retains the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output terminal for output, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width. The invention has the characteristics of low distortion, small transmission delay, small occupied area and easy integration.

Description

Technical Field

[0001] The invention relates to a pulse width filtering circuit and a pulse width filtering method for an input pulse signal, and belongs to the technical field of analog integrated circuits. Background Art

[0002] The input pulse signal is often mixed with various noise signals. If these noise signals are not processed, but the input pulse signal containing the noise signal is directly input into the chip circuit, the output signal of the chip circuit may be distorted or even wrong, thereby reducing the robustness of the chip circuit. Among them, the noise signal can include noise spikes, short pulse signals, etc. Figure 1 As shown, Figure 1 If the input pulse signal IN contains a noise signal, the output signal OUT contains an irregular signal corresponding to the noise signal.

[0003] In order to solve the above problems, a pulse width filter circuit for the input pulse signal is usually designed at the input stage of the chip circuit. The functions implemented by the pulse width filter circuit include at least: when the pulse width of the input pulse signal is smaller than the filter width, the input pulse signal is filtered out and the output signal remains unchanged; when the pulse width of the input pulse signal is larger than the filter width, the output signal is the input pulse signal, so that the input pulse signal can be transmitted to the next stage circuit without distortion.

[0004] A pulse width filter circuit for input pulse signals designed in the related art is an RC filter circuit based on closed-loop feedback switch control, and the pulse width filter circuit includes a rising circuit, a falling circuit, a capacitor C1, a first inverter INV1 and a controller. The rising circuit includes a first current source I 1 , PMOS tube P1 and the first switch S1, used to charge the subsequent capacitor C1; the falling circuit includes a second current source I 2 , NMOS tube N1 and the second switch S2, used to provide a charge discharge channel for the subsequent capacitor C1, and the first current source I 1 , the second current source I 2 The controller includes a second inverter INV2, a first pulse generating unit PG1 and a second pulse generating unit PG2, and the first short pulse signal SP1 generated by the first pulse generating unit PG1 is used to control the first switch S1, and the second short pulse signal SP2 generated by the second pulse generating unit PG2 is used to control the second switch S2. Figure 2As shown. The working principle of the pulse width filter circuit is described below. Assuming that the input pulse signal IN is at a low level in the initial state, the signal MDS1 at the node MDS1 is at a high level, the first short pulse signal SP1 is at a low level, the second short pulse signal SP2 is at a low level, the output signal OUT is at a low level, and / OUT is at a high level. At time T1, the rising edge of the input pulse signal IN comes, the channel of the NMOS tube N1 is turned on, and the capacitor C1 is connected to the NMOS tube N1 and the second current source I 2 The potential of the node MDS1 starts to decrease after discharging. At time T2, the potential of the node MDS1 decreases to the voltage threshold V TH (Capacitor C discharge time t FIT1 ), the output signal of the first inverter INV1 (i.e., the circuit output signal OUT) is flipped from a low level to a high level, and the output signal OUT generates a positive narrow pulse SP2 to the switch S2 through the second pulse generating unit PG2, so that the switch S2 is closed, and the potential of the node MDS1 is quickly pulled down to a low level; at time T3, the narrow pulse of the second short pulse signal SP2 ends, the switch S2 is disconnected, and at this time the node MDS1 has dropped to a low level; at time T4, the falling edge of the input pulse signal IN comes, the channel of the PMOS tube P1 is turned on, and the power supply voltage VDD passes through the first current source I 1 The capacitor C is charged by the PMOS tube P1, and the potential of the node MDS1 begins to rise; at time T5, the potential of the node MDS1 rises to the voltage threshold V of the first inverter INV1 TH (Capacitor C charging time t FIT2 ), the output signal of the first inverter INV1 (i.e., the circuit output signal OUT) is flipped from a high level to a low level, and the output signal OUT generates a positive narrow pulse SP2 to the switch S1 through the first pulse generating unit PG1, so that the switch S1 is closed, and the potential of the node MDS1 is quickly pulled up to the power supply voltage VDD (high level); at time T6, the narrow pulse of the first short pulse signal SP1 ends, and the switch S1 is disconnected. At this time, the potential of the node MDS1 has risen to a high level; at time T6-T7, the pulse width filter circuit returns to the initial state, and the voltage on the capacitor C1 is charged to the voltage VDD again. After that, the pulse width filter circuit will repeat the operation according to the above cycle T1-T7.

[0005] Although the above-mentioned pulse width filter circuit can filter the input pulse signal, the circuit has the following disadvantages: 1) when the input pulse width is close to the filter width of the pulse width filter circuit, the output signal will be distorted; 2) the pulse width filter circuit includes two pulse generating units, and the pulse generating units require additional capacitors, which makes the structure of the pulse width filter circuit more complicated and occupies a larger area. Summary of the invention

[0006] The present invention provides a pulse width filter circuit and a pulse width filter method for an input pulse signal, which can obtain a low-distortion output signal while simplifying the circuit structure, thereby solving the technical problem in the related art that the pulse width filter circuit has a complex circuit structure and the output signal is easily distorted.

[0007] The present invention specifically adopts the following technical solutions to solve the above technical problems:

[0008] A pulse width filter circuit for inputting a pulse signal, the pulse width filter circuit comprising a signal input terminal, a first control circuit, a second control circuit, a filter circuit and a signal output terminal;

[0009] The signal input end is connected to the first input end of the first control circuit, the first input end of the second control circuit and the first input end of the filter circuit respectively; the signal output end is connected to the second input end of the first control circuit, the second input end of the second control circuit and the output end of the filter circuit respectively; the output end of the first control circuit is connected to the second input end of the filter circuit; the output end of the second control circuit is connected to the third input end of the filter circuit;

[0010] When the pulse width of the input pulse signal inputted from the signal input terminal is smaller than the filter width of the pulse width filter circuit, the filter circuit filters out the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output terminal for output;

[0011] When the pulse width of the input pulse signal input into the signal input end is greater than or equal to the filter width of the pulse width filter circuit, the filter circuit retains the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output end for output, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width.

[0012] In an optional embodiment, the first control circuit includes a first delay circuit, a two-input NAND gate and a first P-channel metal oxide semiconductor field effect PMOS tube;

[0013] The first input end of the first delay circuit is the first input end of the first control circuit; the output end of the first delay circuit is connected to the first input end of the two-input NAND gate; the second input end of the two-input NAND gate is the second input end of the first control circuit; the output end of the two-input NAND gate is connected to the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply; the drain of the first PMOS tube is the output end of the first control circuit;

[0014] Wherein, the first delay circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first N-channel metal oxide semiconductor field effect NMOS tube, a second NMOS tube, a third NMOS tube and a first capacitor; the source of the second PMOS tube is connected to a power supply; the gate of the second PMOS tube is connected to a first bias level; the drain of the second PMOS tube is connected to the source of the third PMOS tube; the gate of the third PMOS tube is connected to the gate of the first NMOS tube to form the input end of the first delay circuit; the drain of the third PMOS tube, the drain of the first NMOS tube, one end of the first capacitor, the The drain of the fourth PMOS tube is connected to the drain of the third NMOS tube; the source of the first NMOS tube is connected to the drain of the second NMOS tube; the gate of the second NMOS tube is connected to the second bias level; the source of the second NMOS tube and the other end of the first capacitor are grounded; the source of the fourth PMOS tube is connected to the power supply; the source of the third NMOS tube is grounded; the drain of the fourth PMOS tube and the drain of the third NMOS tube are connected to form the output end of the first delay circuit; wherein the charging speed of the first capacitor is controlled by the second PMOS tube, and the discharging speed of the first capacitor is controlled by the second NMOS tube;

[0015] The two-input NAND gate comprises a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the source of the fifth PMOS tube and the source of the sixth PMOS tube are respectively connected to a power supply; the drain of the fifth PMOS tube, the drain of the sixth PMOS tube and the drain of the fourth NMOS tube are connected to form the output end of the two-input NAND gate; the gate of the fifth PMOS tube and the gate of the fourth NMOS tube are connected to form the second input end of the two-input NAND gate; the gate of the sixth PMOS tube and the gate of the fifth NMOS tube are connected to form the first input end of the two-input NAND gate; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the source of the fifth NMOS tube is grounded.

[0016] In an optional embodiment, the second control circuit includes a second delay circuit, a two-input NOR gate and a sixth NMOS tube;

[0017] The first input end of the second delay circuit is the first input end of the second control circuit; the output end of the second delay circuit is connected to the first input end of the two-input NOR gate; the second input end of the two-input NOR gate is the second input end of the second control circuit; the output end of the two-input NOR gate is connected to the gate of the sixth NMOS tube; the source of the sixth NMOS tube is grounded; the drain of the sixth NMOS tube is the output end of the second control circuit;

[0018] Wherein, the second delay circuit comprises a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a second capacitor; the source of the seventh PMOS tube is connected to a power supply; the gate of the seventh PMOS tube is connected to a first bias level; the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the gate of the eighth PMOS tube and the gate of the seventh NMOS tube are connected to form the input end of the second delay circuit; the drain of the eighth PMOS tube, the drain of the seventh NMOS tube, one end of the second capacitor, the ninth PMOS tube The drain of the ninth NMOS tube is connected to the drain of the ninth NMOS tube; the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube; the gate of the eighth NMOS tube is connected to the second bias level; the source of the eighth NMOS tube and the other end of the second capacitor are grounded; the source of the ninth PMOS tube is connected to the power supply; the source of the ninth NMOS tube is grounded; the drain of the ninth PMOS tube and the drain of the ninth NMOS tube are connected to form the output end of the second delay circuit; wherein the charging speed of the second capacitor is controlled by the seventh PMOS tube, and the discharging speed of the second capacitor is controlled by the eighth NMOS tube;

[0019] The two-input NOR gate includes a tenth PMOS tube, an eleventh PMOS tube, a tenth NMOS tube and an eleventh NMOS tube; the source of the tenth PMOS tube is connected to a power supply; the gate of the tenth PMOS tube and the gate of the eleventh NMOS tube are connected to form a first input end of the two-input NOR gate; the drain of the tenth PMOS tube and the source of the eleventh PMOS tube are connected; the gate of the eleventh PMOS tube and the gate of the tenth NMOS tube are connected to form a second input end of the two-input NOR gate; the drain of the eleventh PMOS tube, the drain of the tenth NMOS tube and the drain of the eleventh NMOS tube are connected to form an output end of the two-input NOR gate; the source of the tenth NMOS tube and the source of the eleventh NMOS tube are grounded respectively.

[0020] In an optional embodiment, the filter circuit includes three inverters and a charge and discharge circuit; the input end of the first inverter is the first input end of the filter circuit; the output end of the first inverter is connected to the input end of the charge and discharge circuit; the output end of the charge and discharge circuit, the second input end of the filter circuit and the third input end of the filter circuit are connected and then connected to the input end of the second inverter; the output end of the second inverter is connected to the input end of the third inverter; the output end of the third inverter is the output end of the filter circuit, or, the filter circuit includes two inverters, a charge and discharge circuit and a Schmitt trigger; the input end of the first inverter is the first input end of the filter circuit; the output end of the first inverter is connected to the input end of the charge and discharge circuit; the output end of the charge and discharge circuit, the second input end of the filter circuit and the third input end of the filter circuit are connected and then connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the input end of the second inverter; the output end of the second inverter is the output end of the filter circuit.

[0021] In an optional implementation, the inverter includes a twelfth PMOS tube and a twelfth NMOS tube;

[0022] The source of the twelfth PMOS tube is connected to a power supply; the gate of the twelfth PMOS tube is connected to the gate of the twelfth NMOS tube and becomes the input end of the inverter; the source of the twelfth NMOS tube is grounded; the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube and becomes the output end of the inverter.

[0023] In an optional implementation, the Schmitt trigger includes a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube;

[0024] The source of the thirteenth PMOS tube is connected to a power supply; the gate of the thirteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube are connected to form the input end of the Schmitt trigger; the drain of the thirteenth PMOS tube, the source of the fourteenth PMOS tube and the source of the fifteenth PMOS tube are connected, the drain of the fifteenth PMOS tube is grounded, the drain of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube, the drain of the thirteenth NMOS tube and the gate of the fifteenth NMOS tube are connected to form the output end of the Schmitt trigger; the drain of the fourteenth NMOS tube, the source of the thirteenth NMOS tube and the source of the fifteenth NMOS tube are connected; the source of the fourteenth NMOS tube is grounded; the drain of the fifteenth NMOS tube is connected to a power supply.

[0025] In an optional embodiment, the charge and discharge circuit includes a sixteenth PMOS tube, a seventeenth PMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and a capacitor; the gate of the seventeenth PMOS tube and the gate of the seventeenth NMOS tube are connected to form the input end of the charge and discharge circuit; the source of the seventeenth PMOS tube is connected to the drain of the sixteenth PMOS tube; the source of the sixteenth PMOS tube is connected to a power supply; the gate of the sixteenth PMOS tube is connected to a first bias level; the drain of the seventeenth PMOS tube, the drain of the seventeenth NMOS tube, and one end of the third capacitor are connected to form the output end of the charge and discharge circuit; the source of the seventeenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the source of the sixteenth NMOS tube and the other end of the third capacitor are grounded respectively, and the gate of the sixteenth NMOS tube is connected to a second bias level; wherein the charging speed of the third capacitor is controlled by the sixteenth PMOS tube as the first current source, and the discharging speed of the capacitor is controlled by the first current source as the second current source. The charging and discharging circuit comprises a first resistor, a second resistor, a seventeenth PMOS tube, a seventeenth NMOS tube, a third resistor, a fourth resistor and a third capacitor; the gate of the seventeenth PMOS tube and the gate of the seventeenth NMOS tube are connected to form the input end of the charging and discharging circuit; the source of the seventeenth PMOS tube is connected to one end of the second resistor; the other end of the second resistor is connected to one end of the first resistor; the other end of the first resistor is connected to a power supply; the drain of the seventeenth PMOS tube, the drain of the seventeenth NMOS tube and one end of the third capacitor are connected to form the output end of the charging and discharging circuit; the source of the seventeenth NMOS tube is connected to one end of the third resistor; the other end of the third resistor is connected to one end of the fourth resistor; the other end of the fourth resistor and the other end of the capacitor are grounded respectively; wherein the charging speed of the third capacitor is controlled by the resistance values ​​of the first resistor and the second resistor, and the discharging speed of the third capacitor is controlled by the resistance values ​​of the third resistor and the fourth resistor.

[0026] In an optional implementation, a charging speed of the first capacitor, a discharging speed of the first capacitor, a charging speed of the second capacitor, and a discharging speed of the second capacitor are equal.

[0027] In an optional implementation, the currents of the first current source and the second current source in the charge-discharge circuit are equal;

[0028] When the filter circuit further includes three inverters, the voltage threshold of the second inverter is half of the voltage value of the power supply;

[0029] When the filtering circuit further includes two inverters and a Schmitt trigger, the forward voltage threshold of the Schmitt trigger is two-thirds of the voltage value of the power supply, and the reverse voltage threshold of the Schmitt trigger is one-third of the voltage value of the power supply.

[0030] In an optional embodiment, the first resistor, the second resistor, the third resistor and the fourth resistor in the charge and discharge circuit have equal resistance values, the first resistor and the third resistor are similar lightly doped Poly resistors with negative temperature coefficients, the second resistor and the fourth resistor are similar heavily doped Poly resistors with positive temperature coefficients, and the sum of the negative temperature coefficients of the first resistor and the third resistor and the positive temperature coefficients of the second resistor and the fourth resistor is 0;

[0031] When the filter circuit further includes three inverters, the voltage threshold of the second inverter is half of the voltage value of the power supply;

[0032] When the filtering circuit further includes two inverters and a Schmitt trigger, the forward voltage threshold of the Schmitt trigger is two-thirds of the voltage value of the power supply, and the reverse voltage threshold of the Schmitt trigger is one-third of the voltage value of the power supply.

[0033] A pulse width filtering method for an input pulse signal is applied to the pulse width filtering circuit as described above, the method comprising:

[0034] receiving an input pulse signal;

[0035] If the pulse width of the input pulse signal is smaller than the filter width of the pulse width filter circuit, the input pulse signal is filtered out and an output signal is output;

[0036] If the pulse width of the input pulse signal is greater than or equal to the filter width of the pulse width filter circuit, the input pulse signal is retained and an output signal is output, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] (1) The present invention controls the first control circuit and the second control circuit through the feedforward of the input pulse signal and the feedback of the output signal, and then controls the filter circuit through the first control circuit and the second control circuit, so that the filter circuit filters out the input pulse signal when the pulse width of the input pulse signal is less than the filter width, and sends the obtained output signal to the signal output end for output, thereby achieving the purpose of filtering the input pulse signal (i.e., the noise signal) whose pulse width is less than the filter width; retaining the input pulse signal when the pulse width of the input pulse signal is greater than or equal to the filter width, and sending the obtained output signal to the signal output end for output. The present invention is based on the feedforward and feedback control strategy, and compared with the traditional RC filtering technology, it has the characteristics of low distortion and small transmission delay.

[0039] (2) The two ports for feeding back the output signal in the present invention are composed of a simple two-input NAND gate, a two-input NOR gate and a MOS tube, so that the circuit structure is relatively simple.

[0040] (3) Compared with the traditional RC filter circuit, the present invention does not require a switching device, which makes the circuit occupy a smaller area and is easy to be integrated into a smart power integrated circuit (SPIC). BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of an input pulse signal including a noise signal and an output signal;

[0042] Figure 2 A circuit diagram of a RC filter based on closed-loop feedback switch control in the related art;

[0043] Figure 3 A schematic diagram of a working waveform of an RC filter based on closed-loop feedback switch control in the prior art;

[0044] Figure 4 A schematic diagram of the principle of a pulse width filter circuit for an input pulse signal provided by the present invention;

[0045] Figure 5 A circuit diagram of a first specific implementation mode provided by the present invention;

[0046] Figure 6 for Figure 5 Schematic diagram of working waveform of the circuit in the figure;

[0047] Figure 7 for Figure 5 Schematic diagram of the working waveform of the noise filtering of the circuit;

[0048] Figure 8 A circuit diagram of a second specific implementation mode provided by the present invention;

[0049] Fig. 9 A circuit diagram of a third specific implementation mode provided by the present invention;

[0050] Fig.10 for Fig. 9 Schematic diagram of working waveform of the circuit in the figure;

[0051] Fig.11 for Fig. 9 Schematic diagram of the working waveform of the noise filtering of the circuit;

[0052] Fig.12 A circuit diagram of a fourth specific implementation mode provided by the present invention;

[0053] Fig.13 A schematic flow chart of the pulse width filtering method provided by the present invention;

[0054] Fig.14 A schematic flow chart of the pulse width filtering method provided by the present invention. DETAILED DESCRIPTION

[0055] In view of the problem that the output signal of the existing RC filter circuit is distorted and the circuit structure is relatively complex during filtering, the solution of the present invention is to abandon the traditional RC filter circuit and filter based on the control strategy of feedforward of the input pulse signal and feedback of the output signal, which has the beneficial effects of low distortion and small transmission delay. The pulse width filter circuit of the present invention is introduced below.

[0056] Please refer to Figure 4 The pulse width filter circuit in this embodiment includes a signal input terminal IN, a first control circuit, a second control circuit, a filter circuit and a signal output terminal OUT. The signal input terminal IN is used to receive an input pulse signal; the first control circuit and the second control circuit are used to control the filter circuit to filter the input pulse signal to obtain an output signal; the signal output terminal OUT is used to output the output signal. The connection relationship of the above parts is introduced below.

[0057] The signal input terminal IN is respectively connected to the first input terminal of the first control circuit, the first input terminal of the second control circuit and the first input terminal of the filter circuit; the signal output terminal OUT is respectively connected to the second input terminal of the first control circuit, the second input terminal of the second control circuit and the output terminal of the filter circuit; the output terminal of the first control circuit is connected to the second input terminal of the filter circuit; the output terminal of the second control circuit is connected to the third input terminal of the filter circuit. Among them, the first input terminal of the first control circuit is a feedforward signal (i.e., input pulse signal) input terminal, and the second input terminal is a feedback signal (i.e., output signal) input terminal; the first input terminal of the second control circuit is a feedforward signal (i.e., input pulse signal) input terminal, and the second input terminal is a feedback signal (i.e., output signal) input terminal.

[0058] When the pulse width of the input pulse signal inputted by the signal input terminal IN is smaller than the filter width of the pulse width filter circuit, the filter circuit filters out the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output terminal for output. The filter width is the maximum width of the noise signal that can be filtered by the pulse width filter circuit.

[0059] When the pulse width of the input pulse signal input at the signal input terminal IN is greater than or equal to the filter width of the pulse width filter circuit, the filter circuit retains the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output terminal for output, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width.

[0060] It should be noted that when the pulse width of the input pulse signal is equal to (or approximate to) the filter width of the pulse width filter circuit, a narrow pulse will appear in the output signal, resulting in distortion of the output signal. In order to solve the above problem, a delay circuit can be set in the first control circuit and the second control circuit. At this time, the delay time between the output signal and the input pulse signal is greater than the filter width; if the delay circuit is not set in the first control circuit and the second control circuit, the delay time between the output signal and the input pulse signal is equal to the filter width. The following is an example of the first control circuit and the second control circuit being provided with a delay circuit.

[0061] To facilitate public understanding, the technical solution of the present invention is further described in detail below through four specific embodiments:

[0062] Embodiment 1,

[0063] The pulse width filter circuit of this embodiment is as follows Figure 5 As shown, the pulse width filter circuit includes a signal input terminal IN, a first control circuit, a second control circuit, a filter circuit and a signal output terminal OUT. The first control circuit, the second control circuit and the filter circuit are introduced below.

[0064] 1. The circuit structure of the first control circuit is as follows:

[0065] The first control circuit includes a first delay circuit, a two-input NAND gate NAND1 and a first PMOS (P-Channel Metal Oxide Semiconductor, P-channel Metal Oxide Semiconductor Field Effect) transistor P9.

[0066] The first input end of the first delay circuit is the first input end of the first control circuit; the output end of the first delay circuit is connected to the first input end of the two-input NAND gate NAND1; the second input end of the two-input NAND gate NAND1 is the second input end of the first control circuit; the output end of the two-input NAND gate NAND1 is connected to the gate of the first PMOS tube P9; the source of the first PMOS tube P9 is connected to the power supply VDD; the drain of the first PMOS tube P9 is the output end of the first control circuit.

[0067] The first delay circuit includes a second PMOS tube P10, a third PMOS tube P11, a fourth PMOS tube P12, a first NMOS (N-Channel Metal Oxide Semiconductor, N-channel Metal Oxide Semiconductor Field Effect) tube N10, a second NMOS tube N11, a third NMOS tube N12 and a first capacitor C2; the source of the second PMOS tube P10 is connected to the power supply VDD; the gate of the second PMOS tube P10 is connected to the first bias level BP; the drain of the second PMOS tube P10 is connected to the source of the third PMOS tube P11; the gate of the third PMOS tube P11 is connected to the gate of the first NMOS tube N10 to form the input end of the first delay circuit; the drain of the third PMOS tube P11 and the drain of the first NMOS tube N10 are connected to the input end of the first delay circuit; , one end of the first capacitor C2, the drain of the fourth PMOS tube P12 and the drain of the third NMOS tube N12 are connected; the source of the first NMOS tube N10 is connected to the drain of the second NMOS tube N11; the gate of the second NMOS tube N11 is connected to the second bias level BN; the source of the second NMOS tube N11 and the other end of the first capacitor C2 are grounded GND; the source of the fourth PMOS tube P12 is connected to the power supply VDD; the source of the third NMOS tube N12 is grounded GND; the drain of the fourth PMOS tube P12 and the drain of the third NMOS tube N12 are connected to form the output end of the first delay circuit. Among them, the charging speed of the first capacitor C2 is controlled by the second PMOS tube P10, and the discharging speed of the first capacitor C2 is controlled by the second NMOS tube N11.

[0068] Among them, the two-input NAND gate NAND1 includes a fifth PMOS tube P5, a sixth PMOS tube P6, a fourth NMOS tube N5 and a fifth NMOS tube N6; the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are respectively connected to the power supply VDD; the drain of the fifth PMOS tube P5, the drain of the sixth PMOS tube P6 and the drain of the fourth NMOS tube N5 are connected to form the output end of the two-input NAND gate NAND1; the gate of the fifth PMOS tube P5 and the gate of the fourth NMOS tube N5 are connected to form the second input end of the two-input NAND gate NAND1; the gate of the sixth PMOS tube P6 and the gate of the fifth NMOS tube N6 are connected to form the first input end of the two-input NAND gate NAND1; the source of the fourth NMOS tube N5 is connected to the drain of the fifth NMOS tube N6, and the source of the fifth NMOS tube N6 is grounded GND.

[0069] 2. The circuit structure of the second control circuit is as follows:

[0070] The second control circuit includes a second delay circuit, a two-input NOR gate NOR1 and a sixth NMOS transistor N9.

[0071] The first input end of the second delay circuit is the first input end of the second control circuit; the output end of the second delay circuit is connected to the first input end of the two-input NOR gate NOR1; the second input end of the two-input NOR gate NOR1 is the second input end of the second control circuit; the output end of the two-input NOR gate NOR1 is connected to the gate of the sixth NMOS transistor N9; the source of the sixth NMOS transistor N9 is grounded GND; the drain of the sixth NMOS transistor N9 is the output end of the second control circuit;

[0072] The second delay circuit includes a seventh PMOS tube P13, an eighth PMOS tube P14, a ninth PMOS tube P15, a seventh NMOS tube N13, an eighth NMOS tube N14, a ninth NMOS tube N15 and a second capacitor C3; the source of the seventh PMOS tube P13 is connected to the power supply VDD; the gate of the seventh PMOS tube P13 is connected to the first bias level BP; the drain of the seventh PMOS tube P13 is connected to the source of the eighth PMOS tube P14; the gate of the eighth PMOS tube P14 and the gate of the seventh NMOS tube N13 are connected to form the input end of the second delay circuit; the drain of the eighth PMOS tube P14, the seventh The drain of the NMOS tube N13, one end of the second capacitor C3, the drain of the ninth PMOS tube P15 and the drain of the ninth NMOS tube N15 are connected; the source of the seventh NMOS tube P13 is connected to the drain of the eighth NMOS tube N14; the gate of the eighth NMOS tube N14 is connected to the second bias level BN; the source of the eighth NMOS tube N14 and the other end of the second capacitor C3 are grounded GND; the source of the ninth PMOS tube P15 is connected to the power supply VDD; the source of the ninth NMOS tube N15 is grounded GND; the drain of the ninth PMOS tube P15 and the drain of the ninth NMOS tube N15 are connected to form the output end of the second delay circuit. Among them, the charging speed of the second capacitor C3 is controlled by the seventh PMOS tube P13, and the discharging speed of the second capacitor C3 is controlled by the eighth NMOS tube N14.

[0073] The two-input NOR gate NOR1 includes a tenth PMOS tube P7, an eleventh PMOS tube P8, a tenth NMOS tube N7 and an eleventh NMOS tube N8; the source of the tenth PMOS tube P7 is connected to the power supply VDD; the gate of the tenth PMOS tube P7 and the gate of the tenth NMOS tube N7 are connected to form a first input terminal of the two-input NOR gate NOR1; the drain of the tenth PMOS tube P7 and the source of the eleventh PMOS tube P8 are connected; the gate of the eleventh PMOS tube P8 and the gate of the eleventh NMOS tube N8 are connected to form a second input terminal of the two-input NOR gate NOR1; the drain of the eleventh PMOS tube P8, the drain of the tenth NMOS tube N7 and the drain of the eleventh NMOS tube N8 are connected to form an output terminal of the two-input NOR gate NOR1; the source of the tenth NMOS tube N7 and the source of the eleventh NMOS tube N8 are grounded GND respectively.

[0074] 3. The circuit structure of the filter circuit is as follows:

[0075] The filter circuit includes three inverters and a charge-discharge circuit; wherein, the input end of the first inverter INV1 is the first input end of the filter circuit; the output end of the first inverter INV1 is connected to the input end of the charge-discharge circuit; the output end of the charge-discharge circuit, the second input end of the filter circuit and the third input end of the filter circuit are connected and then connected to the input end of the second inverter INV2; the output end of the second inverter INV2 is connected to the input end of the third inverter INV3; the output end of the third inverter INV3 is the output end of the filter circuit.

[0076] The circuit structures of the three inverters in the present invention are the same, and the first inverter INV1 is taken as an example for explanation below. The inverter INV1 includes a twelfth PMOS tube P1 and a twelfth NMOS tube N1; the source of the twelfth PMOS tube P1 is connected to the power supply VDD; the gate of the twelfth PMOS tube P1 is connected to the gate of the twelfth NMOS tube N1 to form the input end of the inverter INV1; the source of the twelfth NMOS tube N1 is grounded GND; the drain of the twelfth PMOS tube P1 is connected to the drain of the twelfth NMOS tube N1 to form the output end of the inverter INV1.

[0077] It should be noted that the circuit structure of the second inverter INV2 is the same as that of the first inverter INV1. Figure 5 The twelfth PMOS tube in the second inverter INV2 is marked as P3, and the twelfth NMOS tube is marked as N3. The circuit structure of the third inverter INV3 is the same as that of the first inverter INV1. For the convenience of distinction, Figure 5 In the figure, the twelfth PMOS tube in the third inverter INV3 is marked as P4, and the twelfth NMOS tube is marked as N4.

[0078] The charge and discharge circuit includes a sixteenth PMOS tube P16, a seventeenth PMOS tube P2, a sixteenth NMOS tube N16, a seventeenth NMOS tube N2 and a third capacitor C1; the gate of the seventeenth PMOS tube P2 and the gate of the seventeenth NMOS tube N2 are connected to form the input end of the charge and discharge circuit; the source of the seventeenth PMOS tube P2 is connected to the drain of the sixteenth PMOS tube P16; the source of the sixteenth PMOS tube P16 is connected to the power supply VDD; the gate of the sixteenth PMOS tube P16 is connected to the first bias level BP; the drain of the seventeenth PMOS tube P2, the gate of the seventeenth NMOS tube N2 and the gate of the seventeenth PMOS tube P16 are ... The drain of the seventeenth NMOS tube N2 and one end of the third capacitor C1 are connected to form the output end of the charge and discharge circuit; the source of the seventeenth NMOS tube N2 is connected to the drain of the sixteenth NMOS tube N16; the source of the sixteenth NMOS tube N16 and the other end of the third capacitor C1 are grounded respectively, and the gate of the sixteenth NMOS tube N16 is connected to the second bias level BN; wherein, the charging speed of the third capacitor C1 is controlled by the sixteenth PMOS tube P16 as the first current source I1, and the discharging speed of the third capacitor C1 is controlled by the sixteenth NMOS tube N16 as the second current source I2.

[0079] In this embodiment, in order to ensure that the pulse width of the output signal OUT is the same as the pulse width of the input pulse signal IN, it is required that the charging speed of the first capacitor C2, the discharging speed of the first capacitor C2, the charging speed of the second capacitor C3 and the discharging speed of the second capacitor C3 are equal, and the sixteenth PMOS transistor P16 (i.e., the first current source I 1 ) and the sixteenth NMOS transistor N16 (i.e., the second current source I 2 ) are equal in magnitude.

[0080] The present invention filters the input pulse width based on a dual-path logic feedforward and feedback control strategy. The working process is as follows: Figure 6 As shown. Assuming that the initial state of the input pulse signal IN is low level "0", the initial state of the output signal OUT is also low level "0", the initial state of the signal VA is high level "1", the initial state of the signal VB is high level "1", and the initial state of the signal VC is low level "0".

[0081] When the rising edge of the input pulse signal IN comes, that is, at T A At the moment, the first delay circuit in the first control circuit and the second delay circuit in the second control circuit delay the rising edge of the input pulse signal IN, and the delay time is t d1 , T BAt this moment, the output signal OUT is still at a low level "0", the level of the signal VA at the output end of the two-input NAND gate NAND1 is at a high level "1", and the signal VB at the output end of the two-input NOR gate NOR1 is reversed from a high level "1" to a low level "0", the seventeenth PMOS tube P2 is turned on, and the third capacitor C1 starts to charge, and the charging current I 1 The sixteenth PMOS tube P16 (i.e., the first current source I 1 )supply:

[0082]

[0083] Among them, μ p represents the mobility of holes, C OX is the gate oxide capacitance per unit area, (W / L) P16 represents the width-to-length ratio of the sixteenth PMOS tube P16, V BP is the gate-source voltage of the sixteenth PMOS tube P16, V THP is the voltage threshold of the sixteenth PMOS tube P16.

[0084] Filter width (i.e. charging time of the third capacitor C1) t FLT1 By the charging current I 1 , the voltage threshold V of the third capacitor C1 and the inverter INV2 TH Decide:

[0085]

[0086] t FLT After time:

[0087]

[0088] In T C At this moment, the voltage VC on the third capacitor C1 has been charged to the voltage threshold V TH The output signal OUT is controlled by the inverters INV2 and INV3 to flip from low level "0" to high level "1", and the signal VA at the output end of the two-input NAND gate NAND1 is flipped from high level "1" to low level "0". The first PMOS tube P9 is turned on, and the VC signal immediately changes from V TH Pull up to the power supply voltage VDD.

[0089] When the falling edge of the input pulse signal IN comes, that is, at T D At the moment, the first delay circuit in the first control circuit and the second delay circuit in the second control circuit delay the falling edge of the input pulse signal IN, and the delay time is t d2 .

[0090] In TE At this moment, the level of the signal VA at the output end of the two-input NAND gate NAND1 is reversed from the low level "0" to the high level "1", the seventeenth NMOS tube N2 is turned on, and the voltage value on the third capacitor C1 starts to discharge from VDD, and the discharge current I 2 The sixteenth NMOS transistor N16 (i.e., the second current source I 2 )supply:

[0091]

[0092] Among them, μ n represents the mobility of holes, C OX is the gate oxide capacitance per unit area, (W / L) N16 represents the width-to-length ratio of the sixteenth NMOS tube N16, V BN is the gate-source voltage of the sixteenth NMOS tube N16, V THN is the voltage threshold of the sixteenth NMOS tube N16.

[0093] Capacitor discharge time t FLT2 By the discharge current I 2 , the voltage threshold V of the third capacitor C1 and the inverter INV2 TH Decide:

[0094]

[0095] t FLT2 After time:

[0096]

[0097] In T F At this moment, the voltage on the third capacitor C1 has been discharged to the voltage threshold V of the subsequent inverter INV2. TH The output signal OUT is controlled by the inverters INV2 and INV3 to flip from high level "1" to low level "0", and the signal VB at the output end of the two-input NOR gate NOR2 is flipped from low level "0" to high level "1". The sixth NMOS tube N9 is turned on, and the VC signal immediately changes from V TH Pull down to the ground signal GND, that is, low level "0".

[0098] In T G After the time, the whole pulse width filter circuit works as described above. A -T F Repeat all the time.

[0099] If a noise signal appears in the input pulse signal IN, such as Figure 7 As shown, T HThe input pulse signal IN at time is positive narrow pulse noise, and the pulse width is t noise1 (t noise1 <t FLT1 ), after a delay time t d1 The signal VB at the output end of the second two-input NOR gate NOR1 is reversed from high level "1" to low level "0", the sixth NMOS tube N9 is turned off, the first PMOS tube P9 is turned on, and VDD passes through the sixteenth PMOS tube P16 (i.e., the first current source I 1 ) and the seventeenth PMOS tube P2 charge the third capacitor C1, and the charging current is I 1 , in T I At the moment, the positive narrow pulse noise ends, and after the delay time t d2 After the third capacitor C1 is charged, the voltage VC on the third capacitor C1 is not charged to the voltage threshold V of the subsequent inverter INV2. TH , the output end of the inverter INV2 does not flip and maintains the original state, so the output signal OUT does not flip and maintains the original state, the signal VB at the output end of the two-input NOR gate NOR1 flips from a low level "0" to a high level "1", the sixth NMOS tube N9 is turned on, the signal VC voltage is pulled down to a low level "0" through the sixth NMOS tube N9, and the positive pulse noise is filtered out; at T J At this moment, the input pulse signal IN is a negative narrow pulse noise with a pulse width of t noise2 (t noise2 <t FLT2 ), after a delay time t d2 After that, the signal VA at the output end of the two-input NAND gate NAND1 is reversed from the low level "0" to the high level "1", the seventeenth PMOS tube P2 is turned off, the seventeenth NMOS tube N2 is turned on, and the third capacitor C1 is connected to the seventeenth NMOS tube N2 and the sixteenth NMOS tube N16 (i.e., the second current source I 2 ) discharges to GND, the discharge current is I 2 , in T I At this moment, the negative pulse noise ends, and after a delay time t d1 After that, the discharge of the third capacitor C1 is completed, because the voltage VC on the third capacitor C1 is not discharged to the voltage threshold V of the subsequent inverter INV2 TH , the output end of the inverter INV2 does not flip and maintains the original state, so the output signal OUT does not flip and maintains the original state, the signal VA at the output end of the two-input NAND gate NAND1 flips from a high level "1" to a low level "0", the first PMOS tube P9 is turned on, and the voltage of the signal VC is pulled up to a high level "1" through the first PMOS tube P9, and the negative pulse noise is filtered out.

[0100] In this embodiment, since the sixteenth PMOS transistor P16 (i.e., the first current source I 1 ) and the sixteenth NMOS transistor N16 (i.e., the second current source I 2 ) are equal in magnitude, the voltage threshold V TH =0.5VDD, so the filter width (i.e. the charging time of the third capacitor C1) is t FLT1 The discharge time t of the third capacitor C1 FLT2 The delay time of the rising edge of the signal by the first delay circuit and the second delay circuit is t d1 , the delay time for the falling edge of the signal is t d2 , and t d1 With t d2 equal, the pulse width of the output signal OUT is equal to the pulse width of the input pulse signal IN and the inverter INV2 has only one voltage threshold V TH , then even if the pulse width of the input pulse signal IN is close to the preset filter width t FLT , the output signal OUT still has the same pulse width as the input pulse signal IN, avoiding the problem of signal distortion caused by the traditional RC filtering circuit.

[0101] Embodiment 2,

[0102] The pulse width filter circuit of this embodiment is as follows Figure 8 As shown, the pulse width filter circuit includes a signal input terminal IN, a first control circuit, a second control circuit, a filter circuit and a signal output terminal OUT. The first control circuit, the second control circuit and the filter circuit are introduced below.

[0103] 1. The circuit structure of the first control circuit is the same as that of the first control circuit in Embodiment 1, and will not be described in detail here.

[0104] 2. The circuit structure of the second control circuit is the same as that of the second control circuit in Embodiment 1, and will not be described in detail here.

[0105] 3. The circuit structure of the filter circuit is as follows:

[0106] The difference between the filter circuit in this embodiment and the filter circuit in Embodiment 1 lies in the different circuit structure of the charge and discharge circuit. The circuit structure of the charge and discharge circuit in this embodiment is introduced below.

[0107] In this embodiment, the charge and discharge circuit includes a first resistor R1, a second resistor R2, a seventeenth PMOS transistor P2, a seventeenth NMOS transistor N2, a third resistor R3, a fourth resistor R4 and a third capacitor C1; the gate of the seventeenth PMOS transistor P2 and the gate of the seventeenth NMOS transistor N2 are connected to form an input end of the charge and discharge circuit; the source of the seventeenth PMOS transistor P2 is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the power supply VDD; the seventeenth PMOS transistor P 2, the drain of the seventeenth NMOS tube N2, and one end of the third capacitor C1 are connected to form the output end of the charge and discharge circuit; the source of the seventeenth NMOS tube N2 is connected to one end of the third resistor R3; the other end of the third resistor R3 is connected to one end of the fourth resistor R4; the other end of the fourth resistor R4 and the other end of the third capacitor C1 are grounded GND respectively; wherein the charging speed of the third capacitor C1 is controlled by the resistance values ​​of the first resistor R1 and the second resistor R2, and the discharging speed of the third capacitor C1 is controlled by the resistance values ​​of the third resistor R3 and the fourth resistor R4.

[0108] In this embodiment, in order to ensure that the pulse width of the output signal OUT is the same as the pulse width of the input pulse signal IN, the current I flowing through the first resistor R1 and the second resistor R2 is 1 The current I flowing through the third resistor R3 and the fourth resistor R4 2 Same size, requirements:

[0109] R 1 +R 2 =R 3 +R 4 Formula 7

[0110] The first resistor R1 and the third resistor R3 are the same type of lightly doped Poly resistors with negative temperature coefficients:

[0111]

[0112] The second resistor R2 and the fourth resistor R4 are the same type of heavily doped Poly resistors with positive temperature coefficients:

[0113]

[0114] In order to ensure the symmetry and matching of the circuit and to ensure that it is not affected by temperature, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are required to be the same and:

[0115] TCR + +TCR - =0 Formula 10

[0116] The working process of the pulse width filter circuit in this embodiment is the same as the working process of the pulse width filter circuit in Embodiment 1, and will not be described in detail here.

[0117] Embodiment 3,

[0118] The pulse width filter circuit of this embodiment is as follows Fig. 9 As shown, the pulse width filter circuit includes a signal input terminal IN, a first control circuit, a second control circuit, a filter circuit and a signal output terminal OUT. The first control circuit, the second control circuit and the filter circuit are introduced below.

[0119] 1. The circuit structure of the first control circuit is the same as that of the first control circuit in Embodiment 1, and will not be described in detail here.

[0120] 2. The circuit structure of the second control circuit is the same as that of the second control circuit in Embodiment 1, and will not be described in detail here.

[0121] 3. The circuit structure of the filter circuit is as follows:

[0122] The filter circuit includes two inverters, a charge and discharge circuit and a Schmitt trigger SCH1; the input end of the first inverter INV1 is the first input end of the filter circuit; the output end of the first inverter INV1 is connected to the input end of the charge and discharge circuit; the output end of the charge and discharge circuit, the second input end of the filter circuit and the third input end of the filter circuit are connected and then connected to the input end of the Schmitt trigger SCH1; the output end of the Schmitt trigger SCH1 is connected to the input end of the second inverter INV3; the output end of the second inverter INV3 is the output end of the filter circuit.

[0123] The difference between the filtering circuit in this embodiment and the filtering circuit in Embodiment 1 is that the filtering circuit in this embodiment replaces the second inverter INV2 in Embodiment 1 with a Schmitt trigger SCH1. The circuit structure of the Schmitt trigger SCH1 is described below. The circuit structure of the inverter and the charging and discharging circuit is detailed in the description in Embodiment 1 and will not be repeated here.

[0124] The Schmitt trigger SCH1 includes a thirteenth PMOS tube P17, a fourteenth PMOS tube P18, a fifteenth PMOS tube P19, a thirteenth NMOS tube N17, a fourteenth NMOS tube N18 and a fifteenth NMOS tube N19;

[0125] The source of the thirteenth PMOS tube P17 is connected to the power supply VDD; the gate of the thirteenth PMOS tube P17, the gate of the fourteenth PMOS tube P18, the gate of the thirteenth NMOS tube N17 and the gate of the fourteenth NMOS tube N18 are connected to form the input end of the Schmitt trigger SCH1; the drain of the thirteenth PMOS tube P17, the source of the fourteenth PMOS tube P18 and the source of the fifteenth PMOS tube P19 are connected, and the drain of the fifteenth PMOS tube P19 is grounded GND. The drain of the fourteenth PMOS tube P18, the gate of the fifteenth PMOS tube P19, the drain of the thirteenth NMOS tube N17 and the gate of the fifteenth NMOS tube N19 are connected to form the output end of the Schmitt trigger SCH1; the drain of the fourteenth NMOS tube N18, the source of the thirteenth NMOS tube N17 and the source of the fifteenth NMOS tube N19 are connected; the source of the fourteenth NMOS tube N18 is grounded GND; the drain of the fifteenth NMOS tube N19 is connected to the power supply VDD.

[0126] In this embodiment, in order to ensure that the pulse width of the output signal OUT is the same as the pulse width of the input pulse signal IN, the sixteenth PMOS transistor P16 (i.e., the first current source I 1 ) and the sixteenth NMOS transistor N16 (i.e., the second current source I 2 ) is equal to the current magnitude and the forward voltage threshold V of the Schmitt trigger SCH1 TH+ =2VDD / 3, the reverse voltage threshold V of Schmitt trigger SCH1 TH- =VDD / 3.

[0127] The present invention filters the input pulse width based on a dual-path logic feedforward and feedback control strategy. The working process is as follows: Fig.10 As shown. Assuming that the initial state of the input pulse signal IN is low level "0", the initial state of the output signal OUT is also low level "0", the initial state of the signal VA is high level "1", the initial state of the signal VB is high level "1", and the initial state of the signal VC is low level "0".

[0128] When the rising edge of the input pulse signal IN comes, that is, at T A At the moment, the first delay circuit in the first control circuit and the second delay circuit in the second control circuit delay the rising edge of the input pulse signal IN, and the delay time is t d1 , in T B At this moment, the output signal OUT is still at a low level "0", the level of the signal VA at the output end of the two-input NAND gate NAND1 is at a high level "1", and the signal VB at the output end of the two-input NOR gate NOR1 is reversed from a high level "1" to a low level "0", the seventeenth PMOS tube P2 is turned on, and the third capacitor C1 starts to charge, and the charging current I1 The sixteenth PMOS tube P16 (i.e., the first current source I 1 )supply:

[0129]

[0130] Among them, μ p represents the mobility of holes, C OX is the gate oxide capacitance per unit area, (W / L) P16 represents the width-to-length ratio of the sixteenth PMOS tube P16, V BP is the gate-source voltage of the sixteenth PMOS tube P16, V THP is the voltage threshold of the sixteenth PMOS tube P16.

[0131] Filter width (i.e. charging time of the third capacitor C1) t FLT1 By the charging current I 1 , the third capacitor C1 and the forward voltage threshold V of the Schmitt trigger SCH1 TH+ Decide:

[0132]

[0133] t FLT After time:

[0134]

[0135] In T C At this moment, the voltage VC on the third capacitor C1 has been charged to the forward voltage threshold V of the subsequent Schmitt trigger SCH1. TH+ The output signal OUT is controlled by the Schmitt trigger SCH1 and the inverter INV3 to flip from low level "0" to high level "1", and the signal VA at the output end of the two-input NAND gate NAND1 is flipped from high level "1" to low level "0". The first PMOS tube P9 is turned on, and the VC signal immediately changes from V TH+ Pull up to the power supply voltage VDD.

[0136] When the falling edge of the input pulse signal IN comes, that is, at T D At the moment, the first delay circuit in the first control circuit and the second delay circuit in the second control circuit delay the falling edge of the input pulse signal IN, and the delay time is t d2 , in T E At this moment, the level of the signal VA at the output end of the two-input NAND gate NAND1 is reversed from the low level "0" to the high level "1", the seventeenth NMOS tube N2 is turned on, and the voltage value on the third capacitor C1 starts to discharge from VDD, and the discharge current I 2 The sixteenth NMOS transistor N16 (i.e., the second current source I2 )supply:

[0137]

[0138] Among them, μ n represents the mobility of holes, C OX is the gate oxide capacitance per unit area, (W / L) N16 represents the width-to-length ratio of the sixteenth NMOS tube N16, V BN is the gate-source voltage of the tenth NMOS tube N16, V THN is the voltage threshold of the sixteenth PMOS tube N16.

[0139] Capacitor discharge time t FLT2 By the discharge current I 2 , the third capacitor C1 and the reverse voltage threshold V of the Schmitt trigger SCH1 TH- Decide:

[0140]

[0141] t FLT2 After time:

[0142]

[0143] In T F At this moment, the voltage on the third capacitor C1 has been discharged to the reverse voltage threshold V of the subsequent Schmitt trigger SCH1. TH -, the output signal OUT is controlled by the Schmitt trigger SCH1 and the inverter INV3 to flip from high level "1" to low level "0", and the signal VB at the output end of the two-input NOR gate NOR2 is flipped from low level "0" to high level "1", the sixth NMOS tube N9 is turned on, and the VC signal immediately changes from V TH- Pull down to the ground signal GND, that is, low level "0".

[0144] In T G After the time, the whole pulse width filter circuit works as described above. A -T F Repeat all the time.

[0145] If a noise signal appears in the input pulse signal IN, such as Fig.11 As shown, T H The input pulse signal IN at time is positive narrow pulse noise, and the pulse width is t noise1 (t noise1 <t FLT1 ), after a delay time t d1After that, the signal VB at the output end of the two-input NOR gate NOR1 is reversed from high level "1" to low level "0", the sixth NMOS tube N9 is turned off, the first PMOS tube P9 is turned on, and VDD passes through the sixteenth PMOS tube P16 (i.e., the first current source I 1 ) and the eleventh PMOS tube P2 charge the third capacitor C1, and the charging current is I 1 , in T I At the moment, the positive narrow pulse noise ends, and after the delay time t d2 After the third capacitor C1 is charged, the voltage VC on the third capacitor C1 is not charged to the positive voltage threshold V of the subsequent Schmitt trigger SCH1. TH+ , the output end of the Schmitt trigger SCH1 does not flip and maintains the original state, so the output signal OUT does not flip and maintains the original state, the signal VB at the output end of the two-input NOR gate NOR1 flips from a low level "0" to a high level "1", the sixth NMOS tube N9 is turned on, and the signal VC voltage is pulled down to a low level "0" through the sixth NMOS tube N9, and the positive pulse noise is filtered out; at T J At this moment, the input pulse signal IN is a negative narrow pulse noise with a pulse width of t noise2 (t noise2 <t FLT2 ), after a delay time t d2 After that, the signal VA at the output end of the two-input NAND gate NAND1 is reversed from the low level "0" to the high level "1", the seventeenth PMOS tube P2 is turned off, the seventeenth NMOS tube N2 is turned on, and the third capacitor C1 is connected to the sixteenth NMOS tube N16 (i.e., the second current source I 2 ) discharges to GND, the discharge current is I 2 , in T K At this moment, the negative pulse noise ends, and after a delay time t d1 After the third capacitor C1 is discharged, the voltage VC on the third capacitor C1 is not discharged to the reverse voltage threshold V of the subsequent Schmitt trigger SCH1. TH- , the output end of the Schmitt trigger SCH1 does not flip and remains in the original state, so the output signal OUT does not flip and remains in the original state, the signal VA at the output end of the two-input NAND gate NAND1 flips from a high level "1" to a low level "0", the first PMOS tube P9 is turned on, and the voltage of the signal VC is pulled up to a high level "1" through the first PMOS tube P9, and the negative pulse noise is filtered out.

[0146] In this embodiment, since the sixteenth PMOS transistor P16 (i.e., the first current source I 1 ) and the sixteenth NMOS transistor N16 (i.e., the second current source I 2) is equal to the current magnitude, the forward voltage threshold V TH+ =2VDD / 3, the reverse voltage threshold V of Schmitt trigger SCH1 TH- =VDD / 3, so the filter width (i.e. the charging time of the third capacitor C1) is t FLT1 The discharge time t of the third capacitor C1 FLT2 The delay time of the rising edge of the signal by the first delay circuit and the second delay circuit is t d1 , the delay time for the falling edge of the signal is t d2 , and t d1 With t d2 If the pulse widths of the output signal OUT and the input pulse signal IN are equal, the problem of signal distortion caused by the traditional RC filtering circuit is avoided.

[0147] Embodiment 4,

[0148] The pulse width filter circuit of this embodiment is as follows Fig.12 As shown, the pulse width filter circuit includes a signal input terminal IN, a first control circuit, a second control circuit, a filter circuit and a signal output terminal OUT. The first control circuit, the second control circuit and the filter circuit are introduced below.

[0149] 1. The circuit structure of the first control circuit is the same as that of the first control circuit in Embodiment 1, and will not be described in detail here.

[0150] 2. The circuit structure of the second control circuit is the same as that of the second control circuit in Embodiment 1, and will not be described in detail here.

[0151] 3. The difference between the filter circuit in this embodiment and the filter circuit in Embodiment 3 is that the circuit structure of the charge and discharge circuit is different, and the circuit structure of the charge and discharge circuit in this embodiment is the same as the circuit structure of the charge and discharge circuit in Embodiment 2, which will not be described here.

[0152] The working process of the pulse width filter circuit in this embodiment is the same as the working process of the pulse width filter circuit in Embodiment 3, and will not be described in detail here.

[0153] Please refer to Fig.13 , which shows a schematic flow chart of a pulse width filtering method for an input pulse signal provided by the present invention, and the pulse width filtering method is applied to Figure 4-12 The pulse width filter circuit shown includes:

[0154] Step 1301, receiving an input pulse signal.

[0155] Step 1302: If the pulse width of the input pulse signal is smaller than the filter width of the pulse width filter circuit, the input pulse signal is filtered out and an output signal is output.

[0156] If the pulse width of the input pulse signal IN is smaller than the preset filtering width, the output signal OUT remains unchanged, that is, the input pulse signal IN is filtered out at this time.

[0157] Step 1303, if the pulse width of the input pulse signal is greater than or equal to the filter width of the pulse width filter circuit, retain the input pulse signal and output an output signal, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width.

[0158] If the pulse width of the input pulse signal IN is greater than or equal to the preset filter width, the first control circuit generates a signal VA when the capacitor C1 is charged to the point where the output signal OUT is reversed, and ends the charging process of the third capacitor C1 through the signal VA. The second control circuit generates a signal VB when the third capacitor C1 is discharged to the point where the output signal OUT is reversed, and ends the discharging process of the third capacitor C1 through the signal VB. Finally, the output signal OUT has the same pulse width as the input pulse signal IN. For the circuit implementation principle, please refer to Fig.14 .

[0159] The present invention adopts a dual-path logic feedforward and feedback control strategy to filter the pulse width of the input stage. The present invention is composed of a series of simple logic function circuits such as NAND gates and OR gates. It has a simple structure and does not require the introduction of switching devices. It has the characteristics of low distortion, small transmission delay, small footprint and easy integration, and more reliably realizes low-distortion filtering of the pulse width of the input stage.

[0160] The above description is only a preferred embodiment of the present invention and is not limited to the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pulse width filter circuit for an input pulse signal, characterized in that: The pulse width filter circuit comprises a signal input terminal, a first control circuit, a second control circuit, a filter circuit and a signal output terminal; The signal input end is connected to the first input end of the first control circuit, the first input end of the second control circuit and the first input end of the filter circuit respectively; the signal output end is connected to the second input end of the first control circuit, the second input end of the second control circuit and the output end of the filter circuit respectively; the output end of the first control circuit is connected to the second input end of the filter circuit; the output end of the second control circuit is connected to the third input end of the filter circuit; The first control circuit includes a first delay circuit, a two-input NAND gate and a first P-channel metal oxide semiconductor field effect PMOS tube; the first input end of the first delay circuit is the first input end of the first control circuit; the output end of the first delay circuit is connected to the first input end of the two-input NAND gate; the second input end of the two-input NAND gate is the second input end of the first control circuit; the output end of the two-input NAND gate is connected to the gate of the first PMOS tube; the source of the first PMOS tube is connected to a power supply; the drain of the first PMOS tube is the output end of the first control circuit; The second control circuit includes a second delay circuit, a two-input NOR gate and a sixth NMOS tube; The first input end of the second delay circuit is the first input end of the second control circuit; the output end of the second delay circuit is connected to the first input end of the two-input NOR gate; the second input end of the two-input NOR gate is the second input end of the second control circuit; the output end of the two-input NOR gate is connected to the gate of the sixth NMOS tube; the source of the sixth NMOS tube is grounded; the drain of the sixth NMOS tube is the output end of the second control circuit; The filter circuit includes three inverters and a charge-discharge circuit; the input end of the first inverter is the first input end of the filter circuit; the output end of the first inverter is connected to the input end of the charge-discharge circuit; the output end of the charge-discharge circuit, the second input end of the filter circuit and the third input end of the filter circuit are connected and then connected to the input end of the second inverter; the output end of the second inverter is connected to the input end of the third inverter; the output end of the third inverter is the output end of the filter circuit, or, the filter circuit includes two inverters, a charge-discharge circuit and a Schmitt trigger; the input end of the first inverter is the first input end of the filter circuit; the output end of the first inverter is connected to the input end of the charge-discharge circuit; the output end of the charge-discharge circuit, the second input end of the filter circuit and the third input end of the filter circuit are connected and then connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the input end of the second inverter; the output end of the second inverter is the output end of the filter circuit; The inverter comprises a twelfth PMOS tube and a twelfth NMOS tube; the source of the twelfth PMOS tube is connected to a power supply; the gate of the twelfth PMOS tube is connected to the gate of the twelfth NMOS tube to form the input end of the inverter; the source of the twelfth NMOS tube is grounded; the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube to form the output end of the inverter; The Schmitt trigger comprises a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube; the source of the thirteenth PMOS tube is connected to a power supply; the gate of the thirteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube are connected to form the input end of the Schmitt trigger; the drain of the thirteenth PMOS tube, the source of the fourteenth PMOS tube and the source of the fifteenth PMOS tube are connected, the drain of the fifteenth PMOS tube is grounded, the drain of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube, the drain of the thirteenth NMOS tube and the gate of the fifteenth NMOS tube are connected to form the output end of the Schmitt trigger; the drain of the fourteenth NMOS tube, the source of the thirteenth NMOS tube and the source of the fifteenth NMOS tube are connected; the source of the fourteenth NMOS tube is grounded; the drain of the fifteenth NMOS tube is connected to a power supply; When the pulse width of the input pulse signal inputted from the signal input terminal is smaller than the filter width of the pulse width filter circuit, the filter circuit filters out the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output terminal for output; When the pulse width of the input pulse signal input into the signal input end is greater than or equal to the filter width of the pulse width filter circuit, the filter circuit retains the input pulse signal under the control of the first control circuit and the second control circuit, and sends the obtained output signal to the signal output end for output, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width.

2. The circuit according to claim 1, characterized in that The first delay circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first N-channel metal oxide semiconductor field effect NMOS tube, a second NMOS tube, a third NMOS tube and a first capacitor; the source of the second PMOS tube is connected to a power supply; the gate of the second PMOS tube is connected to a first bias level; the drain of the second PMOS tube is connected to the source of the third PMOS tube; the gate of the third PMOS tube is connected to the gate of the first NMOS tube to form an input end of the first delay circuit; the drain of the third PMOS tube, the drain of the first NMOS tube, one end of the first capacitor, the first The drain of the fourth PMOS tube is connected to the drain of the third NMOS tube; the source of the first NMOS tube is connected to the drain of the second NMOS tube; the gate of the second NMOS tube is connected to the second bias level; the source of the second NMOS tube and the other end of the first capacitor are grounded; the source of the fourth PMOS tube is connected to the power supply; the source of the third NMOS tube is grounded; the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube to form the output end of the first delay circuit; wherein the charging speed of the first capacitor is controlled by the second PMOS tube, and the discharging speed of the first capacitor is controlled by the second NMOS tube; The two-input NAND gate comprises a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the source of the fifth PMOS tube and the source of the sixth PMOS tube are respectively connected to a power supply; the drain of the fifth PMOS tube, the drain of the sixth PMOS tube and the drain of the fourth NMOS tube are connected to form the output end of the two-input NAND gate; the gate of the fifth PMOS tube and the gate of the fourth NMOS tube are connected to form the second input end of the two-input NAND gate; the gate of the sixth PMOS tube and the gate of the fifth NMOS tube are connected to form the first input end of the two-input NAND gate; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the source of the fifth NMOS tube is grounded.

3. The circuit according to claim 2, characterized in that The second delay circuit includes a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a second capacitor; the source of the seventh PMOS tube is connected to a power supply; the gate of the seventh PMOS tube is connected to a first bias level; the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the gate of the eighth PMOS tube and the gate of the seventh NMOS tube are connected to form an input end of the second delay circuit; the drain of the eighth PMOS tube, the drain of the seventh NMOS tube, one end of the second capacitor, and the gate of the ninth PMOS tube are connected to form an input end of the second delay circuit; the drain of the eighth PMOS tube, the drain of the seventh NMOS tube, one end of the second capacitor, and the gate of the ninth PMOS tube are connected to form an input end of the second delay circuit; The drain is connected to the drain of the ninth NMOS tube; the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube; the gate of the eighth NMOS tube is connected to the second bias level; the source of the eighth NMOS tube and the other end of the second capacitor are grounded; the source of the ninth PMOS tube is connected to the power supply; the source of the ninth NMOS tube is grounded; the drain of the ninth PMOS tube and the drain of the ninth NMOS tube are connected to form the output end of the second delay circuit; wherein the charging speed of the second capacitor is controlled by the seventh PMOS tube, and the discharging speed of the second capacitor is controlled by the eighth NMOS tube; The two-input NOR gate includes a tenth PMOS tube, an eleventh PMOS tube, a tenth NMOS tube and an eleventh NMOS tube; the source of the tenth PMOS tube is connected to a power supply; the gate of the tenth PMOS tube and the gate of the eleventh NMOS tube are connected to form a first input end of the two-input NOR gate; the drain of the tenth PMOS tube and the source of the eleventh PMOS tube are connected; the gate of the eleventh PMOS tube and the gate of the tenth NMOS tube are connected to form a second input end of the two-input NOR gate; the drain of the eleventh PMOS tube, the drain of the tenth NMOS tube and the drain of the eleventh NMOS tube are connected to form an output end of the two-input NOR gate; the source of the tenth NMOS tube and the source of the eleventh NMOS tube are grounded respectively.

4. The circuit according to claim 3, characterized in that A charging speed of the first capacitor, a discharging speed of the first capacitor, a charging speed of the second capacitor, and a discharging speed of the second capacitor are equal.

5. The circuit according to claim 1, characterized in that The charge and discharge circuit comprises a sixteenth PMOS tube, a seventeenth PMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and a capacitor; the gate of the seventeenth PMOS tube and the gate of the seventeenth NMOS tube are connected to form the input end of the charge and discharge circuit; the source of the seventeenth PMOS tube is connected to the drain of the sixteenth PMOS tube; the source of the sixteenth PMOS tube is connected to a power supply; the gate of the sixteenth PMOS tube is connected to a first bias level; the drain of the seventeenth PMOS tube, the drain of the seventeenth NMOS tube and one end of the third capacitor are connected to form the output end of the charge and discharge circuit; the source of the seventeenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the source of the sixteenth NMOS tube and the other end of the third capacitor are grounded respectively, and the gate of the sixteenth NMOS tube is connected to a second bias level; wherein the charging speed of the third capacitor is controlled by the sixteenth PMOS tube as the first current source, and the discharging speed of the capacitor is controlled by the sixteenth NMOS tube as the second current source; or, The charge and discharge circuit includes a first resistor, a second resistor, a seventeenth PMOS tube, a seventeenth NMOS tube, a third resistor, a fourth resistor and a third capacitor; the gate of the seventeenth PMOS tube and the gate of the seventeenth NMOS tube are connected to form the input end of the charge and discharge circuit; the source of the seventeenth PMOS tube is connected to one end of the second resistor; the other end of the second resistor is connected to one end of the first resistor; the other end of the first resistor is connected to a power supply; the drain of the seventeenth PMOS tube, the drain of the seventeenth NMOS tube and one end of the third capacitor are connected to form the output end of the charge and discharge circuit; the source of the seventeenth NMOS tube is connected to one end of the third resistor; the other end of the third resistor is connected to one end of the fourth resistor; the other end of the fourth resistor and the other end of the capacitor are grounded respectively; wherein the charging speed of the third capacitor is controlled by the resistance values ​​of the first resistor and the second resistor, and the discharging speed of the third capacitor is controlled by the resistance values ​​of the third resistor and the fourth resistor.

6. The circuit according to claim 5, characterized in that The current magnitudes of the first current source and the second current source in the charge-discharge circuit are equal; When the filter circuit further includes three inverters, the voltage threshold of the second inverter is half of the voltage value of the power supply; When the filtering circuit further includes two inverters and a Schmitt trigger, the forward voltage threshold of the Schmitt trigger is two-thirds of the voltage value of the power supply, and the reverse voltage threshold of the Schmitt trigger is one-third of the voltage value of the power supply.

7. The circuit according to claim 5, characterized in that The first resistor, the second resistor, the third resistor and the fourth resistor in the charge-discharge circuit have equal resistance values, the first resistor and the third resistor are similar lightly doped Poly resistors with negative temperature coefficients, the second resistor and the fourth resistor are similar heavily doped Poly resistors with positive temperature coefficients, and the sum of the negative temperature coefficients of the first resistor and the third resistor and the positive temperature coefficients of the second resistor and the fourth resistor is 0; When the filter circuit further includes three inverters, the voltage threshold of the second inverter is half of the voltage value of the power supply; When the filtering circuit further includes two inverters and a Schmitt trigger, the forward voltage threshold of the Schmitt trigger is two-thirds of the voltage value of the power supply, and the reverse voltage threshold of the Schmitt trigger is one-third of the voltage value of the power supply.

8. A pulse width filtering method for an input pulse signal, characterized in that: Applied to the pulse width filter circuit according to any one of claims 1 to 7, the method comprises: receiving an input pulse signal; If the pulse width of the input pulse signal is smaller than the filter width of the pulse width filter circuit, the input pulse signal is filtered out and an output signal is output; If the pulse width of the input pulse signal is greater than or equal to the filter width of the pulse width filter circuit, the input pulse signal is retained and an output signal is output, and the delay time between the output signal and the input pulse signal is greater than or equal to the filter width.

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