A sawtooth wave generating circuit and buck-boost converter

Abstract

The present invention discloses a sawtooth wave generating circuit, including a current mirror module, a clock generating module, a buck sawtooth wave module and a boost sawtooth wave module, wherein the clock generating module includes a first charge and discharge unit and a comparator unit, the buck sawtooth wave module includes a second charge and discharge unit, and the boost sawtooth wave module includes a third charge and discharge unit, a fourth charge and discharge unit and a control unit; wherein the first to fourth charge and discharge units have the same circuit structure. Correspondingly, the present invention also discloses a buck-boost converter. The embodiment of the present invention can realize flexible setting of sawtooth wave amplitude, thereby improving the anti-interference ability of the buck-boost converter, and can realize that the peak value of the buck sawtooth wave and the valley value of the boost sawtooth wave are equal, thereby ensuring smooth switching of the working mode of the buck-boost converter, thereby improving the efficiency of the buck-boost converter and the stability of the output voltage.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a sawtooth wave generating circuit and a buck-boost converter. Background Art

[0002] BUCK-BOOST converter, also known as step-up / step-down transformer, is a DC converter whose output voltage can be higher, lower or equal to the input voltage. Due to the dual-mode control mode of BUCK-BOOST converter, it works in BUCK mode or BOOST mode within one clock cycle, and the BUCK mode and BOOST mode will not work at the same time, that is, there is no situation where the buck switch tube and the boost switch tube are switched at the same time, which is more efficient than other control modes. Therefore, BUCK-BOOST converters generally use dual-mode control.

[0003] The dual-mode control method of the BUCK-BOOST converter generally has the following two control strategies: first, the dual modulation signal-single sawtooth control strategy; second, the single modulation signal-dual sawtooth control strategy. The modulation signal of the buck switch tube and the boost switch tube of the BUCK-BOOST converter with the single modulation signal-dual sawtooth control strategy is the same, both from the output of the same error amplifier, and the sawtooth signal of the boost switch tube is the sawtooth signal of the buck switch tube superimposed with a DC bias voltage, in order to ensure that only one sawtooth wave is interleaved with the modulation signal at any time, that is, only one switch tube is controlled.

[0004] Figure 1 The figure shows a buck sawtooth wave generating circuit provided by the prior art. The current source 7202 provides a charging current I1 to charge the capacitor C11 according to the input voltage Vin. The control circuit 7204 includes a switch SW1 connected in parallel with the capacitor C11. The frequency Clk switches the switch SW1 to control the charging and discharging of the capacitor C11. When the clock Clk is at a low level, the capacitor C11 is charged by the current I1, and the SAWbuck voltage gradually increases until the Clk level is at a high level. The capacitor is discharged quickly and the SAWbuck voltage is restored to Vbe. Thereafter, when Clk is at a low level, it is charged again. The previous process is repeated to generate a buck sawtooth wave signal SAWbuck. The limiting circuit 7206 is used to fix the valley value of the buck sawtooth wave signal SAWbuck at Vbe. Figure 2The figure shows a boost sawtooth wave generating circuit provided by the prior art, in which the current source 7210 provides a charging current I2 to charge the capacitor C22 according to the input voltage Vin, and the control circuit 7212 includes a switch SW2 connected in parallel with the capacitor C22, and the frequency Clk switches the switch SW2 to control the charging and discharging of the capacitor C22. When the clock Clk is at a low level, the capacitor C22 is charged by the current I2, and the SAWboost voltage gradually increases until the Clk level is at a high level, the capacitor C22 is quickly discharged, and the SAWboost voltage is restored to 2Vbe, and then it is charged again when Clk is at a low level, and the previous process is repeated to generate a boost sawtooth wave signal SAWboost, and the limiting circuit 7214 is used to fix the valley value of the charging voltage V1 at 2Vbe. On the one hand, the amplitude of the buck sawtooth wave and the boost sawtooth wave is Vbe, so the noise resistance is poor; on the other hand, in order to make the amplitude of the two sawtooth waves the same and equal to Vbe, to ensure that the peak value of SAWbuck is equal to the valley value of SAWboost, and to achieve smooth switching, the sawtooth wave needs a precise rising Vbe voltage during the low level time of the clock Clk, which is difficult to achieve in practice. If smooth switching cannot be achieved, the two sawtooth waves will intersect or separate: when the sawtooth waves intersect, two modes work simultaneously in one clock cycle, and both switch tubes are switched once, so the switching loss is large and the efficiency is low; when the double sawtooths are separated, the switching time between the BUCK mode and the BOOST mode is long, the output voltage oscillates greatly, and the output voltage is unstable. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a sawtooth wave generating circuit and a buck-boost converter, which can realize flexible setting of the sawtooth wave amplitude, thereby improving the anti-interference ability of the buck-boost converter, ensuring that the peak value of the buck sawtooth wave and the valley value of the boost sawtooth wave are equal, and realizing smooth switching of the buck-boost converter working mode, thereby improving the efficiency of the buck-boost converter and the stability of the output voltage.

[0006] In order to solve the above technical problems, the present invention provides a sawtooth wave generating circuit, including a current mirror module, a clock generating module, a buck sawtooth wave module and a boost sawtooth wave module, wherein the clock generating module includes a first charge and discharge unit and a comparator unit, the buck sawtooth wave module includes a second charge and discharge unit, and the boost sawtooth wave module includes a third charge and discharge unit, a fourth charge and discharge unit and a control unit; wherein the first to fourth charge and discharge units have the same circuit structure;

[0007] The current mirror module is used to provide a charging current to the first to fourth charging and discharging units to charge the first to fourth charging and discharging units;

[0008] The first charge and discharge unit is used to generate a sawtooth wave with a target amplitude value according to the charging current; the comparator unit is used to generate a clock signal according to the sawtooth wave with the target amplitude value, and send the clock signal to the control unit and the second charge and discharge unit;

[0009] The second charge and discharge unit performs charging and discharging according to the clock signal and outputs a charging voltage;

[0010] The control unit is used to generate a control signal according to the clock signal to control the third charge and discharge unit and the fourth charge and discharge unit to discharge once every two consecutive clock cycles, to control the third charge and discharge unit and the fourth charge and discharge unit to start charging when the other party completes a charging clock cycle and enters another charging clock cycle, and to control the third charge and discharge unit and the fourth charge and discharge unit to output a charging voltage when they complete a charging clock cycle and enter another charging clock cycle.

[0011] Further, the first to fourth charge and discharge units each include a control signal input terminal, a ground terminal, a charging terminal and a charging voltage output terminal, and the comparator unit includes a voltage signal input terminal, a reference signal input terminal and a clock signal output terminal;

[0012] The charging end of the first charge and discharge unit is connected to the current mirror module, the charging voltage output end of the first discharge unit is connected to the voltage signal input end of the comparator unit, the reference signal input end of the comparator unit is connected to a reference voltage source, and the clock signal output end of the comparator unit is connected to the control signal input end of the first charge and discharge unit.

[0013] Further, the comparator unit includes a comparator and an inverter;

[0014] The non-inverting input terminal of the comparator is connected to the reference signal input terminal, the inverting input terminal of the comparator is connected to the voltage signal input terminal, the output terminal of the comparator is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the clock signal output terminal.

[0015] Furthermore, the step-down sawtooth wave module also includes a step-down sawtooth wave output end, the charging end of the second charge and discharge unit is connected to the current mirror module, the control signal input end of the second charge and discharge unit is connected to the clock signal output end of the comparator unit, and the charging voltage output end of the second charge and discharge unit is connected to the step-down sawtooth wave output end.

[0016] Furthermore, the boost sawtooth wave module also includes a boost sawtooth wave output terminal, the control unit includes a logic control circuit, a first switch tube and a second switch tube, and the logic control circuit includes a clock signal input terminal, a first charge and discharge control output terminal, a second charge and discharge control output terminal, a first switch control output terminal and a second switch control output terminal;

[0017] The charging end of the third charge and discharge unit and the charging end of the fourth charge and discharge unit are connected to the current mirror module, the first charge and discharge control output end is connected to the control signal input end of the third charge and discharge unit, the charging voltage output end of the third charge and discharge unit is connected to the first end of the first switch tube, the control end of the first switch tube is connected to the first switch control output end of the logic control circuit, the second charge and discharge control output end is connected to the control signal input end of the fourth charge and discharge unit, the charging voltage output end of the fourth charge and discharge unit is connected to the first end of the second switch tube, the control end of the second switch tube is connected to the second switch control output end, and the second end of the second switch tube and the second end of the first switch tube are connected to the boost sawtooth wave output end.

[0018] Furthermore, the logic control circuit further includes a D flip-flop, a first AND gate and a second AND gate;

[0019] The clock input terminal of the D flip-flop is connected to the clock signal input terminal, the data input terminal of the D flip-flop is connected to the second output terminal of the D flip-flop, the first output terminal of the D flip-flop is respectively connected to the second switch control output terminal and the first input terminal of the first AND gate, the clock input terminal of the D flip-flop is respectively connected to the second input terminal of the first AND gate and the second input terminal of the second AND gate, the output terminal of the first AND gate is connected to the first charge and discharge control output terminal, the second output terminal of the D flip-flop is respectively connected to the first input terminal of the second AND gate and the first switch control output terminal, and the output terminal of the second AND gate is connected to the second charge and discharge control output terminal.

[0020] Furthermore, the first to fourth charge-discharge units all include a discharge switch tube and a capacitor;

[0021] The first end of the discharge switch tube is connected to the charging end and the first end of the capacitor respectively, the first end of the capacitor is connected to the charging voltage output end, the control end of the discharge switch tube is connected to the control signal input end, and the second end of the discharge switch tube and the second end of the capacitor are connected to the ground end.

[0022] Preferably, the discharge switch tube is an N-channel MOS tube, the drain of the N-channel MOS tube is the first end of the discharge switch tube, the source of the N-channel MOS tube is the second end of the discharge switch tube, and the gate of the N-channel MOS tube is the control end of the discharge switch tube.

[0023] Further, the current mirror module includes a current input terminal, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube and a seventh switch tube;

[0024] The current input end is connected to a current source, the second end of the third switch tube is connected to the current input end, the control end of the third switch tube, the second end of the third switch tube, the control end of the fourth switch tube, the control end of the fifth switch tube and the control end of the sixth switch tube are all connected to the control end of the seventh switch tube, the first end of the third switch tube, the first end of the fourth switch tube, the first end of the fifth switch tube and the first end of the sixth switch tube are all connected to the first end of the seventh switch tube, the first end of the seventh switch tube is connected to a power supply, and the second ends of the fourth to seventh switch tubes are respectively connected to the charging ends of the first to fourth charge and discharge units in a one-to-one correspondence.

[0025] Correspondingly, the present invention also provides a buck-boost converter, which includes the sawtooth wave generating circuit as described above.

[0026] The sawtooth wave generating circuit and the buck-boost converter provided by the present invention, the current mirror module provides charging current to the first to fourth charging and discharging units, the first charging and discharging unit generates a sawtooth wave with a target amplitude value according to the charging current, the comparator unit generates a clock signal according to the sawtooth wave with the target amplitude value, the second charging and discharging unit charges and discharges according to the clock signal, and outputs a charging voltage; the control unit generates a control signal according to the clock signal to control the third charging and discharging unit and the fourth charging and discharging unit to discharge once every two consecutive charging clock cycles, to control the third charging and discharging unit and the fourth charging and discharging unit to start charging when the other party completes a charging clock cycle and enters another charging clock cycle, to control the third charging and discharging unit and the fourth charging and discharging unit to output a charging voltage when they complete a charging clock cycle and enter another charging clock cycle. Since the first to fourth charge and discharge units have the same circuit structure and are controlled by the same clock signal, when the charging current is the same, the charging voltage output by the second charge and discharge unit is also a buck sawtooth wave with a target amplitude value; and since the third charge and discharge unit and the fourth charge and discharge unit both start charging when the other party completes a charging clock cycle and enters another charging clock cycle, both output charging voltages when completing a charging clock cycle and entering another charging clock cycle, and discharge once every two consecutive charging clock cycles, a boost sawtooth wave with a valley value equal to the peak value of the buck sawtooth wave and a target amplitude value is generated. The target amplitude value can be flexibly set by changing the reference voltage source of the comparator unit, thereby improving the anti-interference ability of the buck-boost converter; it can achieve that the peak value of the buck sawtooth wave is equal to the valley value of the boost sawtooth wave, ensuring the smooth switching of the working mode of the buck-boost converter, thereby improving the efficiency of the buck-boost converter and the stability of the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a circuit schematic diagram of a step-down sawtooth wave generating circuit provided by the prior art;

[0028] Figure 2 It is a circuit schematic diagram of a boost sawtooth wave generating circuit provided by the prior art;

[0029] Figure 3 is a circuit block diagram of a sawtooth wave generating circuit provided by the present invention;

[0030] Figure 4 is a circuit schematic diagram of an embodiment of a sawtooth wave generating circuit provided by the present invention;

[0031] Figure 5 It is a circuit principle diagram of an embodiment of a logic control circuit of a sawtooth wave generating circuit provided by the present invention;

[0032] Figure 6It is a logic control timing diagram and a sawtooth wave waveform diagram of a logic control circuit of a sawtooth wave generating circuit provided by the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. According to the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] See also Figure 3 , is a circuit block diagram of the sawtooth wave generating circuit provided by the present invention.

[0035] The embodiment of the present invention provides a sawtooth wave generating circuit, comprising a current mirror module 1, a clock generating module 2, a buck sawtooth wave module 3 and a boost sawtooth wave module 4, wherein the clock generating module 2 comprises a first charge and discharge unit 21 and a comparator unit 22, the buck sawtooth wave module 3 comprises a second charge and discharge unit 31, and the boost sawtooth wave module 4 comprises a third charge and discharge unit 41, a fourth charge and discharge unit 42 and a control unit 43; wherein the first to fourth charge and discharge units (21, 31, 41, 42) have the same circuit structure;

[0036] A current mirror module 1, used for providing a charging current to the first to fourth charging and discharging units (21, 31, 41, 42) to charge the first to fourth charging and discharging units (21, 31, 41, 42);

[0037] The first charge and discharge unit 21 is used to generate a sawtooth wave with a target amplitude value according to the charging current; the comparator unit 22 is used to generate a clock signal according to the sawtooth wave with the target amplitude value, and send the clock signal to the control unit 43 and the second charge and discharge unit 31;

[0038] The second charge and discharge unit 31 performs charging and discharging according to the clock signal and outputs a charging voltage;

[0039] The control unit 43 is used to generate a control signal according to the clock signal to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge once every two consecutive charging clock cycles, to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to start charging when the other party completes a charging clock cycle and enters another charging clock cycle, and to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to output a charging voltage when they complete a charging clock cycle and enter another charging clock cycle.

[0040] In a specific implementation, the current mirror module 1 provides a charging current to the first to fourth charge and discharge units (21, 31, 41, 42), the first charge and discharge unit 21 generates a sawtooth wave with a target amplitude value according to the charging current, the comparator unit 22 generates a clock signal according to the sawtooth wave with the target amplitude value, and sends the clock signal to the control unit 43 and the second charge and discharge unit 31, the second charge and discharge unit 31 charges and discharges according to the clock signal, and outputs a charging voltage; the control unit 43 generates a control signal according to the clock signal to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge once every two consecutive charging clock cycles, so as to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to start charging when the other party completes a charging clock cycle and enters another charging clock cycle, so as to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to output a charging voltage when they complete a charging clock cycle and enter another charging clock cycle. Since the first to fourth charge and discharge units (21, 31, 41, 42) have the same circuit structure and are controlled by the same clock signal, when the charging current Ic0=Ic1=Ic2=Ic4, the charging voltage output by the second charge and discharge unit 31 is also a buck sawtooth wave with a target amplitude value; and since the third charge and discharge unit 41 and the fourth charge and discharge unit 42 both output charging voltages when completing a charging clock cycle and entering another charging clock cycle, and discharge once every two consecutive charging clock cycles, a boost sawtooth wave with a valley value equal to the peak value of the buck sawtooth wave and the same target amplitude value is generated. Since the boost sawtooth wave and the buck sawtooth wave are generated under the control of the same clock signal, the phase shifts of the two sawtooth wave signals can be guaranteed to be the same. The target amplitude value can be flexibly set by changing the reference voltage source of the comparator unit 22, thereby improving the anti-interference ability of the buck-boost converter; it can achieve that the peak value of the buck sawtooth wave is equal to the valley value of the boost sawtooth wave, ensuring the smooth switching of the working mode of the buck-boost converter, thereby improving the efficiency of the buck-boost converter and the stability of the output voltage.

[0041] Further, the first to fourth charge and discharge units (21, 31, 41, 42) each include a control signal input terminal (c1, c2, c3, c4), a ground terminal (b1, b2, b3, b4), a charging terminal (a1, a2, a3, a4) and a charging voltage output terminal (d1, d2, d3, d4), and the comparator unit 22 includes a voltage signal input terminal VI, a reference signal input terminal VR and a clock signal output terminal CLK;

[0042] The charging terminal a1 of the first charge and discharge unit 21 is connected to the current mirror module 1, the charging voltage output terminal d1 of the first discharge unit 21 is connected to the voltage signal input terminal VI of the comparator unit 22, the reference signal input terminal VR of the comparator unit 22 is connected to the reference voltage source Vsaw, and the clock signal output terminal CLK of the comparator unit 22 is connected to the control signal input terminal c1 of the first charge and discharge unit 21.

[0043] In a specific implementation, the current mirror module 1 provides a charging current Ic0 to the charging terminal a1 of the first charging and discharging unit 21, and the first charging and discharging unit 21 is charged. When the voltage output by the charging voltage output terminal d1 of the first charging and discharging unit 21 is greater than the reference voltage Vsaw connected to the reference signal input terminal VR of the comparator unit 22, the comparator unit 22 flips, and the output clock signal controls the first charging and discharging unit 21 to discharge quickly. When the voltage output by the charging voltage output terminal d1 of the first charging and discharging unit 21 is less than the reference voltage Vsaw connected to the reference signal input terminal VR of the comparator unit 22, the comparator unit 22 flips again, and the output clock signal controls the charging of the first charging and discharging unit 21. The previous process is repeated, and the first charging and discharging unit 21 outputs a sawtooth wave with an amplitude value equal to Vsaw. At the same time, the comparator unit 22 outputs a clock signal through the clock signal output terminal CLK.

[0044] It should be noted that the sawtooth wave signal generated by the charging and discharging process of the first charge and discharge unit 21 is compared with a reference voltage Vsaw to generate a clock signal, so that the amplitude values ​​of the boost sawtooth wave and the buck sawtooth wave in the embodiment of the present invention are the reference voltage of the comparator unit, and thus the amplitudes of the boost sawtooth wave and the buck sawtooth wave can be flexibly set.

[0045] See also Figure 4 , is a circuit diagram of an embodiment of a sawtooth wave generating circuit provided by the present invention. Figure 3 and Figure 4 As shown, the comparator unit 22 includes a comparator U1 and an inverter U2;

[0046] The non-inverting input terminal of the comparator U1 is connected to the reference signal input terminal VR, the inverting input terminal of the comparator U1 is connected to the voltage signal input terminal VI, the output terminal of the comparator U1 is connected to the input terminal of the inverter U2, and the output terminal of the inverter U2 is connected to the clock signal output terminal CLK.

[0047] Furthermore, the first to fourth charge and discharge units (21, 31, 41, 42) also include discharge switch tubes (MN1, MN3, MN7, MN8) and capacitors (CO, C1, C2, C3);

[0048] Here, the first charge and discharge unit 21 is taken as an example for description. The first end of the discharge switch tube MN1 is connected to the charging end a1 and the first end of the capacitor CO respectively, the first end of the capacitor CO is connected to the charging voltage output end d1, the control end of the discharge switch tube MN1 is connected to the control signal input end c1, and the second end of the discharge switch tube MN1 and the second end of the capacitor C0 are connected to the ground end b1.

[0049] It should be noted that the clock generation module 2 composed of the first charge and discharge unit 21 and the comparator unit 22 uses the relaxation oscillator principle. When the clock signal outputted from the output end of the inverter U2 is at a low level, the capacitor C0 is charged by the current Ic0, and the voltage across the capacitor CO begins to rise. When it rises to equal Vsaw, the voltage at the output end of the inverter U2 turns to a high level, and then the switch tube MN1 is turned on to quickly discharge the capacitor CO. When the voltage of the capacitor CO drops below Vsaw, the voltage at the output end of the inverter U2 turns to a low level again, and the previous process is repeated to form a clock signal. The high level time of the voltage at the output end of the inverter U2 is determined by the delay of the comparator U1 and the time when the voltage on the capacitor C0 drops below Vsaw. The capacitance of the second charge and discharge unit 31 matches that of the first charge and discharge unit 21, and the current also matches, that is, C0=C1, Ic0=Ic1, and the clock signal also matches, so the voltage outputted by the second charge and discharge unit 31 is a sawtooth wave with an amplitude value equal to Vsaw.

[0050] Preferably, the discharge switch tube (MN1, MN3, MN7, MN8) is an N-channel MOS tube, the drain of the N-channel MOS tube is the first end of the discharge switch tube (MN1, MN3, MN7, MN8), the source of the N-channel MOS tube is the second end of the discharge switch tube (MN1, MN3, MN7, MN8), and the gate of the N-channel MOS tube is the control end of the discharge switch tube (MN1, MN3, MN7, MN8).

[0051] Furthermore, the buck sawtooth wave module 3 also includes a buck sawtooth wave output terminal Vsaw-buck, the charging terminal a2 of the second charge and discharge unit 3 is connected to the current mirror module 1, the control signal input terminal c2 of the second charge and discharge unit 31 is connected to the clock signal output terminal CLK of the comparator unit 22, and the charging voltage output terminal d2 of the second charge and discharge unit 31 is connected to the buck sawtooth wave output terminal Vsaw-buck.

[0052] It should be noted that the current mirror module 1 provides a charging current to the charging terminal a2 of the second charge and discharge unit 31, and the second charge and discharge unit 31 is charged. The comparator unit 22 outputs a clock signal to the second charge and discharge unit 31 through the clock signal output terminal CLK to control the charging and discharging of the second charge and discharge unit 31. Since the clock signals for controlling the charging and discharging of the second charge and discharge unit 31 and the first charge and discharge unit 31 are the same, and the circuit structures of the two are the same, when the current Ic0=Ic1, the second charge and discharge unit 31 generates a sawtooth wave with the same amplitude value as the first charge and discharge unit 21.

[0053] Further, the boost sawtooth wave module 4 also includes a boost sawtooth wave output terminal Vsaw-boost, the control unit 43 includes a logic control circuit 431, a first switch tube MN5 and a second switch tube MN6, and the logic control circuit 431 includes a clock signal input terminal CLK1, a first charge and discharge control output terminal CLK2, a second charge and discharge control output terminal CLK3, a first switch control output terminal CLKC and a second switch control output terminal CLKD;

[0054] The charging terminal a3 of the third charge and discharge unit 31 and the charging terminal a4 of the fourth charge and discharge unit 32 are connected to the current mirror module 1, the first charge and discharge control output terminal CLK2 is connected to the control signal input terminal c3 of the third charge and discharge unit 41, the charging voltage output terminal d3 of the third charge and discharge unit 41 is connected to the first end of the first switch tube MN5, the control end of the first switch tube MN5 is connected to the first switch control output terminal CLKC of the logic control circuit 431, the second charge and discharge control output terminal CLK3 is connected to the control signal input terminal c4 of the fourth charge and discharge unit 42, the charging voltage output terminal d4 of the fourth charge and discharge unit 42 is connected to the first end of the second switch tube MN6, the control end of the second switch tube MN6 is connected to the second switch control output terminal CLKD, and the second end of the second switch tube MN6 and the second end of the first switch tube MN5 are connected to the boost sawtooth wave output terminal Vsaw-boost.

[0055] In a specific implementation, the current mirror module 1 provides charging currents Ic2 and Ic4 to the third charge and discharge unit 41 and the fourth charge and discharge unit 42 respectively, and the logic control circuit 431 outputs a charging control signal through the first charge and discharge control output terminal CLK2 to control the charging of the third charge and discharge unit 41. When the third charge and discharge unit 41 completes one clock cycle of charging, the logic control circuit 431 outputs a charging control signal through the second charge and discharge control output terminal CLK3 to control the charging of the fourth charge and discharge unit 42, and the third charge and discharge unit 41 continues to charge, and at the same time outputs a high level signal through the first switch control output terminal CLKC to turn on the first switch tube MN5; when the third charge and discharge unit 41 completes ... During two clock cycles, the logic control circuit 431 outputs a discharge control signal through the first charge and discharge control output terminal CLK2 to control the third charge and discharge unit 41 to discharge quickly. At this time, the fourth charge and discharge unit 42 completes charging for one clock cycle and continues to charge. The logic control circuit 431 outputs a high-level signal through the second switch control output terminal CLKD to turn on the second switch tube MN6. The logic control circuit 431 outputs a charge control signal through the first charge and discharge control output terminal CLK2 again to control the charging of the third charge and discharge unit 41, thereby outputting a boost sawtooth wave with a target amplitude value whose valley value is equal to the peak value of the buck sawtooth wave through the boost sawtooth wave output terminal Vsaw-boost.

[0056] Preferably, the first switch tube MN5 is an N-channel MOS tube, the drain of the N-channel MOS tube is the first end of the first switch tube MN5, the source of the N-channel MOS tube is the second end of the first switch tube MN5, and the gate of the N-channel MOS tube is the control end of the first switch tube MN5;

[0057] The second switch tube MN6 is an N-channel MOS tube, the drain of the N-channel MOS tube is the first end of the second switch tube MN6, the source of the N-channel MOS tube is the second end of the second switch tube MN6, and the gate of the N-channel MOS tube is the control end of the second switch tube MN6.

[0058] Further, the current mirror module 1 includes a current input terminal IB, a third switch tube MP1, a fourth switch tube MP2, a fifth switch tube MP4, a sixth switch tube MP5 and a seventh switch tube MP8;

[0059] The current input terminal IB is connected to the current source, the second end of the third switch tube MP1 is connected to the current input terminal IB, the control end of the third switch tube MP1, the second end of the third switch tube MP1, the control end of the fourth switch tube MP2, the control end of the fifth switch tube MP4 and the control end of the sixth switch tube MP5 are connected to the control end of the seventh switch tube MP8, the first end of the third switch tube MP1, the first end of the fourth switch tube MP2, the first end of the fifth switch tube MP4 and the first end of the sixth switch tube MP5 are connected to the first end of the seventh switch tube MP8, the first end of the seventh switch tube MP8 is connected to the power supply VDD, and the second ends of the fourth to seventh switch tubes (MP2, MP4, MP5, MP8) are respectively connected to the charging ends (a1, a2, a3, a4) of the first to fourth charge and discharge units (21, 31, 41, 42) in a one-to-one correspondence.

[0060] See also Figure 5 , is a circuit diagram of an embodiment of a logic control circuit of a sawtooth wave generating circuit provided by the present invention. Figure 5 As shown, the logic control circuit 431 also includes a D flip-flop U3, a first AND gate U4 and a second AND gate U5;

[0061] The clock input terminal of the D flip-flop U3 is connected to the clock signal input terminal CLK1, the data input terminal of the D flip-flop U1 is connected to the second output terminal of the D flip-flop U3, the first output terminal of the D flip-flop U3 is respectively connected to the second switch control output terminal CLKD and the first input terminal of the first AND gate, the clock input terminal of the D flip-flop U3 is respectively connected to the second input terminal of the first AND gate U4 and the second input terminal of the second AND gate U5, the output terminal of the first AND gate U4 is connected to the first charge and discharge control output terminal CLK2, the second output terminal of the D flip-flop U2 is respectively connected to the first input terminal of the second AND gate U5 and the first switch control output terminal CLKC, and the output terminal of the second AND gate is connected to the second charge and discharge control output terminal CLK3.

[0062] like Figure 3 and Figure 4 As shown, in a specific implementation, the capacitances of the first to fourth charge and discharge units (21, 31, 41, 42) are matched, that is, C0=C1=C2=C3, and the currents are also matched, that is, Ic0=Ic1=Ic2=Ic4. The control clock signals output by the first switch control output terminal CLKC, the second switch control output terminal CLKD, the first charge and discharge control output terminal CLK2, and the second charge and discharge control output terminal CLK3 are represented by Figure 5 The logic control circuit in is generated.

[0063] See also Figure 6 , is a logic control timing diagram and a sawtooth wave waveform diagram of the logic control circuit of the sawtooth wave generating circuit provided by the present invention. Figure 4 , Figure 5and Figure 6 To illustrate, when a high pulse of the clock signal at the comparator output terminal CLK arrives, the capacitor C1 is quickly discharged to 0 potential, the first charge and discharge control output terminal CLK2 outputs a high pulse signal, the capacitor C2 is quickly discharged to 0 potential, the second charge and discharge control output terminal CLK3 outputs a low level signal, and the capacitor C3 is continuously charged; when the clock signal at the comparator output terminal CLK is at a low level, the charging voltage of the capacitor C1 gradually rises, the first charge and discharge control output terminal CLK2 and the second charge and discharge control output terminal CLK3 both output low level signals, so the voltages of the capacitors C2 and C3 rise, and the second switch control output terminal CLKD outputs a high level signal, so the boost sawtooth wave output terminal Vsaw_boost takes the potential of the capacitor C3. After one clock cycle, the second charge and discharge control output terminal CLK3 outputs a high pulse signal, and the clock signal of the comparator output terminal CLK is a high pulse signal, so the voltages on the capacitors C1 and C3 are quickly discharged to 0 potential, and the first charge and discharge control output terminal CLK2 outputs a low level signal, and the voltage on the capacitor C2 continues to rise. During this clock cycle, the charging time of the capacitor C1 is the same as that of C0, and because the current size is the same and the capacitance is the same, the period of the sawtooth wave output by the buck sawtooth wave output terminal Vsaw_buck is equal to the period of the clock signal output by the comparator output terminal CLK, and the amplitude is equal to Vsaw. The capacitor C2 is charged for one clock cycle, and the voltage amplitude of the capacitor C2 is also equal to Vsaw at this time; thereafter, when the first charge and discharge control output terminal CLK2 and the second charge and discharge control output terminal CLK3 output low level signals, the voltages of the capacitors C2 and C3 rise, and the first switch control output terminal CLKC outputs a high level signal, so the boost sawtooth wave output terminal Vsaw_boost takes the potential of the capacitor C2, and the voltage of the capacitor C2 is also equal to Vsaw at this time. After another clock cycle, the first charge and discharge control output terminal CLK2 outputs a high pulse signal, capacitors C1 and C2 quickly discharge to 0 potential, and capacitor C3 continues to charge. During this clock cycle, the buck sawtooth wave output terminal Vsaw_buck is also charged from 0 to Vsaw, and the capacitor C2 potential is charged for two clock cycles as a whole, so its output voltage peak is 2Vsaw, that is, the boost sawtooth wave output terminal Vsaw_boost rises from the initial value Vsaw to 2Vsaw, thereby achieving the sawtooth wave amplitude value of the boost sawtooth wave output terminal Vsaw_boost to be Vsaw, and the valley potential is Vsaw. Since the value of Vsaw can be set by itself, the boost sawtooth wave and buck sawtooth wave amplitude can be flexibly set.

[0064] The present invention provides a buck-boost converter, comprising the sawtooth wave generating circuit as described in the above embodiment.

[0065] It should be noted that, in the sawtooth wave generating circuit and the buck-boost converter provided in the above embodiments, the discharge switch tube (MN1, MN3, MN7, MN8), the first switch tube MN5 and the second switch tube MN6 are N-channel MOS tubes, which is only one implementation mode. In other implementation modes, the discharge switch tube (MN1, MN3, MN7, MN8), the first switch tube MN5 and the second switch tube MN6 can also be replaced with P-channel MOS tubes or other three-terminal control switch devices or their derivative devices. In different application scenarios, the switch tubes are reasonably selected and set according to the power consumption, cost, driving power and parameter matching of the driving control element of the actual circuit. The selection and setting of the switch tubes is a common design process in the prior art and will not be elaborated here.

[0066] The sawtooth wave generating circuit and the buck-boost converter provided by the present invention, the current mirror module provides charging current to the first to fourth charging and discharging units, the first charging and discharging unit generates a sawtooth wave with a target amplitude value according to the charging current, the comparator unit generates a clock signal according to the sawtooth wave with the target amplitude value, the second charging and discharging unit charges and discharges according to the clock signal, and outputs a charging voltage; the control unit generates a control signal according to the clock signal to control the third charging and discharging unit and the fourth charging and discharging unit to discharge once every two consecutive charging clock cycles, to control the third charging and discharging unit and the fourth charging and discharging unit to start charging when the other party completes a charging clock cycle and enters another charging clock cycle, to control the third charging and discharging unit and the fourth charging and discharging unit to output a charging voltage when they complete a charging clock cycle and enter another charging clock cycle. Since the first to fourth charge and discharge units have the same circuit structure and are controlled by the same clock signal, when the charging current is the same, the charging voltage output by the second charge and discharge unit is also a buck sawtooth wave with a target amplitude value; and since the third charge and discharge unit and the fourth charge and discharge unit both start charging when the other party completes a charging clock cycle and enters another charging clock cycle, both output charging voltages when completing a charging clock cycle and entering another charging clock cycle, and discharge once every two consecutive charging clock cycles, a boost sawtooth wave with a valley value equal to the peak value of the buck sawtooth wave and a target amplitude value is generated. The target amplitude value can be flexibly set by changing the reference voltage source of the comparator unit, thereby improving the anti-interference ability of the buck-boost converter; it can achieve that the peak value of the buck sawtooth wave is equal to the valley value of the boost sawtooth wave, ensuring the smooth switching of the working mode of the buck-boost converter, thereby improving the efficiency of the buck-boost converter and the stability of the output voltage.

[0067] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A sawtooth wave generating circuit, characterized in that: It includes a current mirror module, a clock generation module, a buck sawtooth wave module and a boost sawtooth wave module, wherein the clock generation module includes a first charge and discharge unit and a comparator unit, the buck sawtooth wave module includes a second charge and discharge unit, and the boost sawtooth wave module includes a third charge and discharge unit, a fourth charge and discharge unit and a control unit; wherein the first to fourth charge and discharge units have the same circuit structure; The current mirror module is used to provide a charging current to the first to fourth charging and discharging units to charge the first to fourth charging and discharging units; The first charge and discharge unit is used to generate a sawtooth wave with a target amplitude value according to the charging current; the comparator unit is used to generate a clock signal according to the sawtooth wave with the target amplitude value, and send the clock signal to the control unit and the second charge and discharge unit; The second charge and discharge unit performs charging and discharging according to the clock signal and outputs a charging voltage; The control unit is used to generate a control signal according to the clock signal to control the third charge and discharge unit and the fourth charge and discharge unit to discharge once every two consecutive clock cycles, to control the third charge and discharge unit and the fourth charge and discharge unit to start charging when the other party completes a charging clock cycle and enters another charging clock cycle, and to control the third charge and discharge unit and the fourth charge and discharge unit to output a charging voltage when they complete a charging clock cycle and enter another charging clock cycle.

2. The sawtooth wave generating circuit according to claim 1, characterized in that: The first to fourth charge and discharge units each include a control signal input terminal, a ground terminal, a charging terminal and a charging voltage output terminal, and the comparator unit includes a voltage signal input terminal, a reference signal input terminal and a clock signal output terminal; The charging end of the first charge and discharge unit is connected to the current mirror module, the charging voltage output end of the first charge and discharge unit is connected to the voltage signal input end of the comparator unit, the reference signal input end of the comparator unit is connected to a reference voltage source, and the clock signal output end of the comparator unit is connected to the control signal input end of the first charge and discharge unit.

3. The sawtooth wave generating circuit as claimed in claim 2, characterized in that: The comparator unit includes a comparator and an inverter; The non-inverting input terminal of the comparator is connected to the reference signal input terminal, the inverting input terminal of the comparator is connected to the voltage signal input terminal, the output terminal of the comparator is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the clock signal output terminal.

4. The sawtooth wave generating circuit as claimed in claim 2, characterized in that: The step-down sawtooth wave module also includes a step-down sawtooth wave output end, the charging end of the second charge and discharge unit is connected to the current mirror module, the control signal input end of the second charge and discharge unit is connected to the clock signal output end of the comparator unit, and the charging voltage output end of the second charge and discharge unit is connected to the step-down sawtooth wave output end.

5. The sawtooth wave generating circuit according to any one of claims 2 to 4, characterized in that: The boost sawtooth wave module also includes a boost sawtooth wave output terminal, the control unit includes a logic control circuit, a first switch tube and a second switch tube, the logic control circuit includes a clock signal input terminal, a first charge and discharge control output terminal, a second charge and discharge control output terminal, a first switch control output terminal and a second switch control output terminal; The charging end of the third charge and discharge unit and the charging end of the fourth charge and discharge unit are connected to the current mirror module, the first charge and discharge control output end is connected to the control signal input end of the third charge and discharge unit, the charging voltage output end of the third charge and discharge unit is connected to the first end of the first switch tube, the control end of the first switch tube is connected to the first switch control output end of the logic control circuit, the second charge and discharge control output end is connected to the control signal input end of the fourth charge and discharge unit, the charging voltage output end of the fourth charge and discharge unit is connected to the first end of the second switch tube, the control end of the second switch tube is connected to the second switch control output end, and the second end of the second switch tube and the second end of the first switch tube are connected to the boost sawtooth wave output end.

6. The sawtooth wave generating circuit as claimed in claim 5, characterized in that: The logic control circuit also includes a D flip-flop, a first AND gate and a second AND gate; The clock input terminal of the D flip-flop is connected to the clock signal input terminal, the data input terminal of the D flip-flop is connected to the second output terminal of the D flip-flop, the first output terminal of the D flip-flop is respectively connected to the second switch control output terminal and the first input terminal of the first AND gate, the clock input terminal of the D flip-flop is respectively connected to the second input terminal of the first AND gate and the second input terminal of the second AND gate, the output terminal of the first AND gate is connected to the first charge and discharge control output terminal, the second output terminal of the D flip-flop is respectively connected to the first input terminal of the second AND gate and the first switch control output terminal, and the output terminal of the second AND gate is connected to the second charge and discharge control output terminal.

7. The sawtooth wave generating circuit according to any one of claims 2 to 4, characterized in that: The first to fourth charge and discharge units all further include a discharge switch tube and a capacitor; The first end of the discharge switch tube is connected to the charging end and the first end of the capacitor respectively, the first end of the capacitor is connected to the charging voltage output end, the control end of the discharge switch tube is connected to the control signal input end, and the second end of the discharge switch tube and the second end of the capacitor are connected to the ground end.

8. The sawtooth wave generating circuit as claimed in claim 7, characterized in that: The discharge switch tube is an N-channel MOS tube, the drain of the N-channel MOS tube is the first end of the discharge switch tube, the source of the N-channel MOS tube is the second end of the discharge switch tube, and the gate of the N-channel MOS tube is the control end of the discharge switch tube.

9. The sawtooth wave generating circuit according to any one of claims 2 to 4, characterized in that: The current mirror module includes a current input terminal, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube and a seventh switch tube; The current input end is connected to a current source, the second end of the third switch tube is connected to the current input end, the control end of the third switch tube, the second end of the third switch tube, the control end of the fourth switch tube, the control end of the fifth switch tube and the control end of the sixth switch tube are all connected to the control end of the seventh switch tube, the first end of the third switch tube, the first end of the fourth switch tube, the first end of the fifth switch tube and the first end of the sixth switch tube are all connected to the first end of the seventh switch tube, the first end of the seventh switch tube is connected to a power supply, and the second ends of the fourth to seventh switch tubes are respectively connected to the charging ends of the first to fourth charge and discharge units in a one-to-one correspondence.

10. A buck-boost converter, characterized in that: The buck-boost converter comprises the sawtooth wave generating circuit as claimed in any one of claims 1 to 9.

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