Semiconductor package

Abstract

A semiconductor package is disclosed that includes a first semiconductor structure and a second semiconductor structure spaced apart from each other on a first substrate, a heat spreader covering the first semiconductor structure and the second semiconductor structure and the first substrate, and a layer of thermal interface material between the heat spreader and the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The layer of thermal interface material includes a first thermal interface material portion between the first semiconductor structure and the second semiconductor structure and a second thermal interface material portion that protrudes beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first thermal interface material portion is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second thermal interface material portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0080463, filed with the Korean Intellectual Property Office on July 11, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor packaging. Background Technology

[0004] A semiconductor package is provided to realize an integrated circuit chip suitable for electronic products. The semiconductor package is typically constructed such that the semiconductor chip is mounted on a printed circuit board (PCB), and the semiconductor chip is electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, much research has been conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide semiconductor packages with higher reliability.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package includes: a first substrate; a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite to the first sidewall; a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure; a heat sink covering at least a portion of the first semiconductor structure, the second semiconductor structure, and the first substrate; and a thermal interface material layer between the first semiconductor structure and the heat sink and between the second semiconductor structure and the heat sink, the thermal interface material layer including a first thermal interface material portion between the first semiconductor structure and the second semiconductor structure and a second thermal interface material portion protruding beyond the second sidewall, wherein a first distance from the top surface of the first substrate to the lowest point of the bottom surface of the first thermal interface material portion is less than a second distance from the top surface of the first substrate to the lowest point of the bottom surface of the second thermal interface material portion.

[0007] According to an example embodiment of the inventive concept, a semiconductor package includes: a first substrate; a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite the first sidewall; a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure adjacent the first sidewall of the first semiconductor structure; a heat spreader covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate; and a layer of thermal interface material between the first semiconductor structure and the heat spreader and between the second semiconductor structure and the heat spreader, the layer of thermal interface material including a first portion of thermal interface material adjacent the first sidewall and a second portion of thermal interface material adjacent the second sidewall, the first portion of thermal interface material being thicker than the second portion of thermal interface material.

[0008] According to an example embodiment of the inventive concept, a semiconductor package includes: a package substrate; a first semiconductor structure and a second semiconductor structure mounted on the package substrate, the first semiconductor structure and the second semiconductor structure spaced apart from each other in a direction parallel to a top surface of the package substrate; a heat spreader covering at least portions of the first semiconductor structure, the second semiconductor structure, and the package substrate; and a layer of thermal interface material between the first semiconductor structure and the heat spreader and between the second semiconductor structure and the heat spreader, the layer of thermal interface material having different thicknesses depending on its location, the layer of thermal interface material having a maximum thickness at a location between the first semiconductor structure and the second semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A plan view showing a semiconductor package according to an example embodiment of the inventive concept is shown.

[0010] Figure 2 A cross-sectional view taken along line II-II' of Figure 1 is shown.

[0011] Figure 3 An enlarged view showing portion III of Figure 2 is shown.

[0012] Figure 4 A partial perspective view of Figure 2 is shown.

[0013] Figure 5 A cross-sectional view taken along line V-V' of Figure 1 is shown.

[0014] Figure 6 A cross-sectional view showing a method of manufacturing a semiconductor package in conjunction with Figure 2 is shown.

[0015] Figure 7An example embodiment of the concept of the present invention is shown along Figure 1 A cross-sectional view of the semiconductor package taken from line II-II'.

[0016] Figure 8 It shows Figure 7 An enlarged view of part VIII in the diagram.

[0017] Figure 9 and Figure 10 A plan view illustrating some example embodiments of a semiconductor package according to a concept of the present invention is shown.

[0018] Figure 11 It shows along Figure 9 or Figure 10 The cross-sectional view taken from line XI-XI'.

[0019] Figure 12 A cross-sectional view of a semiconductor package according to an example embodiment of the present invention is shown.

[0020] Figure 13 and Figure 14 The demonstration is shown Figure 12 A magnified view of part XIII.

[0021] Figures 15 to 17 A cross-sectional view is shown illustrating some example embodiments of a semiconductor package according to a concept proposed in this invention. Detailed Implementation

[0022] Some exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings, in order to explain the inventive concept in detail and completely to those skilled in the art.

[0023] Figure 1 A plan view illustrating an example embodiment of a semiconductor package according to a concept of the present invention is shown. Figure 2 It shows along Figure 1 The cross-sectional view taken from line II-II'. Figure 3 The demonstration is shown Figure 2 Enlarged view of part III. Figure 4 It shows Figure 2 A partial perspective view. Figure 5 It shows along Figure 1 A cross-sectional view taken from line V-V'.

[0024] refer to Figures 1 to 5The semiconductor package 100 can include a first substrate 10. A second substrate 30 can be disposed on the first substrate 10. A first semiconductor chip 50 can be mounted on the second substrate 30. A second semiconductor chip 60 can be further mounted on the second substrate 30. The second semiconductor chip 60 can be spaced apart from the first semiconductor chip 50 in a first direction X. A heat spreader 80 can cover at least portions of the first semiconductor chip 50, the second semiconductor chip 60, the second substrate 30, and the first substrate 10. An adhesive layer 82 can be interposed between the first substrate 10 and a bottom surface of the heat spreader 80. A thermal interface material layer 70 can be interposed between the heat spreader 80 and the first semiconductor chip 50 and between the heat spreader 80 and the second semiconductor chip 60.

[0025] The first substrate 10 can be, for example, a printed circuit board. The first substrate 10 can be referred to as a package substrate. The first substrate 10 can include a first core board 11, a first substrate upper conductive pattern 13 on a top surface of the first core board 11, a first substrate upper passivation layer 17 covering the top surface of the first core board 11, a first substrate lower conductive pattern 15 on a bottom surface of the first core board 11, and a first substrate lower passivation layer 19 covering the bottom surface of the first core board 11. Although not specifically shown in the drawings, the first substrate upper conductive pattern 13 can be electrically connected to the first substrate lower conductive pattern 15. An external connection terminal 22 can be attached to the first substrate lower conductive pattern 15. The external connection terminal 22 can be, for example, a solder ball. The external connection terminal 22 can include, for example, one or more of tin and lead.

[0026] The first core board 11 can include, but is not limited to, a thermosetting resin (e.g., an epoxy resin), a thermoplastic resin (e.g., a polyimide), a resin into which a reinforcement (e.g., a glass fiber and / or an inorganic filler) is injected in a thermosetting or thermoplastic resin, or a photosensitive resin. The first substrate upper passivation layer 17 and the first substrate lower passivation layer 19 can include a photosensitive solder resist (PSR). The photosensitive solder resist can include a photosensitive polymer. The photosensitive polymer can include one or more of a photosensitive polyimide (PSPI), a polybenzoxazole (PBO), a phenol polymer, and a benzocyclobutene (BCB) polymer. The photosensitive solder resist can further include an inorganic filler. The first substrate upper conductive pattern 13 and the first substrate lower conductive pattern 15 can include one or more of copper, aluminum, and gold.

[0027] The second substrate 30 may be, for example, an interposer substrate. The second substrate 30 may include a second core plate 31, an upper conductive pattern 33 on the top surface of the second core plate 31, an upper passivation layer 37 covering the top surface of the second core plate 31, a lower conductive pattern 35 on the bottom surface of the second core plate 31, and a lower passivation layer 39 covering the bottom surface of the second core plate 31.

[0028] The second core board 31 may include, for example, silicon. The upper passivation layer 37 and the lower passivation layer 39 of the second substrate may include a photosensitive solder resist (PSR). The photosensitive solder resist may include a photosensitive polymer. The photosensitive polymer may include one or more of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymers, and benzocyclobutene (BCB) polymers. The photosensitive solder resist may also include an inorganic filler. The upper conductive pattern 33 and the lower conductive pattern 35 of the second substrate may include one or more of copper, aluminum, and gold.

[0029] The first substrate 10 and the second substrate 30 can be electrically connected to each other via a first internal connection terminal 26. The first internal connection terminal 26 can electrically connect the upper conductive pattern 13 of the first substrate to the lower conductive pattern 35 of the second substrate. The first internal connection terminal 26 can be a solder ball, a conductive bump, a conductive pillar, or any combination thereof. The first internal connection terminal 26 can include one or more of copper, tin, and lead. A first lower filler layer 24 can be inserted between the first substrate 10 and the second substrate 30.

[0030] The first semiconductor chip 50 may include a first chip body 51, a first chip conductive pad 53 on the bottom surface of the first chip body 51, and a first chip passivation layer 55 covering the bottom surface of the first chip body 51. Although Figures 1 to 5 Not specifically shown, but the first chip body 51 may include a plurality of transistors and interconnects disposed on a semiconductor substrate. The first chip conductive pad 53 may include metal (e.g., aluminum or copper). The first chip passivation layer 55 may be formed of, for example, a silicon nitride layer or a polyimide layer. The first chip conductive pad 53 may be electrically connected via a second internal connection terminal 40 to a corresponding second substrate upper conductive pattern 33. The second internal connection terminal 40 may be a solder ball, conductive bump, conductive pillar, or any combination thereof. The second internal connection terminal 40 may include one or more of copper, tin, and lead. A second underfill layer 42 may be inserted between the first semiconductor chip 50 and the second substrate 30. The first semiconductor chip 50 may include a first chip right sidewall 50sr adjacent to the second semiconductor chip 60 and a first chip left sidewall 50sl opposite to the first chip right sidewall 50sr. Figure 1As shown, the first semiconductor chip 50 may further include a first chip front sidewall 50sf and a first chip rear sidewall 50sb. The first chip front sidewall 50sf connects the first chip right sidewall 50sr to the first chip left sidewall 50sl on the front side of the first semiconductor chip 50. The first chip rear sidewall 50sb is opposite to the first chip front sidewall 50sf and connects the first chip right sidewall 50sr to the first chip left sidewall 50sl on the rear (back) side of the first semiconductor chip 50. The first semiconductor chip 50 may have a top surface 50u that is spaced apart from the top surface of the second substrate 30 by a first distance D1.

[0031] The second semiconductor chip 60 may include a second chip body 61, a second chip conductive pad 63 on the bottom surface of the second chip body 61, and a second chip passivation layer 65 covering the bottom surface of the second chip body 61. Although Figures 1 to 5 Not specifically shown, but the second chip body 61 may include a plurality of transistors and interconnects disposed on a semiconductor substrate. The second chip conductive pads 63 may include metal (e.g., aluminum or copper). The second chip passivation layer 65 may be formed of, for example, a silicon nitride layer or a polyimide layer. The second chip conductive pads 63 may be electrically connected via a third internal connection terminal 44 to corresponding upper conductive patterns 33 on the upper second substrate. The third internal connection terminal 44 may be a solder ball, conductive bump, conductive pillar, or any combination thereof. The third internal connection terminal 44 may include one or more of copper, tin, and lead. A third underfill layer 46 may be inserted between the second semiconductor chip 60 and the second substrate 30. The second semiconductor chip 60 may include a second chip left side wall 60sl adjacent to the first semiconductor chip 50 and a second chip right side wall 60sr opposite to the second chip left side wall 60sl. Figure 1 As shown, the second semiconductor chip 60 may further include a second chip front sidewall 60sf and a second chip rear sidewall 60sb. The second chip front sidewall 60sf connects the second chip right sidewall 60sr to the second chip left sidewall 60sl on the front side of the second semiconductor chip 60. The second chip rear sidewall 60sb is opposite to the second chip front sidewall 60sf and connects the second chip right sidewall 60sr to the second chip left sidewall 60sl on the rear (back) side of the second semiconductor chip 60. The second semiconductor chip 60 may have a top surface 60u that is spaced apart from the top surface of the second substrate 30 by a second distance D2.

[0032] The first distance D1 can be equal to the second distance D2. For example, the top surface 50u of the first semiconductor chip 50 can be at the same height (or level) as the top surface 60u of the second semiconductor chip 60.

[0033] The first semiconductor chip 50 and the second semiconductor chip 60 can each be independently selected from a system LSI (large scale integrated circuit), a logic circuit, an image sensor (for example, a CIS (CMOS image sensor), a MEMS (micro electro mechanical system) device, an ASIC (application specific integrated circuit) device, and a memory (for example, a flash memory, a DRAM, a SRAM, an EEPROM, a PRAM, an MRAM, a ReRAM, an HBM (high bandwidth memory), or an HMC (hybrid memory cube)).

[0034] The first lower filling layer 24, the second lower filling layer 42, and the third lower filling layer 46 can include a thermosetting resin or a photosensitive resin. The first lower filling layer 24, the second lower filling layer 42, and the third lower filling layer 46 can further include an organic or inorganic filler. The second lower filling layer 42 can be spaced apart from the third lower filling layer 46. The second lower filling layer 42 can include a second lower filling protrusion 42a protruding beyond a first chip right sidewall 50sr of the first semiconductor chip 50. The third lower filling layer 46 can include a third lower filling protrusion 46a protruding beyond a second chip left sidewall 60sl of the second semiconductor chip 60.

[0035] The heat spreader 80 can be, for example, a metal plate. The thermal interface material layer 70 can include, for example, a thermosetting resin layer. The thermal interface material layer 70 can further include filler particles (not shown) distributed in the thermosetting resin layer. The filler particles can include one or more of silicon dioxide, aluminum oxide, zinc oxide, and boron nitride. The thermal interface material layer 70 can include a first thermal interface material portion 70a to a sixth thermal interface material portion 70f. The first thermal interface material portion 70a to the sixth thermal interface material portion 70f can constitute one single body. The first thermal interface material portion 70a can be interposed between the heat spreader 80 and a top surface 50u of the first semiconductor chip 50. The second thermal interface material portion 70b can be interposed between the heat spreader 80 and a top surface 60u of the second semiconductor chip 60. The third thermal interface material portion 70c can be interposed between a first chip right sidewall 50sr of the first semiconductor chip 50 and a second chip left sidewall 60sl of the second semiconductor chip 60. An upper surface of the third thermal interface material portion 70c can have an upper surface located at the same height as the top surface 50u of the first semiconductor chip 50 or the top surface 60u of the second semiconductor chip 60. The fourth thermal interface material portion 70d can be interposed between the third thermal interface material portion 70c and the heat spreader 80 in a vertical direction. The fourth thermal interface material portion 70d can also be interposed between the first thermal interface material portion 70a and the second thermal interface material portion 70b in a horizontal direction. The fifth thermal interface material portion 70e can protrude beyond a first chip left sidewall 50sl of the first semiconductor chip 50. The sixth thermal interface material portion 70f can protrude beyond a second chip right sidewall 60sr of the second semiconductor chip 60.

[0036] like Figure 1 As shown, the fifth thermal interface material portion 70e can extend beyond the front sidewall 50sf of the first chip. The fifth thermal interface material portion 70e can also extend beyond the rear sidewall 50sb of the first chip. The sixth thermal interface material portion 70f can extend beyond the front sidewall 60sf of the second chip. The sixth thermal interface material portion 70f can also extend beyond the rear sidewall 60sb of the second chip. The fourth thermal interface material portion 70d can extend between the first thermal interface material portion 70a and the sixth thermal interface material portion 70f. The third thermal interface material portion 70c can be located between the first thermal interface material portion 70a and the sixth thermal interface material portion 70f.

[0037] The third distance D3 from the top surface of the second substrate 30 to the lowest point of the bottom surface of the third thermal interface material portion 70c can be less than the fourth distance D4 from the top surface of the second substrate 30 to the lowest point of the bottom surface of the fifth thermal interface material portion 70e. The fifth distance D5 from the top surface of the second substrate 30 to the lowest point of the bottom surface of the sixth thermal interface material portion 70f can be greater than the third distance D3. In some example embodiments, the third distance D3 can be less than each of the fourth distance D4 and the fifth distance D5. The fourth distance D4 can be equal to or substantially similar to the fifth distance D5. Any of the third distance D3, the fourth distance D4, and the fifth distance D5 can be less than the first distance D1 and the second distance D2. The first semiconductor chip 50 and the second semiconductor chip 60 can be spaced apart from each other by a sixth distance D6, which is equal to or less than, for example, about 1 mm. The thermal interface material layer 70 can have different thicknesses depending on the location. For example, as Figure 5 As shown, the seventh distance D7 or minimum distance from the lowest point of the bottom surface of the fifth thermal interface material portion 70e to the heat sink 80 can be less than the eighth distance D8 or minimum distance from the lowest point of the bottom surface of the third thermal interface material portion 70c to the heat sink 80. The thermal interface material layer 70 can be thickest between the first semiconductor chip 50 and the second semiconductor chip 60, and thinnest between the heat sink 80 and the first semiconductor chip 50, or between the heat sink 80 and the second semiconductor chip 60. The thickness of the thermal interface material layer 70 between the first semiconductor chip 50 and the second semiconductor chip 60 can correspond to the sum of the thicknesses of the third thermal interface material portion 70c and the fourth thermal interface material portion 70d.

[0038] refer to Figures 2 to 5The gap region AR1 can be provided between the first semiconductor chip 50 and the second semiconductor chip 60. An upper end of the gap region AR1 can be defined by a height of the top surface 50u of the first semiconductor chip 50 or by a height of the top surface 60u of the second semiconductor chip 60. A lower end of the gap region AR1 can be defined by a top surface of the second substrate 30. One side of the gap region AR1 can be defined by the first chip right sidewall 50sr of the first semiconductor chip 50. The other side of the gap region AR1 opposite to the one side of the gap region AR1 can be defined by the second chip left sidewall 60sl of the second semiconductor chip 60.

[0039] The gap region AR1 can have an empty space AG1 therein which is not occupied by the third thermal interface material portion 70c, the second underfill protrusion 42a, and the third underfill protrusion 46a. The empty space AG1 can separate the third thermal interface material portion 70c from the second underfill protrusion 42a and the third underfill protrusion 46a. In this case, the empty space AG1 can be located between the third thermal interface material portion 70c, the second underfill protrusion 42a, and the third underfill protrusion 46a.

[0040] The thermal interface material layer 70 can have physical properties (e.g., coefficient of thermal expansion or modulus of elasticity) different from those of the second underfill layer 42 and the third underfill layer 46. The manufacturing of the semiconductor package 100 can be subjected to temperature changes, for example, between room temperature and about 200°C. When the thermal interface material layer 70 contacts any one of the second underfill protrusion 42a or the third underfill protrusion 46a in the gap region AR1, one or both of the second underfill layer 42 and the third underfill layer 46 can be subjected to cracking due to stress caused by the difference in physical properties between the thermal interface material layer 70, the second underfill protrusion 42a, and the third underfill protrusion 46a. For example, cracking can occur at the interface between the second substrate 30 and one or both of the second underfill layer 42 and the third underfill layer 46. In the case where cracking occurs, the degree of cracking can be greatly increased due to rapid temperature changes during subsequent testing processes of the semiconductor package. Thus, the problem of bump open (referring to one or more of the second internal connection terminals 40 and the third internal connection terminals 44 being disconnected from the second substrate upper conductive pattern 33) can occur.

[0041] However, according to the present inventive concept, since the empty space AG1 separates the third thermal interface material portion 70c from the second underfill protrusion 42a and the third underfill protrusion 46a, even when the semiconductor package is subjected to temperature changes, stress does not occur between the third thermal interface material portion 70c and the second underfill protrusion 42a and the third underfill protrusion 46a, and thus cracking problems can be mitigated or avoided. Accordingly, the semiconductor package 100 can be improved in reliability.

[0042] The sum of the volumes of the third thermal interface material portion 70c, the second underfill protrusion 42a, and the third underfill protrusion 46a located in the gap region AR1 can be equal to or less than about 90% of the total volume of the gap region AR1. The volume of the empty space AG1 in the gap region AR1 between the first semiconductor chip 50 and the second semiconductor chip 60 can be equal to or greater than about 10% of the total volume of the gap region AR1. If these conditions are satisfied, even when the thermal interface material layer 70, the second underfill layer 42, and the third underfill layer 46 thermally expand during manufacturing and testing of the semiconductor package, the empty space AG1 can still exist and separate the third thermal interface material portion 70c from the second underfill protrusion 42a and the third underfill protrusion 46a. Accordingly, the semiconductor package 100 can exhibit improved reliability.

[0043] Figure 6 A cross-sectional view showing a method of manufacturing a semiconductor package is shown in conjunction with Figure 2 A cross-sectional view showing a method of manufacturing a semiconductor package is shown in conjunction with

[0044] Referring to Figure 6 A first substrate 10 can be prepared. The first substrate 10 can include a first core board 11, a first substrate upper conductive pattern 13 on a top surface of the first core board 11, a first substrate upper passivation layer 17 covering the top surface of the first core board 11, a first substrate lower conductive pattern 15 on a bottom surface of the first core board 11, and a first substrate lower passivation layer 19 covering the bottom surface of the first core board 11. A second substrate 30 can be attached to the first substrate 10 by one or more first internal connection terminals 26 interposed therebetween. The second substrate 30 can include a second core board 31, a second substrate upper conductive pattern 33 on a top surface of the second core board 31, a second substrate upper passivation layer 37 covering the top surface of the second core board 31, a second substrate lower conductive pattern 35 on a bottom surface of the second core board 31, and a second substrate lower passivation layer 39 covering the bottom surface of the second core board 31.

[0045] A first underfill layer 24 can be formed between the first substrate 10 and the second substrate 30. For example, the first underfill layer 24 can be formed by providing a thermosetting or photosensitive resin solution into a space between the first substrate 10 and the second substrate 30, and then curing the resin solution. The first semiconductor chip 50 can be mounted on the second substrate 30 with one or more second internal connection terminals 40 interposed between the first semiconductor chip 50 and the second substrate 30. A second underfill layer 42 can be formed between the first semiconductor chip 50 and the second substrate 30. Similar to the formation of the first underfill layer 24, the second underfill layer 42 can be formed by providing a thermosetting or photosensitive resin solution into a space between the second substrate 30 and the first semiconductor chip 50, and then curing the resin solution. A portion of the second underfill layer 42 can protrude beyond the first chip right side wall 50sr of the first semiconductor chip 50, thereby forming a second underfill protrusion 42a. The second semiconductor chip 60 can be mounted on the second substrate 30 with one or more third internal connection terminals 44 interposed between the second semiconductor chip 60 and the second substrate 30.

[0046] Figure 6 A dashed line is shown to represent a gap region AR1 between the first semiconductor chip 50 and the second semiconductor chip 60. The second underfill protrusion 42a can be located in the gap region AR1. Figure 6

[0047] Subsequently, with reference to Figure 2 A third underfill layer 46 can be formed between the second semiconductor chip 60 and the second substrate 30. A resin solution can be applied on the top surface 50u of the first semiconductor chip 50 and the top surface 60u of the second semiconductor chip 60, and then cured at a temperature of about 2000C while pressing a heat sink 80 over the resin solution with a jig or the like, thereby providing a thermal interface material layer 70. In this step, the resin solution can be pressed downward and then forced to move outward beyond the edges of the first semiconductor chip 50 and the second semiconductor chip 60. The outward movement of the resin solution can form a third thermal interface material portion 70c, a fourth thermal interface material portion 70d, a fifth thermal interface material portion 70e, and a sixth thermal interface material portion 70f. Due to the high integration of the semiconductor package, the spacing between the first semiconductor chip 50 and the second semiconductor chip 60 can be reduced, such that the resin solution pushed outward beyond the edges of the first semiconductor chip 50 and the second semiconductor chip 60 can be connected, thereby causing the thermal interface material layer 70 to have a relatively large thickness between the first semiconductor chip 50 and the second semiconductor chip 60. The above process can manufacture a semiconductor package as shown in FIG. 2. Figure 2 ​The semiconductor package 100 is shown configured as described above. The lower end of the heat spreader 80 can be attached to the top surface of the first substrate 10 by an adhesive layer 82. The adhesive layer 82 can include the same material as the material of the thermal interface material layer 70. The adhesive layer 82 and the thermal interface material layer 70 can be formed simultaneously. Subsequently, the external connection terminals 22 can be attached to the first substrate lower conductive pattern 15.

[0048] According to the present example embodiment, since the empty space AG1 separates the third thermal interface material portion 70c from the second and third underfill protrusions 42a, 46a, even when the manufacturing of the semiconductor package 100 is subjected to temperature changes, stress does not occur between the third thermal interface material portion 70c and the second and third underfill protrusions 42a, 46a, thereby the cracking problem can be mitigated or avoided. Thus, the semiconductor package 100 can be improved in reliability, have a reduced defect rate and / or have an increased manufacturing yield.

[0049] Figure 7 A cross-sectional view of a semiconductor package taken along the line II-II' of Figure 1 showing an example embodiment according to the inventive concept is shown. Figure 8 An enlarged view showing part VIII of Figure 7 is shown.

[0050] With reference to Figure 7 and Figure 8 , the semiconductor package 101 can be configured such that the second underfill protrusion 42a can extend to contact the first chip right sidewall 50sr of the first semiconductor chip 50. The third underfill protrusion 46a can extend to contact the second chip left sidewall 60sl of the second semiconductor chip 60. The second underfill protrusion 42a can also contact the third underfill protrusion 46a. A ninth distance D9 can be provided between the top surface of the second substrate 30 and the upper end of the second underfill protrusion 42a. The ninth distance D9 can be equal to or less than about 50% of the first distance Dl. A tenth distance DlO can be provided between the top surface of the second substrate 30 and the upper end of the third underfill protrusion 46a. The tenth distance DlO can be equal to or less than about 50% of the first distance Dl. In the gap region ARl, the third thermal interface material portion 70c can have a relatively large volume compared to the case of the semiconductor package 100 of Figure 2 However, when the thermal interface material layer 70, the second underfill layer 42 and the third underfill layer 46 thermally expand during the manufacturing and testing of the semiconductor package, the empty space AG1 can still be present and separate the third thermal interface material portion 70c from the second and third underfill protrusions 42a, 46a. Thus, the semiconductor package 101 can have a higher reliability. Other configurations can be used with reference toFigures 1 to 5 The configurations discussed can be the same or substantially similar.

[0051] Figure 9 and Figure 10 A plan view showing a semiconductor package according to some example embodiments of inventive concepts is shown. Figure 11 A cross-sectional view taken along the line XI-XI' is shown. Figure 9 or Figure 10 A cross-sectional view taken along the line XI-XI' is shown.

[0052] Referring to Figure 9 and Figure 11 The semiconductor package 102 can be configured such that the first semiconductor chip 50 can be mounted at a central portion of the second substrate 30, and the second semiconductor chips 60a and 60b can be mounted on the second substrate 30 at opposite sides of the first semiconductor chip 50. The second semiconductor chips 60a and 60b can include a first second semiconductor chip 60a and a second second semiconductor chip 60b. The third thermal interface material portions 70c can be disposed between the first second semiconductor chip 60a and the first semiconductor chip 50 and between the second semiconductor chip 60b and the first semiconductor chip 50. The first second semiconductor chip 60a and the second second semiconductor chip 60b can have the same function or different functions from each other. Other configurations can be the same or substantially similar to the configurations discussed with reference to Figures 1 to 5 The configurations discussed can be the same or substantially similar.

[0053] Referring to Figure 10 and Figure 11 The semiconductor package 103 can be configured such that the first semiconductor chip 50 can be mounted at a central portion of the second substrate 30, and the second semiconductor chips 60a, 60b, 60c, and 60d can be mounted on the second substrate 30 at opposite sides of the first semiconductor chip 50. The second semiconductor chips 60a, 60b, 60c, and 60d can include a first second semiconductor chip 60a, a second second semiconductor chip 60b, a third second semiconductor chip 60c, and a fourth second semiconductor chip 60d. The first second semiconductor chip 60a and the third second semiconductor chip 60c can be disposed adjacent to one side of the first semiconductor chip 50. The second and fourth second semiconductor chips 60b and 60d can be disposed adjacent to another side of the first semiconductor chip 50, which is opposite to the one side of the first semiconductor chip 50. The second semiconductor chips (alternatively, the first to fourth second semiconductor chips) 60a, 60b, 60c, and 60d can be spaced apart from each other. The second semiconductor chips 60a, 60b, 60c, and 60d can have the same function or different functions from each other. Other configurations can be the same or substantially similar to the configurations discussed with reference to Figures 1 to 5 The configurations discussed can be the same or substantially similar.

[0054] Figure 12 A cross-sectional view showing a semiconductor package according to example embodiments of the inventive concepts is illustrated. Figure 13 and Figure 14 A cross-sectional view showing a semiconductor package according to example embodiments of the inventive concepts is illustrated. Figure 12 An enlarged view of a portion XIII of

[0055] Referring to Figure 12 and Figure 13 , the semiconductor package 104 can be configured such that the first distance D1 can be different from the second distance D2. For example, the first distance D1 can be smaller than the second distance D2. In this case, the top end of the air gap region AR1 can be defined by the height of the top surface 50u of the first semiconductor chip 50. The fourth thermal interface material portion 70d can cover the upper portion of the second chip left sidewall 60sl of the second semiconductor chip 60.

[0056] If the second distance D2 is smaller than the first distance D1, the top end of the air gap region AR1 can be defined by the height of the top surface 60u of the second semiconductor chip 60. The fourth thermal interface material portion 70d can cover the upper portion of the first chip right sidewall 50sr of the first semiconductor chip 50. Other configurations can be the same as or substantially similar to the configurations discussed with reference to Figures 1 to 5

[0057] Referring to Figure 14 , the cross-section of the third thermal interface material portion 70c can have a kink point PA. For further examples, the third thermal interface material portion 70c can have a groove-containing bottom surface. Due to the first distance D1 and the second distance D2 being different from each other, the resin solution used to form the thermal interface material layer 70 can be pressed under the heat spreader 80 covering the resin solution non-uniformly. Thus, the kink point PA or the groove can be formed on the lower surface of the thermal interface material layer 70. When the first distance D1 is smaller than the second distance D2, the kink point PA can be closer to the first semiconductor chip 50 than to the second semiconductor chip 60. When the first distance D1 is greater than the second distance D2, the kink point PA can be closer to the second semiconductor chip 60 than to the first semiconductor chip 50. Other configurations can be the same as or substantially similar to the configurations discussed with reference to Figure 12 and Figure 13

[0058] Figures 15 to 17 A cross-sectional view showing a semiconductor package according to example embodiments of the inventive concepts is illustrated.

[0059] Referring to Figure 15 ​​, the semiconductor package 105 can be configured such that the second sub semiconductor package 160 can be mounted on the second substrate 30, and the third internal connection terminal 44 is interposed between the second sub semiconductor package 160 and the second substrate 30. The second sub semiconductor package 160 can be spaced apart from the first semiconductor chip 50. The second sub semiconductor package 160 can include a second sub package substrate 162 and a plurality of second semiconductor chips 164 stacked in sequence on the second sub package substrate 162. The second semiconductor chips 164 can include a through electrode 166 therein. The second semiconductor chips 164 can be stacked in a flip-chip bonded manner. A second sub molding layer 165 can cover sidewalls of the second semiconductor chips 164 and a top surface of the second sub package substrate 162. An uppermost one of the second semiconductor chips 164 can have a top surface coplanar with a top surface of the second sub molding layer 165. A second thermal interface material portion 70b of the thermal interface material layer 70 can directly contact the uppermost second semiconductor chip 164. In this case, heat generated by the uppermost second semiconductor chip 164 can be dissipated outward through the thermal interface material layer 70. Other configurations can be the same as or substantially similar to the configurations discussed with reference to Figures 1 to 5 .

[0060] With reference to Figure 16 , the semiconductor package 106 can be configured such that the first sub semiconductor package 150 can be mounted on the second substrate 30, and the second internal connection terminal 40 is interposed between the first sub semiconductor package 150 and the second substrate 30. The first sub semiconductor package 150 can be spaced apart from the second sub semiconductor package 160. The first sub semiconductor package 150 can include a first sub package substrate 151, a first semiconductor chip 153 wire-bonded to the first sub package substrate 151, and a first sub molding layer 154 covering the first semiconductor chip 153. Other configurations can be the same as or substantially similar to the configurations discussed with reference to Figure 15 .

[0061] With reference to Figure 17 , the semiconductor package 107 does not provide the second substrate 30 as shown in Figure 15 and Figure 16 , and can be configured such that the first semiconductor chip 50 is directly mounted on the first substrate 10, and the second internal connection terminal 40 is interposed between the first semiconductor chip 50 and the first substrate 10. In addition, the second semiconductor chip 60 can be directly mounted on the first substrate 10, and the third internal connection terminal 44 is interposed between the second semiconductor chip 60 and the first substrate 10. Other configurations can be the same as or substantially similar to the configurations discussed with reference to Figures 1 to 5 .

[0062] Figure 2 the first semiconductor chip 50 andFigure 16 The first sub semiconductor packages 150 of the first semiconductor chip 50 can each be referred to as a first semiconductor structure. Figure 2 The second semiconductor chip 60 and Figure 16 The second sub semiconductor packages 160 of the second semiconductor chip 60 can each be referred to as a second semiconductor structure.

[0063] According to the inventive concept, the semiconductor package can include a lower fill layer and a thermal interface material layer spaced apart from each other, thereby mitigating or avoiding defects (e.g., cracking) caused by a difference in physical properties between the lower fill layer and the thermal interface material layer, thereby improving reliability.

[0064] Further, a method of manufacturing the semiconductor package can mitigate or avoid defects (e.g., cracking) and can improve manufacturing yield.

[0065] Although the inventive concept has been described with reference to some example embodiments illustrated in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical spirit and essential features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes can be made thereto without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor package comprising: a first substrate; a first semiconductor structure mounted on the first substrate, the first semiconductor structure comprising a first sidewall and a second sidewall opposite the first sidewall; a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure, the second semiconductor structure comprising a third sidewall adjacent to the first semiconductor structure and a fourth sidewall opposite the third sidewall; a heat spreader covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate; and a thermal interface material layer between the first semiconductor structure and the heat spreader and between the second semiconductor structure and the heat spreader, the thermal interface material layer comprising a plurality of thermal interface material portions constituting one single body, the plurality of thermal interface material portions comprising a first thermal interface material portion between the first semiconductor structure and the second semiconductor structure and in contact with the first sidewall of the first semiconductor structure and the third sidewall of the second semiconductor structure and a second thermal interface material portion protruding beyond the second sidewall, a first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first thermal interface material portion being less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second thermal interface material portion.

2. The semiconductor package of claim 1, further comprising: a first underfill layer between the first substrate and the first semiconductor structure, wherein the first underfill layer comprises a first underfill protrusion protruding beyond the first sidewall, and wherein the first thermal interface material portion is spaced apart from the first underfill protrusion.

3. The semiconductor package of claim 2, wherein a third distance from the top surface of the first substrate to a highest point of an upper surface of the first underfill protrusion is equal to or less than 50% of a fourth distance from the top surface of the first substrate to a top surface of the first semiconductor structure.

4. The semiconductor package of claim 2, wherein the plurality of thermal interface material portions further comprises a third thermal interface material portion protruding beyond the fourth sidewall, and a fifth distance from the top surface of the first substrate to a lowest point of a bottom surface of the third thermal interface material portion is greater than the first distance.

5. The semiconductor package of claim 4, further comprising: a second underfill layer between the first substrate and the second semiconductor structure, wherein the second underfill layer comprises a second underfill protrusion protruding beyond the third sidewall, and wherein the first thermal interface material portion is spaced apart from the second underfill protrusion.

6. The semiconductor package of claim 5, wherein the second underfill protrusion is in contact with the first underfill protrusion. ​ 7. The semiconductor package of claim 5, wherein a sixth distance from a top surface of the first substrate to an uppermost point of an upper surface of the second underfill protrusion is equal to or less than 50% of a seventh distance from the top surface of the first substrate to a top surface of the second semiconductor structure.

8. The semiconductor package of claim 5, wherein the first semiconductor structure and the second semiconductor structure define a gap region between the first semiconductor structure and the second semiconductor structure, an upper end of the gap region corresponds to a lower one of a height of a top surface of the first semiconductor structure and a height of a top surface of the second semiconductor structure, a lower end of the gap region corresponds to a top surface of the first substrate, a first side of the gap region corresponds to the first sidewall, a second side of the gap region opposite the first side of the gap region corresponds to the third sidewall, and a sum of volumes of the first thermal interface material portion, the first underfill protrusion, and the second underfill protrusion located in the gap region is equal to or less than 90% of a total volume of the gap region.

9. The semiconductor package of claim 8, wherein the gap region includes an empty space not occupied by the first thermal interface material portion, the first underfill protrusion, and the second underfill protrusion, and a volume of the empty space is equal to or greater than 10% of the total volume of the gap region.

10. The semiconductor package of claim 1, further comprising: a second substrate under the first substrate, wherein the heat spreader is attached to the second substrate.

11. The semiconductor package of claim 10, further comprising: an adhesive layer between the heat spreader and the second substrate, wherein the adhesive layer includes a same material as a material of the thermal interface material layer.

12. The semiconductor package of claim 1, wherein each of the first semiconductor structure and the second semiconductor structure is one of a semiconductor chip and a sub-semiconductor package.

13. The semiconductor package of claim 1, wherein a profile of a cross-section of the first thermal interface material portion has a kink point at a lower surface thereof.

14. The semiconductor package of claim 13, wherein: a top surface of the first semiconductor structure is lower than a top surface of the second semiconductor structure, and the kink point is closer to the first semiconductor structure than to the second semiconductor structure.

15. The semiconductor package of claim 1, wherein one of the first semiconductor structure and the second semiconductor structure includes a sub-package substrate and at least one semiconductor chip mounted on the sub-package substrate, wherein the thermal interface material layer is in contact with a top surface of the semiconductor chip.

16. A semiconductor package, comprising: a first substrate; a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite the first sidewall; a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure, the second semiconductor structure including a third sidewall adjacent to the first semiconductor structure and a fourth sidewall opposite to the third sidewall; a heat spreader covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate; and a thermal interface material layer between the first semiconductor structure and the heat spreader and between the second semiconductor structure and the heat spreader, the thermal interface material layer including a plurality of thermal interface material portions constituting one single body, the plurality of thermal interface material portions including a first thermal interface material portion adjacent to the first sidewall and in contact with the first sidewall and the third sidewall, and a second thermal interface material portion adjacent to the second sidewall, the first thermal interface material portion being thicker than the second thermal interface material portion.

17. The semiconductor package of claim 16, further comprising: a first underfill layer between the first substrate and the first semiconductor structure, the first underfill layer including a first underfill protrusion protruding beyond the first sidewall, wherein the first thermal interface material portion is spaced apart from the first underfill protrusion.

18. The semiconductor package of claim 17, further comprising: a second underfill layer between the first substrate and the second semiconductor structure, the second underfill layer including a second underfill protrusion protruding beyond the third sidewall of the second semiconductor structure, wherein the first thermal interface material portion is spaced apart from the second underfill protrusion.

19. The semiconductor package of claim 18, wherein the second underfill protrusion is in contact with the first underfill protrusion.

20. The semiconductor package of claim 16, further comprising: a second substrate under the first substrate, wherein the heat spreader is attached to the second substrate.

21. The semiconductor package of claim 16, wherein a cross-section profile of the first thermal interface material portion has a kink point at its lower surface.

22. The semiconductor package of claim 16, wherein one of the first semiconductor structure and the second semiconductor structure includes at least one semiconductor chip, wherein the thermal interface material layer contacts a top surface of the semiconductor chip included in the one of the first semiconductor structure and the second semiconductor structure.

23. A semiconductor package, comprising: a package substrate; a first semiconductor structure and a second semiconductor structure mounted on the package substrate, the first semiconductor structure and the second semiconductor structure being spaced apart from each other in a direction parallel to a top surface of the package substrate; a heat spreader covering at least portions of the first semiconductor structure, the second semiconductor structure, and the package substrate; a layer of thermal interface material between the first semiconductor structure and the heat spreader and between the second semiconductor structure and the heat spreader, the layer of thermal interface material having different thicknesses depending on its location, the layer of thermal interface material having a maximum thickness at a location between the first semiconductor structure and the second semiconductor structure; an interposer substrate between the package substrate and the first semiconductor structure and between the package substrate and the second semiconductor structure; a first underfill layer between the interposer substrate and the first semiconductor structure, the first underfill layer protruding beyond a sidewall of the first semiconductor structure; and a second underfill layer between the interposer substrate and the second semiconductor structure, the second underfill layer protruding beyond a sidewall of the second semiconductor structure, wherein the layer of thermal interface material is spaced apart from both the first underfill layer and the second underfill layer.

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