Fabrication method of array substrate, array substrate and display panel

Abstract

The present invention provides a method for manufacturing an array substrate, an array substrate, and a display panel. The array substrate includes a substrate and metal oxide thin film transistors and polysilicon thin film transistors located on the substrate. The metal oxide thin film transistors and the polysilicon thin film transistors are arranged at intervals. The metal oxide thin film transistors are located in a first region and are used to drive pixel electrodes, and the polysilicon thin film transistors are located in a second region and are used to control the metal oxide thin film transistors. The method for manufacturing an array substrate, the array substrate, and the display panel provided by the embodiments of the present invention simultaneously adopt polysilicon thin film transistors and metal oxide thin film transistors, are designed in regions, are compatible in process, effectively solve the technical bottleneck of polysilicon thin film transistors, enable them to be applied to large-size display panels, and can effectively reduce the power consumption of the display panel.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display, and particularly to a manufacturing method of an array substrate, an array substrate and a display panel. Background Art

[0002] With the development of display technology, flat panel display devices such as liquid crystal displays (LCDs for short) have been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, and laptop computers due to their advantages of high-definition picture quality, power saving, thin body, and no radiation, and have become the mainstream in display devices. A liquid crystal display panel generally consists of an array substrate, a color filter substrate disposed opposite to each other, and a liquid crystal molecule layer sandwiched between the array substrate and the color filter substrate. By applying a driving voltage between the array substrate and the color filter substrate, the rotation of liquid crystal molecules can be controlled, so that the light of the backlight module is refracted to generate an image.

[0003] Currently, flat panel display devices are developing towards large size, high integration, high resolution, and high driving frequency, and the requirement for mobility is getting higher and higher. Therefore, the panel technology based on LTPS (Low Temperature Poly-silicon) TFT (Thin Film Transistor) has become the mainstream.

[0004] However, although the low-temperature poly-silicon thin film transistor provided by the above-mentioned prior art has a high mobility, its off-state current is large, and there is a problem of high power consumption when driving pixel electrodes with it. Summary of the Invention

[0005] The present invention provides a manufacturing method of an array substrate, an array substrate and a display panel. By simultaneously using a poly-silicon thin film transistor and a metal oxide thin film transistor, the power consumption of the display panel can be effectively reduced.

[0006] On one hand, the present invention provides a manufacturing method of an array substrate, including: depositing a first metal layer on a substrate, and through a first photolithography, forming a first gate located in a first region on the first metal layer;

[0007] Depositing a buffer layer and a metal oxide semiconductor layer, and through a second photolithography, forming a first semiconductor layer located in the first region on the metal oxide semiconductor layer;

[0008] Depositing an amorphous silicon layer, performing a first high-temperature annealing process to form a poly-silicon layer from the amorphous silicon layer, and through a third photolithography, forming a second semiconductor layer located in a second region on the poly-silicon layer, and forming a source / drain metal isolation layer on the first semiconductor layer on the poly-silicon layer;

[0009] Deposit an insulating layer and a second metal layer in sequence. Through the fourth photolithography, form a second gate of the second metal layer located in the second region.

[0010] Deposit a first metal oxide protection layer. Through the fifth photolithography, form a plurality of vias on the insulating layer and the first metal oxide protection layer.

[0011] Deposit a third metal layer. Through the sixth photolithography, form a first source electrode and a first drain electrode of the first region and a second source electrode and a second drain electrode of the second region with the third metal layer, and make the first source electrode and the first drain electrode communicate with the first semiconductor layer through the vias respectively, and the second source electrode and the second drain electrode communicate with the second semiconductor layer through the vias respectively.

[0012] The manufacturing method as described above further includes:

[0013] Deposit a second metal oxide protection layer. Through the seventh photolithography, form a contact via located in the first region on the second metal oxide protection layer.

[0014] Deposit a transparent conductive layer. Through the eighth photolithography, form a pixel electrode with the transparent conductive layer and make the pixel electrode communicate with the first drain electrode through the contact via.

[0015] The manufacturing method as described above, the deposition of the buffer layer specifically includes:

[0016] Deposit a first buffer layer and a second buffer layer in sequence. The first buffer layer is silicon nitride and the second buffer layer is silicon oxide, and then perform a high-temperature annealing process once to reduce the hydrogen content in the second buffer layer.

[0017] The manufacturing method as described above, the thickness of the first buffer layer is The thickness of the second buffer layer is

[0018] The manufacturing method as described above, the first photolithography further includes: forming a light-shielding layer of the second region with the first metal layer.

[0019] The manufacturing method as described above, the projections of the second source electrode and the second drain electrode on the substrate are located within the projection range of the light-shielding layer on the substrate.

[0020] The manufacturing method as described above, the first region is the display area of the array substrate, and the second region is the peripheral circuit area of the array substrate.

[0021] The manufacturing method as described above, the high-temperature annealing process includes an excimer laser annealing process.

[0022] The manufacturing method as described above, wherein the high-temperature annealing process includes annealing at a temperature above 600°C using a rapid annealing furnace.

[0023] On the other hand, the present invention provides an array substrate, which is manufactured according to the manufacturing method as described above, and includes: a substrate substrate, and a first thin-film transistor and a second thin-film transistor respectively located on a first region and a second region of the substrate substrate;

[0024] The first thin-film transistor includes a first gate, a buffer layer, a first semiconductor layer, an insulating layer, a first metal oxide protection layer, and a source-drain metal isolation layer. A first source electrode and a first drain electrode are disposed on the source-drain metal isolation layer. A plurality of vias are provided on the insulating layer and the first metal oxide protection layer. The first source electrode and the first drain electrode are connected to the first semiconductor layer through the vias;

[0025] The second thin-film transistor includes a second semiconductor layer, an insulating layer, a second gate, and a first metal oxide protection layer which are sequentially disposed. A second source electrode and a second drain electrode are disposed on the first metal oxide protection layer. The second semiconductor layer is located in the second region and covers the buffer layer. The second source electrode and the second drain electrode are respectively connected to the second semiconductor layer through the vias;

[0026] The first semiconductor layer is a metal oxide semiconductor layer, and the second semiconductor layer and the source-drain metal isolation layer are polysilicon layers.

[0027] The present invention further provides a display panel, including the array substrate as described above.

[0028] The manufacturing method of the array substrate, the array substrate and the display panel provided by the embodiments of the present invention design the array substrate as a dual thin-film transistor structure. By utilizing the characteristics of high mobility of polysilicon thin-film transistors, the polysilicon thin-film transistors control the metal oxide thin-film transistors, and at the same time, the metal oxide thin-film transistors drive the pixel electrodes. Such a design can make full use of the advantages of polysilicon thin-film transistors and metal oxide thin-film transistors. On the one hand, it can meet the requirements of high integration and high mobility requirements in the peripheral area. On the other hand, it can reduce the power consumption of the display panel. At the same time, silicon oxide is used as the buffer layer to directly contact the metal oxide semiconductor layer to avoid hydrogen diffusion into the metal oxide semiconductor layer. After depositing the buffer layer, a high-temperature annealing process is performed on the buffer layer to reduce the hydrogen in the buffer layer and further improve the performance of the metal oxide thin-film transistors. By arranging a polysilicon thin film between the first source electrode, the first drain electrode and the metal oxide semiconductor layer, the first source electrode and the first drain electrode are in contact with the metal oxide semiconductor layer through the polysilicon thin film, which improves the on-state current and performance of the metal oxide thin-film transistors. By making full use of the characteristics of the manufacturing process of metal oxide thin-film transistors and the manufacturing process of polysilicon thin-film transistors, without increasing the process steps, the performance and stability of the metal oxide thin-film transistors are improved by reasonably designing the structure and process flow of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 It is a schematic structural diagram of the array substrate provided by the embodiments of the present invention;

[0031] Figure 2 It is a flowchart of the manufacturing method of the array substrate provided by the embodiments of the present invention;

[0032] Figure 3 It is a schematic structural diagram of the array substrate after completing step S101 provided by the embodiments of the present invention;

[0033] Figure 4 It is a schematic structural diagram of the array substrate after completing step S102 provided by the embodiments of the present invention;

[0034] Figure 5 It is a schematic structural diagram of the array substrate after completing step S103 provided by the embodiments of the present invention;

[0035] Figure 6Schematic diagram of the array substrate provided by the embodiment of the present invention after completing step S104;

[0036] Figure 7 Schematic diagram of the array substrate provided by the embodiment of the present invention after completing step S105;

[0037] Figure 8 Schematic diagram of the array substrate provided by the embodiment of the present invention after completing step S106;

[0038] Figure 9 Schematic diagram of the array substrate provided by the embodiment of the present invention after completing step S107.

[0039] Reference numerals:

[0040] 11 - First region;

[0041] 12 - Second region;

[0042] 13 - Substrate;

[0043] 141 - First gate;

[0044] 142 - Light-shielding layer;

[0045] 151 - First buffer layer;

[0046] 152 - Second buffer layer;

[0047] 16 - First semiconductor layer;

[0048] 171 - Source-drain metal isolation layer;

[0049] 172 - Second semiconductor layer;

[0050] 18 - Insulating layer;

[0051] 19 - Second gate;

[0052] 20 - First metal oxide protection layer;

[0053] 211 - First drain;

[0054] 212 - First source;

[0055] 213 - Second source;

[0056] 214 - Second drain;

[0057] 22 - Second metal oxide protection layer;

[0058] 23 - Pixel electrode;

[0059] 241 - Via;

[0060] 25 - Contact via hole. Detailed implementation mode

[0061] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0062] Embodiment 1

[0063] Figure 1 It is a schematic structural diagram of the array substrate provided by the embodiment of the present invention. Refer to Figure 1 As shown, the array substrate provided by the embodiment of the present invention has a dual thin - film transistor structure, including a substrate 13, and a first thin - film transistor and a second thin - film transistor located on the substrate 13. Among them, the first thin - film transistor is a metal - oxide thin - film transistor, and the second thin - film transistor is a polysilicon thin - film transistor. The two thin - film transistors are arranged at intervals. For the convenience of description, Figure 1 the array substrate is divided into two regions. The left dashed box is the first region 11, and the right dashed box is the second region 12. The metal - oxide transistor is located in the first region 11, and the polysilicon thin - film transistor is located in the second region 12. It should be noted that the dashed box is not an actual structure in the array substrate, but is shown only for the convenience of description in Figure 1 and is not shown in the subsequent drawings.

[0064] The array substrate provided by the embodiment of the present invention has a dual thin - film transistor structure. By utilizing the characteristic of the high mobility of the polysilicon thin - film transistor, it controls the metal - oxide thin - film transistor, and at the same time makes the metal - oxide thin - film transistor drive the pixel electrode. Such a design can make full use of the advantages of the polysilicon thin - film transistor and the metal - oxide thin - film transistor. On the one hand, it can meet the requirements of high integration degree and high mobility requirements in the peripheral circuit area. On the other hand, it can reduce the power consumption of the display panel.

[0065] The metal - oxide thin - film transistor includes a first gate 141, a buffer layer, a first semiconductor layer 16, an insulating layer 18, and a first metal - oxide protection layer 20 that are sequentially arranged on the substrate 13. A first drain 211 and a first source 212 are arranged on the first metal - oxide protection layer 20. There are two vias 241 on the insulating layer 18 and the first metal - oxide protection layer 20 located in the first region 11: the first drain 211 and the first source 212 are connected to the first semiconductor layer 16 through the vias 241.

[0066] The first gate 141 can be made of metals or alloys such as Cr, W, Cu, Ti, Ta, Mo, etc., or a black organic resin, or other light-blocking materials, and is formed by deposition using sputtering or thermal evaporation, with a thickness of about

[0067] The first semiconductor layer 16 is a metal oxide semiconductor layer, which is formed by deposition using sputtering or thermal evaporation, with a thickness of about The metal oxide semiconductor layer can be indium gallium zinc oxide IGZO, or it can also be lithium niobate indium zinc oxide Ln-IZO, indium tin zinc oxide ITZO, ITGZO, hydrogenated indium zinc oxide HIZO, indium zinc oxide IZO (InZnO), fluorine-doped zinc oxide ZnO:F, tin-doped indium oxide In 2 O 3 :Sn, molybdenum-doped indium oxide In 2 O 3 :Mo, cadmium stannate Cd 2 SnO 4 、aluminum-doped zinc oxide ZnO:Al, niobium-doped titanium dioxide TiO 2 :Nb, Cd-Sn-O or other metal oxides.

[0068] The buffer layer is divided into two layers and is formed by deposition using plasma-enhanced chemical vapor deposition (PECVD). The bottom layer is the first buffer layer 151, which can be silicon nitride SiNx, with a thickness of The corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 The upper layer is the second buffer layer 152, which is made of silicon oxide, with a thickness of The corresponding reaction gases are SiH 4 , N 2 O. The layer in contact with the metal oxide semiconductor layer is the second buffer layer 152. Since the silicon nitride layer has a high hydrogen content, if the metal oxide semiconductor layer is in direct contact with it, the hydrogen in it will diffuse into the metal oxide semiconductor, resulting in the failure of the metal oxide thin film transistor. To improve the stability of the thin film transistor, silicon oxide is used as the second buffer layer 152 to be in direct contact with the metal oxide semiconductor layer. After depositing the buffer layer, a high-temperature annealing process can be performed on the buffer layer to reduce the hydrogen in the buffer layer, and at the same time, it can prevent the explosion of hydrogen when forming polycrystalline silicon using excimer laser annealing (ELA) process later. While improving the performance of the metal oxide thin film transistor, it also prevents the occurrence of a large hydrogen explosion when forming polycrystalline silicon.

[0069] The insulating layer 18 can be made of silicon oxide and deposited by plasma enhanced chemical vapor deposition (PECVD). The corresponding reaction gas can be SiH 4 , N 2 O; metal oxides can also be used, such as Al formed by magnetron sputtering 2 O 3 .

[0070] The first drain 211 and the first source 212 are deposited by sputtering or thermal evaporation, and metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu may be used. A metal layer composed of multiple layers of metals may also meet the needs.

[0071] When the first drain electrode 211 and the first source electrode 212 are in direct contact with the metal oxide semiconductor layer, they will react with the metal oxide semiconductor layer and take away oxygen in the metal oxide semiconductor layer. The metal oxide semiconductor layer is very sensitive to oxygen, and the performance of the thin film transistor deteriorates after losing oxidation. Therefore, a source-drain metal isolation layer 171 is provided between the first drain electrode 211, the first source electrode 212 and the metal oxide semiconductor layer. The first drain electrode 211 and the first source electrode 212 are not in direct contact with the metal oxide semiconductor layer, but are first in contact with the source-drain metal isolation layer 171, and then the source-drain metal isolation layer 171 is in direct contact with the metal oxide semiconductor layer. The source-drain metal isolation layer 171 is a polysilicon layer, which has good electrical conductivity, can reduce the contact resistance between the first drain electrode 211, the first source electrode 212 and the metal oxide semiconductor layer, improve the on-state current of the metal oxide thin film transistor and increase its conduction capacity; the polysilicon layer can also improve the characteristics of the contact interface between the metal oxide semiconductor layer and the source and drain electrodes, and improve the performance of the metal oxide thin film transistor.

[0072] The metal oxide thin film transistor is used to drive the pixel electrode 23. Specifically, the first gate 141 of the metal oxide thin film transistor is connected to the scan line and receives the scan signal transmitted by the scan line, and the first source 212 is connected to the data line and receives the data signal transmitted by the data line, thereby providing an operating voltage for the pixel electrode 23.

[0073] Polysilicon thin film transistors are used to connect to peripheral circuits to control metal oxide thin film transistors. Since polysilicon thin film transistors have the characteristic of low off current, only a low threshold voltage is needed to ensure that the voltage between the gate and source of the polysilicon thin film transistor is zero, so that the polysilicon thin film transistors of the peripheral circuits are in the off state, ensuring the normal operation of the peripheral circuits of the array substrate.

[0074] It should be noted that a storage capacitor is also provided on the array substrate. The storage capacitor is formed between the electrode metal layer and the pixel electrode and is electrically connected to the metal oxide thin film transistor and the polysilicon thin film transistor respectively, enabling the two thin film transistors to play the roles of switch and control respectively.

[0075] The polysilicon thin film transistor has a top-gate structure and is disposed on the second buffer layer 152. It includes a second semiconductor layer 172, an insulating layer 18, a second gate 19, a first metal oxide protection layer 20 that are sequentially disposed on the second buffer layer 152. The second source electrode 213 and the second drain electrode 214 are disposed on the first metal oxide protection layer 20. There are two vias 241 on the insulating layer 18 and the first metal oxide semiconductor layer in the second region 12. The second source electrode 213 and the second drain electrode 214 are connected to the second semiconductor layer 172 through the vias 241.

[0076] The second semiconductor layer 172 is a polysilicon semiconductor layer, which is formed by performing high-temperature annealing on an amorphous silicon layer. The excimer laser annealing process can be used to melt the amorphous silicon layer within a short time and recrystallize it into a polysilicon layer. Excimer laser annealing means that a laser with a certain beam shape is scanned on the surface of a substrate coated with amorphous silicon. After heating for several nanoseconds, the amorphous silicon melts and recrystallizes into polysilicon. An excimer is a composite particle in an excited state. Under standard conditions, that is, in the ground state, it is in a separated state, while in the excited state, it is in a molecular state. High-temperature annealing can also be performed using a rapid annealing furnace, such as annealing at a temperature above 600 °C to melt the amorphous silicon and grow it into a polysilicon layer again. The source-drain metal isolation layer 171 and the second semiconductor layer 172 are formed in the same photolithography process.

[0077] The second gate 19 is deposited by sputtering or thermal evaporation, and the thickness is Metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. can be selected, and a gate metal layer composed of multiple layers of metals can also meet the requirements.

[0078] The first metal oxide protection layer 20 can be selected from oxides or oxynitrides and is deposited by the PECVD method, and the thickness is The reaction gas corresponding to the oxide of silicon can be SiH4 and N2O; the corresponding gases for nitrides or oxynitrides are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .

[0079] The second source electrode 213 and the second drain electrode 214 are formed in the same photolithography process as the first drain electrode 211 and the first source electrode 212, and the materials used are also the same.

[0080] The array substrate provided by the embodiment of the present invention further includes a light-shielding layer 142 disposed between the substrate 13 and the first buffer layer 151. The light-shielding layer 142 is located below the second semiconductor layer 172. The light-shielding layer 142 and the first gate electrode 141 are formed in the same photolithography process, and the material is the same as that of the first gate electrode 141. The light-shielding layer 142 is disposed below the second semiconductor layer 172, and can block ambient light or the backlight source to prevent light from irradiating on the second semiconductor layer 172 and affecting the performance of the polysilicon thin-film transistor.

[0081] The projections of the second source electrode 213 and the second drain electrode 214 on the substrate 13 are located within the projection range of the light-shielding layer 142 on the substrate 13. Such a setting can prevent light from irradiating on the channel region between the second source electrode 213 and the second drain electrode 214 and avoid generating extra current. The array substrate provided by the embodiment of the present invention further includes a second metal oxide protection layer 22 and a pixel electrode 23. The second metal oxide protection layer 22 covers the first drain electrode 211, the first source electrode 212, the second source electrode 213, and the second drain electrode 214. The second metal oxide protection layer 22 has contact vias 25, and the pixel electrode 23 covers the second metal oxide protection layer 22 and is connected to the first drain electrode 211 through the contact vias 25.

[0082] The second metal oxide protection layer 22 is deposited by PECVD method, and the thickness is Oxides or oxynitrides can be selected. The reaction gas corresponding to the oxide of silicon can be SiH 4 , N 2 O; the corresponding gases for nitrides or oxynitrides are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .

[0083] The pixel electrode 23 can be indium tin oxide ITO or indium zinc oxide IZO, or other transparent metal oxides, and the thickness is about

[0084] The array substrate provided by the embodiment of the present invention is designed as a dual thin-film transistor structure. By utilizing the characteristics of high mobility of polycrystalline silicon thin-film transistors, the polycrystalline silicon thin-film transistors control the metal oxide thin-film transistors, and at the same time, the metal oxide thin-film transistors drive the pixel electrodes. Such a design can make full use of the advantages of polycrystalline silicon thin-film transistors and metal oxide thin-film transistors. On the one hand, it can meet the requirements of high integration in the peripheral area and high mobility requirements. On the other hand, it can reduce the power consumption of the display panel. At the same time, silicon oxide is used as the second buffer layer to be in direct contact with the metal oxide semiconductor layer to avoid hydrogen diffusion into the metal oxide semiconductor layer. After depositing the buffer layer, a high-temperature annealing process is performed on the buffer layer to reduce the hydrogen in the buffer layer and further improve the performance of the metal oxide thin-film transistors. A polycrystalline silicon thin film is provided between the first source electrode, the first drain electrode and the metal oxide semiconductor layer, so that the first source electrode and the first drain electrode are in contact with the metal oxide semiconductor layer through the polycrystalline silicon thin film, improving the on-state current and performance of the metal oxide thin-film transistors.

[0085] Embodiment 2

[0086] Figure 2 It is a flowchart of the manufacturing method of the array substrate provided by the embodiment of the present invention. Refer to Figure 2 As shown, the embodiment of the present invention provides a manufacturing method of an array substrate, including the following steps:

[0087] S101. Deposit a first metal layer on the substrate 13. Through the first photolithography, the first metal layer forms a first gate electrode 141 located in the first region 11 and a light-shielding layer 142 located in the second region 12.

[0088] Figure 3 It is a schematic structural diagram of the array substrate provided by the embodiment of the present invention after completing step S101. Refer to Figure 3 As shown, a first metal layer with a thickness of about is sequentially deposited on the substrate 13 by sputtering or thermal evaporation. The substrate 13 can be selected from a glass substrate or an organic substrate, such as a substrate made of materials such as PI and PET. The first metal layer can be selected from metals or alloys such as Cr, W, Cu, Ti, Ta, Mo, etc., or a black organic resin, or other light-blocking materials. After the first photolithography, the first metal layer forms a first gate electrode 141 located in the first region 11 and a light-shielding layer 142 located in the second region 12.

[0089] S102. Deposit a buffer layer and a metal oxide semiconductor layer. Through the second photolithography, the metal oxide semiconductor layer forms a first semiconductor layer 16 located in the first region 11.

[0090] Figure 4Schematic diagram of the structure of the array substrate provided by the embodiment of the present invention after completing step S102, as shown in Figure 3 After that, a buffer layer with a thickness of is continuously deposited on the substrate 13 that has completed step S101 by the PECVD method. The buffer layer is divided into two layers. The bottom layer is the first buffer layer 151, which can be silicon nitride SiNx, and the deposited thickness is The corresponding reaction gases are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 ; The upper layer is the second buffer layer 152, which is made of silicon oxide, and the deposited thickness is The corresponding gas used is SiH 4 , N 2 O.

[0091] Then, a metal oxide semiconductor layer with a thickness of about is deposited by sputtering or thermal evaporation. The metal oxide semiconductor layer can be indium gallium zinc oxide IGZO, or it can also be lithium niobate indium zinc oxide Ln-IZO, indium tin zinc oxide ITZO, ITGZO, hydrogenated indium zinc oxide HIZO, indium zinc oxide IZO (InZnO), fluorine-doped zinc oxide ZnO:F, tin-doped indium oxide In 2 O 3 :Sn, molybdenum-doped indium oxide In 2 O 3 :Mo, cadmium stannate Cd 2 SnO 4 , aluminum-doped zinc oxide ZnO:Al, niobium-doped titanium dioxide TiO 2 :Nb, Cd-Sn-O or other metal oxides. Through the second photolithography, the metal oxide semiconductor layer forms the first semiconductor layer 16 located in the first region 11.

[0092] Figure 4 The second buffer layer 152 in that contacts the metal oxide semiconductor layer is made of silicon oxide. If silicon nitride or silicon oxynitride is used, since the hydrogen content in silicon nitride or silicon oxynitride is relatively high, the hydrogen therein will diffuse into the metal oxide semiconductor layer, resulting in the failure of the thin film transistor in the metal oxide semiconductor layer. In order to improve the stability of the thin film transistor, a high-temperature annealing process is performed on the first buffer layer and the second buffer layer to reduce the hydrogen content therein and improve the performance of the metal oxide thin film transistor. Doing so can also prevent a large hydrogen explosion from occurring during the subsequent high-temperature annealing process of amorphous silicon.

[0093] S103 , depositing an amorphous silicon layer, performing a high temperature annealing process to form the amorphous silicon layer into a polycrystalline silicon layer, and performing a third photolithography to form the polycrystalline silicon layer into a second semiconductor layer 172 located in the second region 12 .

[0094] Figure 5 The schematic diagram of the structure of the array substrate after completing step S103 provided by the embodiment of the present invention is as follows Figure 5 As shown, on the substrate 13 after completing step S102, a PECVD method is used to continuously deposit a thickness of An amorphous silicon layer is then subjected to a high temperature annealing process, such as using an excimer laser annealing process to melt the amorphous silicon layer in a short time, and recrystallize and grow it into a polycrystalline silicon layer. A fast annealing furnace can also be used for high temperature annealing, such as annealing at a temperature above 600°C, to melt the amorphous silicon layer and grow it into a polycrystalline silicon layer again; through a third photolithography, the amorphous silicon layer is formed into a second semiconductor layer 172 located in the second region 12.

[0095] When depositing amorphous silicon, some hydrogen atoms will enter the metal oxide semiconductor layer, causing the performance of the metal oxide thin film transistor to deteriorate. However, in the subsequent high-temperature annealing process to form polycrystalline silicon, the annealing temperature is higher than 450°C, and the hydrogen diffused into the metal oxide semiconductor layer escapes, allowing the metal oxide thin film transistor to restore its original performance, or even better than the original performance.

[0096] In addition, the source and drain electrodes in contact with the metal oxide semiconductor layer are generally metal Mo, Ti or Mo alloy, Ti alloy, which will react with the metal oxide semiconductor layer, capture oxygen in the metal oxide semiconductor layer, and form Mo oxide or Ti oxide. The metal oxide semiconductor layer is very sensitive to oxygen, and the performance of the thin film transistor deteriorates after oxidation. Therefore, in the third photolithography, the polysilicon layer is retained in the source and drain contact area on the first semiconductor layer 16, so that the polysilicon layer forms a source and drain metal isolation layer 171 located on the first semiconductor layer 16, so that the source and drain electrodes are in contact with the first semiconductor layer 16 through the source and drain metal isolation layer 171. The source and drain metal isolation layer 171 can improve the characteristics of the contact interface between the metal oxide semiconductor layer and the source and drain electrodes, and improve the performance of the metal oxide thin film transistor. The source and drain metal isolation layer 171 also has good conductivity, reduces the contact resistance between the source and drain electrodes and the metal oxide semiconductor layer, improves the on-state current of the metal oxide thin film transistor, and increases its conduction capability.

[0097] S104 , depositing an insulating layer 18 and a second metal layer in sequence, and performing a fourth photolithography to form the second metal layer into a second gate 19 located in the second region 12 .

[0098] Figure 6 The schematic diagram of the structure of the array substrate after the step S104 is completed according to the embodiment of the present invention.Figure 6 As shown, an insulating layer 18 with a thickness of is deposited on the substrate 13 after step S103 by PECVD method. The insulating layer 18 can be selected as silicon oxide, and the corresponding reaction gases can be SiH4 and N2O. Metal oxides can also be used, such as forming Al2O3 by magnetron sputtering method. Then, a second metal layer with a thickness of about is sequentially deposited by sputtering or thermal evaporation. The second metal layer can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. A gate metal layer composed of multiple layers of metals can also meet the requirements. Through the fourth photolithography, the second metal layer forms the second gate 19 located in the second region 12.

[0099] S105. Deposit the first metal oxide protection layer 20. Through the fifth photolithography, a plurality of vias 241 are formed on the insulating layer 18 and the first metal oxide protection layer 20.

[0100] Figure 7 FIG. is a schematic structural diagram of the array substrate provided by the embodiment of the present invention after step S105. As Figure 7 shown, a first metal oxide protection layer 20 with a thickness of is deposited on the substrate 13 after step S104 by PECVD method. The first metal oxide protection layer 20 can be selected as an oxide or an oxynitride. The corresponding reaction gas for silicon oxide can be SiH 4 , N 2 O; the corresponding gases for nitrides or oxynitrides are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 ; through the fifth photolithography, a plurality of vias 241 are formed on the insulating layer 18 and the first metal oxide protection layer 20.

[0101] S106. Deposit the third metal layer. Through the sixth photolithography, the third metal layer forms the first drain 211 and the first source 212 located in the first region 11 and the second source 213 and the second drain 214 located in the second region 12. The first drain 211 and the first source 212 are respectively connected to the first semiconductor layer 16 through the vias 241, and the second source 213 and the second drain 214 are respectively connected to the second semiconductor layer 172 through the vias 241.

[0102] Figure 8 FIG. is a schematic structural diagram of the array substrate provided by the embodiment of the present invention after step S106. As Figure 8As shown, on the substrate 13 after completing step S105, a third metal layer with a thickness of about is deposited in sequence by sputtering or thermal evaporation. The third metal layer can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. A gate metal layer composed of multiple layers of metal can also meet the requirements; through the sixth photolithography, the third metal layer forms a first drain 211 and a first source 212 located in the first region 11 and a second source 213 and a second drain 214 located in the second region 12. The first drain 211 and the first source 212 are respectively connected to the first semiconductor layer 16 through vias 241, and the second source 213 and the second drain 214 are respectively connected to the second semiconductor layer 172 through vias 241.

[0103] Among them, the projections of the second source 213 and the second drain 214 on the substrate 13 are located within the projection range of the light-shielding layer 142 on the substrate 13.

[0104] Furthermore, when the polysilicon layer on the first semiconductor layer 16 is retained in the third photolithography, the polysilicon layer forms a source-drain metal isolation layer 171. Then, in the sixth photolithography, the first drain 211 and the first source 212 are in contact with and connected to the source-drain isolation layer 171 through vias 241, rather than directly contacting the first semiconductor layer 16.

[0105] Specifically, the manufacturing method of the array substrate further includes the following steps:

[0106] S107. Deposit a second metal oxide protection layer 22, and form a contact via 25 on the second metal oxide protection layer 22 through the seventh photolithography.

[0107] Figure 9 FIG. is a schematic structural diagram of the array substrate provided by the embodiment of the present invention after completing step S106. As Figure 9 shown, a second metal oxide protection layer 22 with a thickness of is deposited on the substrate 13 after completing step S106 by the PECVD method. Oxides or oxynitrides can be selected. The reaction gas corresponding to the oxide of silicon can be SiH 4 , N 2 O; the corresponding gases for nitrides or oxynitrides are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 ; through the seventh photolithography, a contact via 25 is formed on the second metal oxide protection layer 22.

[0108] S108. Deposit a transparent conductive layer. Through the eighth photolithography, the transparent conductive layer forms the pixel electrode 23 and the pixel electrode 23 is connected to the first drain 211 through the contact via 25.

[0109] Deposit a transparent conductive layer with a thickness of approximately on the substrate 13 after completing step S107. The transparent conductive layer can be ITO or IZO, or other transparent metal oxides. Through the eighth photolithography, the transparent conductive layer forms the pixel electrode 23 and the pixel electrode 23 is connected to the first drain 211 through the contact via 25. The structure of the array substrate after completing step S108 is as Figure 1 shown.

[0110] The manufacturing method of the array substrate provided by the embodiment of the present invention makes full use of the influence of the manufacturing processes of metal oxide thin film transistors and polysilicon thin film transistors. Without increasing the process steps, by reasonably designing the structure and process flow of the array substrate, the performance and stability of the metal oxide thin film transistors are improved.

[0111] Embodiment III

[0112] This embodiment provides a display panel, which includes the array substrate described in the above embodiment.

[0113] In the description of the present invention, it should be understood that the terms "center", "length", "width", "thickness", "top end", "bottom end", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated position or element must have a specific orientation, be constructed and operated in a specific manner. Therefore, it should not be construed as a limitation to the present invention.

[0114] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0115] In the present invention, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected to", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or capable of communicating with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal connection of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0116] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A manufacturing method of an array substrate, characterized in that, comprising: Depositing a first metal layer on a substrate, and through a first photolithography, forming a first gate located in a first region on the first metal layer; Depositing a buffer layer and a metal oxide semiconductor layer, and through a second photolithography, forming a first semiconductor layer located in the first region on the metal oxide semiconductor layer; Depositing an amorphous silicon layer, performing a high-temperature annealing process once to form a polysilicon layer from the amorphous silicon layer, and through a third photolithography, forming a second semiconductor layer located in a second region on the polysilicon layer, and forming a source-drain metal isolation layer on the first semiconductor layer from the polysilicon layer; Sequentially depositing an insulating layer and a second metal layer, and through a fourth photolithography, forming a second gate located in the second region on the second metal layer; Depositing a first metal oxide protection layer, and through a fifth photolithography, forming a plurality of vias on the insulating layer and the first metal oxide protection layer; Depositing a third metal layer, and through a sixth photolithography, forming a first source electrode and a first drain electrode located in the first region and a second source electrode and a second drain electrode located in the second region on the third metal layer, and connecting the first source electrode and the first drain electrode to the first semiconductor layer through the vias respectively, and connecting the second source electrode and the second drain electrode to the second semiconductor layer through the vias respectively.

2. The manufacturing method according to claim 1, characterized in that, further comprising: Depositing a second metal oxide protection layer, and through a seventh photolithography, forming a contact via on the second metal oxide protection layer; Depositing a transparent conductive layer, and through an eighth photolithography, forming a pixel electrode on the transparent conductive layer and connecting the pixel electrode to the first drain electrode through the contact via.

3. The manufacturing method according to claim 1, characterized in that, the depositing of the buffer layer specifically comprises: Sequentially depositing a first buffer layer and a second buffer layer, the first buffer layer being silicon nitride and the second buffer layer being silicon oxide, and then performing a high-temperature annealing process once to reduce the hydrogen content in the second buffer layer.

4. The manufacturing method according to claim 3, characterized in that, the thickness of the first buffer layer is 1000 - 4000 Å, and the thickness of the second buffer layer is 200 - 2000 Å.

5. The manufacturing method according to claim 1, characterized in that, the first photolithography further comprises: forming a light-shielding layer located in the second region on the first metal layer.

6. The manufacturing method according to claim 5, characterized in that, the projections of the second source electrode and the second drain electrode on the substrate are located within the projection range of the light-shielding layer on the substrate.

7. The manufacturing method according to claim 1, characterized in that, the high-temperature annealing process includes an excimer laser annealing process.

8. The manufacturing method according to claim 1, characterized in that, the high-temperature annealing process includes annealing using a rapid thermal annealing furnace at a temperature above 600 °C.

9. An array substrate, characterized in that, Manufactured by using the manufacturing method according to any one of claims 1-8, comprising a substrate and a first thin film transistor and a second thin film transistor located on the substrate; the first thin film transistor is located in a first region, and the second thin film transistor is located in a second region; The first thin film transistor includes a first gate, a buffer layer, a first semiconductor layer, an insulating layer, a first metal oxide protection layer, and a source-drain metal isolation layer arranged in sequence. A first source electrode and a first drain electrode are arranged on the source-drain metal isolation layer. A plurality of vias are arranged on the insulating layer and the first metal oxide protection layer. The first source electrode and the first drain electrode are connected to the first semiconductor layer through the vias; The second thin film transistor includes a second semiconductor layer, the insulating layer, a second gate, and the first metal oxide protection layer arranged in sequence. A second source electrode and a second drain electrode are arranged on the first metal oxide protection layer. The second semiconductor layer is located in the second region and covers the buffer layer. The second source electrode and the second drain electrode are respectively connected to the second semiconductor layer through the vias; The first semiconductor layer is a metal oxide semiconductor layer, and the second semiconductor layer and the source-drain metal isolation layer are polysilicon layers; The first semiconductor layer is arranged on a second buffer layer, and the second semiconductor layer is arranged on the second buffer layer; the source-drain metal isolation layer is arranged on the first semiconductor layer and is located on the side of the first semiconductor layer facing away from the substrate.

10. A display panel, Characterized in that, It includes the array substrate according to claim 9.

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