Display device

Abstract

The present disclosure relates to a display device, which includes: a substrate, a transistor layer, a plurality of partition walls, a light-emitting element, and a spacer, wherein the substrate has a display area and a non-display area located at the periphery of the display area; the transistor layer is arranged on the substrate; the plurality of partition walls are arranged on the transistor layer in the display area; the light-emitting element is arranged between the partition walls; and the spacer is configured to be arranged in the non-display area of ​​the substrate, wherein the spacer may include a spacer body arranged on the same layer as the partition walls and arranged on at least a portion of the transistor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0082807, filed on Jul. 17, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the invention relate to a display device, and more particularly, to a display device capable of preventing damage to the display device during a manufacturing process using a mask. Background Art

[0004] A pixel of an organic light emitting diode (OLED) display includes two electrodes and an organic emission layer interposed therebetween, wherein electrons injected from a cathode, one of the two electrodes, and holes injected from an anode are recombined in the organic emission layer to generate excitons, and the generated excitons release energy to emit light.

[0005] An organic emission layer of an OLED display may be formed by using a mask during a manufacturing process. However, the display device and the mask come into contact with each other during a process of positioning the mask. Such contact causes the display device to be damaged.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] A display device constructed according to an exemplary embodiment of the invention is capable of preventing a display such as an organic light emitting diode from being damaged during a manufacturing process by minimizing the height difference between partition wall spacers in a display area and spacers in a non-display area and / or adjusting the density of partition wall spacers in the display area relative to the density of spacers in the non-display area.

[0008] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0009] According to one aspect of the invention, a display device includes: a substrate, a transistor layer, a plurality of partition walls, a light-emitting element, and a spacer, wherein the substrate has a display area and a non-display area located at the periphery of the display area; the transistor layer is arranged on the substrate; a plurality of partition walls are arranged on the transistor layer in the display area; the light-emitting element is arranged between the partition walls; and the spacer is arranged in the non-display area of ​​the substrate, wherein the spacer may include a spacer body arranged on the same layer as the partition walls and arranged on at least a portion of the transistor layer.

[0010] The transistor layer may include a source electrode and a drain electrode, and the spacer may include a dummy electrode disposed in the same layer as the source electrode and the drain electrode.

[0011] The transistor layer may further include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer, and the spacer may include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer.

[0012] The transistor layer may further include a coating layer coating the source electrode and the drain electrode, and the spacer may further include a coating layer disposed on the dummy electrode.

[0013] The transistor layer may include two or more data conductors disposed on different layers, and the spacer may include two or more data conductors disposed on different layers.

[0014] A plurality of partition wall spacers may be disposed on some of the plurality of partition walls.

[0015] Each of the plurality of partition walls and the plurality of partition wall spacers may be formed of the same material and connected to each other.

[0016] A ratio of partition walls where the partition wall spacers are disposed among all partition walls may be about 10% to about 20%.

[0017] A ratio of a height of the spacer to a sum of heights of the partition wall and the partition wall spacer may be about 0.7 to about 1.

[0018] The height of the spacer may be about 3 μm to about 6 μm.

[0019] The spacer may be disposed to be separated from an edge of the display area by about 150 μm to about 200 μm.

[0020] The spacer body may include the same material as that of the partition wall.

[0021] The display device may further include a dam disposed in the non-display area, and the spacer may be disposed between the dam and the display area.

[0022] According to another aspect of the invention, a display device includes: a substrate, a transistor layer, a plurality of partition walls, a plurality of partition wall spacers, a light-emitting element, and a spacer, wherein the substrate has a display area and a non-display area located at the periphery of the display area; the transistor layer is arranged on the substrate; a plurality of partition walls are arranged on the transistor layer in the display area; a plurality of partition wall spacers are arranged on some of the plurality of partition walls; the light-emitting element is arranged between the partition walls; and the spacer is arranged in the non-display area of ​​the substrate, wherein the spacers arranged in the non-display area can be arranged at a density higher than the density of the partition wall spacers arranged in the display area.

[0023] A ratio of partition walls provided with the partition wall spacer among all partition walls provided in the display region may be about 10% to about 20%.

[0024] An arrangement density of the spacers disposed in the non-display region may be about 1.5 to about 3 times an arrangement density of the partition wall spacers disposed in the display region.

[0025] The partition wall and the partition wall spacer may include the same material, and may be connected to each other.

[0026] The spacer may include a spacer body disposed on the same layer as the partition wall and disposed on at least a portion of the transistor layer.

[0027] The transistor layer may include a source electrode and a drain electrode, and the spacer may include a dummy electrode disposed in the same layer as the source electrode and the drain electrode.

[0028] The transistor layer may further include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer, and the spacer may further include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer.

[0029] A ratio of a height of the spacer to a sum of heights of the partition wall and the partition wall spacer may be about 0.5 to about 1.

[0030] According to another aspect of the invention, a display device includes: a substrate, a transistor layer, a plurality of partition walls, a plurality of partition wall spacers, a light-emitting element, and a plurality of spacers, wherein the substrate has a display area and a non-display area located at the periphery of the display area; the transistor layer is arranged on the substrate; a plurality of partition walls are arranged on the transistor layer in the display area; a plurality of partition wall spacers are arranged on some of the plurality of partition walls; the light-emitting element is arranged between the partition walls; and a plurality of spacers are arranged in the non-display area of ​​the substrate, wherein the spacers may include a spacer body arranged on the same layer as the partition walls and arranged on at least a portion of the transistor layer, and the spacers are arranged in the non-display area with a density higher than the density of the partition wall spacers arranged in the display area.

[0031] An arrangement density of the spacers disposed in the non-display region may be about 1.5 to about 3 times an arrangement density of the partition wall spacers disposed in the display region.

[0032] The transistor layer may include a source electrode and a drain electrode, and the spacer may include a dummy electrode disposed in the same layer as the source electrode and the drain electrode.

[0033] A ratio of a height of the spacer to a sum of heights of the partition wall and the partition wall spacer may be about 0.7 to about 1.

[0034] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0036] Figure 1 is a schematic cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0037] Figure 2 is a schematic cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention.

[0038] Figure 3 is a schematic cross-sectional view of yet another exemplary embodiment of a display device constructed according to the principles of the invention.

[0039] Figures 4 to 7 are images and cross-sectional views showing how partition wall spacers are damaged when a mask is positioned in a display device according to a comparative example. Specifically, Figure 4 is an image showing a plan view of a portion of a display area of ​​a display device, Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line A-A' of Figure 6 is an image showing a plan view of a portion of a display area and a non-display area of ​​a display device, and Figure 7 It is along Figure 6 Schematic cross-sectional view taken along line BB'.

[0040] Figure 8 This is an image of an actual damaged partition wall spacer.

[0041] Fig. 9 is based on Figure 1 A cross-sectional view of a structure in which a mask is provided in a display device according to an exemplary embodiment.

[0042] Fig.10 is based on Figure 2 A cross-sectional view of a structure in which a mask is provided in a display device of an exemplary embodiment.

[0043] Fig.11 is an image of a display device according to a comparative example.

[0044] Fig.12 is based on Figure 2 An image of a display device of an exemplary embodiment.

[0045] Fig.13 is a top plan view of a display device according to an exemplary embodiment.

[0046] Fig.14 is an equivalent circuit diagram of a representative pixel of a display device according to an exemplary embodiment.

[0047] Fig.15 It is along Fig.13 Schematic cross-sectional view taken along line XV-XV of .

[0048] Fig.16 is a schematic cross-sectional view illustrating a stacked structure of spacers according to a comparative example.

[0049] Figures 17 to 19 are schematic cross-sectional views of various stacking structures of spacers according to exemplary embodiments.

[0050] Fig. 20 is a display device according to another exemplary embodiment Fig.15 A cross-sectional view similar to a cross-sectional view of .

[0051] Fig.21 is a display device according to another exemplary embodiment Fig.15 A cross-sectional view similar to a cross-sectional view of . DETAILED DESCRIPTION

[0052] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid unnecessary confusion of various exemplary embodiments, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0053] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of different details of some ways in which the inventive concept can actually be implemented. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0054] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performance, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two continuously described processes may be performed substantially simultaneously or in an order opposite to the described sequence. Moreover, the same reference numerals represent the same elements.

[0055] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, the element may be directly on, directly connected to, or directly coupled to another element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system such as an X-axis, a Y-axis, and a Z-axis, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0056] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0057] For descriptive purposes, spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another element(s) as shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would subsequently be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and, accordingly, the spatially relative descriptors used herein interpreted accordingly.

[0058] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", "the" are also intended to include the plural forms. In addition, when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, it indicates that there are stated features, wholes, steps, operations, elements, components and / or their clusters, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their clusters. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and therefore, the terms "substantially", "about" and other similar terms are used to explain the inherent deviations in the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0059] Hereinafter, a display device according to exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is a schematic cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the invention. Figure 1, the display device according to the exemplary embodiment includes a display area DA and a non-display area NDA. For convenience, although the exemplary embodiment describes the display device as an organic light emitting diode (OLED) display, the principles of the invention may be applicable to other types of display devices that those skilled in the art will recognize.

[0061] The display area DA includes: a transistor layer TFT, which is disposed on the substrate 100; a plurality of light emitting elements, such as an organic light emitting element 70, which are disposed on the transistor layer TFT; and a partition wall 190. Figure 1 In the figure, for better understanding and ease of description, the transistor layer TFT is simply shown as a single layer, but as known in the art, the transistor layer TFT may be a multi-layer structure including a gate electrode, a semiconductor layer, a source electrode, a drain electrode, an insulating layer, etc. Fig.15 , Fig. 20 and Fig.21 A specific exemplary structure of the transistor layer TFT is described. Similarly, Figure 1 The organic light emitting element 70 includes a pixel electrode, an organic emission layer and a common electrode. Fig.15 , Fig. 20 and Fig.21 A specific exemplary structure of the organic light emitting element 70 is described.

[0062] Reference Figure 1 , the partition wall 190 is disposed between the plurality of organic light emitting elements 70. The partition wall spacer 195 is disposed at a portion of the partition wall 190, such as the top. The partition wall spacer 195 may be made of the same material as that of the partition wall, and when forming the partition wall 190, the partition wall spacer 195 may be formed by a single process by using a halftone mask, etc. That is, a portion of the partition wall may protrude outward to form the partition wall spacer 195.

[0063] The partition wall spacer 195 contacts a mask used in a process of forming an organic emission layer of the organic light emitting element 70. That is, the partition wall spacer 195 prevents the partition wall 190 and the mask from directly contacting each other. When the partition wall 190 and the mask are in direct contact with each other, the contact area therebetween is wide, so the mask and the partition wall 190 are not easily separated, and the various layers including the partition wall 190 may be delaminated during the mask separation process. However, by disposing the partition wall spacer 195 at some of the partition walls 190 and making the partition wall spacer 195 and the mask in direct contact, the contact area between the partition wall spacer 195 and the mask can be reduced, thereby facilitating the separation of the mask.

[0064] The partition wall spacer 195 is disposed only on some of the plurality of partition walls 190. For example, the partition wall spacer 195 may be disposed only on one or two of ten partition walls. That is, the arrangement density of the partition wall spacers 195 in the display area DA may be 10% to 20%. In the illustrated exemplary embodiment, the arrangement density is a value obtained by dividing the number of partition walls having the partition wall spacer 195 by the number of all partition walls.

[0065] Reference Figure 1 , the spacer SP is disposed in the non-display area NDA. The spacer SP of the non-display area NDA contacts the mask in the same manner as the partition wall spacer 195 of the display area DA.

[0066] In some exemplary embodiments of the invention, the spacer SP includes at least a portion of the transistor layer TFT. That is, the spacer SP includes a spacer body 193 and the transistor layer TFT formed by the same process as that for the partition wall 190, so that the height of the spacer SP substantially matches the height of the partition wall spacer 195.

[0067] In the case of the comparative example, the spacer SP includes only the spacer body 193 formed by the same process as that for the partition wall 190. In this case, the transistor layer TFT is disposed on the lower portion of the partition wall 190, but the transistor layer TFT is not disposed on the lower portion of the spacer SP of the non-display area NDA. Therefore, the height of the partition wall spacer 195 of the display area DA is different from the height of the spacer SP of the non-display area NDA. In the exemplary embodiment shown, the height of the partition wall spacer 195 means the shortest distance between the farthest protrusion of the partition wall spacer 195 and the substrate 100. Likewise, the height of the spacer SP means the shortest distance between the farthest protrusion of the spacer SP and the substrate 100.

[0068] When the height of the partition wall spacer 195 of the display area DA is different from the height of the spacer SP of the non-display area NDA, in the process of providing a mask for forming the organic emission layer, the mask is unevenly provided. Therefore, stress is concentrated on the partition wall spacer 195 provided at the edge of the display area DA. Due to the stress, the partition wall spacer 195 provided at the edge of the display area DA is pressed or damaged. Damage to the partition wall spacer 195 may cause delamination of another layer provided at the lower portion of the partition wall spacer 195.

[0069] However, referring to Figure 1In the display device according to the exemplary embodiment, the spacer SP disposed in the non-display area NDA includes a spacer body 193 formed on the transistor layer TFT. That is, when the insulating layer, the data line, etc. are disposed on the lower portion of the spacer SP, the height difference between the partition wall spacer 195 of the display area DA and the spacer SP of the non-display area NDA is minimized. The spacer SP may include all layers forming the transistor layer TFT disposed in the display area DA, or may include only some of the transistor layers TFT in the transistor layer TFT. For example, the spacer SP may include only the data line at its lower portion. In addition, the spacer SP may include the data line and the insulating layer, and may include another conductive layer forming the display area, such as a gate line or a semiconductor layer. For example, when the display area DA includes two or more data conductors disposed in different layers, the spacer SP may also include two or more data conductors disposed in different layers. This may be appropriately selected by those skilled in the art within the range of minimizing the height difference between the partition wall spacer 195 of the display area DA and the spacer SP of the non-display area NDA.

[0070] For example, the height of the spacer SP of the non-display area NDA may be 70% to 100% of the height of the partition wall spacer 195 of the display area DA. The height of the spacer SP of the non-display area NDA may be about 3 μm to about 6 μm.

[0071] Figure 2 is a schematic cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention. Figure 2 , according to Figure 2 In the display device of the exemplary embodiment of the present invention, the arrangement density of the partition wall spacers 195 of the display area DA and the arrangement density of the spacers SP of the non-display area NDA are different. That is, the density at the spacers SP provided in the non-display area NDA is higher than the density at the partition wall spacers 195 provided in the display area DA. The arrangement density of the spacers SP of the non-display area NDA is defined in the same manner as the arrangement density of the partition wall spacers 195 of the display area DA. That is, the arrangement density of the spacers SP of the non-display area NDA is defined as the ratio of the unit area in which the spacers SP are formed in the total area of ​​the non-display area NDA. Here, the unit area may be an area corresponding to one light emitting area of ​​the display area DA.

[0072] For example, the arrangement density of the spacers SP of the non-display area NDA may be 1.5 to 3 times the arrangement density of the partition wall spacers 195 of the display area DA.

[0073] exist Figure 2In an exemplary embodiment, the spacer SP does not include the transistor layer TFT. The spacer SP includes only the spacer body 193, so that the height of the spacer SP of the non-display area NDA and the height of the partition wall spacer 195 of the display area DA are different.

[0074] For example, the height of the spacer SP of the non-display area NDA may be 50% to 100% of the height of the partition wall spacer 195 of the display area DA.

[0075] However, in the display device according to the exemplary embodiment shown, the stress occurring when the mask is applied thereto is dispersed by the spacers SP disposed in the non-display area NDA in a configuration having a high arrangement density. Therefore, the partition wall spacers 195 disposed at the edge of the non-display area NDA can be minimized or prevented from being damaged.

[0076] Figure 3 is a schematic cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention. Figure 3 According to the exemplary embodiment shown, the display device includes Figure 1 Features and principles of exemplary embodiments Figure 2 That is, in accordance with Figure 3 In the display device of the exemplary embodiment of the present invention, the spacer SP of the non-display area NDA includes a transistor layer TFT at a lower portion thereof and has an arrangement density higher than that of the partition wall spacer 195 of the display area DA. In this case, since the height of the spacer SP of the non-display area NDA and the height of the partition wall spacer 195 of the display area DA are similar to each other, when the mask is applied, the stress applied to the partition wall spacer 195 disposed at the edge of the display area DA can be minimized. In addition, since the spacer SP of the non-display area NDA is disposed at an arrangement density higher than that of the partition wall spacer 195 of the display area DA, the stress applied to the partition wall spacer 195 of the display area DA is dispersed. Therefore, damage to the partition wall spacer 195 by the mask can be effectively prevented.

[0077] Figures 4 to 7 1 is an image and a cross-sectional view showing how the partition wall spacer 195 is damaged when the mask 800 is positioned in the display device according to the comparative example. Specifically, Figure 4 is an image showing a plan view of a portion of a display area of ​​a display device, Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line A-A' of Figure 6 is an image showing a plan view of a portion of a display area and a non-display area of ​​a display device, and Figure 7 It is along Figure 6Schematic cross-sectional view taken along line BB'.

[0078] Figure 4 shows an image of a display area of ​​a display device, and Figure 5 Shown by Figure 4 The dashed line in FIG. indicates a cross-sectional view of a portion of the image. Figure 5 , in the display area DA, the partition wall spacer 195 is disposed at a portion of the partition wall 190. Since the heights of the partition wall spacers 195 are substantially the same in the display area DA, the mask 800 is stably disposed.

[0079] Figure 6 An image showing both the display area and the non-display area of ​​the display device is shown. Figure 6 In FIG. 1 , the portion indicated by the bright diamond is the display area, and the portion indicated by the dark diamond is the non-display area. Figure 6 In FIG, the spacers are shown as black circles. Figure 7 Shown by Figure 6 The dashed line in the figure indicates the cross-sectional view of the portion.

[0080] Reference Figure 7 , the height of the spacer SP of the non-display area NDA is lower than the height of the partition wall spacer 195 of the display area DA. This is because the structure of the transistor layer such as the data line is not disposed under the non-display area NDA. Figure 7 As shown in FIG. 8 , the mask 800 is at an inclined angle. In this case, stress is concentrated on the boundary between the display area DA and the non-display area NDA, that is, on the partition wall spacer 195 provided at the edge of the display area DA. Therefore, the partition wall spacer 195 is stressed by the pressure and is damaged.

[0081] Figure 8 An image of a partition wall spacer 195 that is actually damaged is shown. Figure 8 , it can be seen that the damaged partition wall spacer 195 appears dark. When the partition wall spacer 195 is damaged, there is a high possibility that another layer below the partition wall spacer 195 is delaminated. Figure 8 As shown in , it is seen as a dark spot, which causes malfunction of the display device. Figure 8 It can be seen from the figure that damage of the partition wall spacer 195 mainly occurs at the edge of the display area DA, that is, at the portion adjacent to the non-display area NDA. This is because the stress caused by the height difference between the partition wall spacer 195 of the display area DA and the spacer SP of the non-display area NDA is concentrated on the edge of the display area DA.

[0082] However, in Figure 1In the display device according to the exemplary embodiment shown in , the spacer SP of the non-display area NDA includes at least a portion of the transistor layer TFT at a lower portion thereof, and therefore, the height of the spacer SP of the non-display area NDA is similar to the height of the partition wall spacer 195 of the display area DA. Therefore, stress due to the height difference between the partition wall spacer 195 and the spacer SP does not occur, so that damage to the partition wall spacer 195 and delamination of the lower layer in the display area DA can be prevented.

[0083] Fig. 9 is based on Figure 1 8 is a cross-sectional view of a structure in which a mask 800 is provided in a display device according to an exemplary embodiment of the present invention. Fig. 9 Since the height of the partition wall spacer 195 is similar to the height of the spacer SP of the non-display area NDA, the stress due to the mask 800 is not concentrated on any one point. Therefore, the partition wall spacer 195 can be prevented from being damaged.

[0084] Fig.10 is based on Figure 2 8 is a cross-sectional view of a structure in which a mask 800 is provided in a display device according to an exemplary embodiment of the present invention. Fig.10 In the exemplary embodiment shown, the height of the partition wall spacer 195 and the height of the spacer SP are different. Here, since the spacers SP are densely arranged in the non-display area NDA with a high arrangement density, the stress caused by the height difference between the partition wall spacer 195 and the spacer SP is dispersed. Therefore, the stress is not concentrated on the partition wall spacer 195, thereby reducing or preventing damage.

[0085] Fig.11 An image of a display device according to a comparative example is shown, and Fig.12 Show according to Figure 2 An image of a display device of an exemplary embodiment. Fig.11 and Fig.12 Compared with Fig.11 In comparison, Fig.12 It is shown that the spacers SP are disposed in the non-display area NDA with high arrangement density. As described above, when the arrangement density of the spacers SP is increased in the non-display area, the partition wall spacers 195 of the display area DA may be reduced or prevented from being damaged because stress is dispersed.

[0086] In the following, reference will be made to Figures 13 to 15 A detailed structure of a display device according to an exemplary embodiment is described. Fig.13 A top plan view of a display device according to an exemplary embodiment is shown, and Fig.14 An equivalent circuit diagram of a representative pixel of a display device according to an exemplary embodiment is shown. Fig.15 It is along Fig.13 Schematic cross-sectional view taken along line XV-XV of .

[0087] Reference Fig.13 , the display device according to the illustrated exemplary embodiment includes a display area DA for displaying an image and a non-display area NDA located at the periphery of the display area.

[0088] The non-display area NDA includes a driving area PA in which a driver 600 for transmitting a signal to the display area DA is disposed. A common voltage transmission line 400 for transmitting a common voltage and driving voltage transmission lines 500a and 500b for transmitting a driving voltage are disposed in the non-display area NDA. However, Fig.13 The arrangement of the common voltage transmission line 400 and the driving voltage transmission lines 500a and 500b shown in FIG. 1 is merely an example, but the present invention is not limited thereto.

[0089] Will refer to Fig.14 and Fig.15 The structures of the display area DA and the non-display area NDA are described.

[0090] Reference Fig.14 The display area DA of the display device according to the exemplary embodiment includes a plurality of signal lines 121, 171, and 172, and a plurality of pixels connected to the plurality of signal lines 121, 171, and 172, and the plurality of pixels are arranged in an approximately matrix form. A representative pixel PX is referred to as Fig.14 The display device displays an image by using a plurality of pixels.

[0091] The signal lines include a plurality of gate lines 121 for transmitting gate signals (or scanning signals), a plurality of data lines 171 for transmitting data signals, and a plurality of driving voltage lines 172 for transmitting driving voltage ELVDD. The data lines 171, the driving voltage lines 172, the data conductors, and the gate lines 121 are referred to as gate conductors.

[0092] The gate lines 121 extend substantially in a row direction and are substantially parallel to each other, and portions of the data lines 171 and the driving voltage lines 172 extend substantially in a column direction and are substantially parallel to each other.

[0093] The pixel PX includes a switching thin film transistor Qs, a driving thin film transistor Qd, a storage capacitor Cst, and an organic light emitting diode (OLED) LD. One pixel PX may further include a thin film transistor and a capacitor to compensate for current supplied to the organic light emitting diode LD.

[0094] The switching thin film transistor Qs transmits the data signal applied to the data line 171 to the driving thin film transistor Qd in response to the scan signal applied to the gate line 121. The driving thin film transistor Qd outputs an output current I variable according to the voltage applied between the control terminal and the output terminal. LD The capacitor Cst charges the data signal applied to the control terminal of the driving thin film transistor Qd and holds it when the switching thin film transistor Qs is turned off.

[0095] The organic light emitting diode LD includes an anode connected to the output terminal of the driving thin film transistor Qd and a cathode connected to the common voltage ELVSS. The organic light emitting diode LD is electrically connected to the output current I of the driving thin film transistor Qd. LD Changes intensity and emits light, thus showing an image.

[0096] Now, refer to Fig.15 Describe the inter-layer structure of a display device.

[0097] As described above, the display device includes the display area DA and the non-display area NDA.

[0098] The display device includes a substrate 100, and the substrate 100 is flexible and may include a first insulating layer 100a and a second insulating layer 100b overlapping each other. The first insulating layer 100a and the second insulating layer 100b may include polyimide. However, the first insulating layer 100a and the second insulating layer 100b are not limited thereto, and may include other materials that are heat-resistant, chemical-resistant, wear-resistant, and flexible.

[0099] The substrate 100 may further include a first barrier film 100c disposed between the first and second insulating layers 100a and 100b. The first barrier film 100c prevents external moisture and gas from flowing between the first and second insulating layers 100a and 100b and prevents deformation of the first and second insulating layers 100a and 100b.

[0100] The substrate 100 includes first and second insulating layers 100a and 100b overlapping each other, thereby preventing the substrate 100 from being deteriorated even if the first insulating layer 100a contacting the outside is damaged. However, the structure of the substrate 100 is only an example, and the substrate 100 may be a single layer including a flexible material.

[0101] A buffer layer 120 is disposed on the substrate 100. The buffer layer 120 may include silicon nitride (SiN x ) and silicon oxide (SiO x ) of a single layer or multiple layers and prevent the penetration of unnecessary components such as impurities or moisture.

[0102] A second barrier film may be disposed between the second insulating layer 100 b and the buffer layer 120 .

[0103] A first semiconductor layer 135 is disposed on the buffer layer 120 of the display area DA. The first semiconductor layer 135 may include polysilicon or an oxide semiconductor.

[0104] The first semiconductor layer 135 includes a first channel region 1355 and a first source region 1356 and a first drain region 1357 disposed at respective sides of the first channel region 1355. The first channel region 1355 of the first semiconductor layer 135 may be a region not doped with impurities, and the first source region 1356 and the first drain region 1357 of the first semiconductor layer 135 may be regions doped with conductive impurities.

[0105] A gate insulating layer 140 is disposed on the first semiconductor layer 135. The gate insulating layer 140 may be a layer including tetraethylorthosilicate (TEOS), silicon oxide (SiO x ), silicon nitride (SiN x ) or a single layer of silicon oxynitride (SiON), or may be a multilayer including the above materials.

[0106] A first gate electrode 155 is disposed on the gate insulating layer 140 . The first gate electrode 155 overlaps the first channel region 1355 .

[0107] The first gate electrode 155 may be a single layer or a multilayer including a low resistance material such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), nickel (Ni), or an alloy thereof, or a material having strong corrosion resistance.

[0108] A first interlayer insulating layer 160 is disposed on the first gate electrode 155. The first interlayer insulating layer 160 may be made of tetraethyl orthosilicate (TEOS), silicon oxide (SiO x ), silicon nitride (SiN x ) or a single layer of silicon oxynitride (SiON), or a multilayer including the above materials.

[0109] The first interlayer insulating layer 160 and the gate insulating layer 140 have a first source contact hole 166 and a first drain contact hole 167 overlapping with the first source region 1356 and the first drain region 1357 , respectively.

[0110] A first source electrode 173 and a first drain electrode 175 are disposed on the first interlayer insulating layer 160. In addition, a dummy electrode 177 is disposed on the first interlayer insulating layer 160 of the non-display area NDA. The dummy electrode 177 may be formed in the same process as that for the first source electrode 173 and the first drain electrode 175, and may have the same thickness as the first source electrode 173 and the first drain electrode 175. In addition, a common voltage transmission line 400 is disposed on the first interlayer insulating layer 160 of the non-display area NDA. The dummy electrode 177 may be disposed between the display area DA and the common voltage transmission line 400.

[0111] The dummy electrode 177 may be disposed to be separated from the edge of the display area DA by 150 μm to 200 μm.

[0112] The first source electrode 173 and the first drain electrode 175 are connected to the first source region 1356 and the first drain region 1357 of the first semiconductor layer 135 through the first source contact hole 166 and the first drain contact hole 167 , respectively.

[0113] The first source electrode 173 and the first drain electrode 175 may be made of a single layer or multiple layers including a low resistance material or a strong corrosion resistant material such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), nickel (Ni), or an alloy thereof. The dummy electrode 177 and the common voltage transmission line 400 may be formed simultaneously with the first source electrode 173 and the first drain electrode 175 using the same layer.

[0114] The first semiconductor layer 135, the first gate electrode 155, the first source electrode 173, and the first drain electrode 175 of the display area DA are formed. Fig.14 . In addition, a thin film transistor included in a gate driver and the like may be disposed in the non-display area NDA.

[0115] A second interlayer insulating layer 180 is disposed on the first source electrode 173 and the first drain electrode 175. Similar to the first interlayer insulating layer 160, the second interlayer insulating layer 180 may be a layer including tetraethyl orthosilicate (TEOS), silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiON), or a multilayer including the above materials.

[0116] The second interlayer insulating layer 180 is provided with a contact hole 82 overlapping the first drain electrode 175. The second interlayer insulating layer 180 is removed at the region overlapping the common voltage transmission line 400, so that most of the common voltage transmission line 400 does not overlap with the second interlayer insulating layer 180, and only a portion of the edge of the common voltage transmission line 400 may overlap with the second interlayer insulating layer 180. However, all of the common voltage transmission line 400 may not overlap with the second interlayer insulating layer 180.

[0117] A pixel electrode 710 is disposed on the second interlayer insulating layer 180. The pixel electrode 710 may be Fig.14 In the illustrated exemplary embodiment, the second interlayer insulating layer 180 is disposed between the pixel electrode 710 and the first drain electrode 175 , however, it may be disposed on the same layer as the pixel electrode 710 and the first drain electrode 175 and may be formed integrally with the first drain electrode 175 .

[0118] A partition wall 190 is formed on the pixel electrode 710. The partition wall 190 is provided with an opening 197 overlapping the pixel electrode 710. The partition wall 190 may include a polyacrylate resin, a polyimide resin, a silicon-based inorganic material, etc. A portion of the partition wall 190 protrudes upward to form a partition wall spacer 195. The description of the partition wall spacer 195 is substantially the same as described above. A detailed description of the same constituent elements will be omitted to avoid repetition. That is, the partition wall spacer 195 may be formed in the same process as that for the partition wall 190, and may be formed by using a halftone mask, etc. to have a height that is more prominent than the partition wall 190. The partition wall spacer 195 is formed on a portion of the partition wall 190, thereby reducing or preventing the partition wall 190 from being damaged when the mask is positioned.

[0119] The spacer body 193 formed by the same process as that for the partition wall 190 is disposed in the non-display area NDA. The spacer body 193 is formed by the same process as that for the partition wall 190, and thus it may include the same material as the partition wall 190. The thickness (i.e., height) of the spacer body 193 may be the same as the sum of the thickness (i.e., height) of the partition wall 190 and the partition wall spacer 195.

[0120] The spacer body 193 may be disposed to overlap the dummy electrode 177. Fig.15 As can be seen in FIG. 1 , the spacer body 193 , the dummy electrode 177 , the second interlayer insulating layer 180 , the first interlayer insulating layer 160 , the gate insulating layer 140 , the buffer layer 120 , etc. may form a spacer SP.

[0121] Since the spacer SP includes the dummy electrode 177 at the lower portion thereof, it has a height similar to that of the partition wall spacer 195 of the display area DA. That is, since the dummy electrode 177 corresponding to the first source electrode 173 and the first drain electrode 175 disposed under the partition wall spacer 195 of the display area DA is disposed under the spacer SP, the height difference between the partition wall spacer 195 of the display area DA and the spacer SP of the non-display area NDA can be minimized.

[0122] The spacer SP may be disposed between the display area DA and the common voltage transmission line 400. The spacer SP may be disposed to be separated from the edge of the display area by about 150 μm to about 200 μm.

[0123] An organic emission layer 720 is disposed in the opening 197 of the partition wall 190 .

[0124] The organic emission layer 720 may be made of a plurality of layers including an emission layer and one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). In the case where the organic emission layer 720 includes all layers, the hole injection layer is disposed on the pixel electrode 710 as an anode, and the hole transport layer, the emission layer, the electron transport layer, and the electron injection layer may be sequentially stacked on the hole injection layer.

[0125] A common electrode 730 is disposed on the partition wall 190 and the organic emission layer 720 . The common electrode 730 may be a cathode of the organic light emitting element. Therefore, the pixel electrode 710 , the organic emission layer 720 , and the common electrode 730 form the organic light emitting element 70 .

[0126] The organic light emitting diode display may have any one structure of a front display type, a rear display type, and a double-sided display type according to the direction in which the organic light emitting element 70 emits light.

[0127] The common electrode 730 may be disposed on the entire surface of the substrate 100 including the display area DA and the non-display area NDA, and contact the common voltage transmission line 400 of the non-display area NDA to receive a common voltage.

[0128] A dam D1 is provided outside the common voltage transmission line 400 of the non-display area NDA. The dam D1 may be formed of an insulating layer and an additional insulating layer 199, and the insulating layer is formed of the same layer as the second interlayer insulating layer 180 and the partition wall 190 provided in the display area DA. Through the additional insulating layer 199, the dam D1 may have a high height, which may prevent the organic material from flowing during the process of forming the organic encapsulation layer, etc. The dam D1 is provided farther from the display area DA than the spacer SP, and the height of the dam D1 may be higher than the height of the spacer SP. That is, since the dam D1 and the spacer SP both include a layer formed of the same layer as the first interlayer insulating layer 160, the second interlayer insulating layer 180, and the partition wall 190, their structures are somewhat similar, but their functions are different. That is, the spacer SP has a height similar to the partition wall spacer 195 of the display area DA, and supports the mask in the process. However, the dam D1 has a height higher than the partition wall spacer 195 of the display area DA, and prevents the organic material from flowing.

[0129] An encapsulation layer 80 is disposed on the common electrode 730. The encapsulation layer 80 may be formed by alternately stacking at least one inorganic layer and at least one organic layer, and a plurality of inorganic layers or a plurality of organic layers may be provided.

[0130] In the illustrated exemplary embodiment, the encapsulation layer 80 includes a first inorganic encapsulation layer 810 and a second inorganic encapsulation layer 820 , and an organic encapsulation layer 830 disposed between the first inorganic encapsulation layer 810 and the second inorganic encapsulation layer 820 .

[0131] An additional plate 90 such as a touch part, a polarizer, etc. is disposed on the encapsulation layer 80 , and an adhesive layer 900 may be disposed between the encapsulation layer 80 and the additional plate 90 .

[0132] Although in Fig.15 17 is shown as being disposed under the spacer SP, but another structure disposed in the transistor of the display area DA may be included under the spacer SP. That is, the semiconductor layer 135, the gate electrode 155, etc. may be further included. In addition, when the display area DA includes two or more source electrodes disposed in different layers, the two or more source electrodes disposed in different layers may be included under the spacer SP of the non-display area NDA.

[0133] Fig.16 : is a schematic cross-sectional view showing a stacked structure of a spacer SP according to a comparative example.

[0134] Figures 17 to 19 2 are schematic cross-sectional views of various stack structures of spacers SP according to exemplary embodiments.

[0135] Reference Fig.16, the spacer SP according to the comparative example includes a first interlayer insulating layer 160, a second interlayer insulating layer 180, and a spacer body 193. That is, since the dummy electrode 177 or any other transistor layer structure is not included in the lower portion of the spacer SP, the height of the partition wall spacer 195 of the display area DA and the height of the spacer SP of the non-display area NDA are different from each other.

[0136] Figures 17 to 19 is a cross-sectional view of a stacked structure of spacers SP according to various exemplary embodiments.

[0137] Reference Fig.17 According to an exemplary embodiment, the spacer SP may include a first interlayer insulating layer 160, a dummy electrode 177, a second interlayer insulating layer 180, and a spacer body 193. In addition, the spacer SP may further include a buffer layer 120 under the first interlayer insulating layer 160, a gate insulating layer 140, and the like.

[0138] Reference Fig.18 , the spacer SP according to the exemplary embodiment may include a dummy electrode 177, a coating layer 181 coating the side surfaces of the source electrode and the drain electrode of the display area, a first interlayer insulating layer 160, a second interlayer insulating layer 180, and a spacer body 193. Referring to Fig.18 , the dummy electrode 177 is disposed at a lower portion of the spacer SP, and the first interlayer insulating layer 160 and the second interlayer insulating layer 180 are disposed to overlap with the dummy electrode 177. In the spacer SP of the non-display area NDA, the stacking order of the dummy electrode 177, the first interlayer insulating layer 160, and the second interlayer insulating layer 180 may be changed according to the stacking order of the display area DA. That is, when the source electrode and the like are disposed under the first interlayer insulating layer 160 in the display area DA, the dummy electrode 177 may be disposed under the first interlayer insulating layer 160 in the spacer SP of the non-display area NDA.

[0139] The coating layer 181 is a layer surrounding the source electrode and the drain electrode in the display area DA. The coating layer 181 may coat the side surface of the source electrode and the side surface of the drain electrode. The spacer SP of the non-display area NDA may include the coating layer 181.

[0140] Fig.19 FIG. 2 shows a spacer SP according to another exemplary embodiment. Fig.19 , the spacer SP according to the illustrated exemplary embodiment includes a dummy electrode 177 and an auxiliary dummy electrode 176 disposed at different layers. That is, referring to Fig.19, the dummy electrode 177, the coating layer 181, the first interlayer insulating layer 160, the auxiliary dummy electrode 176, the second interlayer insulating layer 180, and the spacer body 193 are sequentially stacked. The auxiliary dummy electrode 176 may be disposed on the same layer as the ELVDD line in the display area DA. That is, when the ELVDD line of the display area DA is stacked, the auxiliary dummy electrode 176 may be formed by the same process as that for the ELVDD line.

[0141] Figures 17 to 19 The exemplary embodiment of FIG. 1 is only an example, and the stack structure of the spacer SP is not limited thereto. That is, the spacer SP may appropriately include the entire or a portion of the stack structure of the display area DA.

[0142] Hereinafter, a display device according to another exemplary embodiment will be described with reference to the accompanying drawings.

[0143] Fig. 20 is a display device according to another exemplary embodiment Fig.15 A cross-sectional view similar to that of Fig. 20 , except for the stacking structure and arrangement density of the spacers SP, the display device according to the illustrated exemplary embodiment is Fig.15 The display devices of the exemplary embodiments of the present invention are substantially the same. Detailed description of the same constituent elements will be omitted to avoid redundancy.

[0144] Reference Fig. 20 , in the display device according to the exemplary embodiment shown, the dummy electrode is not disposed at the lower portion of the spacer SP. However, in the display device according to the exemplary embodiment shown, the arrangement density of the partition wall spacers 195 of the display area DA is lower than the arrangement density of the spacers SP of the non-display area NDA. That is, the partition wall spacers 195 of the display area DA are disposed on one or two of the ten partition walls 190, while the spacers SP of the non-display area NDA may be disposed at a higher arrangement density. For example, the arrangement density of the spacers SP of the non-display area NDA may be 1.5 to 3 times the arrangement density of the partition wall spacers 195 of the display area DA.

[0145] When the arrangement density of the spacers SP of the non-display area NDA is high, it is possible to prevent stress from being concentrated on the surface such as the Fig.10 On the partition wall spacer 195 at the edge of the display area DA shown in FIG.

[0146] Fig.21 is a display device according to another exemplary embodiment Fig.15 A cross-sectional view similar to that of Fig.21 , except for the arrangement density of the spacers SP, the display device according to the illustrated exemplary embodiment is Fig.15The display devices of the exemplary embodiments of the present invention are substantially the same. Detailed description of the same constituent elements will be omitted to avoid redundancy.

[0147] Reference Fig.21 , the spacer SP of the display device according to the illustrated exemplary embodiment includes a spacer body 193 and a dummy electrode 177 overlapping the spacer body 193. In this case, the arrangement density of the spacers SP of the non-display area NDA is higher than the arrangement density of the partition wall spacers 195 of the display area DA. That is, according to Fig.21 The display device of the exemplary embodiment is Fig.15 The display device and Fig. 20 That is, according to Figure 3 The specific structure of the display device of the exemplary embodiment corresponds to Fig.21 Display device. Fig.21 Since the display device according to the illustrated exemplary embodiment includes the dummy electrode 177 disposed at the lower portion of the spacer SP, the step between the spacer SP and the partition wall spacer 195 is minimized. In addition, since the arrangement density of the spacers SP of the non-display area NDA is higher than that of the display area DA, stress concentration on the partition wall spacer 195 disposed at the edge of the display area DA can be prevented.

[0148] As described above, in the display device according to the exemplary embodiment, a part or all of the structure of the transistor layer TFT is included in the lower portion of the spacer SP of the non-display area NDA. Therefore, the step between the partition wall spacer 195 of the display area DA and the spacer SP of the non-display area NDA can be minimized, and the stress applied to the partition wall spacer 195 of the display area DA can be minimized. In addition, in the display device according to some exemplary embodiments, the spacers SP of the non-display area NDA are densely arranged at a higher arrangement density than the partition wall spacers 195 of the display area DA. Therefore, the stress applied to the partition wall spacer 195 of the display area DA can be dispersed.

[0149] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that are apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: a substrate having a display area and a non-display area located at a periphery of the display area; a transistor layer, wherein the transistor layer is disposed on the substrate; a plurality of partition walls disposed on the transistor layer in the display region, and a plurality of partition wall spacers disposed on some of the plurality of partition walls; a light emitting element, the light emitting element being disposed between the partition walls; as well as a spacer, the spacer being disposed in the non-display area of ​​the substrate, wherein the spacer includes a spacer body and at least a portion of the transistor layer disposed in the non-display area, and the spacer body is disposed on the same layer as the partition wall and on the at least a portion of the transistor layer, and Wherein, a height of the spacer in the non-display area is the same as a height of the partition wall spacer in the display area.

2. The display device according to claim 1, wherein: The transistor layer includes a source electrode and a drain electrode, and The spacer includes a dummy electrode disposed in a same layer as the source electrode and the drain electrode.

3. The display device according to claim 2, wherein: The transistor layer further includes a gate insulating layer, a first interlayer insulating layer and a second interlayer insulating layer. The spacer further includes the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer, The transistor layer further includes a coating layer coating the source electrode and the drain electrode, and The spacer further includes the coating layer disposed on the dummy electrode.

4. The display device according to claim 1, wherein: The transistor layer includes two or more data conductors disposed on different layers, and The spacer includes two or more data conductors disposed on different layers.

5. The display device according to claim 1, wherein: Each of the plurality of partition walls and the plurality of partition wall spacers is formed of the same material and is connected to each other.

6. The display device according to claim 5, wherein: A ratio of the partition walls provided with the partition wall spacers among all the partition walls is 10% to 20%.

7. The display device according to claim 5, wherein: A ratio of a height of the spacer to a sum of heights of the partition wall and the partition wall spacer is 0.7 to 1.

8. The display device according to claim 7, wherein: The height of the spacer is 3 μm to 6 μm.

9. The display device according to claim 1, wherein: The spacer is disposed 150 μm to 200 μm apart from an edge of the display area.

10. The display device according to claim 1, wherein: The spacer body includes the same material as that of the partition wall.

Images