Method and electronic circuit for driving a transistor device

Abstract

Disclosed are a method and an electronic circuit for driving a transistor device. The method comprises: in a conducting state of the transistor device (1), setting a driving voltage (V GS ) from the maximum voltage level (V MAX ) drops to a level above the threshold voltage of the transistor device (1) (V TH ) of the intermediate voltage level (V INT ); in a predetermined time period (T INT ) to maintain the intermediate voltage level (V INT ); and within a predetermined time period (T INT ) and then increase the drive voltage (V GS ) drops to the threshold voltage level (V TH ) below to switch the transistor device to the cut-off state.

Description

Technical Field

[0001] The present disclosure generally relates to methods for driving transistor devices and electronic circuits having driver circuits configured to drive transistor devices. Background Art

[0002] Transistor devices, such as MOSFETs (metal oxide field effect transistors), are widely used as electronic switches in various types of applications, such as automotive, industrial, household or consumer electronics applications. Inevitably, an electronic circuit including a transistor device used as an electronic switch further includes a parasitic inductance in series with a load path of the transistor device. Such parasitic inductance may originate from connecting wires connecting the transistor device to other devices in the electronic circuit. When the transistor device switches from its on-state, in which it conducts current, to its off-state, in which it blocks, the parasitic inductance may cause a voltage spike in the load path voltage of the transistor device.

[0003] It is desirable to reduce such voltage spikes. Summary of the invention

[0004] One example relates to a method. The method includes: in the on-state of the transistor device, reducing the drive voltage of the transistor device from a maximum voltage level to an intermediate voltage level higher than the threshold voltage level of the transistor device, and maintaining the intermediate voltage level for a predetermined time period. The method further includes: after the predetermined time period, reducing the drive voltage below the threshold voltage level to switch the transistor device to an off-state.

[0005] Another example relates to an electronic circuit having a driving circuit. The driving circuit is configured to: in the on-state of the transistor device, reduce the driving voltage of the transistor device from a maximum voltage level to a level higher than a threshold voltage level (V TH ), maintaining the intermediate voltage level for a predetermined time period, and reducing the drive voltage to below the threshold voltage level after the predetermined time period to switch the transistor device to a cut-off state. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Examples are explained below with reference to the accompanying drawings. These drawings are used to illustrate specific principles so that only aspects necessary for understanding these principles are shown. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features.

[0007] Figure 1 An example of an electronic circuit including a transistor device and a driving circuit configured to drive the transistor device is shown;

[0008] Figure 2A-2C showing different examples of how a transistor device may be connected to at least one load;

[0009] Figure 3A-3B Different examples are shown where the transistor device is one of two transistor devices of a half bridge;

[0010] Figure 4 is a flow chart illustrating one example of a method for driving a transistor device;

[0011] Figure 5 Shown according to Figure 4 timing diagrams of on-resistance, load path voltage and drive voltage of a transistor device driven by the method and a transistor device driven in a conventional manner;

[0012] Figure 6 An example of a driving circuit including a control circuit, a switch-on circuit, and a switch-off circuit is shown;

[0013] Figure 7 Shows Figure 6 Examples of signal diagrams of signals appearing in the illustrated drive circuit;

[0014] Figure 8 An example of a switched-on circuit is shown;

[0015] Fig. 9 An example of a disconnected circuit is shown;

[0016] Fig.10 Shows Fig. 9 Examples of signal diagrams showing signals occurring in the disconnected circuit;

[0017] Fig.11 An example of a discharge circuit showing an intermediate voltage circuit and an open circuit;

[0018] Figure 12A-12B Different examples of intermediate voltage generating circuits are shown;

[0019] Figure 13A-13B A further example of an intermediate voltage generating circuit is shown;

[0020] Fig.14 Another example of an intermediate voltage generating circuit is shown;

[0021] Fig.15 A disconnect circuit with a discharge circuit according to another example is shown;

[0022] Fig.16 Shows the description Fig.15 A signal diagram showing the function of the discharge circuit;

[0023] Fig.17 Shows Fig.16 An example of a comparator circuit is shown;

[0024] Fig.18 Shows Fig.16 Another example of a comparator circuit is shown;

[0025] Fig.19 A disconnect circuit with a discharge circuit according to another example is shown;

[0026] Fig. 20 Shows the description Fig.19 A signal diagram showing the function of the discharge circuit;

[0027] Fig.21 A flow chart showing a modified method for driving a transistor device;

[0028] Fig. 22 Shown according to Fig.21 A signal diagram of a driving voltage of a transistor device operated by the method shown;

[0029] Fig.23 shows a configuration according to Fig.21 The method shown operates an example of a disconnect circuit of a driving circuit of a transistor device;

[0030] Fig.24 Shows Fig.23 Modification of the disconnect circuit shown;

[0031] Fig.25 Shows Fig.24 The signal diagram of the function of disconnecting the circuit shown;

[0032] Fig.26 It is shown Figure 4 a flowchart of a modification of the method shown;

[0033] Fig. 27 Shown according to Fig.26 A signal diagram of a driving voltage and a load path voltage of a transistor device driven by the method shown;

[0034] Fig.28 shows a configuration according to Fig.26 An example of a driving circuit for driving a transistor device according to the method shown;

[0035] Fig.29 Shows Fig.28 An example of a switched-on circuit is shown;

[0036] Fig.30 Shows Fig.28 An example of a disconnect circuit is shown; and

[0037] Fig.31 Shows Fig.28 Another example of a disconnect circuit is shown. DETAILED DESCRIPTION

[0038] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings constitute a part of the specification and, for the purpose of illustration, show how the invention can be used and implemented. It should be understood that the features of the various embodiments described herein can be combined with each other unless otherwise specifically stated.

[0039] Figure 1 An example of an electronic circuit comprising a transistor device 1 and a drive circuit 2 is shown. The transistor device 1 is configured to drive a transistor according to a drive voltage V received at a drive input. GS The driving circuit 2 is configured to be turned on or off based on the driving signal S received by the driving circuit 2. DRV Generate drive voltage V GS .exist Figure 1 In the example shown, the driving input of the transistor device 1 is formed by a control node G of the transistor device and a first load node S. The transistor device 1 further comprises a second load node D, wherein the first load node S and the second load node D form a load path DS of the transistor device 1 .

[0040] According to one example, the transistor device 1 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It should be noted that the term MOSFET as used herein refers to any type of field effect transistor (commonly referred to as IGFET) having an insulated gate electrode, regardless of whether the gate electrode comprises metal or other types of conductive materials and regardless of whether the gate dielectric comprises oxide or other types of dielectric insulating materials. Figure 1 The circuit symbol of the transistor device 1 shown represents an n-type enhancement MOSFET. However, this is for illustration purposes only. Any other type of MOSFET may also be used, such as a p-type enhancement MOSFET, a p-type depletion MOSFET, an n-type depletion MOSFET or any other type of field effect transistor, such as an IGBT (insulated gate bipolar transistor) or a JFET (junction field effect transistor).

[0041] In MOSFET, the control node G is also called the gate node, the first load node S is also called the source node, the second load node D is also called the drain node, and the drive voltage V GS Also called the gate-source voltage. Figure 1 The transistor device 1 shown is not limited to being implemented as a MOSFET, but the terms gate node G, source node S, and drain node D will be used hereinafter to represent the control node, the first load node, and the second load node, respectively. Figure 1In the MOSFET shown, the drive input is formed by the gate node G and the source node S, but this is only an example. According to additional examples (not shown), the drive input is formed by the gate node and an auxiliary source node different from the source node. For example, a resistor may be connected to the source node, and the drive input may be formed by the gate node and the resistor at a circuit node away from the source node.

[0042] The electronic circuit having the transistor device 1 and the drive circuit 2 can be used as an electronic switch in various types of electronic circuits. FIG. 2A to FIG. 2C Some examples of how electronic circuits can be used as electronic switches are shown in FIG. 1 . For ease of illustration, only transistor devices 1 are shown in these figures and drive circuits 2 are omitted. Figure 2A , the electronic circuit can be used as a low-side switch. In this case, the load path DS of the transistor device 1 is connected between the load Z and the first power supply node (where the negative power supply potential or ground potential GND is available). The series circuit with the load path DS of the transistor device 1 and the load Z is connected between the first power supply node and the second power supply node (where the positive power supply potential V++ is available).

[0043] exist Figure 2B In the example shown, the electronic circuit is used as a high-side switch. In this example, the load path DS of the transistor device 1 is connected between the second power supply node (where the positive power supply potential V++ is available) and the load Z, wherein the load Z is connected between the first power supply node and the load path DS.

[0044] according to Figure 2C In another example shown, the load path DS is connected between two loads Z1 and Z2 , wherein a series circuit including the loads Z1 and Z2 and the load path DS is connected between a first power supply node and a second power supply node.

[0045] refer to Figure 3A and Figure 3B , the load Z may include a further transistor device Z3, whose load path is connected in series with the load path DS of the transistor device 1, so that the transistor device 1 and the further transistor device Z3 form a half bridge. The circuit node shared by the load paths of the transistor device 1 and the further transistor device Z3 forms the output OUT of the half bridge. Figure 3A In the example shown, transistor device 1 forms the high-side switch of the half-bridge, while Figure 3B In the example shown, the transistor device 1 forms the low-side switch of a half-bridge. Figure 3A and Figure 3B A half-bridge of the type shown can be used in various ways to supply a load circuit ( Figure 3A and Figure 3BThe AC voltage provided by such a half-bridge has a first voltage level when the low-side switch is turned off and the high-side switch is turned on, and has a second voltage level when the low-side switch is turned on and the high-side switch is turned off.

[0046] Inevitably, the connecting lines connecting the load path DS of the transistor device 1 to the power supply node or the load have an inductance, which may also be referred to as a parasitic inductance. Such connecting lines may be implemented in various ways. These connecting lines may include traces of a printed circuit board (PCB) on which the transistor device may be mounted. According to one example, the transistor device includes a semiconductor body (die) arranged in a housing (package), the housing (package) including an internal metallization layer and contact pads or legs located at the outer surface of the package. Such metallization layer, contact pads or legs may also include parasitic inductance. In Figure 1 These parasitic inductances are connected to the drain node D by the first inductor L P1 and a second inductor L connected to the source node S of the transistor device 1 P2 express.

[0047] With reference to the above, the transistor device 1 can be operated in an on state or an off state. The "on state" is when the transistor device 1 conducts a load current I different from zero. DS The “off state” is the load current I DS The load current I in the on state is substantially zero (so that a leakage current of, for example, several microamperes (μA) at most can flow). DS The current level depends on the supply voltage received by the series circuit having the transistor device 1 and at least one load and the type of the load. When the transistor device 1 switches from the on state to the off state, the parasitic inductance Lp1, Lp2 in series with the load path DS may cause the load path voltage (drain-source voltage) V of the transistor device 1 to increase. DS The “load path voltage DS” is the voltage between the drain node D and the source node S. Generally, the load current I DS The faster the drop and the greater the parasitic inductance L p1 , L p2 The higher it is, the higher these voltage overshoots will be.

[0048] For the purpose of explanation only, it is assumed that the load current I before the transistor device 1 is turned off is DS is 50 amperes (A), and when transistor device 1 is turned off, the load current I DS The total parasitic inductance (given by L p1 +L p2In this case, when transistor device 1 is turned off, a voltage spike of 18 volts (V) (=60A / ns·300pH) will occur. Transistor device 1 must sustain the voltage spike occurring during the transition phase plus the supply voltage, which is FIG. 2A to FIG. 2C In the example shown, it is given by the voltage between the second power supply node and the first power supply node. For example, if the power supply voltage is 12V and the voltage spike is 18V, the transistor device 1 must maintain a voltage of 30V, which is 2.5 times the power supply voltage. If the transistor device 1 is designed to maintain only the power supply voltage plus the safety margin voltage, the high voltage that occurs when the transistor device 1 is turned off can operate the transistor device 1 in avalanche mode. However, repeatedly operating the transistor device 1 in avalanche mode can cause irreversible performance degradation of the transistor device. This performance degradation may include an increase in the on-resistance of the transistor device 1. "On-resistance" is the resistance between the drain node D and the source node S in the on state. On the other hand, designing the transistor device 1 so that it can maintain the high voltage that occurs during the cut-off scenario explained previously increases the on-resistance of the transistor device compared to a transistor device with a lower voltage blocking capability, or increases the size of the transistor device and thereby increases the cost. The increased size of the transistor device is in turn associated with the reduced switching speed of the transistor device, that is, the transistor device switches from the on state to the off state more slowly, and vice versa. Therefore, it is desirable to reduce the voltage overshoot that may occur when turning off the transistor device 1 .

[0049] exist Figure 4 An example of a method that can reduce such voltage overshoot is shown in the flowchart shown. Figure 4 The method includes setting the driving voltage V of the transistor device 1 GS From the maximum voltage level V MAX drops to a level above the threshold voltage V of transistor device 1 TH The intermediate voltage level V INT (See Figure 4 101 in the method further comprises: in a predetermined time period T INT The intermediate voltage level V INT (See 102), and after a predetermined time period, the driving voltage V GS drops to the threshold voltage level V TH In the following, the driving voltage V having the maximum (voltage) level GS Also known as the maximum drive voltage V MAX , with a driving voltage V at an intermediate level GS Also known as the intermediate drive voltage V INT , and the driving voltage with a threshold voltage level is also called the threshold voltage V TH . "Threshold voltage level VTH ” is the transistor device at the driving voltage V GS When the drive voltage V GS The voltage level at which conduction stops when it decreases.

[0050] exist Figure 5 It is shown in Figure 4 The effect of the method shown, Figure 5 Shown according to Figure 4 The load path resistance R of the transistor device driven by the method shown DS , load path voltage V DS and the driving voltage V GS The load path resistance R DS ” is the resistance of transistor device 1 between drain node D and source node S. In addition, Figure 5 A signal diagram showing corresponding signals occurring in a transistor device driven in a conventional manner. More specifically, Figure 5 The curves 301, 302 and 303 shown show the Figure 4 The load path resistance R of the transistor device driven by the method shown DS , load path voltage V DS and the driving voltage V GS , and curves 201, 202 and 203 show the load path resistance R of a transistor device driven in a conventional manner. DS , load path voltage V DS and the driving voltage V GS When the driving voltage V GS With maximum level V MAX When the load path resistance R DS Min. load path resistance R DS The minimum value of is usually referred to as the on-resistance. According to one example, the on-resistance of the transistor device is a few milliohms (mΩ) or even lower, and the load path resistance R in the off state is DS It is several hundred kiloohms (kΩ) to several megaohms (MΩ). GS When the threshold voltage is reached, the load path resistance R DS Between the minimum and maximum values.

[0051] refer to Figure 1 , the transistor device includes an internal capacitor C between the gate node G and the source node S GS (Often called gate-source capacitance). Drive voltage V GS (often called the gate-source voltage) is the gate-source capacitance C GS The voltage across the two ends. Figure 5As shown in curves 201, 202, and 203, driving the transistor device 1 in a conventional manner includes rapidly discharging the gate-source capacitance C GS , thereby quickly reducing the driving voltage V GS Due to the so-called Miller effect, the driving voltage V GS Maintain the drive voltage V GS Before finally dropping to zero, it is temporarily basically at the threshold voltage V TH In the on state, the load path resistance R DS Lower, the driving voltage V GS Reaching the threshold voltage V TH before it starts to increase, and the driving voltage V GS Reaching the threshold voltage V TH Then it increases significantly. DS_ON This rapid increase in drive voltage V DS The rapid increase of load current I DS The rapid decline is associated with Figure 5 The load current I DS This rapid drop in causes the voltage overshoot explained previously. Figure 5 In the example shown, the load path voltage V DS The maximum voltage overshoot occurs during the first cycle of the parasitic oscillation, which is caused by the parasitic inductance L of transistor device 1. p1 , L p2 and output capacitor C DS The parasitic oscillation circuit formed by the output capacitor C DS ” is the capacitance C between the drain node D and the source node S of transistor device 1 DS The frequency of this parasitic oscillation can be in the range of several hundred megahertz (MHz). According to one example, when the driving voltage V GS With maximum level V MAX When the on-resistance RDS_ON is several milliohms (mΩ).

[0052] refer to Figure 5 The curves 301 and 303 shown in FIG. 1 are used to determine the driving voltage V in a predetermined time period. GS Keep at the mid level V INT Including: above the on-resistance (which is the transistor device 1 at the maximum drive voltage V MAX load path resistance when operating at low voltage) but below the threshold voltage V TH Before the transistor device 1 is finally turned off, at the intermediate drive voltage V INT Under operation, transistor device 1 dissipates the power stored in the parasitic inductance L P1 , LP2 In this way, the maximum amplitude of the parasitic oscillation is reduced, as Figure 5 As shown by curve 302 in FIG.

[0053] According to one example, the intermediate voltage level V INT Between the threshold voltage level V TH According to one example, the intermediate voltage level V INT According to another example, in a predetermined time period T INT During this period, the intermediate voltage level V INT That is, the intermediate voltage level V INT In the scheduled time period T INT At the beginning of INT_H And in the predetermined time period T INT At the end of the INT_L According to one example, the higher level V INT_H Less than the lower level V INT_L According to an example, the predetermined time period is between 0.1 nanoseconds (ns) and 10 nanoseconds, in particular between 1 nanosecond and 2 nanoseconds.

[0054] According to one example, the intermediate voltage level V is selected INT , so that the intermediate voltage V INT The associated load path resistance R DS_INT Given by:

[0055]

[0056] To effectively suppress parasitic oscillation, Lp TOT is the total parasitic inductance connected in series with transistor device 1, C DS is the output capacitance value, and c is the proportionality coefficient. Figure 1 In the example shown, the total parasitic inductance Lp TOT By parasitic inductance L p1 , L p2 The sum gives (Lp TOT =Lp1+Lp2). According to one example, c is selected from a range between 0.01 and 10, in particular between 0.02 and 5 or between 0.5 and 2. GS With an intermediate level, with the intermediate voltage V INT ” The associated load path resistance R DS_INT is the load path resistance of transistor device 1.

[0057] According to one example, the intermediate voltage level V is selected INT , so that the intermediate voltage V INT The associated load path resistance R DS_INT According to one example, the load path resistance R DS_INT According to another example, the load path resistance R DS_INT In the range between 1 ohm and 5 ohms or between 1 ohm and 2 ohms.

[0058] Figure 6 shows a configuration according to Figure 4 The method shown is an example of operating a driving circuit 2 of a transistor device 1. More specifically, Figure 6 The driving circuit 2 shown is configured according to Figure 4 The method shown disconnects the transistor device 1 .

[0059] Reference Figure 6 The driving circuit 2 includes a control circuit 3, a connection circuit 4, a disconnection circuit 5, a first output node 21 and a second output node 22. The first output node 21 and the second output node 22 of the driving circuit 2 are connected to the driving input of the transistor device 1. More specifically, Figure 6 In the example shown, the first output node 21 is connected to the gate node G, and the second output node 22 is connected to the source node S of the transistor device 1. The drive voltage V GS is the voltage between the first output node 21 and the second output node 22 of the drive circuit 2.

[0060] The on circuit 4 is connected between the first output node 21 of the driving circuit 2 and the power supply node 23 of the driving circuit 2, and the off circuit 5 is connected between the first output node 21 and the second output node 22 of the driving circuit 2. At the power supply node 23, a power supply V+ with reference to the second output node 22 can be used. According to one example, the power supply voltage V+ is generated by a voltage source 24 connected between the power supply node 23 and the second output node 22. The voltage source 24 is only Figure 6 Schematically shown in FIG. According to one example, the voltage source includes a bootstrap circuit. The voltage source 24 may be integrated in the driver circuit 2, or may be an external voltage source, so that the power supply node 23 may be an internal circuit node or an external circuit node of the driver circuit 2. According to one example, the voltage level of the power supply voltage is equal to the maximum voltage level V MAX .

[0061] The control circuit 3 is configured to receive a drive signal S DRV , and based on the driving signal S DRVControl the operation of the on-circuit 4 and the off-circuit 5. According to one example, the drive signal S DRV has one of an on level and an off level, wherein the on level indicates that the transistor device 1 is expected to be turned on, and the off level indicates that the transistor device 1 is expected to be turned off. According to an example, the control circuit 3 drives the drive signal S DRV When the turn-on circuit 4 is activated and the turn-off circuit is deactivated to turn on the transistor device 1, the control circuit 3 drives the driving signal S DRV When the control circuit 3 has a cut-off level, the disconnection circuit 5 is activated and the connection circuit 4 is deactivated to disconnect the transistor device 1. Activating or deactivating the connection circuit 4 by the control circuit 3 includes: generating a first control signal S4 by the control circuit 3 and receiving it by the connection circuit 4. In addition, activating or deactivating the disconnection circuit 5 by the control circuit 3 includes: generating a second control signal S5 by the control circuit 3 and receiving it by the disconnection circuit 5. The function of the control circuit 3 is as follows: Figure 7 As shown, Figure 7 shows the driving signal S DRV And examples of signal diagrams of the first and second control signals S4, S5.

[0062] refer to Figure 7 , when the driving signal S DRV When the drive signal S DRV When the drive signal S4 has an off level, the control circuit 3 deactivates the on circuit 4 by generating the deactivation level of the first control signal S4 and activates the off circuit 5 by generating the activation level of the second control signal S5. In the following, the activation levels of the first and second control signals S4, S5 are also referred to as on levels, and the deactivation levels of the first and second control signals S4, S5 are also referred to as off levels. For the purpose of explanation only, the drive signal S DRV The conduction level of the first and second control signals S4 and S5 is high signal level, and the driving signal S DRV The cut-off level of the first and second control signals S4 and S5 and the deactivation level of the first and second control signals S4 and S5 are low signal levels.

[0063] Figure 8 An example of the turn-on circuit 4 is shown. In this example, the turn-on circuit 4 includes an electronic switch 41 connected between the power supply node 23 and the first output node 21. The electronic switch 41 is controlled by a control signal S4 received by the turn-on circuit 4 and is turned on when the control signal S4 has a conduction level. When the electronic switch 41 is turned on, the driving voltage V GS The voltage level is essentially equal to the gate-source capacitance C GSThe voltage level of the power supply voltage V+ after being charged. According to one example, the voltage level of the power supply voltage V+ is the maximum voltage level V MAX , so that when the on-circuit is activated, the driving voltage V GS With a maximum voltage level V MAX Optionally, a current source 42 is connected in series with the electronic switch 41. This optional current source defines the current driven by the switch circuit 4 into the gate-source capacitance C GS Therefore, the optional current source 42 defines the gate-source capacitance C GS The speed of charging to the maximum level thus defines the speed at which the transistor device 1 switches from the off state to the on state. According to another example, the current source is omitted, and the charging current is defined by the supply voltage of the electronic switch 41 and the inevitable on-resistance (i.e., the resistance in the on state). The electronic switch 41 can be designed to include a desired on-resistance in order to define the (maximum) charging current. The electronic switch 41 can be implemented using any type of electronic switch. According to one example, the electronic switch 41 is implemented using a transistor device.

[0064] Fig. 9 An example of disconnection circuit 5 is shown. Fig. 9 , the disconnection circuit 5 includes an intermediate voltage circuit 6 and a discharge circuit 7. The intermediate voltage circuit 6 is configured to generate an intermediate voltage V INT , and the discharge circuit 7 is configured to eventually make the gate-source capacitance C GS Discharge, where the intermediate voltage stage is the driving voltage V GS The time period during which the intermediate voltage level is maintained.

[0065] Reference Fig. 9 The intermediate voltage circuit includes an intermediate voltage generating circuit 62 and an electronic switch 61 connected in series with the intermediate voltage generating circuit 62. The series circuit including the intermediate voltage generating circuit 62 and the electronic switch 61 is connected between the first output node 21 and the second output node 22. The electronic switch 61 of the intermediate voltage circuit 6 receives the second control signal S5, wherein when the control signal S5 has a conduction level, the electronic switch 61 is turned on. The intermediate voltage generating circuit 62 is configured to generate an intermediate voltage V INT , wherein when the second control signal S5 activates the intermediate voltage circuit 6, that is, when the control signal S5 turns on the electronic switch 61, the driving voltage V GS Basically equal to the intermediate voltage V INT The electronic switch 61 may be implemented using any type of electronic switch. According to one example, the electronic switch 61 is implemented using a transistor device.

[0066] Referring to the above, when the make circuit 4 is activated and the break circuit 5 is deactivated, the driving voltage V GS With maximum level V MAX Therefore, before the second control signal S5 activates the disconnection circuit 5 by switching on the electronic switch 61 of the intermediate voltage circuit 6, the driving voltage V GS With maximum level V MAX . Referring to the above, the intermediate voltage V INT The voltage level is lower than the maximum voltage V MAX Therefore, when the electronic switch 61 of the intermediate voltage circuit 6 is turned on, the driving voltage V GS Not immediately equal to the intermediate voltage V INT Instead, the electronic switch 61 of the intermediate voltage circuit 6 is first turned on to make the gate-source capacitance C GS Rapidly discharge until the driving voltage V GS The voltage level is basically equal to the intermediate voltage V INT until.

[0067] refer to Fig. 9 The discharge circuit 7 comprises an electronic switch 71 connected between the first output node 21 and the second output node 22. Optionally, a current source 74 is connected in series with the electronic switch 71, wherein the optional current source 74 defines or limits the discharge current conducted by the electronic switch 71 in the on state. Fig. 9 The discharge circuit 7 shown is time controlled. In this example, the discharge circuit 7 receives the second control signal S5. More specifically, the delay element 72 of the discharge circuit 7 receives the second control signal S5 and turns on (activates) the electronic switch 71 after the delay time after the intermediate voltage circuit 6 is activated. This Fig.10 Shown in.

[0068] exist Fig. 9In the example shown, the delay element 72 is an asymmetric delay element, which delays the change of the signal level of the second control signal S5 from the cut-off level to the on-level but does not delay the change from the on-level to the cut-off level. Therefore, when the control signal S5 changes from the on-level to the cut-off level, the signal S71 provided by the delay element 72 immediately turns off the electronic switch 71. Alternatively, the delay element 72 delays the signal from the cut-off level to the on-level and from the on-level to the cut-off level in the same manner. In this case, the discharge circuit 7 also includes a latch connected between the delay element 72 and the electronic switch 71. In addition to the output signal of the delay element 72, the latch 73 also receives the second control signal S5. In addition, the latch 73 generates the control signal S71 received by the electronic switch 71. According to an example, the latch 73 is an SR trigger, which is set and turns on the electronic switch 71 when the output signal of the delay element 73 changes from the cut-off level to the on-level. In this example, the output signal of the delay element 73 is received by the (non-inverting) setting input S of the trigger 73. Furthermore, the flip-flop 73 is reset by the control signal S5, and turns off the electronic switch 71 when the control signal S5 changes from the on level to the off level. In this example, the reset input R is an inverting input.

[0069] Fig.10 FIG. 2 shows a signal diagram of a second control signal S5 and a drive signal S71 received by the electronic switch 71 from the delay element 72. For illustration purposes only, Fig.10 In the example shown, the on-level of the control signals S5 and S71 (i.e., the signal level that turns on the corresponding switches 61 and 71) is a high signal level, while the off-level (the signal level that turns off the corresponding switches 61 and 71) is a low signal level. Fig.10 The delay time T after the second control signal S5 changes from the cut-off level to the on-level is the delay time T of the control signal S71 received by the electronic switch 71 in the discharge circuit 7. DEL Then it changes from the disconnection level to the connection level. The delay time T DEL defines the time period between activating the intermediate voltage circuit 6 and activating the discharge circuit 7. The delay time T DEL Affects references in the following ways Figure 4 and Figure 5 Explanation of the scheduled time period T INT :When the delay time T DEL When increasing, the scheduled time period T INT Increase, and when the delay time T DEL When decreasing, the scheduled time period T INT reduce.

[0070] Fig.10 The delay time T DEL Basically equal to the predetermined time period T INT, but not exactly equal to the predetermined time period T INT , because the delay time T DEL Including the scheduled time period T INT Add the gate-source capacitance C GS From the driving voltage V GS The maximum level V MAX Discharge to the intermediate level V INT According to one example, the gate-source capacitance C GS From the maximum level V MAX Discharge to the intermediate level V INT The time spent is less than 20% of the delay time, making the delay time T DEL Basically, the predetermined time period T is defined INT . It can be based on the gate-source capacitance C GS capacitance value, the on-resistance of the electronic switch 61, and the maximum voltage level V MAX and the intermediate level V INT To calculate the gate-source capacitance C GS From the maximum level V MAX Discharge to the intermediate level V INT The time it takes, or it can be obtained by simulating the circuit. Therefore, based on this calculation or simulation and the delay time T DEL , the predetermined time period T can be adjusted accurately INT .

[0071] Fig.11 Another example of the disconnect circuit 5 is shown. In this example, the timing of activating the intermediate voltage circuit 6 and the discharge circuit 7 is defined by the control circuit 3. More specifically, the second control signal S5 generated by the control circuit 3 and received by the disconnect circuit 5 includes a first sub-signal S51 received by the intermediate voltage circuit 6 and a second sub-signal S52 received by the discharge circuit 7. In this example, the delay time between activating the intermediate voltage circuit 6 by turning on the electronic switch 61 and activating the discharge circuit 7 by turning on the electronic switch 71 is defined by the control circuit 3.

[0072] Fig. 12A FIG. 6 shows an intermediate voltage generating circuit 62 according to an example. In this example, the intermediate voltage generating circuit 62 includes a bipolar diode 621 connected in series with the electronic switch 61. The bipolar diode 621 is coupled between the first output node 21 and the second output node 22 of the driving circuit 2, so that when the electronic switch 61 is turned on, the diode 621 passes the driving voltage (gate-source voltage) V GS In the intermediate voltage circuit 6, the intermediate voltage V INT Basically defined by the forward voltage of diode 621. Fig. 12B Shows Fig. 12AA modification of the intermediate voltage circuit 6 is shown. Fig. 12B In the intermediate voltage circuit 6 shown in FIG. 1 , the intermediate voltage generating circuit 62 includes a plurality of bipolar diodes 6211-621 connected in series. n These diodes 6211-621 n is connected between the first output node 21 and the second output node 22, so that when the electronic switch 61 is turned on, the gate-source voltage V GS Forward biased diode 6211-621 n In this example, the intermediate voltage V INT Basically, diode 6211-621 n For illustration purposes only, Fig. 12B In the example shown, the intermediate voltage generating circuit 62 includes three diodes 6211-621 n However, this is just an example. The number of diodes connected in series can be arbitrary and depends on the intermediate voltage V INT The desired voltage level.

[0073] Fig.13A Shown based on Fig. 12A The intermediate voltage generating circuit 62 shown in FIG. Fig. 12A The intermediate voltage generating circuit 62 shown is different in that it includes a Zener diode 622 instead of a bipolar diode. The Zener diode 622 is coupled between the first output node 21 and the second output node 22 so that when the electronic switch 61 is turned on, it is connected to the gate-source voltage V GS Reverse bias. Intermediate voltage V INT The voltage level of is basically limited by the breakdown voltage (Zener voltage) of the Zener diode 622. Fig. 13B Shown with Fig.13A The intermediate voltage generating circuit 62 shown in FIG. 6 is different from the intermediate voltage generating circuit 62, which includes a plurality of Zener diodes 6221-622 connected in series. n When the electronic switch 61 is turned on, the Zener diodes 6221-622 n is reverse biased. The intermediate voltage V INT The voltage level is basically determined by the series connection of the individual Zener diodes 6221-622 n For illustration purposes only, Fig. 13B In the example shown, three Zener diodes 6221-622 n It goes without saying that any number of Zener diodes can be connected in series.

[0074] Furthermore, a Schottky diode or a MOS diode may be used instead of one or more Zener diodes or one or more bipolar diodes. Even any combination may be used, including at least two different elements selected from a Zener diode, a bipolar diode, a Schottky diode or a MOS diode.

[0075] Fig.14 An intermediate voltage circuit 6 according to another example is shown. In this example, the intermediate voltage generating circuit 62 comprises a voltage source 623 connected in series with an electronic switch 61 .

[0076] Fig.15 FIG. 2 shows a discharge circuit 7 according to another example. In this example, the discharge circuit 7 is voltage-controlled. More specifically, the electronic switch 71 of the discharge circuit 7 is controlled according to the driving voltage V GS To this end, the discharge circuit 7 includes a comparator circuit 75 connected between the first output node 21 and the second output node 22. The comparator circuit 75 is configured to detect the driving voltage V GS When it falls below the lower intermediate voltage level V INT_L This is Fig.16 Shown in.

[0077] Fig.16 The driving voltage V is received by the electronic switch 71 of the discharge circuit 7 and generated by the comparator circuit 75. GS and a signal diagram of the control signal S71. In this example, the intermediate voltage circuit 6 generates an intermediate voltage level V INT , so that it is in the middle voltage phase T INT For example, Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B Any intermediate voltage generating circuit 62 shown generates a reduced intermediate voltage level V INT When the intermediate voltage circuit 6 includes an intermediate voltage generating circuit 62 of one of these types, once the drive circuit V GS The at least one bipolar diode 621, 6211-621 is provided. n The forward voltage of the circuit or at least one Zener diode 622, 6221-622 n The Zener voltage of the circuit defines the voltage level that discharges the gate-source capacitance C GS However, as long as the drive voltage is higher than this forward voltage or Zener voltage, the gate-source capacitance C GS is slowly discharged, and the driving voltage V GS The lower intermediate voltage level V detected by the comparator circuit 75 INT_LEither the voltage level given by the forward voltage or the Zener voltage, or higher than that.

[0078] exist Fig.15 In the disconnected circuit shown, the predetermined time period T INT By the driving voltage V GS from Fig.16 The higher intermediate voltage level V INT_H The time taken to decrease to the lower intermediate voltage level is given by: In particular, this time period can be adjusted by appropriately selecting the on-resistance of the electronic switch 61 .

[0079] The comparator circuit 75 can be implemented in various ways. Fig.17 In one example shown, the comparator circuit 75 includes a resistor divider 751, 752 connected between the first output node 21 and the second output node 22 and a Schmitt trigger 753 connected to a tap of the resistor divider. According to one example, the control signal S71 is provided by the inverting output of the Schmitt trigger 753.

[0080] according to Fig.18 In another example shown, the comparator circuit 75 includes a comparator 754, which is configured to convert the driving voltage V GS is compared with a reference voltage provided by reference voltage source 755. The voltage level of the reference voltage is equal to the lower intermediate voltage level V INT_L According to an example, the inverting input of the comparator 754 is connected to the first output node 21 of the driving circuit, and the non-inverting input is connected to the second output node 22 via the reference voltage source 755 .

[0081] Fig.19 Shows Figure 7 In this example, the discharge circuit 7 includes a comparator circuit 76, which is configured to convert the drive voltage V GS The voltage level is different from the higher intermediate voltage level V INT_H The delay element 77 is connected downstream of the comparator circuit 76 and is configured to detect the driving voltage V GS has reached a higher intermediate voltage level V INT_H After a predetermined delay time, the electronic switch 71 is turned on. Fig. 20 It is shown in Fig. 20 shows the driving voltage V GS , an output signal S76 generated by the comparator circuit 76, and a control signal S71 received by the electronic switch 71 and generated by the delay element 77. Fig. 20 In the example shown, when the driving voltage V GSThe voltage level reaches the higher intermediate voltage level V INT_H When the output signal S76 of the comparator circuit 76 changes from the cut-off level to the on level. The delay element 77 generates the on level of the control signal S71 to turn on the electronic switch 71 after a predetermined delay time after the signal level of the comparator signal S76 has changed from the cut-off level to the on level. In this example, the intermediate voltage circuit 6 can be configured so that the intermediate voltage level V INT is substantially constant during this delay time, such as Fig. 20 However, the intermediate voltage circuit 6 can also be implemented so that during the delay time, the intermediate voltage level drops to the intermediate voltage threshold value V INT_L This is like Fig. 20 According to one example, the upper threshold used by the comparator circuit 76 is selected to be equal to the upper intermediate voltage threshold V explained previously. IN'T_H In this example, the predetermined time period T of the intermediate voltage phase INT = is equal to the delay time of the delay element 77. According to one example, the delay element 77 is an asymmetric delay element. Alternatively, reference Fig. 9 Explain the latch.

[0082] Fig.21 A flow chart showing a modification of the method explained earlier in this document is shown. Fig.21 The method includes setting the driving voltage V GS From the maximum voltage level V MAX to at least two different intermediate voltage levels. Fig.21 The method includes setting the driving voltage V GS From the maximum voltage level V MAX Reduced to the first intermediate voltage level V INT1 , and in the predetermined first time period T INT1 The first intermediate voltage level V INT1 (See Fig.21 In addition, the method includes setting the driving voltage V DS From the first intermediate voltage level V INT1 drops below the threshold voltage V TH The additional intermediate voltage level V INTn , and in an additional predetermined time period T INTn The additional intermediate voltage level V INTn (See Fig.21 Step 101 n , 102 n Finally, the method comprises adding a predetermined time period T INTn Then the driving voltage V GSReduced to the threshold voltage V TH The following (see Fig.21 Method step 103 in ).

[0083] Fig.21 The method shown includes two different intermediate voltage levels V INT1 、V INTn The drive voltage is increased from the maximum voltage level V MAX Reduced to the threshold voltage V TH Below, where these intermediate voltage levels V INT1 、V INTn Each of them maintains a corresponding time period T INT1 , T INTn However, using two different intermediate voltages V INT1 、V INTn This is just an example. Generally, any number of intermediate voltages can be implemented. According to one example, the number of different intermediate voltages is selected from between 2 and 5.

[0084] Fig. 22 Shown according to Fig.21 The driving voltage V of the transistor device 1 operated by the method shown is GS An example of a signal plot of . Fig. 22 It can be seen that in this example, the driving voltage V GS From the maximum level V MAX Reduced to the first intermediate level V INT1 , which in the first time period T INT1 In addition, in the first time period T INT1 After that, the driving voltage V GS From the first intermediate level V INT1 Reduced to an additional intermediate level V INTn , which is driven by voltage V GS Reduced to the threshold voltage V TH The following additional time period T is required before turning off the transistor device. INTn The interior remains basically unchanged.

[0085] Fig.23 An example of a disconnect circuit 5 is shown, which is configured according to reference Fig.21 and Fig. 22 The disconnection circuit 5 comprises a plurality of intermediate voltage circuits 61-6 n , wherein these intermediate voltage circuits 61-6 n Each of the intermediate voltage generation circuits 621-62 is implemented according to the intermediate voltage circuit described above and includes intermediate voltage generation circuits 621-62 n and intermediate voltage generating circuit 621-62 nElectronic switches connected in series 611-61 n These intermediate voltage generating circuits 621-62 n are implemented so that they generate different intermediate voltages V INT1 、V INT2 、V INTn These intermediate voltage circuits 61-6 n Each of them is connected by a corresponding electronic switch 611-61 n The corresponding control signals S511-S51 received from the control circuit 3 n To activate ( Fig.23 not shown).

[0086] For illustrative purposes only, Fig.23 The disconnect circuit 5 shown comprises three intermediate voltage circuits 61-6 n , so that when the transistor device 1 is turned off, up to three different intermediate voltage levels can be continuously generated using the disconnection circuit 5. However, implementing three intermediate voltage circuits is only an example. Any number of different intermediate voltage levels 61-6 n .

[0087] exist Fig.23 In the disconnection circuit 5 shown, the control circuit 3 is used to limit the activation of different intermediate voltage circuits 61-6 n In addition, in this example, the control circuit 3 controls the discharge circuit 7 by generating a drive signal S52 received by the electronic switch 71 of the discharge circuit 7. Therefore, relative to activating the intermediate voltage circuit 61-6 n , the timing of activating the discharge circuit 7 is also defined by the control circuit 3 .

[0088] Fig.24 A disconnection circuit 5 according to another example is shown. The disconnection circuit 5 is based on Fig.23 The disconnect circuit shown, and with Fig.23 The disconnect circuit shown is different in that only a plurality of intermediate voltage circuits 61-6 n The first intermediate voltage circuit 61 in the embodiment receives a control signal S5 ( Fig.24 ), and a plurality of intermediate voltage circuits 61-6 n Other circuits in 62-6 n And the discharge circuit 7 is voltage controlled. That is, these intermediate voltage circuits 62-6 n Each of the comparator circuits 632-63 n , the comparator circuit detects the driving voltage V GS And at the driving voltage V GS to a corresponding lower intermediate voltage level V INT1_L 、VINT2_L The corresponding intermediate voltage circuit 62-6 is activated when n The discharge circuit 7 includes a comparator circuit 73, which detects the driving voltage V GS And at the driving voltage V GS Reaching another intermediate voltage level V INTn_L The discharge circuit 7 is activated. Fig.24 The intermediate voltage circuit 61-6 shown n These are referred to hereinafter as first, second and third intermediate voltage circuits.

[0089] exist Fig.25 Shown in Fig.24 The function of the disconnect circuit 5 shown is Fig.25 shows the driving voltage V GS and the comparator circuits 632, 63 in the intermediate voltage circuits 62, 63 n The generated switch control signals S612, S61 n , and a signal diagram of a switch control signal S71 generated by a comparator circuit 73 in the discharge circuit 7. Fig.25 , when the driving voltage V GS The intermediate voltage V generated by the first intermediate voltage circuit 61 is reduced to INT1 The low level V INT1_L When the driving voltage V GS The voltage drops to the low level V of the intermediate voltage generated by the second intermediate voltage circuit 62. INT2_L When the third intermediate voltage circuit 6 n Comparator circuit 63 in n Activate the third intermediate voltage circuit 6 n Finally, when the driving voltage V GS The third intermediate voltage circuit 6 n The generated intermediate voltage V INTn The lower level V INTn_L When the comparator circuit 73 of the discharge circuit 7 activates the discharge circuit, the discharge circuit is activated. Fig.25 In the example shown, the intermediate voltage circuits 62, 6 n and discharge circuit 7 are equivalent to the corresponding control signals S612, S61 n , high signal level of S71.

[0090] Fig.26 Shown is a reference Figure 4 A further modification of the method is explained. GS From the maximum voltage level V MAX Reduce to the intermediate voltage V INT Previously, according to Fig.26 The method comprises measuring a load current I DS (see method step 104), and based on the measured load current I DS Select an intermediate voltage. In an electronic circuit of the type explained previously, the voltage stored in the parasitic inductance L p2 , L p2 The energy in the DS According to one example, the intermediate voltage V is selected from a plurality of different intermediate voltages. INT , so that the intermediate voltage changes with the load current I DS As described above, the lower the intermediate voltage, the higher the on-resistance of the transistor device 1 during the intermediate stage. Therefore, the higher the load current I DS is associated with a lower on-resistance during the intermediate phase to dissipate the parasitic inductance L stored in the transistor device 1 during the intermediate phase. p1 , L p2 The power in.

[0091] Fig. 27 It is shown that when the transistor device 1 is conventionally turned off (ie, without an intermediate stage (see Fig. 27 Curves 203, 202) in FIG. 1 and the driving voltage V when the transistor device is turned off using one of a plurality of different intermediate voltages. GS and the load path voltage V DS Curve 3031 shows the use of the first intermediate voltage to turn off the transistor device V GS , and curve 3021 shows the associated load path voltage V DS Curve 3032 shows the use of a second intermediate voltage lower than the first intermediate voltage 3031 to turn off the transistor device, and curve 3022 shows the associated load path voltage V DS In addition, curve 303 n The transistor device is turned off using a third intermediate voltage lower than the second intermediate voltage 3032, and the curve 302 n shows the associated load path voltage V DS .from Fig. 27 It can be seen that as the intermediate voltage increases, the amplitude of the parasitic oscillation decreases. It should be noted that Fig. 27 The curves shown are for the same load current I DS and different intermediate voltages are obtained.

[0092] Fig.28 An example of a drive circuit 2 is shown, which is configured according to Fig.26 and Fig. 27The method shown operates the transistor device. The driving circuit differs from the driving circuit explained previously in this document in that the control circuit 3 receives a current I representing the load current through the transistor device 1 DS The load current signal S IDS The load current signal S IDS The current can be obtained using any type of conventional current measurement circuit configured to measure the current through the transistor device 1. Such current measurement circuits are well known and no further explanation is needed in this regard. Fig.28 The schematic diagram shows the load current I DS And generate load current signal S IDS Current measurement circuit 8.

[0093] In addition, reference Fig.28 , the disconnect circuit 5 includes a plurality of intermediate voltage circuits 61-6 n , wherein the control circuit 3 is further configured to control the load current signal S IDS Activate these intermediate voltage circuits 61-6 n Use Fig.28 The turn-off circuit 5 shown in FIG. 5 is a circuit in which the transistor device 1 is turned off according to the load current I flowing through the transistor device 1 which is in the on state before the transistor device 1 is turned off. DS And disconnect.

[0094] According to one example, instead of just turning off the transistor device 1 , turning on the transistor device 1 also depends on the load current I measured before turning off the transistor device 1 DS .exist Fig.29 is configured according to the load current I DS An example of a turn-on circuit 4 for turning on a transistor device 1. In this example, the turn-on circuit 4 includes a plurality of electronic switches 411-41 m These electronic switches 411-41 m are connected in parallel between the power supply node 23 and the first output node 21. In addition, these electronic switches 411-41 m According to one example, the electronic switches 411-41 m is implemented as a MOSFET, such as a p-type MOSFET. Receives a load current signal S IDS The control circuit 3 is configured to DRV These electronic switches 411-41 are turned on when it is desired to turn on transistor device 1 m According to one example, the control circuit 3 is configured to select at least one electronic switch 411-41 switched on by the control circuit 3. m , so that the load current I detected before turning off the transistor device 1 DSThe larger the load current I is, the higher the resistance between the power supply node and the first output node 21 in the on state of at least one electronic switch selected by the control circuit 3 is. DS The larger it is, the slower the transistor device 1 turns on.

[0095] Fig.30 An example of a disconnect circuit 5 is shown. In this example, each intermediate voltage circuit 61-6 n By reference Fig. 9 The discharge circuit 7 can be implemented according to any of the examples explained above. In the example shown in FIG. 13 , the activation of the intermediate voltage circuit 61-6 is controlled by the control circuit 3. n One and the timing of the discharge circuit 7.

[0096] Fig.31 FIG. 5 shows a disconnection circuit 5 according to another example. In this example, the discharge circuit 7 includes a plurality of electronic switches 711-712 having different on-resistances. n , which are connected in parallel between the first output node 21 and the second output node 22. In this example, when the discharge circuit 7 is activated, the control circuit turns on these electronic switches 711-71 n According to one example, the control circuit 3 is configured to turn on different switch groups one by one to form a discharge current and a drive voltage V GS , wherein each of the “different switch groups” includes one or more electronic switches 711-71 n .

[0097] According to another example, the control circuit 3 is configured to simultaneously turn on one or more electronic switches 711-71 n , and during the complete time period, the discharge circuit 7 is activated. n The information of being turned on may be stored in a memory (such as a register) of the control circuit 3. The switch to be turned on may be selected according to the type of transistor device 1 connected to the driving circuit.

[0098] According to an example, the control circuit 3 receives a signal indicating the driving voltage V GS The driving voltage signal S VGS , and is configured to be based on the driving voltage signal S VGS The discharge circuit 7 is activated. According to one example, for example, the control circuit 3 monitors the drive voltage S VG , and the driving voltage signal S VG When the first threshold is reached, the first intermediate voltage generator 621 is activated. VGWhen the second threshold value lower than the first threshold value is reached, the second intermediate voltage generator 622 is activated, and the driving voltage signal S VG When a third threshold value lower than the second threshold value is reached, the third intermediate voltage generator 62 is activated. n , to obtain Fig.25 The driving voltage curve is shown.

[0099] No need to elaborate, refer to Fig.26 and Fig.21 The methods of interpretation can be combined in the following way: Fig.26 In the method explained, there are two or more intermediate voltage stages with different intermediate voltage levels, each of which is higher than the threshold voltage level V TH According to the load current signal S IDS At least one of the different intermediate voltage levels is selected.

[0100] Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the present disclosure.

[0101] Example 1. A method comprising: in an on-state of the transistor device, reducing a driving voltage of the transistor device from a maximum voltage level to an intermediate voltage level higher than a threshold voltage level of the transistor device; maintaining the intermediate voltage level for a predetermined time period; and reducing the driving voltage to below the threshold voltage level after the predetermined time period to switch the transistor device to an off-state.

[0102] Example 2. The method of Example 1, wherein the predetermined time period is selected from a range between 0.1 nanoseconds and 10 nanoseconds.

[0103] Example 3. The method of any combination of Examples 1-2, wherein during the predetermined time period, the intermediate voltage level decreases from a higher intermediate voltage level to a lower intermediate voltage level, wherein the higher intermediate voltage level is less than 1.3 times the lower intermediate voltage level.

[0104] Example 4. The method of any combination of Examples 1 to 3, wherein the transistor device includes an intermediate load path resistance associated with the intermediate voltage level, the intermediate voltage being selected such that the intermediate load path resistance is between 0.01 ohms and 1000 ohms.

[0105] Example 5. The method of any combination of Examples 1 to 4, wherein at least one parasitic inductance is connected in series with the transistor device and a parasitic capacitance is connected in parallel with a load path of the transistor device, wherein the transistor device includes an intermediate load path resistance associated with an intermediate voltage level, and the intermediate voltage is selected such that the intermediate load path resistance is given by the following equation:

[0106]

[0107] Among them, Lp TOT is the inductance value of at least one parasitic inductor connected in series with the transistor device, C DS is the capacitance value of the parasitic capacitance, and c is a proportionality coefficient selected from between 0.01 and 100.

[0108] Example 6. The method of any combination of Examples 1 to 5, further comprising: measuring a load current through the transistor device; and selecting the intermediate voltage from a plurality of intermediate voltages based on the measured load current.

[0109] Example 7. A method according to any combination of Examples 1 to 6, wherein maintaining the intermediate voltage includes: activating an intermediate voltage circuit connected between driving nodes of the transistor device, and the intermediate voltage circuit includes an intermediate voltage generating circuit and an electronic switch connected in series with the intermediate voltage generating circuit.

[0110] Example 8. The method of any combination of Examples 1 to 7, wherein the intermediate voltage generating circuit comprises at least one diode.

[0111] Example 9. The method of any combination of Examples 1 to 8, wherein reducing the drive voltage below the threshold voltage level comprises activating a discharge circuit connected between drive nodes of the transistor device.

[0112] Example 10. The method of any combination of Examples 1 to 9, further comprising: before reducing the drive voltage below the threshold voltage, reducing the drive voltage from the intermediate voltage level to at least one additional intermediate voltage level, and maintaining the at least one additional intermediate voltage for an additional predetermined time period.

[0113] Example 11. The method of any combination of Examples 1 to 10, wherein the transistor device is a MOSFET.

[0114] Example 12. An electronic circuit comprising: a driving circuit, the driving circuit being configured to reduce a driving voltage of a transistor device from a maximum voltage level to an intermediate voltage level higher than a threshold voltage level of the transistor device when the transistor device is in an on state; maintain the intermediate voltage level for a predetermined time period; and reduce the driving voltage to below the threshold voltage after the predetermined time period to switch the transistor device to an off state.

[0115] Example 13. An electronic circuit according to Example 12, wherein the driving circuit includes: an output node configured to be coupled to a driving node of a transistor device; an intermediate voltage circuit connected between the output nodes and including an intermediate voltage generating circuit and an electronic switch connected in series with the intermediate voltage generating circuit; and a discharge circuit connected between the output nodes.

[0116] Example 14. The electronic circuit of any combination of Examples 12 to 13, wherein the intermediate voltage generating circuit comprises at least one diode.

[0117] Example 15. The electronic circuit according to any combination of Examples 12 to 14, further comprising a transistor device.

[0118] Although the invention has been described with reference to the illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art after reference to the description.

Claims

1. A method comprising: When the transistor device (1) is in the on state, the load current (I DS ); According to the load current measured (I DS ) selects an intermediate voltage level (V INT ), so that the larger the load current is, the higher the selected intermediate voltage level is; In the on-state of the transistor device (1), the driving voltage (V GS ) from the maximum voltage level (V MAX ) drops to a level above the threshold voltage (V TH ) of the intermediate voltage level (V INT ); During the predetermined time period (T INT ) to maintain the intermediate voltage level (V INT );as well as During the predetermined time period (T INT ) and then the driving voltage (V GS ) drops to the threshold voltage level (V TH ) below to switch the transistor device to the cut-off state, The intermediate voltage level (V INT ) has a higher intermediate voltage level (V INT_H ), and has a lower intermediate voltage level (V INT_L ),and The intermediate voltage level (V INT ) includes: converting the intermediate voltage level (V INT ) is maintained at the higher intermediate voltage level (V INT_H ) with the lower intermediate voltage level (V INT_L )between.

2. The method according to claim 1, wherein the predetermined time period (T INT ).

3. The method according to claim 1 or 2, The higher intermediate voltage level (V INT_H ) is less than the lower intermediate voltage level (V INT_L ) is 1.3 times.

4. The method according to any one of claims 1 to 3, wherein the transistor device (1) comprises a INT ) is associated with the intermediate load path resistance (R DS_INT ), The intermediate voltage level (V INT ), so that the intermediate load path resistance is between 0.01 ohms and 1000 ohms.

5. The method according to any one of claims 1 to 3, wherein at least one parasitic inductance is connected in series with the transistor device (1) and a parasitic capacitance is connected in parallel with a load path of the transistor device, wherein the transistor device includes a transistor connected to the intermediate voltage level (V INT ) is associated with the intermediate load path resistance (R DS_INT ),and The intermediate voltage level (V INT ), so that the intermediate load path resistance is given by the following equation: Among them, Lp TOT is the inductance value of the at least one parasitic inductor connected in series with the transistor device (1), C DS is the capacitance value of the parasitic capacitance, and c is a proportionality coefficient selected between 0.01 and 100.

6. The method according to any one of the preceding claims, which maintains the intermediate voltage level (V INT )include: activating an intermediate voltage circuit (6) connected between the driving nodes (G, S) of the transistor device (1), and The intermediate voltage circuit (6) comprises an intermediate voltage generating circuit (62) and an electronic switch (61) connected in series with the intermediate voltage generating circuit (62).

7. The method according to claim 6, The intermediate voltage generating circuit (62) comprises at least one diode.

8. The method according to claim 6 or 7, The driving voltage (V GS ) falls below the threshold voltage level including: A discharge circuit connected between the drive nodes (G, S) of the transistor device (1) is activated.

9. The method according to any one of the preceding claims, further comprising: When the driving voltage (V GS ) drops to the threshold voltage level (V TH ) before the drive voltage (V GS ) from the intermediate voltage level (V INT ) to at least one additional intermediate voltage level and maintaining the at least one additional intermediate voltage level for an additional predetermined time period.

10. A method according to any preceding claim, wherein the transistor device is a MOSFET.

11. An electronic circuit comprising: Drive circuit (2), The driving circuit is configured as follows: When the transistor device (1) is in the on state, the load current (I DS ); According to the load current measured (I DS ) selects an intermediate voltage level (V INT ), so that the larger the load current is, the higher the selected intermediate voltage level is; In the on-state of the transistor device (1), the driving voltage (V GS ) from the maximum voltage level (V MAX ) drops to a level above the threshold voltage (V TH ) of the intermediate voltage level (V INT ); During the predetermined time period (T INT ) to maintain the intermediate voltage level (V INT );as well as During the predetermined time period (T INT ) and then the driving voltage (V GS ) drops to the threshold voltage level (V TH ) below to switch the transistor device to the cut-off state, The intermediate voltage level (V INT ) has a higher intermediate voltage level (V INT_H ), and has a lower intermediate voltage level (V INT_L ),and The intermediate voltage level (V INT ) includes: converting the intermediate voltage level (V INT ) is maintained at the higher intermediate voltage level (V INT_H ) with the lower intermediate voltage level (V INT_L )between.

12. The electronic circuit according to claim 11, wherein the drive circuit comprises: An output node (21, 22) configured to be coupled to a driving node of the transistor device (1); An intermediate voltage circuit (6) connected between the output nodes (21, 22) and comprising an intermediate voltage generating circuit (62) and an electronic switch (61) connected in series with the intermediate voltage generating circuit (62); A discharge circuit (7) is connected between the output nodes (21, 22).

13. The electronic circuit according to claim 12, The intermediate voltage generating circuit (62) comprises at least one diode.

14. The electronic circuit according to any one of claims 11 to 13, further comprising the transistor device (1).

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