Semiconductor package including interposer

Abstract

A semiconductor package including an interposer is provided. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; a plurality of first connection pillars respectively located on at least a portion of the plurality of lower redistribution line patterns; at least one interposer located on the lower redistribution line structure and spaced apart from each other, each interposer including a plurality of connection wiring patterns and a plurality of second connection pillars respectively located on a portion of the plurality of connection wiring patterns and spaced apart from each other; an upper redistribution line structure located on at least one interposer and the plurality of first connection pillars and including a plurality of upper redistribution line patterns respectively connected to the plurality of first connection pillars and the plurality of second connection pillars; and at least two semiconductor chips attached to the upper redistribution line structure spaced apart from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0089508 filed on Jul. 31, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package including a plurality of semiconductor chips, and more particularly, to a semiconductor package including an interposer for interconnecting the plurality of semiconductor chips to one another. Background Art

[0004] According to the development of the electronic industry and the continuous improvement of user demands, electronic devices have been further miniaturized, multifunctionalized and / or increased in capacity, and therefore, a semiconductor package including a plurality of semiconductor chips is required.

[0005] When each of a plurality of semiconductor chips included in a semiconductor package is highly integrated, a printed circuit board may not be able to accommodate such high integration. In this regard, a semiconductor package that interconnects a plurality of semiconductor chips through an interposer has been developed. Summary of the invention

[0006] The inventive concept provides a semiconductor package including an interposer that can be implemented at a lower cost.

[0007] According to one aspect of the inventive concept, a semiconductor package is provided, the semiconductor package comprising: a lower redistribution line structure, the lower redistribution line structure comprising a plurality of lower insulating layers and a plurality of lower redistribution line patterns respectively located on at least one of top surfaces and bottom surfaces of the plurality of lower insulating layers; a plurality of first connecting pillars, the plurality of first connecting pillars respectively located on at least a portion of the plurality of lower redistribution line patterns; an interposer, the interposer being located on the lower redistribution line structure and spaced apart from the plurality of first connecting pillars, and comprising an interposer substrate, a top surface of the interposer substrate, and a bottom surface of the interposer substrate; A plurality of connection wiring patterns on a surface thereof and a plurality of second connection pillars respectively located on at least a portion of the plurality of connection wiring patterns; an upper redistribution line structure, the upper redistribution line structure comprising at least one upper insulating layer and a plurality of upper redistribution line patterns located on a top surface or a bottom surface of the at least one upper insulating layer and respectively connected to the plurality of first connection pillars and the plurality of second connection pillars; and at least two semiconductor chips, the at least two semiconductor chips being located on the upper redistribution line structure, the at least two semiconductor chips being electrically connected to the plurality of upper redistribution line patterns spaced apart from each other.

[0008] According to another aspect of the inventive concept, a semiconductor package is provided, the semiconductor package comprising: a package base substrate; a lower redistribution line structure, the lower redistribution line structure being located on the package base substrate and comprising a plurality of lower redistribution line patterns; a plurality of first connecting pillars, the plurality of first connecting pillars being respectively located on at least a portion of the plurality of lower redistribution line patterns; at least one interposer, the at least one interposer being located on the lower redistribution line structure and spaced apart from each other, each of the at least one interposer comprising a plurality of connection wiring patterns and a plurality of second connecting pillars spaced apart from each other, the upper redistribution line structure being located on the at least one interposer and the plurality of first connecting pillars, and comprising a plurality of upper redistribution line patterns respectively connected to the plurality of first connecting pillars and the plurality of second connecting pillars; and at least two semiconductor chips, the at least two semiconductor chips being spaced apart from each other on the upper redistribution line structure and electrically connected to the plurality of upper redistribution line patterns.

[0009] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a lower redistribution line structure, the lower redistribution line structure comprising a plurality of lower redistribution line patterns; a plurality of first connecting pillars, the plurality of first connecting pillars being connected to the plurality of lower redistribution line patterns; an interposer, the interposer being located on the lower redistribution line structure, the interposer comprising an interposer substrate, a plurality of connecting wiring patterns located on the interposer substrate, and a plurality of second connecting pillars located on the plurality of connecting wiring patterns; an upper redistribution line structure, the upper redistribution line structure comprising a plurality of upper redistribution line patterns located on the plurality of first connecting pillars and the interposer and electrically connected to the plurality of first connecting pillars and the plurality of second connecting pillars; and at least two semiconductor chips, the at least two semiconductor chips being located on the upper redistribution line structure and electrically connected to the plurality of upper redistribution line patterns, wherein a portion of the plurality of upper redistribution line patterns and a portion of the plurality of lower redistribution line patterns extend in a horizontal direction beyond a coverage area occupied by the at least two semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a cross-sectional view of a semiconductor package according to one embodiment;

[0012] Figure 1B It is the planar layout of the wiring of the interposer and the wiring of the upper redistribution line structure in the semiconductor package;

[0013] Figures 2 to 8 is a cross-sectional view of a semiconductor package according to an embodiment;

[0014] FIG. 9A to FIG. 9I is a cross-sectional view for explaining a method of manufacturing a semiconductor package according to one embodiment;

[0015] FIG. 10A to FIG. 10G is a cross-sectional view for explaining a method of manufacturing a semiconductor package according to another embodiment; and

[0016] Figures 11 to 14 is a planar layout of a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0017] Figure 1A is a cross-sectional view of a semiconductor package 1 according to an embodiment.

[0018] Reference Figure 1A The semiconductor package 1 includes a lower redistribution line structure 210, an interposer 230, an upper redistribution line structure 260, and / or at least two semiconductor chips 300. The interposer 230 may be disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and at least two semiconductor chips 300 may be attached to the upper redistribution line structure 260.

[0019] The lower redistribution line structure 210 may include a plurality of lower insulating layers 216 , a plurality of lower redistribution line patterns 212 respectively disposed on at least one of top and bottom surfaces of the plurality of lower insulating layers 216 , and a plurality of lower via patterns 214 respectively penetrating the plurality of lower insulating layers 216 and respectively contacting the plurality of lower redistribution line patterns 212 .

[0020] Each of the plurality of lower insulating layers 216 may be formed of, for example, a material layer including an organic compound. According to one embodiment, each of the plurality of lower insulating layers 216 may be formed of a material layer including an organic polymer material. According to one embodiment, each of the plurality of lower insulating layers 216 may be formed of photosensitive polyimide (PSPI).

[0021] The lower redistribution line pattern 212 and the lower via pattern 214 may each include a metal such as copper (Cu), tungsten (W), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga) or ruthenium (Ru), their alloys or metal nitrides, but are not limited thereto.

[0022] The lower redistribution line pattern 212 and the lower via pattern 214 may each include a seed layer contacting the lower insulating layer 216 and a conductive material layer located on the seed layer. According to one embodiment, the seed layer may be formed by physical vapor deposition, and the conductive material layer may be formed by chemical plating. A portion of the lower redistribution line pattern 212 may be formed integrally with a portion of the lower via pattern 214. For example, the lower redistribution line pattern 212 may be formed integrally with a portion of the lower via pattern 214 that contacts the top of the lower redistribution line pattern 212; or the lower redistribution line pattern 212 may be formed integrally with a portion of the lower via pattern 214 that contacts the bottom of the lower redistribution line pattern 212.

[0023] exist Figure 1A In the embodiment, the lower redistribution line pattern 212 is disposed only between two adjacent layers among the plurality of lower insulation layers 216, but is not limited thereto. According to one embodiment, the lower redistribution line pattern 212 may also be disposed on a top surface of an uppermost lower insulation layer 216 and / or a bottom surface of a lowermost lower insulation layer 216 among the plurality of lower insulation layers 216.

[0024] The lower redistribution line pattern 212 disposed on the top surface or the bottom surface of the lower insulating layer 216 may be referred to as or may constitute a lower redistribution line pattern layer. The lower redistribution line structure 210 may have a plurality of lower redistribution line pattern layers including a first lower redistribution line pattern layer LY11 (hereinafter referred to as the first lower layer LY11), a second lower redistribution line pattern layer LY12 (hereinafter referred to as the second lower layer LY12), and a third lower redistribution line pattern layer LY13 (hereinafter referred to as the third lower layer LY13).

[0025] A plurality of first connection pillars 220 and an interposer 230 may be attached on the lower redistribution line structure 210. Each of the plurality of first connection pillars 220 may be disposed on the lower redistribution line structure 210 and spaced apart from the interposer 230.

[0026] A plurality of first connection pillars 220 may be respectively disposed on a plurality of portions of the plurality of lower redistribution line patterns 212. The first connection pillars 220 may be connected to, for example, the uppermost lower redistribution line pattern layer of the lower redistribution line structure 210, for example, when the lower redistribution line structure 210 has three lower redistribution line pattern layers, the first connection pillars 220 may be connected to the third lower layer LY13. For example, the first connection pillars 220 may be formed of the same material as the lower redistribution line pattern 212 or the lower via pattern 214.

[0027] The interposer 230 may be attached on the lower redistribution line structure 210 by, for example, a die attach film 240. According to one embodiment, the interposer 230 may be attached on a top surface of an uppermost lower insulation layer 216 among a plurality of lower insulation layers 216 included in the lower redistribution line structure 210.

[0028] The interposer 230 may include an interposer substrate 232 and a plurality of connection wiring patterns 234 disposed on a top surface of the interposer substrate 232 .

[0029] The interposer substrate 232 may be a semiconductor substrate. For example, the interposer substrate 232 may include silicon (Si). A plurality of connection wiring patterns 234 may be formed on the interposer substrate 232 by a common wiring process of a semiconductor device. The plurality of connection wiring patterns 234 may include a layer of connection line wiring, but are not limited thereto. According to one embodiment, the plurality of connection wiring patterns 234 may include at least one layer of connection line wiring and a via plug that interconnects the connection line wiring of different layers. Here, an inter-wiring insulating layer may be provided between the connection line wiring and the via plug. The interposer 230 may be formed by performing only a wiring process on a semiconductor substrate without forming a separate electronic device.

[0030] The interposer 230 may further include a plurality of second connection pillars 236 respectively disposed on portions of the plurality of connection wiring patterns 234. According to one embodiment, the plurality of second connection pillars 236 may be attached to portions adjacent to both ends of the plurality of connection wiring patterns 234, respectively.

[0031] The upper redistribution line structure 260 may be located on the first connection pillars 220 and the interposer 230. The upper redistribution line structure 260 may include at least one upper insulating layer 266, a plurality of upper redistribution line patterns 262 disposed on a top surface or a bottom surface of the at least one upper insulating layer 266, and / or a plurality of upper via patterns 264 penetrating the upper insulating layer 266 and contacting portions of the plurality of upper redistribution line patterns 262, respectively.

[0032] The upper redistribution line pattern 262 , the upper via pattern 264 , and the upper insulating layer 266 are respectively the same as the lower redistribution line pattern 212 , the lower via pattern 214 , and the lower insulating layer 216 , and thus their details will not be provided.

[0033] The upper redistribution line pattern 262 disposed on the top surface or the bottom surface of the upper insulating layer 266 may be referred to as or may constitute an upper redistribution line pattern layer. The upper redistribution line structure 260 may have a plurality of upper redistribution line pattern layers including a first upper redistribution line pattern layer LY21 (hereinafter referred to as the first upper layer LY21) and a second upper redistribution line pattern layer LY22 (hereinafter referred to as the second upper layer LY22). The number of redistribution line pattern layers of the upper redistribution line structure 260 may be less than the number of redistribution line pattern layers of the lower redistribution line structure 210. For example, the lower redistribution line structure 210 may include at least three redistribution line pattern layers, and the upper redistribution line structure 260 may include at least two upper redistribution line pattern layers, which is less than the at least three redistribution line pattern layers of the lower redistribution line structure 210.

[0034] The first connection pillar 220 may interconnect the lower redistribution line pattern 212 of the lower redistribution line structure 210 and the upper redistribution line pattern 262 of the upper redistribution line structure 260. For example, the first connection pillar 220 may contact the uppermost lower redistribution line pattern layer of the lower redistribution line structure 210 (e.g., the top surface of the lower redistribution line pattern 212 of the third lower layer LY13) and the lowermost upper redistribution line pattern layer of the upper redistribution line structure 260 (e.g., the bottom surface of the upper redistribution line pattern 262 of the first upper layer LY21) and electrically interconnect them.

[0035] The second connection pillars 236 may interconnect the connection wiring patterns 234 of the interposer 230 and the upper redistribution line patterns 262 of the upper redistribution line structure 260. For example, the second connection pillars 236 may contact the top surface of the connection wiring patterns 234 and the lowermost upper redistribution line pattern layer of the upper redistribution line structure 260 (e.g., the bottom surface of the upper redistribution line pattern 262 of the first upper layer LY21) and electrically interconnect them.

[0036] A filling insulation layer 252 surrounding the first connection pillars 220 and the interposer 230 may be filled between the lower redistribution line structure 210 and the upper redistribution line structure 260. The filling insulation layer 252 may include epoxy mold compound (EMC) or a polymer material.

[0037] Side surfaces of the lower redistribution line structure 210 , side surfaces of the filling insulation layer 252 , and side surfaces of the upper redistribution line structure 260 may be aligned with each other in a vertical direction.

[0038] The first connection pillar 220 may have a first height H1, and the second connection pillar 236 may have a second height H2. The first height H1 may be greater than the second height H2. The interposer 230 may have a third height H3. The first height H1 may be greater than the third height H3. Since the interposer 230 includes the second connection pillar 236, the third height H3 may be greater than the second height H2.

[0039] The uppermost portion (i.e., top surface) of the first connection pillar 220 and the uppermost portion of the second connection pillar 236 may be located at the same level. Since the first height H1 of the first connection pillar 220 may be greater than the third height H3 of the interposer 230, the lowermost portion (i.e., bottom surface) of the first connection pillar 220 may be located at a level lower than the bottom surface of the interposer 230.

[0040] The first connection pillar 220 and the second connection pillar 236 may both be in contact with the bottom surface of the upper redistribution line pattern 262 exposed to the bottom surface of the upper redistribution line structure 260. Therefore, the uppermost portion of the first connection pillar 220, the uppermost portion of the second connection pillar 236, and the bottom surface of the upper redistribution line structure 260 may be located at the same level. Also, the uppermost portion of the first connection pillar 220, the uppermost portion of the second connection pillar 236, and the top surface of the filling insulation layer 252 may be coplanar.

[0041] The first connection pillar 220 may contact the top surface of the lower redistribution line pattern 212 by penetrating a portion of the lower insulating layer 216 of the lower redistribution line structure 210. Therefore, the lowermost portion of the first connection pillar 220 may be located at a lower level than the top surface of the lower redistribution line structure 210.

[0042] At least two semiconductor chips 300 may be attached to the upper redistribution line structure 260. The at least two semiconductor chips 300 may include a first semiconductor chip 310 and a second semiconductor chip 320. The first semiconductor chip 310 and the second semiconductor chip 320 may be spaced apart from each other on the upper redistribution line structure 260.

[0043] At least one of the semiconductor chips 300 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. At least one of the semiconductor chips 300 may be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0044] According to one embodiment, the first semiconductor chip 310 may be a CPU chip, a GPU chip or an AP chip, and the second semiconductor chip 320 may be a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip or an RRAM chip.

[0045] The first semiconductor chip 310 includes a first semiconductor substrate 312 and a first chip pad 314 disposed on one surface of the first semiconductor substrate 312. The second semiconductor chip 320 includes a second semiconductor substrate 322 and a second chip pad 324 disposed on one surface of the second semiconductor substrate 322.

[0046] The first chip pads 314 of the first semiconductor chip 310 and the second chip pads 324 of the second semiconductor chip 320 may be connected to the upper redistribution line patterns 262 of the upper redistribution line structure 260 via chip connection members 370. The chip connection members may be, for example, bumps, solder balls, or conductive pillars.

[0047] The first semiconductor substrate 312 and the second semiconductor substrate 322 may include, for example, Si. Alternatively, the first semiconductor substrate 312 and the second semiconductor substrate 322 may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor substrate 312 and the second semiconductor substrate 322 may each have an active surface and an inactive surface opposite to the active surface. According to one embodiment, the active surface of each of the first semiconductor substrate 312 and the second semiconductor substrate 322 may face the upper redistribution line structure 260.

[0048] A semiconductor device including a plurality of individual devices of various types may be formed on an active surface of each of the first semiconductor substrate 312 and the second semiconductor substrate 322 .

[0049] An underfill material layer 380 surrounding the chip connection member 370 may be filled between the upper redistribution line structure 260 and each of the first semiconductor chip 310 and the second semiconductor chip 320. The underfill material layer 380 may include epoxy resin and may be formed by, for example, a capillary underfill method. According to one embodiment, the underfill material layer 380 may be a non-conductive film (NCF).

[0050] The semiconductor package 1 may be, for example, a fan-out package. The coverage area occupied by the at least two semiconductor chips 300 may be smaller than the horizontal area of ​​the upper redistribution line structure 260 and the lower redistribution line structure 210. The coverage area occupied by the at least two semiconductor chips 300 may overlap with the entire upper redistribution line structure 260 and / or the entire lower redistribution line structure 210 in the vertical direction. A portion of the upper redistribution line pattern 262 of the upper redistribution line structure 260 and a portion of the lower redistribution line pattern 212 of the lower redistribution line structure 210 may extend to further protrude outward from the coverage area occupied by the at least two semiconductor chips 300 in total in the horizontal direction.

[0051] The semiconductor package 1 may further include a board connection member 270 attached below the lower redistribution line structure 210. According to one embodiment, the board connection member 270 may contact the bottom surface of the lower redistribution line pattern 212 by penetrating the pad opening PO of the lowermost lower insulation layer 216 of the plurality of lower insulation layers 216 of the lower redistribution line structure 210. The board connection member 270 may be, for example, a bump, a solder ball, or a conductive column. A board bottom filling material layer 280 surrounding the board connection member 270 may be filled between the package base substrate 100 and the lower redistribution line structure 210.

[0052] According to one embodiment, the semiconductor package 1 may further include a package base substrate 100. The package base substrate 100 may include a base board layer 110, and upper and lower pads 122 and 124 disposed on top and bottom surfaces of the base board layer 110, respectively.

[0053] According to one embodiment, the package base substrate 100 may be a printed circuit board (PCB). For example, the package base substrate 100 may be a multilayer PCB. The base plate layer 110 may include at least one material selected from phenolic resin, epoxy resin, and PI. The base plate layer 110 may include, for example, at least one material selected from flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), polyamide staple fiber mat (Thermount), cyanate ester, PI, and liquid crystal polymer.

[0054] A top solder resist layer 132 exposing the upper pads 122 and a bottom solder resist layer 134 exposing the lower pads 124 may be formed on the top and bottom surfaces of the base board layer 110, respectively. A board connection member 270 may be connected to the upper pads 122, and an external connection terminal 150 may be connected to the lower pads 124.

[0055] The package base substrate 100 may include a wiring pattern electrically connecting the upper pad 122 and the lower pad 124 and a conductive path electrically interconnecting the wiring pattern. The wiring pattern may be disposed on the top surface, the bottom surface and / or the interior of the base plate layer 110. The wiring pattern may include, for example, an electrolytically deposited (ED) copper foil, a rolled annealed (RA) copper foil, a stainless steel foil, an aluminum foil, an ultra-thin copper foil, sputtered copper, or a copper alloy.

[0056] The conductive via may penetrate at least a portion of the base plate layer 110. According to one embodiment, the conductive via may include Cu, Ni, stainless steel, or BeCu.

[0057] According to one embodiment, when the semiconductor package 1 does not include the package base substrate 100 , the board connection member 270 may perform the function of an external connection terminal.

[0058] According to one embodiment, the semiconductor package 1 may further include a heat dissipation member 500. The heat dissipation member 500 may be, for example, a heat sink or a heat sink. Figure 1A As shown in FIG. 1 , the heat dissipation member 500 contacts the top surface of the package base substrate 100 and surrounds at least two semiconductor chips 300, but is not limited thereto. According to one embodiment, the heat dissipation member 500 may contact the top surface of the at least two semiconductor chips 300, but may not contact the top surface of the package base substrate 100. According to one embodiment, a thermal interface material (TIM) may be disposed between the heat dissipation member 500 and the top surface of the at least two semiconductor chips 300.

[0059] According to one embodiment, an electromagnetic interface (EMI) shielding layer may be formed on an outer surface of the heat dissipation member 500. The EMI shielding layer may be electrically connected to a ground layer included in the package base substrate 100.

[0060] Figure 1B 2 is a planar layout of the connection wiring pattern 234 of the interposer 230 and the upper redistribution line pattern 262 of the upper redistribution line structure 260 in the semiconductor package 1 . Figure 1B yes Figure 1A Semiconductor packages or Figures 2 to 8 A planar layout of wiring of each of the interposers and upper redistribution line structures in each of the semiconductor packages.

[0061] Reference Figure 1A and Figure 1B, the interposer 230 includes a connection wiring pattern 234 and a second connection column 236 connected to both ends of the connection wiring pattern 234. The upper redistribution line structure 260 includes an upper redistribution line pattern 262 interconnecting the upper via pattern 264 and the second connection column 236. The upper via pattern 264 may be electrically connected to the first chip pad 314 of the first semiconductor chip 310 and the second chip pad 324 of the second semiconductor chip 320.

[0062] The width W1 and the minimum pitch P1 of the upper redistribution line pattern 262 may be respectively greater than the width W2 and the minimum pitch P2 of the connection wiring pattern 234. The width, the minimum pitch, and the thickness of the lower redistribution line pattern 212 may be equal to or similar to the width W1, the minimum pitch P1, and the thickness t1 of the upper redistribution line pattern 262. According to one embodiment, the thickness t1 of the upper redistribution line pattern 262 may be greater than the thickness t2 of the connection wiring pattern 234.

[0063] The first semiconductor chip 310 may be electrically connected to the package base substrate 100 via the upper redistribution line pattern 262 and the upper via pattern 264 of the upper redistribution line structure 260, the first connection pillar 220, and the lower redistribution line pattern 212 and the lower via pattern 214 of the lower redistribution line structure 210. The second semiconductor chip 320 may be electrically connected to the package base substrate 100 via the upper redistribution line pattern 262 and the upper via pattern 264 of the upper redistribution line structure 260, the first connection pillar 220, and the lower redistribution line pattern 212 and the lower via pattern 214 of the lower redistribution line structure 210. In the semiconductor package 1, the first semiconductor chip 310 and the second semiconductor chip 320 may be electrically connected to each other through the upper redistribution line pattern 262 and the upper via pattern 264 of the upper redistribution line structure 260 and the interposer 230, without through the lower redistribution line pattern 212 and the lower via pattern 214 of the lower redistribution line structure 210.

[0064] For example, transmission of a power signal, a ground signal, a control signal, a clock signal, etc. from the board connection member 270 to each of the first semiconductor chip 310 and the second semiconductor chip 320 and data transmission and / or reception between the board connection member 270 and each of the first semiconductor chip 310 and the second semiconductor chip 320 may be performed via the lower redistribution line pattern 212 and the lower via pattern 214 of the lower redistribution line structure 210, the first connection pillar 220, and the upper redistribution line pattern and the upper via pattern 264 of the upper redistribution line structure 260. On the other hand, for example, data transmission and / or reception between the first semiconductor chip 310 and the second semiconductor chip 320 and signal transmission for clock synchronization between the first semiconductor chip 310 and the second semiconductor chip 320 may be performed only via the upper redistribution line pattern 262 and the upper via pattern 264 of the upper redistribution line structure 260 and the interposer 230 without passing through the lower redistribution line pattern 212 and the lower via pattern 214 of the lower redistribution line structure 210.

[0065] A semiconductor package 1 according to one embodiment transmits signals between at least two semiconductor chips 300 (e.g., a first semiconductor chip 310 and a second semiconductor chip 320) via an inserter 230 capable of achieving a relatively fine pitch, and transmits signals between a board connecting member 270 and each of the first semiconductor chip 310 and the second semiconductor chip 320 via a first connecting column 220 and a lower redistribution line structure 210 manufactured at a relatively low cost.

[0066] For example, since a semiconductor package (in which a signal between a package base substrate and each of two semiconductor chips and a signal between two semiconductor chips are transmitted via an interposer) includes a relatively large interposer, manufacturing costs may be increased. On the other hand, since a semiconductor package (in which a signal between a package base substrate and each of two semiconductor chips and a signal between two semiconductor chips are transmitted via a redistribution line structure) cannot achieve a fine pitch, the size of the semiconductor package may be increased or the yield may be reduced.

[0067] However, since the semiconductor package 1 transmits signals between the first semiconductor chip 310 and the second semiconductor chip 320 via the interposer 230, and transmits signals between the package base substrate 100 and each of the first semiconductor chip 310 and the second semiconductor chip 320 via the first connection pillar 220 and the lower redistribution line structure 210, the required size of the interposer 230 is relatively small. Therefore, the semiconductor package 1 can have low manufacturing cost and high yield.

[0068] Figures 2 to 81a to 1g are cross-sectional views of semiconductor packages 1a to 1g according to the embodiment. Figures 2 to 8 Zhongyu Figure 1A and Figure 1B Repeat the details, and focus on describing their differences.

[0069] Reference Figure 2 The semiconductor package 1a includes a lower redistribution line structure 210, an interposer 230, an upper redistribution line structure 260, and / or at least two semiconductor chips 300. The interposer 230 is disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and at least two semiconductor chips 300 may be attached to the upper redistribution line structure 260.

[0070] The semiconductor package 1a further includes a molding member 400 surrounding at least two semiconductor chips 300 on the upper redistribution line structure 260. The molding member 400 may be formed of, for example, EMC. The molding member 400 may cover the top surface of the upper redistribution line structure 260 and each of the at least two semiconductor chips 300, for example, the side surface of the first semiconductor chip 310 and the side surface of the second semiconductor chip 320.

[0071] The molding member 400 may expose top surfaces of at least two semiconductor chips 300, for example, a top surface of the first semiconductor chip 310 and a top surface of the second semiconductor chip 320. The top surface of the molding member 400 and the top surfaces of the at least two semiconductor chips 300 (for example, the top surface of the first semiconductor chip 310 and the top surface of the second semiconductor chip 320) may be coplanar.

[0072] According to one embodiment, the bottom filling material layer 380 may be a part of the molding member 400 formed of a molded under-fill (MUF). The heat dissipation member 500 may be in contact with the top surface of at least two semiconductor chips 300 and the top surface of the molding member 400. The side surface of the lower redistribution line structure 210, the side surface of the filling insulation layer 252, the side surface of the upper redistribution line structure 260, and / or the side surface of the molding member 400 may be aligned in the vertical direction.

[0073] Reference Figure 3 The semiconductor package 1b includes a lower redistribution line structure 210, an interposer 231, an upper redistribution line structure 260, and at least two semiconductor chips 300. The interposer 231 is disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and / or at least two semiconductor chips 300 may be attached to the upper redistribution line structure 260.

[0074] The interposer 231 includes an interposer substrate 232, a connection wiring pattern 234 disposed on a top surface of the interposer substrate 232, a second connection column 236 disposed on a portion of the connection wiring pattern 234, and / or a through electrode 238 penetrating the interposer substrate 232 and contacting a bottom surface of the connection wiring pattern 234.

[0075] The through electrodes 238 may electrically interconnect the connection wiring patterns 234 and the lower redistribution line patterns 212. According to one embodiment, connection bumps 225 penetrating the die attach film 240 may be disposed between the through electrodes 238 and the lower redistribution line patterns 212. The die attach film 240 may be, for example, a non-conductive film.

[0076] According to one embodiment, the connection bump 225 may be formed on the lower redistribution line pattern 212 in a manner similar to the first connection pillar 220. According to another embodiment, the connection bump 225 may be formed on the through electrode 238 on the bottom surface of the interposer 231 while manufacturing the interposer 231. According to another embodiment, the connection bump 225 may include an upper portion formed on the through electrode 238 on the bottom surface of the interposer 231 while manufacturing the interposer 231 and a lower portion formed on the lower redistribution line pattern 212 in a manner similar to the first connection pillar 220.

[0077] According to one embodiment, a semiconductor package 1b can transmit signals between at least two semiconductor chips 300 (for example, between the first semiconductor chip 310 and the second semiconductor chip 320) via the inner plug 231 instead of the lower redistribution line structure 210, transmit some signals between the board connecting member 270 and each of the first semiconductor chip 310 and the second semiconductor chip 320 via the first connecting column 220 and the lower redistribution line structure 210 instead of the inner plug 230, and transmit the remaining signals between the board connecting member 270 and each of the first semiconductor chip 310 and the second semiconductor chip 320 via the inner plug 230 and the lower redistribution line structure 210.

[0078] For example, among the signals between the board connection member 270 and each of the first semiconductor chip 310 and the second semiconductor chip 320, the transmission and reception of power signals, ground signals, and data can be performed via the lower redistribution line structure 210, while the transmission and reception of control signals and clock signals can be performed via the interposer 230 and the lower redistribution line structure 210. However, this is merely exemplary and not restrictive. In other words, the path of each signal between the board connection member 270 and each of the first semiconductor chip 310 and the second semiconductor chip 320 can be determined in consideration of the electrical characteristics and horizontal cross-section of the first connection column 220 and the through electrode 238.

[0079] Reference Figure 4 , the semiconductor package 1c includes a lower redistribution line structure 210, an interposer 231, an upper redistribution line structure 260, and / or at least two semiconductor chips 300. The interposer 231 may be disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and the at least two semiconductor chips 300 may be attached to the upper redistribution line structure 260. The semiconductor package 1c further includes a molding member 400 surrounding the at least two semiconductor chips 300 on the upper redistribution line structure 260.

[0080] The interposer 231 includes an interposer substrate 232 , a connection wiring pattern 234 disposed on a top surface of the interposer substrate 232 , a second connection column 236 disposed on a portion of the connection wiring pattern 234 , and a through electrode 238 penetrating the interposer substrate 232 and contacting a bottom surface of the connection wiring pattern 234 .

[0081] Reference Figure 5 The semiconductor package 1d includes a lower redistribution line structure 210, an interposer 230, an upper redistribution line structure 260, and / or at least two semiconductor chips 300. The interposer 230 may be disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and at least two semiconductor chips 300 may be attached to the upper redistribution line structure 260.

[0082] The semiconductor package 1d also includes a passive device 600 attached to the lower redistribution line structure 210. The passive device 600 may be, for example, a chip resistor, a chip capacitor, an inductor, a quartz for generating a clock, or a temperature sensor. According to one embodiment, the semiconductor package 1d may also include an active device attached to the lower redistribution line structure 210 like the passive device 600, such as a switch, a direct current (DC)-DC converter, or a voltage regulator.

[0083] The passive device 600 may be disposed on the lower redistribution line structure 210 but spaced apart from the first connection pillar 220 and the interposer 230. The passive device 600 may be disposed on a portion of the lower redistribution line pattern 212. The passive device 600 may be disposed on the uppermost lower redistribution line pattern layer of the lower redistribution line structure 210, for example, when the lower redistribution line structure 210 includes three lower redistribution line pattern layers, the passive device 600 may be disposed on the lower redistribution line pattern 212 of the third lower layer LY13.

[0084] The filling insulation layer 252 may surround the first connecting pillars 220 , the interposer 230 , and the passive device 600 between the lower redistribution line structure 210 and the upper redistribution line structure 260 .

[0085] Reference Figure 6, the semiconductor package 1e includes a lower redistribution line structure 210, a passive device 600 attached to the lower redistribution line structure 210, an interposer 230, an upper redistribution line structure 260, at least two semiconductor chips 300, and / or a molding member 400 surrounding the at least two semiconductor chips 300 on the upper redistribution line structure 260. The interposer 230 may be disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and the at least two semiconductor chips 300 may be attached to the upper redistribution line structure 260.

[0086] Reference Figure 7 The semiconductor package 1f includes a lower redistribution line structure 210, an interposer 230, an upper redistribution line structure 260, and / or a plurality of semiconductor chips 300a. The interposer 230 may be disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and the plurality of semiconductor chips 300a may be attached to the upper redistribution line structure 260.

[0087] The plurality of semiconductor chips 300a may include a first semiconductor chip 310 and a second semiconductor chip 330. The first semiconductor chip 310 may be, for example, a CPU chip, a GPU chip, or an AP chip, and the second semiconductor chip 330 may be a high bandwidth memory (HBM) DRAM chip.

[0088] According to one embodiment, the second semiconductor chip 320 may be a stack of a plurality of memory semiconductor chips, wherein, according to the JEDEC standard definition, a stack represents all memory chips in a memory system employed in one component. In other words, the second semiconductor chip 320 may include a plurality of slices 330a to 330d, wherein, according to the JEDEC standard definition, a slice represents one memory chip in a memory chip stack.

[0089] According to one embodiment, among the plurality of slices 330 a to 330 d , the bottom slice 330 a may be a buffer chip including a serial-to-parallel conversion circuit, and the remaining slices 330 b to 330 d may all be HBM DRAM semiconductor chips.

[0090] Each of the plurality of slices 330a to 330d includes a semiconductor substrate 332 and a lower chip pad 334 disposed on a bottom surface (e.g., an active surface) of the semiconductor substrate 332. Among the plurality of slices 330a to 330d, each of the slices 330a to 330c except the slice 330d may include a through electrode 338 electrically interconnecting an upper chip pad 336 disposed on a top surface (e.g., an inactive surface) of the semiconductor substrate 332 with the lower chip pad 334.

[0091] The slice connection terminal 372 and the slice adhesive layer 382 surrounding the slice connection terminal 372 can be arranged between the plurality of slices 330a to 330d, wherein the slice connection terminal 372 and the slice adhesive layer 382 electrically interconnect the lower chip pad 334 of the top slice and the upper chip pad 336 of the bottom slice among the plurality of slices 330a to 330d. The slice connection terminal 372 can be, for example, a bump or a solder ball. The slice adhesive layer 382 can be, for example, a non-conductive film.

[0092] Reference Figure 8 , the semiconductor package 1g includes a lower redistribution line structure 210, a passive device 600 attached to the lower redistribution line structure 210, an interposer 230, an upper redistribution line structure 260, a plurality of semiconductor chips 300a, and / or a molding member 400 surrounding the plurality of semiconductor chips 300a on the upper redistribution line structure 260. The interposer 230 may be disposed between the lower redistribution line structure 210 and the upper redistribution line structure 260, and the plurality of semiconductor chips 300a may be attached to the upper redistribution line structure 260.

[0093] FIG. 9A to FIG. 9I is a cross-sectional view for illustrating a method for manufacturing a semiconductor package according to an embodiment. For example, FIG. 9A to FIG. 9I It is used to illustrate the manufacturing Figure 1A A cross-sectional view of a method of manufacturing a semiconductor package 1.

[0094] Reference Fig. 9A , a lower redistribution line structure 210 is formed on the carrier substrate 10 to which the release film 20 is attached. The lower redistribution line structure 210 may include a plurality of lower insulating layers 216, a lower redistribution line pattern 212 disposed on a top surface or a bottom surface of each of the plurality of lower insulating layers 216, and / or a lower via pattern 214 penetrating each of the plurality of lower insulating layers 216.

[0095] The lower redistribution line structure 210 may be formed by sequentially stacking each of a plurality of lower insulation layers 216 and the lower redistribution line pattern 212 (or both the lower via pattern 214 and the lower redistribution line pattern 212 ).

[0096] For example, a detailed method of manufacturing the lower redistribution line structure 210 is as follows. First, the lowest lower insulating layer 216 is formed, and the lowest lower redistribution line pattern 212 (for example, the lower redistribution line pattern 212 of the first lower layer LY11) is formed on the lowest lower insulating layer 216. Then, a lower insulating layer 216 exposing a portion of the lower redistribution line pattern 212 of the first lower layer LY11 is formed on the lower redistribution line pattern 212 of the first lower layer LY11, and a lower path pattern 214 connected to the lower redistribution line pattern 212 of the first lower layer LY11 is formed. Here, the lower path pattern 214 and the lower redistribution line pattern 212 can be formed integrally. By repeating these processes, a lower redistribution line structure 210 having a plurality of lower insulating layers 216 and a plurality of lower redistribution line pattern layers including the first lower layer LY11, the second lower layer LY12, and the third lower layer LY13 can be formed.

[0097] According to one embodiment, the uppermost lower insulating layer 216 of the lower redistribution line structure 210 may be formed to cover the entire uppermost lower redistribution line pattern layer, for example, the third lower layer LY13 .

[0098] Reference Fig. 9B A first connection pillar 220 connected to a portion of the uppermost lower redistribution line pattern layer (eg, the lower redistribution line pattern 212 of the third lower layer LY13 ) of the lower redistribution line structure 210 is formed on the lower redistribution line structure 210 .

[0099] In order to form the first connection pillar 220, a mask pattern for exposing a position where the first connection pillar 220 is to be formed is formed on the lower redistribution line structure 210, and an exposed portion of the uppermost lower insulating layer 216 of the lower redistribution line structure 210 is removed by using the mask pattern as an etching mask, thereby exposing a portion of the lower redistribution line pattern 212 of the uppermost lower redistribution line pattern layer (e.g., the third lower layer LY13) of the lower redistribution line structure 210. Then, chemical plating is performed on the exposed lower redistribution line pattern 212 to form the first connection pillar 220. According to one embodiment, after a seed layer is formed on the lower redistribution line structure 210, a conductive material layer may be formed by chemical plating using the seed layer as a seed, and then the mask pattern may be removed to form the first connection pillar 220.

[0100] Reference Fig. 9C, an interposer 230 is attached on the lower redistribution line structure 210. The interposer 230 may be disposed on the lower redistribution line structure 210, for example, spaced apart from the first connection pillars 220. The interposer 23 may be attached to the lower redistribution line structure 210 by using, for example, a die attach film 240. The interposer 230 may be attached on the top surface of the uppermost lower insulating layer 216 among the plurality of lower insulating layers 216 included in the lower redistribution line structure 210.

[0101] The interposer 230 may include an interposer substrate 232, a connection wiring pattern 234 disposed on a top surface of the interposer substrate 232, and / or a second connection pillar 236 disposed on a portion of the connection wiring pattern 234. The top surface of the interposer substrate 232 may be at a level lower than the uppermost portion of the first connection pillar 220.

[0102] exist Figure 3 The semiconductor package 1b or Figure 4 In the semiconductor package 1c, a lower redistribution line structure 210 may be attached. Figure 3 or Figure 4 An insert 231 is provided instead of the insert 230, wherein the insert 231 includes an insert substrate 232, a connecting wiring pattern 234 arranged on the top surface of the insert substrate 232, a second connecting column 236 arranged on a portion of the connecting wiring pattern 234, and a through electrode 238 that penetrates the insert substrate 232 and contacts the bottom surface of the connecting wiring pattern 234.

[0103] Reference Fig.9D A filling insulating material layer 250 covering the first connection pillars 220 and the interposer 230 is formed on the lower redistribution line structure 210. The filling insulating material layer 250 may be formed of an epoxy molding compound (EMC) or a polymer material.

[0104] exist Figure 5 Semiconductor package 1d or Figure 6 In the semiconductor package 1e, before forming the filling insulating material layer 250, Figure 5 or Figure 6 The passive device 600 is attached on the lower redistribution line structure 210 , for example, to be spaced apart from the first connecting pillar 220 and the interposer 230 .

[0105] Reference Fig.9E ,Will Fig.9DThe carrier substrate 10 to which the release film 20 is attached is separated from the lower redistribution line structure 210. Then, a portion of the lowest lower insulation layer 216 among the plurality of lower insulation layers 216 is removed to form a pad opening PO exposing a portion of the lower redistribution line pattern 212 of the first lower layer LY11, and a board connection member 270 in contact with the bottom surface of the lower redistribution line pattern 212 of the first lower layer LY11 is attached through the pad opening PO.

[0106] Reference Fig.9F , remove Fig.9E The upper portion of the filling insulating material layer 250 is filled so that the first connection pillar 220 and the second connection pillar 236 are exposed, thereby forming a filling insulating layer 252. The filling insulating layer 252 may cover the top surface of the lower redistribution line structure 210 and the side surface of the first connection pillar 220, and may cover the side surface and the top surface of the interposer 230 except the uppermost portion of the second connection pillar 236. In other words, the filling insulating layer 252 may cover the side surface of the first connection pillar 220 and the side surface of the second connection pillar 236, but expose their top surfaces.

[0107] The uppermost portion of the first connection pillar 220, the uppermost portion of the second connection pillar 236, and the bottom surface of the upper redistribution line structure 260 may be on the same horizontal plane. Also, the uppermost portion of the first connection pillar 220, the uppermost portion of the second connection pillar 236, and the top surface of the filling insulation layer 252 may be coplanar.

[0108] Reference Figure 9G , an upper redistribution line structure 260 is formed on the filling insulation layer 252. The upper redistribution line structure 260 may include at least one upper insulation layer 266, an upper redistribution line pattern 262 disposed on a top surface or a bottom surface of the at least one upper insulation layer 266, and an upper via pattern 264 penetrating the at least one upper insulation layer 266.

[0109] The upper redistribution line structure 260 may be formed by sequentially stacking an upper redistribution line pattern 262 (or an upper via pattern 264 and an upper redistribution line pattern 262 ) and an upper insulating layer 266 .

[0110] For example, a detailed method of manufacturing the upper redistribution line structure 260 is as follows. First, an upper redistribution line pattern 262 of the lowest upper redistribution line pattern layer (e.g., the first upper layer LY21) of the upper redistribution line structure 260 is formed to contact each of the first connection pillar 220 and the second connection pillar 236. Then, an upper insulating layer 266 exposing a portion of the upper redistribution line pattern 262 of the first upper layer LY21 is formed on the upper redistribution line pattern 262 of the first upper layer LY21, and an upper path pattern 264 connected to the upper redistribution line pattern 262 of the first upper layer LY21 is formed. Here, the upper path pattern 264 and the upper redistribution line pattern 262 can be formed integrally. By repeating these processes, an upper redistribution line structure 260 having at least one upper insulating layer 266 and a plurality of upper redistribution line pattern layers including the first upper layer LY21 and the second upper layer LY22 can be formed.

[0111] The upper redistribution line structure 260 may include fewer layers than the lower redistribution line structure 210. For example, the lower redistribution line structure 210 may include at least three layers, and the upper redistribution line structure 260 may include at least two layers less than the lower redistribution line structure 210.

[0112] Reference Figure 9H , at least two semiconductor chips 300 are attached on the upper redistribution line structure 260 . The at least two semiconductor chips 300 may include a first semiconductor chip 310 and a second semiconductor chip 320 .

[0113] The first chip pads 314 of the first semiconductor chip 310 and the second chip pads 324 of the second semiconductor chip 320 may each be connected to the upper redistribution line pattern 262 of the upper redistribution line structure 260 via a chip connection member 370 .

[0114] An underfill material layer 380 surrounding the chip connection member 370 may be filled between the upper redistribution line structure 260 and each of the first and second semiconductor chips 310 and 320 .

[0115] exist Figure 7 In the semiconductor package 1f, a redistribution line structure 260 may be attached to the upper redistribution line structure 260. Figure 7 The second semiconductor chip 330 instead of the second semiconductor chip 320 is used.

[0116] Reference Fig.9I , preparing a package base substrate 100 including a base board layer 110 and upper pads 122 and lower pads 124 respectively disposed on the top surface and the bottom surface of the base board layer 110, and then attaching a Figure 9H The resulting product is such that the board connection member 270 is connected to the upper pad 122 of the package base substrate 100 .

[0117] The external connection terminals 150 may be attached to the lower pads 124 of the package base substrate 100 .

[0118] Then, if Figure 1A As shown, the heat dissipation member 500 is provided to contact the top surface of at least two semiconductor chips 300 to form the semiconductor package 1. According to one embodiment, the semiconductor package 1 can be formed by providing the heat dissipation member 500 to contact the top surface of the package base substrate 100 and surrounding at least two semiconductor chips 300.

[0119] FIG. 10A to FIG. 10G is a cross-sectional view for illustrating a method for manufacturing a semiconductor package according to another embodiment. For example, FIG. 10A to FIG. 10G It is used to illustrate the manufacturing Figure 2 A cross-sectional view of a method of a semiconductor package 1a, wherein Fig. 10A Shows Fig.9D The process afterwards.

[0120] Reference Fig. 10A , by removing Fig.9D The filling insulating layer 252 is formed by covering the upper portion of the filling insulating material layer 250, thereby exposing the first connection pillars 220 and the second connection pillars 236. The filling insulating layer 252 may cover the top surface of the lower redistribution line structure 210 and the side surfaces of the first connection pillars 220, and cover the side surfaces and top surfaces of the interposer 230 except for the uppermost portion of the second connection pillars 236. In other words, the filling insulating layer 252 may cover the side surfaces of each of the first connection pillars 220 and the second connection pillars 236, but expose their top surfaces.

[0121] Reference Fig. 10B , an upper redistribution line structure 260 is formed on the filling insulation layer 252. The upper redistribution line structure 260 may include at least one upper insulation layer 266, an upper redistribution line pattern 262 disposed on a top surface or a bottom surface of the at least one upper insulation layer 266, and an upper via pattern 264 penetrating the at least one upper insulation layer 266.

[0122] The upper redistribution line structure 260 may be formed by sequentially stacking an upper redistribution line pattern 262 (or an upper via pattern 264 and an upper redistribution line pattern 262 ) and an upper insulating layer 266 .

[0123] For example, a detailed method of manufacturing the upper redistribution line structure 260 is as follows. First, an upper redistribution line pattern 262 of the lowest upper redistribution line pattern layer (e.g., the first upper layer LY21) constituting the upper redistribution line structure 260 is formed to contact each of the first connection pillar 220 and the second connection pillar 236. Then, an upper insulating layer 266 exposing a portion of the upper redistribution line pattern 262 of the first upper layer LY21 is formed on the upper redistribution line pattern 262 of the first upper layer LY21, and an upper path pattern 264 connected to the upper redistribution line pattern 262 of the first upper layer LY21 is formed. Here, the upper path pattern 264 and the upper redistribution line pattern 262 can be formed integrally. By repeating these processes, an upper redistribution line structure 260 having at least one upper insulating layer 266 and a plurality of upper redistribution line pattern layers including the first upper layer LY21 and the second upper layer LY22 can be formed.

[0124] The number of upper redistribution line pattern layers of the upper redistribution line structure 260 may be less than the number of lower redistribution line pattern layers of the lower redistribution line structure 210. For example, the lower redistribution line structure 210 may include at least three lower redistribution line pattern layers, and the upper redistribution line structure 260 may include at least two upper redistribution line pattern layers, which is less than the at least three lower redistribution line pattern layers of the lower redistribution line structure 210.

[0125] Reference Fig. 10C , at least two semiconductor chips 300 are attached on the upper redistribution line structure 260 . The at least two semiconductor chips 300 may include a first semiconductor chip 310 and a second semiconductor chip 320 .

[0126] The first chip pads 314 of the first semiconductor chip 310 and the second chip pads 324 of the second semiconductor chip 320 may each be connected to the upper redistribution line pattern 262 of the upper redistribution line structure 260 via a chip connection member 370 .

[0127] An underfill material layer 380 surrounding the chip connection member 370 may be filled between the upper redistribution line structure 260 and each of the first and second semiconductor chips 310 and 320 .

[0128] exist Figure 8 In the semiconductor package 1g, a redistribution line structure 260 may be attached to the upper redistribution line structure 260. Figure 8 The second semiconductor chip 330 instead of the second semiconductor chip 320 is used.

[0129] Reference Fig. 10D, forming a preliminary molding member 400P surrounding at least two semiconductor chips 300 on the upper redistribution line structure 260. The preliminary molding member 400P may be formed of, for example, EMC. The preliminary molding member 400P may cover the top surface of the upper redistribution line structure 260 and the side surfaces and top surfaces of at least two semiconductor chips 300 (e.g., the first semiconductor chip 310 and the second semiconductor chip 320).

[0130] Reference Fig.10E , remove Fig. 10D The upper portion of the preliminary molding member 400P is formed so that the top surfaces of at least two semiconductor chips 300 (e.g., the first semiconductor chip 310 and the second semiconductor chip 320) are exposed, thereby forming the molding member 400. The top surface of the molding member 400 and the top surfaces of the at least two semiconductor chips 300 (e.g., the first semiconductor chip 310 and the second semiconductor chip 320) may be coplanar. The molding member 400 may cover the top surface of the upper redistribution line structure 260 and the side surfaces of the at least two semiconductor chips 300 (e.g., the first semiconductor chip 310 and the second semiconductor chip 320).

[0131] Reference Fig.10F ,Will Fig.10E The carrier substrate 10 to which the release film 20 is attached is separated from the lower redistribution line structure 210. Then, a portion of the lowest lower insulation layer 216 among the plurality of lower insulation layers 216 is removed to form a pad opening PO exposing a portion of the lower redistribution line pattern 212 of the first lower layer LY11, and a board connection member 270 in contact with the bottom surface of the lower redistribution line pattern 212 of the first lower layer LY11 is attached through the pad opening PO.

[0132] Reference Figure 10G , preparing a package base substrate 100 including a base board layer 110 and upper pads 122 and lower pads 124 respectively disposed on the top surface and the bottom surface of the base board layer 110, and then attaching a Fig.10F The resulting product is such that the board connection member 270 is connected to the upper pad 122 of the package base substrate 100 .

[0133] The external connection terminals 150 may be attached to the lower pads 124 of the package base substrate 100 .

[0134] Then, if Figure 2 As shown, a heat dissipation member 500 is provided to contact the top surface of at least two semiconductor chips 300 to form a semiconductor package 1a. According to one embodiment, a semiconductor package 1a may be formed by providing a heat dissipation member 500 to contact the top surface of a package base substrate 100 and surrounding at least two semiconductor chips 300.

[0135] Figures 11 to 14 2 and 3 are planar layouts of semiconductor packages 2 to 5 according to the embodiments. Figures 1A to 8 The semiconductor packages 1 and 1a to 1f may be Figures 11 to 14 sectional views of all or part of the semiconductor packages 2 to 5.

[0136] Reference Fig.11 The semiconductor package 2 includes an upper redistribution line structure 260 located on the interposer 230 a and at least two semiconductor chips 302 disposed on the upper redistribution line structure 260 and including a first semiconductor chip 310 a and a second semiconductor chip 320 .

[0137] The first semiconductor chip 310a and the second semiconductor chip 320a may be disposed, for example, spaced apart from each other on the upper redistribution line structure 260. A portion of the first semiconductor chip 310a and a portion of the second semiconductor chip 320a may overlap different portions of the interposer 230a.

[0138] In the semiconductor package 2 , the first semiconductor chip 310 a and the second semiconductor chip 320 a may be electrically connected to each other via the upper redistribution line structure 260 and the interposer 230 a .

[0139] For example, data transmission and / or reception between the first semiconductor chip 310 a and the second semiconductor chip 320 a and signal transmission for clock synchronization between the first semiconductor chip 310 a and the second semiconductor chip 320 a may be performed only via the upper redistribution line structure 260 and the interposer 230 .

[0140] In the semiconductor package 2 according to an embodiment, since the signals between the first semiconductor chip 310a and the second semiconductor chip 320a are transmitted via the upper redistribution line structure 260 and the interposer 230a, and other signals do not pass through the interposer 230a, the required size of the interposer 230a is relatively small. Therefore, the semiconductor package 2 can have low manufacturing cost and high yield.

[0141] Fig.12 2 is a planar layout of a semiconductor package 3 according to an embodiment.

[0142] Reference Fig.12, the semiconductor package 3 includes an upper redistribution line structure 260 located on a plurality of interposers 230b and a plurality of semiconductor chips 303 disposed on the upper redistribution line structure 260. The plurality of semiconductor chips 303 may be disposed on the upper redistribution line structure 260 spaced apart from each other. The plurality of semiconductor chips 303 may include a main semiconductor chip 310b, a first sub-semiconductor chip 320b-I, a second sub-semiconductor chip 320b-II, a third sub-semiconductor chip 320b-III, and a fourth sub-semiconductor chip 320b-IV.

[0143] The plurality of interposers 230b may be spaced apart from each other. The plurality of interposers 230b may include a first sub-interposer 230b-I, a second sub-interposer 230b-II, a third sub-interposer 230b-III, and a fourth sub-interposer 230b-IV.

[0144] Different portions of the main semiconductor chip 310b may overlap portions of the plurality of interposers 230b, respectively. Portions of the first to fourth sub-semiconductor chips 320b-I to 320b-IV may overlap portions of the first to fourth sub-interposers 230b-I to 230b-IV, respectively.

[0145] exist Fig.12 In the embodiment, the plurality of semiconductor chips 303 include one main semiconductor chip 310b and four surrounding sub-semiconductor chips (e.g., first sub-semiconductor chip 320b-I to fourth sub-semiconductor chip 32b-IV), or the plurality of semiconductor chips 303 may include one main semiconductor chip 310b and at least two surrounding sub-semiconductor chips. The number of interposers 230b may be equal to the number of sub-semiconductor chips included in the plurality of semiconductor chips 303, or an integer multiple thereof.

[0146] In the semiconductor package 3 , the main semiconductor chip 310 b and the first to fourth sub semiconductor chips 320 b -I to 320 b -IV may be electrically connected to each other via the upper redistribution line structure 260 and the first to fourth sub interposers 230 b -I to 230 b -IV.

[0147] In the semiconductor package 3 according to an embodiment, since the signals between the main semiconductor chip 310b and each of the first to fourth sub-semiconductor chips 320b-I to 320b-IV are transmitted via the upper redistribution line structure 260 and the first to fourth sub-interposers 230b-I to 230b-IV spaced apart from each other, and other signals do not pass through the plurality of interposers 230b, the required size of the plurality of interposers 230b is relatively small. Therefore, the semiconductor package 3 can have low manufacturing cost and high yield.

[0148] Fig.13 is a planar layout of a semiconductor package 4 according to another embodiment.

[0149] Reference Fig.13 The semiconductor package 4 includes an upper redistribution line structure 260 located on a plurality of interposers 230c spaced apart from each other and a plurality of semiconductor chips 304 located on the upper redistribution line structure 260, the semiconductor chips 304 including first to third semiconductor chips 310c to 330c. The plurality of interposers 230c may include a first sub-interposer 230c-I and a second sub-interposer 230c-II.

[0150] The first to third semiconductor chips 310c to 330c may be disposed spaced apart from each other on the upper redistribution line structure 260. A portion of the first semiconductor chip 310c and a portion of the second semiconductor chip 320c may overlap different portions of the first sub-interposer 230c-I, respectively, and another portion of the second semiconductor chip 320c and a portion of the third semiconductor chip 330c may overlap different portions of the second sub-interposer 230c-II, respectively.

[0151] In the semiconductor package 4, the first semiconductor chip 310c and the second semiconductor chip 320c can be electrically connected to each other via the upper redistribution line structure 260 and the first sub-interposer 230c-I, and the second semiconductor chip 320c and the third semiconductor chip 330c can be electrically connected to each other via the upper redistribution line structure 260 and the second sub-interposer 230c-II.

[0152] In the semiconductor package 4 according to an embodiment, since the signals between the first semiconductor chip 310c and the second semiconductor chip 320c and the signals between the second semiconductor chip 320c and the third semiconductor chip 330c are transmitted via the upper redistribution line structure 260 and the plurality of interposers 230c spaced apart from each other, and other signals do not pass through the plurality of interposers 230c, the required size of the plurality of interposers 230c is relatively small. Therefore, the semiconductor package 4 can have low manufacturing cost and high yield.

[0153] Fig.14 is a planar layout of a semiconductor package 5 according to another embodiment.

[0154] Reference Fig.14 The semiconductor package 5 includes an upper redistribution line structure 260 located on a plurality of interposers 230d spaced apart from each other and at least two semiconductor chips 305 disposed on the upper redistribution line structure 260 and including a first semiconductor chip 310d and a second semiconductor chip 320d. The plurality of interposers 230 may include a first sub-interposer 230d-I and a second sub-interposer 230d-II.

[0155] The first semiconductor chip 310d and the second semiconductor chip 320d may be disposed spaced apart from each other on the upper redistribution line structure 260. Different portions of the first semiconductor chip 310d and the second semiconductor chip 320d may overlap different portions of the plurality of interposers 230, respectively. For example, different portions of the first semiconductor chip 310d may overlap a portion of the first sub-interposer 230d-I and a portion of the second sub-interposer 230d-II, respectively, and different portions of the second semiconductor chip 320d may overlap another portion of the first sub-interposer 230d-I and another portion of the second sub-interposer 230d-II, respectively.

[0156] In the semiconductor package 5 , the first semiconductor chip 310 d and the second semiconductor chip 320 d may be electrically connected to each other via the upper redistribution line structure 260 and the first sub-interposer 230 d -I and via the upper redistribution line structure 260 and the second sub-interposer 230 d -II.

[0157] In the semiconductor package 5 according to one embodiment, since the signal between the first semiconductor chip 310d and the second semiconductor chip 320d is transmitted via the upper redistribution line structure 260 and the plurality of interposers 230d, and other signals do not pass through the plurality of interposers 230d. Moreover, since the plurality of interposers 230d include the first sub-interposer 230d-I and the second sub-interposer 230d-II spaced apart from each other, the required size of the plurality of interposers 230d is relatively small. Moreover, since the signal between the first semiconductor chip 310d and the second semiconductor chip 320d is separately transmitted via the first sub-interposer 230d-I and the second sub-interposer 230d-II spaced apart from each other, the chip pads (e.g., Figure 1A The first die pad 314 and the second die pad 324 can be designed with a greater degree of freedom. Therefore, the semiconductor package 5 can have a low manufacturing cost and a high yield.

[0158] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a lower redistribution line structure including a plurality of lower insulating layers and a plurality of lower redistribution line patterns respectively located on at least one of top surfaces and bottom surfaces of the plurality of lower insulating layers; a plurality of first connection pillars, each of which is located on at least a portion of the lower redistribution line patterns among the plurality of lower redistribution line patterns; an interposer located on the lower redistribution line structure and spaced apart from the plurality of first connection pillars, and comprising an interposer substrate, a plurality of connection wiring patterns located on a top surface of the interposer substrate, and a plurality of second connection pillars respectively located on at least a portion of the plurality of connection wiring patterns; an upper redistribution line structure including at least one upper insulating layer and a plurality of upper redistribution line patterns located on a top surface or a bottom surface of the at least one upper insulating layer and respectively connected to the plurality of first connection pillars and the plurality of second connection pillars; as well as at least two semiconductor chips, the at least two semiconductor chips being located on the upper redistribution line structure, the at least two semiconductor chips being spaced apart from each other and electrically connected to the plurality of upper redistribution line patterns, Wherein, the horizontal plane where the bottom surfaces of the plurality of first connecting columns are located is lower than the bottom surface of the inner plug-in unit.

2. The semiconductor package according to claim 1, wherein: Each of the plurality of lower redistribution line patterns constitutes a lower redistribution line pattern layer, and each of the plurality of upper redistribution line patterns constitutes an upper redistribution line pattern layer. Wherein, the number of the upper redistribution line pattern layers is less than the number of the lower redistribution line pattern layers.

3. The semiconductor package according to claim 1, wherein: The height of the first connection pillars is greater than the height of the second connection pillars.

4. The semiconductor package according to claim 1, wherein: The height of the plurality of first connection columns is greater than the height of the inner plug.

5. The semiconductor package according to claim 1, wherein: Top surfaces of the plurality of first connection pillars and top surfaces of the plurality of second connection pillars are located on the same horizontal plane. 6 . The semiconductor package according to claim 1 , further comprising a filling insulation layer surrounding the plurality of first connection pillars and the interposer between the lower redistribution line structure and the upper redistribution line structure.

7. The semiconductor package according to claim 6, wherein: Top surfaces of the plurality of first connection pillars, top surfaces of the plurality of second connection pillars, and a top surface of the filling insulation layer are coplanar.

8. A semiconductor package, comprising: Package base substrate; a lower redistribution line structure, the lower redistribution line structure being located on the package base substrate and comprising a plurality of lower redistribution line patterns; a plurality of first connection pillars, each of which is located on at least a portion of the lower redistribution line patterns among the plurality of lower redistribution line patterns; at least one interposer, the at least one interposer being located on the lower redistribution line structure and spaced apart from each other, each of the at least one interposer comprising a plurality of connection wiring patterns and a plurality of second connection pillars spaced apart from each other and respectively located on a portion of the plurality of connection wiring patterns; an upper redistribution line structure located on the at least one interposer and the plurality of first connection pillars and comprising a plurality of upper redistribution line patterns respectively connected to the plurality of first connection pillars and the plurality of second connection pillars; as well as at least two semiconductor chips spaced apart from each other on the upper redistribution line structure and electrically connected to the plurality of upper redistribution line patterns, Wherein, the horizontal plane where the bottom surfaces of the plurality of first connecting columns are located is lower than the bottom surface of the inner plug-in unit.

9. The semiconductor package according to claim 8, the semiconductor package being configured to transmit signals between the at least two semiconductor chips via the upper redistribution line structure and the at least one interposer, and The semiconductor package is configured to transmit signals between the at least two semiconductor chips and the package base substrate via the upper redistribution line structure, the plurality of first connection pillars, and the lower redistribution line structure.

10. The semiconductor package according to claim 8, wherein: A minimum pitch of the plurality of upper redistribution line patterns is greater than a minimum pitch of the plurality of connection wiring patterns.

11. The semiconductor package according to claim 8, wherein: A width and a thickness of the plurality of upper redistribution line patterns are respectively greater than a width and a thickness of the plurality of connection wiring patterns.

12. The semiconductor package according to claim 8, wherein: The at least two semiconductor chips include a main semiconductor chip and a plurality of sub-semiconductor chips, Wherein, the at least one interposer includes a plurality of sub-interposers, and the plurality of sub-interposers respectively overlap with a portion of the main semiconductor chip and a portion of each of the plurality of sub-semiconductor chips to electrically interconnect the main semiconductor chip with each of the plurality of sub-semiconductor chips.

13. The semiconductor package according to claim 8, wherein: The at least two semiconductor chips include a first semiconductor chip, a second semiconductor chip and a third semiconductor chip, The at least one interposer includes a first sub-interposer and a second sub-interposer, wherein the first sub-interposer overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip, and the second sub-interposer overlaps another portion of the second semiconductor chip and a portion of the third semiconductor chip to electrically connect the second semiconductor chip to the third semiconductor chip. 14 . The semiconductor package of claim 8 , further comprising a heat dissipation member contacting top surfaces of the at least two semiconductor chips.

15. The semiconductor package according to claim 14, wherein: The heat dissipation member surrounds the at least two semiconductor chips by contacting a top surface of the package base substrate.

16. The semiconductor package according to claim 8, wherein The at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip, The at least one interposer includes a first sub-interposer and a second sub-interposer, wherein the first sub-interposer overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip, and the second sub-interposer overlaps another portion of the first semiconductor chip and another portion of the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip.

17. A semiconductor package, comprising: a lower redistribution line structure, the lower redistribution line structure comprising a plurality of lower redistribution line patterns; a plurality of first connection pillars connected to the plurality of lower redistribution line patterns; an interposer, the interposer being located on the lower redistribution line structure, the interposer comprising an interposer substrate, a plurality of connection wiring patterns located on the interposer substrate, and a plurality of second connection pillars located on the plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns located on the plurality of first connection pillars and the interposer and electrically connected to the plurality of first connection pillars and the plurality of second connection pillars; as well as at least two semiconductor chips located on the upper redistribution line structure and electrically connected to the plurality of upper redistribution line patterns, wherein a portion of the plurality of upper redistribution line patterns and a portion of the plurality of lower redistribution line patterns extend in a horizontal direction beyond a footprint occupied by the at least two semiconductor chips, Wherein, the horizontal plane where the bottom surfaces of the plurality of first connecting columns are located is lower than the bottom surface of the inner plug-in unit. 18 . The semiconductor package of claim 17 , further comprising a passive device connected to a portion of the plurality of lower redistribution line patterns on the lower redistribution line structure.

19. The semiconductor package according to claim 17, wherein: The interposer further includes through electrodes interconnecting the plurality of connection wiring patterns with the plurality of lower redistribution line patterns by penetrating the interposer substrate.

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