Loop compensation method for phase-locked loop frequency synthesizer based on voltage-controlled delay line

Abstract

The present invention discloses a loop compensation method for a phase-locked loop frequency synthesizer based on a voltage-controlled delay line, and proposes a loop compensation structure based on a voltage-controlled delay line, which generates a zero point for loop stability compensation with a small chip area and a very low power consumption cost. The zero point replaces the role of the zero point 1 / R0C0 generated by the second-order filter R0 and C0 in the traditional structure, thereby significantly reducing R0 and C0 in the second-order filter, while still being able to achieve loop stability and keeping the bandwidth unchanged, as shown in FIG1. ​​At the same time, theoretical analysis shows that in a PLL frequency synthesizer based on loop compensation of a voltage-controlled delay line, the noise introduced by the voltage-controlled delay line module is suppressed due to the low-pass characteristics of the loop, and thus has little effect on the output phase noise.

Description

Technical Field

[0001] The invention relates to the fields of electronic information technology and wireless communication, and in particular to a loop compensation method for a phase-locked loop frequency synthesizer based on a voltage-controlled delay line. Background Art

[0002] With the development of modern electronic information technology and wireless communications, the demand for clock signals has increased. Phase-locked loop frequency synthesizers are widely used to generate signal sources due to their good stability, high integration, and wide frequency range. However, when the input reference frequency of the phase-locked loop is low, the loop filter circuit of the traditional Type-II charge pump phase-locked loop requires a larger filter capacitor, which occupies a larger chip area, which is not conducive to low-cost on-chip integration of the phase-locked loop system. Summary of the invention

[0003] The purpose of the present invention is to provide a loop compensation method for a phase-locked loop frequency synthesizer based on a voltage-controlled delay line in order to solve the above-mentioned problem.

[0004] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0005] The present invention comprises the following steps:

[0006] (1) Figure 1 As shown, the input reference frequency signal is delayed by the voltage-controlled delay line (VCDL) module and then input to the phase frequency detector (PFD) module, and then outputs the control voltage V through the charge pump filter (CP+LPF) module. C The voltage controlled oscillator (VCO) module is controlled, and the output signal is fed back to the PFD module through the frequency divider (N) module to achieve the negative feedback regulation of the loop. The delay time of (VCDL) is controlled by the control voltage V C Control, V C If it is increased, the delay time will increase;

[0007] (2) Through loop transfer function analysis, appropriate design parameters are selected to achieve loop stability compensation.

[0008] 1. Transfer function of frequency detector and charge pump

[0009] First, analyze the phase detector model without the charge pump connected to the output. Assume that the PLL has been locked, the phase difference between the input signal and the output signal is θe, and one of the two output signals of the phase detector is a useful output, which can be used to show the magnitude of the phase difference. The average DC voltage at the output is V d Indicated by V H Indicates the high level of the useful output terminal. For a phase detector with a linear phase range between 0 and 2π and a phase center at π, V d It can be expressed by formula (1):

[0010]

[0011] The phase detector transfer function is then,

[0012]

[0013] For PLLs with a charge pump structure, it is not possible to separate the phase detector and the charge pump for linear model transfer function analysis. The signal output by the phase detector enters the charge pump to control the on and off of the charge pump switch, and the effective output DC average value of the phase detector cannot be directly analyzed.

[0014] It can be known that the charge / discharge time of the frequency detector and phase detector for the charge pump in one cycle is approximately (θ e / ω in ), which is accurate when the output signal leads the input signal phase, and approximate otherwise, and only holds true under small bandwidths, because the frequency / phase of the voltage-controlled oscillator will change during the pulse opening process. In this way, the average charge and discharge current of the frequency detector to the charge pump is,

[0015]

[0016] Then the transfer function from phase difference to average charge pump output current is,

[0017]

[0018] 2. Second-order filter transfer function

[0019] The s-domain transfer function of the second-order filter can be expressed as,

[0020]

[0021] 3. Voltage Controlled Delay Line (VCDL) Module Transfer Function

[0022] The input variable of the voltage-controlled delay line is the control voltage V C The output variable is the delay information. The delay of each level of delay unit is represented by t d Indicates that the total delay of N-stage delay units is D = Nt d , then the voltage-controlled delay gain of VCDL can be expressed as,

[0023]

[0024] If the phase is the output variable, the input reference clock period is T in (The reference frequency is ω in ), we can get the transfer function of VCDL as,

[0025] K1=KVCDL 2π / T in =K VCDL ·ω in (7)

[0026] 4. Voltage Controlled Oscillator (VCO) Module Transfer Function

[0027] According to the working principle of voltage controlled oscillator, the control voltage V C is the input of the voltage-controlled ring oscillator, and the output is the frequency. Since the phase is the integral of the frequency over time, assuming the phase difference as the output of the voltage-controlled oscillator, we can get,

[0028] θ ex =K VCO ∫V C dt (8)

[0029] It can be seen that the voltage-controlled oscillator can be regarded as an integrator. After Laplace transform, the transfer function of the voltage-controlled oscillator is:

[0030]

[0031] 5. System loop transfer function

[0032] In summary, under the condition of loop locking, the loop can be linearized and the phase error of the input phase detector can be obtained as follows:

[0033]

[0034] Combining the transfer functions of each module, the loop transfer function of the linear model of the phase-locked loop system based on voltage-controlled delay line compensation is obtained as follows:

[0035]

[0036] Simplifying equation (11), the loop transfer function can also be expressed as equation (12):

[0037]

[0038] From equation (12), we can see that the designed loop contains two zero poles at the origin and one left half plane pole. and two left half plane zeros ( and ). It can be seen that the ratio of the voltage-controlled delay line gain to the voltage-controlled oscillator gain K VCO / K VCDL The left half plane zero point can be determined The position of the voltage-controlled delay line gain and the voltage-controlled oscillator gain are properly designed to set the zero point Placing it within the bandwidth for loop stability compensation can ensure the required bandwidth and phase margin, without the need for loop filter capacitors for zero point compensation. Therefore, the 1 / R0C0 zero point generated by the filter can be placed at a high frequency outside the bandwidth, so the filter capacitor can take a smaller value, such as Figure 2 shown.

[0039] (3) Phase noise analysis is performed using transfer functions. The results show that the noise introduced by the voltage-controlled delay line module is suppressed due to the low-pass characteristics of the loop, so its effect on the output phase noise is very small.

[0040] Analyze the impact of each submodule on the output frequency phase noise in the phase-locked loop compensation structure based on the voltage-controlled delay line, such as Figure 3 shown.

[0041] 1. First, the open-loop transfer function is expressed as,

[0042] G(s)=K d F(s)(K vco / s+K vcdl ) (13)

[0043] The loop transfer function is expressed as,

[0044]

[0045] 2. Phase noise generated by the reference clock

[0046] By calculating the effect of the phase noise introduced by the reference input clock signal on the output, we can get:

[0047]

[0048] From equation (15), we can get the phase noise transfer formula from the input reference clock to the output phase noise:

[0049]

[0050] 3. Phase noise generated from the phase detector to the charge pump

[0051] Calculating the effect of the phase noise generated by the phase detector to the charge pump on the output, we can get,

[0052]

[0053] From equation (17), we can get the phase noise transfer formula from the phase detector to the charge pump to the output:

[0054]

[0055] 4. Filter Phase Noise Transfer

[0056] Calculating the effect of the phase noise generated by the low-pass filter on the output, we can get,

[0057]

[0058] From equation (19), we can get the phase noise transfer formula from the voltage noise generated by the low-pass filter to the output:

[0059]

[0060] 5. Phase noise transfer of voltage-controlled delay lines

[0061] Calculating the effect of the phase noise introduced by the voltage-controlled delay line on the output, we can get:

[0062]

[0063] From equation (21), we can get the phase noise transfer formula from the voltage-controlled delay line to the output phase noise:

[0064]

[0065] 6. Phase noise transfer of voltage controlled oscillators

[0066] Calculating the effect of the phase noise introduced by the voltage-controlled oscillator on the output, we can get:

[0067]

[0068] From equation (23), we can get the phase noise transfer formula from the voltage-controlled oscillator to the output phase noise:

[0069]

[0070] 7. Overall system output phase noise

[0071] In summary, the overall loop output phase noise can be obtained as follows:

[0072]

[0073] It can be seen from formula (25) that the noise introduced by the voltage-controlled delay line module is suppressed due to the low-pass characteristic of the loop, so the impact on the output phase noise is very small.

[0074] It can also be seen from formula (25) that the loop phase noise can be reduced in the following ways: (1) reducing the noise caused by the power supply voltage; (2) reducing the division ratio of the divider by adopting a multi-loop structure; (3) reducing the gain of the voltage-controlled oscillator; (4) increasing the charge pump current; (5) reducing the internal phase noise of the voltage-controlled oscillator and the voltage-controlled delay line; (6) appropriately increasing the loop bandwidth while ensuring the loop stability and being able to accurately capture the phase and lock within the required time.

[0075] The beneficial effects of the present invention are:

[0076] The present invention is a loop compensation method for a phase-locked loop frequency synthesizer based on a voltage-controlled delay line. Compared with the prior art, the present invention proposes a loop compensation structure based on a voltage-controlled delay line, which generates a left half plane zero point for loop stability compensation with a smaller chip area and a very low power consumption cost. The zero point replaces the role of the zero point 1 / R0C0 generated by the second-order filter R0 and C0 in the traditional structure, thereby significantly reducing R0 and C0 in the second-order filter, while still being able to achieve loop stability and keeping the bandwidth unchanged. At the same time, theoretical analysis shows that in a PLL frequency synthesizer based on loop compensation of a voltage-controlled delay line, the noise introduced by the voltage-controlled delay line module is suppressed due to the low-pass characteristics of the loop, so the impact on the output phase noise is very small. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 It is a system structure block diagram of a phase-locked loop frequency synthesizer based on voltage-controlled delay line loop compensation of the present invention;

[0078] Figure 2 a is the loop compensation schematic diagram of the traditional Type-II phase-locked loop;

[0079] Figure 2 b is a schematic diagram of loop compensation based on voltage-controlled delay line compensation of the present invention;

[0080] Figure 3 It is a noise analysis block diagram of a phase-locked loop frequency synthesizer based on voltage-controlled delay line compensation of the present invention;

[0081] Figure 4 is a block diagram of the voltage-controlled delay line circuit structure of the present invention;

[0082] Figure 5 a is the amplitude-frequency and phase-frequency curves of the loop transfer function MATLAB simulation when the output is 90.5MHz;

[0083] Figure 5 b is the control voltage transient response of the actual circuit when the stable output of the present invention is 90.5MHz; DETAILED DESCRIPTION

[0084] The present invention will be further described below in conjunction with specific embodiments:

[0085] Based on the voltage-controlled delay line compensation method, a phase-locked loop frequency synthesizer was designed using a 0.18μm CMOS process, a reference clock period of 31μs (frequency of approximately 32kHz), and an output frequency of 90.5MHz.

[0086] 1. Determine loop system-level parameters based on transfer function

[0087] To ensure the stability and capture lock of the loop, the system-level parameters of each module are determined according to the loop transfer function.

[0088] Step 1: First determine the loop frequency division coefficient. Since the reference clock period is 31μs and the output frequency is 90.5MHz, N is 2828.

[0089] Step 2: Determine the loop bandwidth. To avoid the continuous-time approximation effect of the charge pump, the loop bandwidth is generally set as small as possible compared to the input reference frequency. However, to suppress the VCO phase noise (the main source of system phase noise), the bandwidth needs to be increased as much as possible. As a compromise, the bandwidth can be set to 1 / 10 of the reference frequency, that is,

[0090]

[0091] Step 3: Determine the charge pump current and loop filter capacitor. According to the loop transfer function, the loop DC gain is,

[0092]

[0093] It can be seen from formula (27) that the loop DC gain is determined by the capacitor, charge pump current, and voltage-controlled oscillator gain. The loop compensation structure based on the voltage-controlled delay line does not require the filter capacitor for zero-point compensation. Therefore, a smaller capacitance value can be used. It is only necessary to ensure that the capacitance value and the charge pump current Icp can ensure that the loop gain meets the project requirements and realize the loop's ability and stability to suppress phase noise.

[0094] Step 4: Determine the voltage controlled oscillator (VCO) and voltage controlled delay line (VDCL) gain. The control voltage of the VCO is limited by the power supply voltage and the minimum voltage that can make the charge pump saturate. When the power supply voltage is 2.4V, assuming that the control voltage range of the VCO is 0.5~1.5V, through

[0095]

[0096] That is, equation (28) can be used to obtain the voltage-controlled oscillator gain.

[0097] Similarly, when the power supply voltage is 2.4V, assuming that the VCDL control voltage range is 0.5~1.5V,

[0098]

[0099] That is, equation (29) can be used to obtain the gain of the voltage-controlled delay line VCDL.

[0100] At the same time, the left half plane zero [K VCO / (K VCDL ·ω in )] is placed within the unity gain bandwidth and the RC zero generated by the filter is placed outside the bandwidth. The final VCO gain is 10M / Hz and the delay line VCDL gain is 3.6μs / V.

[0101] 2. Stability simulation verification

[0102] The stability is verified by simulation based on the parameters obtained from the above design. First, MATLAB is used to simulate the loop amplitude-frequency and phase-frequency characteristic curves based on the aforementioned small signal loop transfer function model to determine whether the loop gain, bandwidth, and phase margin are within the design range. Then, the actual circuit time domain simulation is performed based on Cadence Spectre to further verify the stability of the system.

[0103] Taking the output of 90.5MHz as an example, the system parameters calculated by the above method are as follows:

[0104] (1) Power supply voltage VDD = 2.4 V;

[0105] (2) Reference frequency 32768 Hz, ω 3dB =30krad / s, division ratio N=2828.

[0106] (3) R0=80kΩ, C0=80pF, C1=6pF;

[0107] (4)K VCO =10MHz / V,ω in K VCDL =2000rad / V, Icp=20μA.

[0108] The actual circuit design is as follows: the frequency detector, charge pump, voltage controlled oscillator VCO and frequency divider are replaced by VerilogA macro model, and the voltage controlled delay line VCDL module design is as follows: Figure 4 As shown, it is composed of 12 delay units in series, and the delay unit selects a push-pull delay unit structure. This structure controls the voltage V C Adjust the inverter to charge and discharge the output capacitor current I C, changing the charging and discharging speed of the output capacitor, thereby changing the delay. It can be deduced that the delay of a single-stage delay unit is,

[0109]

[0110] It can be seen from formula (30) that I C It is inversely proportional to the delay time formed by the delay unit. It can be seen that by changing the current flowing through the delay unit, that is, changing the charge and discharge current of the equivalent output capacitor of each level of delay unit, the delay time of the push-pull delay unit can be adjusted. This structure can meet the requirements of the system and has the advantages of low power consumption, small area, and wide output range.

[0111] Control voltage V C The charge and discharge current I of the push-pull delay unit C The relationship is,

[0112]

[0113] Substituting equation (31) into equation (30), we can get that the total delay of the voltage-controlled delay line formed by connecting multiple delay units in series is approximately:

[0114]

[0115] From formula (32), we can get that changing the control voltage V C The delay time of the delay line can be changed. Ideally, the control voltage of the voltage-controlled delay line is proportional to the delay time, that is, the gain of the voltage-controlled delay line is a constant determined by the designed device equivalent capacitance and resistance.

[0116] Based on the MATLAB simulation of the loop transfer function, we can get Figure 5 The amplitude-frequency and phase-frequency characteristic curves shown in a are Figure 5 It can be seen that the bandwidth of the phase-locked loop linearization system loop is 30 krad / s and the phase margin is 74 0 The Spectre time domain simulation waveform of the actual circuit is as follows Figure 5 As shown in b, from Figure 5 b It can be seen that the loop can capture and lock within 300μs to obtain the required output frequency of 90.5MHz, the control voltage jitter is less than 0.1%, and the control voltage jitter is within 5mV at the moment the clock pulse signal arrives.

[0117] The model-based MATLAB frequency characteristic simulation and the Spectre time domain simulation based on the actual circuit both verified that the design parameters obtained by the above design steps meet the requirements of loop stability and noise suppression capability set initially. This shows that the loop compensation method based on the voltage-controlled delay line can indeed achieve loop stability compensation while ensuring the loop bandwidth.

[0118] The present invention introduces in detail the principle of loop compensation of a voltage-controlled delay line of a phase-locked loop. The voltage-controlled delay line generates a zero point for loop stability compensation at the cost of a small chip area and very low power consumption. The zero point replaces the role of the zero point 1 / R0C0 generated by the second-order filter in the traditional structure, thereby significantly reducing the resistance R0 and the capacitance C0 in the second-order filter, while still being able to achieve loop stability and keeping the bandwidth unchanged. The present invention analyzes the compensation principle of the proposed structure based on the small signal linearization analysis method; the influence of the noise introduced by the voltage-controlled delay line module on the output phase noise is theoretically analyzed. The analysis shows that the noise introduced by the voltage-controlled delay line module is suppressed due to the low-pass characteristics of the loop, so the influence on the output phase noise is very small. The present invention also introduces in detail the specific circuit implementation technology of the voltage-controlled delay line and the design process of the system parameters of the PLL frequency synthesizer with voltage-controlled delay line compensation through a specific embodiment.

[0119] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A loop compensation method based on a voltage-controlled delay line, characterized in that: (1) The input reference frequency signal is delayed by the voltage-controlled delay line module and then input to the frequency detector module. The charge pump filter module outputs the control voltage VC to control the voltage-controlled oscillator module, and then the output signal is fed back to the PFD module through the frequency divider module to achieve the loop negative feedback regulation function; (2) The delay time of the voltage-controlled delay line VCDL is controlled by the control voltage VC. When the control voltage VC increases, the delay time increases. Determine loop system-level parameters based on transfer function To ensure the stability and capture lock of the loop, the system-level parameters of each module are determined according to the loop transfer function; Step 1: First determine the loop frequency division coefficient; since the reference clock period is 31μs and the output frequency is 90.5MHz, N is 2828; Step 2: Determine the loop bandwidth: To avoid the continuous-time approximation effect of the charge pump, the loop bandwidth should be as small as possible from the input reference frequency. However, to suppress the phase noise of the VCO, the bandwidth should be as large as possible. As a compromise, the bandwidth can be set to 1 / 10 of the reference frequency, that is: Step 3: Determine the charge pump current and loop filter capacitor: According to the loop transfer function, the loop DC gain is: It can be seen from formula (27) that the loop DC gain is determined by the capacitor, charge pump current, and voltage-controlled oscillator gain. The loop compensation structure based on the voltage-controlled delay line does not require the filter capacitor for zero-point compensation. Therefore, a smaller capacitance value is selected. It is only necessary to ensure that the capacitance value and the charge pump current Icp can ensure that the loop gain meets the project requirements and realize the loop's ability and stability to suppress phase noise. Step 4: Determine the gain of the voltage-controlled oscillator and voltage-controlled delay line: The control voltage of the VCO is limited by the power supply voltage and the minimum voltage that can make the charge pump saturate; when the power supply voltage is 2.4V, assuming that the control voltage range of the VCO is 0.5~1.5V, through That is, the voltage-controlled oscillator gain can be obtained from equation (28); Similarly, when the power supply voltage is 2.4V, assuming that the VCDL control voltage range is 0.5~1.5V, That is, equation (29) can obtain the gain of the voltage-controlled delay line VCDL; At the same time, the left half plane zero [K VCO / (K VCDL ·ω in )] is placed within the unity gain bandwidth, and the RC zero point generated by the filter is placed outside the bandwidth; the final VCO gain is 10M / Hz, and the delay line VCDL gain is 3.6μs / V; The stability is simulated and verified by the parameters obtained by the above design. First, MATLAB is used to simulate the loop amplitude-frequency and phase-frequency characteristic curves based on the above small signal loop transfer function model to determine whether the loop gain, bandwidth and phase margin are within the design range. Then, actual circuit time domain simulation is performed based on Cadence Spectre to further verify the stability of the system.

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