Annular oscillator with adjustable phase noise and maximum oscillation frequency and control method

Abstract

The invention aims to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator comprises a main path and a third auxiliary path, the third auxiliary path is connected with the main path and is used for improving the oscillation frequency; by inserting the adjustable phase inverter, when the frequency of the ring oscillator does not meet the specification under the extreme corner condition, the oscillation frequency is improved by adjusting the phase inverter to sacrifice some phase noise.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a ring oscillator with adjustable phase noise and maximum oscillation frequency and a control method thereof. Background Art

[0002] The ‌ring oscillator‌ is a ring circuit composed of an odd number of NOT gates, with its output and input connected end to end to form a ring structure. The characteristics of the ring oscillator are simple circuit, easy to start oscillation, and no need for additional resistors and capacitors, which is easy to integrate. Its working principle is to achieve oscillation by generating periodic high and low level changes through the delay effect of the NOT gate. The basic working principle of the ring oscillator is to achieve oscillation through the delay effect of an odd number of NOT gates. Taking three NOT gates as an example, the output of NOT gate A is connected to the input of NOT gate B, the output of NOT gate B is connected to the input of NOT gate C, and the output of NOT gate C is connected to the input of NOT gate A to form a closed loop. When the input end of NOT gate A becomes a high level, its output end becomes a low level, and so on, forming a periodic high and low level change, thereby achieving oscillation. Ring oscillators are mainly used for high-frequency oscillations with low requirements for internal integration of integrated circuits, as well as simple oscillators in ordinary digital circuits. Due to its simple circuit, easy start-up and no need for additional resistors and capacitors, ring oscillators have certain advantages in integrated circuit design. In addition, the ring oscillator can also change the oscillation period by adding a resistor-capacitor delay network, which is suitable for application scenarios that require flexible frequency adjustment.

[0003] Different process corners represent different extreme conditions of process parameters. For example, at the fastest process corner, all process deviations increase the drive current of the transistor, so the speed is the fastest; while at the slowest process corner, the device speed is slowed down by the process deviation. Changes in these process parameters will cause changes in parameters such as the threshold voltage and transconductance of the transistor, thereby affecting the delay time of basic units such as the inverter in the ring oscillator, and ultimately causing the oscillation frequency to fail to meet the requirements. Summary of the invention

[0004] The purpose of the present invention is to provide a ring oscillator with adjustable phase noise and maximum oscillation frequency and a control method. The oscillator inserts an adjustable inverter to achieve the purpose of increasing the oscillation frequency by sacrificing some phase noise by adjusting the inverter when the ring oscillator frequency does not meet the requirements under extreme corner conditions.

[0005] A ring oscillator with adjustable phase noise and maximum oscillation frequency, comprising: a main path and a third auxiliary path; The third auxiliary path is connected to the main path and is used to increase the oscillation frequency; The third auxiliary path includes: a twenty-fourth inverter, a twenty-fifth inverter, a twenty-sixth inverter, a twenty-seventh inverter, a twenty-eighth inverter, a twenty-ninth inverter, a thirtieth inverter and a thirty-first inverter; The input end of the twenty-fourth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-fifth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the twenty-sixth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twenty-seventh inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the twenty-eighth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the twenty-ninth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the 30th inverter is connected to the output end of the 4th inverter and the input end of the 5th inverter, and the output end is connected to the output end of the 7th inverter and the input end of the 0th inverter; The input end of the thirty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter.

[0006] Preferably, the main path includes: a zeroth inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter; The input end of the zeroth inverter is connected to the output end of the seventh inverter, and the output end is connected to the input end of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output terminal of the second inverter is connected to the input terminal of the third inverter; The output terminal of the third inverter is connected to the input terminal of the fourth inverter; The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter; The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter; The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter; The output terminal of the seventh inverter is connected to the input terminal of the zeroth inverter.

[0007] Preferably, it further comprises: a first auxiliary passage; The first auxiliary path includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter and a fifteenth inverter; The input end of the eighth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the ninth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the tenth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the eleventh inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twelfth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the thirteenth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the fourteenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input end of the fifteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the seventh inverter and the input end of the zeroth inverter.

[0008] Preferably, it further comprises: a second auxiliary passage; The second auxiliary path includes: a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first inverter, a twenty-second inverter and a twenty-third inverter; The input end of the sixteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the seventeenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the eighteenth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the nineteenth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the 20th inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-second inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input terminal of the twenty-third inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal of the twenty-third inverter is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter.

[0009] Preferably, the zeroth inverter has the same structure as the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter, the fifteenth inverter, the sixteenth inverter, the seventeenth inverter, the tenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter; The zeroth inverter comprises: a first NMOS tube and a first PMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the source of the first NMOS tube, the source is connected to a high level, and the gate is connected to the gate of the first PMOS tube; The source of the first NMOS tube is grounded.

[0010] Preferably, the structure of the twenty-fourth inverter is consistent with the structures of the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter; The twenty-four inverters include: a plurality of switch branches; Each of the switch branches is connected in parallel; The switch branch includes: a second NMOS transistor, a second PMOS transistor, a first switch and a second switch; The drain of the second PMOS tube is connected to the first switch, the gate is connected to the gate of the second NMOS tube, and the source is connected to a high level; The drain of the second NMOS tube is connected to the second switch, and the source is grounded.

[0011] Preferably, the driving capabilities of the zeroth inverter, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter are 2-3 times that of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter.

[0012] Preferably, the driving capabilities of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter are 3-4 times that of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter.

[0013] Preferably, the driving capabilities of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter are 1.2-1.6 times the driving capabilities of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter.

[0014] A phase noise and maximum oscillation frequency adjustable ring oscillator control method, applied to a phase noise and maximum oscillation frequency adjustable ring oscillator, comprising: Under the TT, FF corner conditions, the switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are disconnected, that is, the third auxiliary path of the oscillator is disconnected. At this time, the oscillation frequency and phase noise of the oscillator meet the requirements; Under the SS corner condition, switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are gradually turned on to increase the frequency to a specified value.

[0015] The beneficial effect of the present invention is that compared with the existing 8-phase output ring oscillator, under the same power consumption conditions, the present invention inserts the adjustable inverters: the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter, so that when the ring oscillator frequency does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by adjusting the adjustable inverters to sacrifice some phase noise to meet the working requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A structural diagram of a ring oscillator with adjustable phase noise and maximum oscillation frequency according to the present invention; Figure 2 It is a schematic diagram of the structure of the non-adjustable inverter of the present invention; Figure 3 It is a schematic diagram of the structure of the adjustable inverter of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] Different process corners represent different extreme conditions of process parameters. For example, at the fastest process corner, all process deviations increase the drive current of the transistor, so the speed is the fastest; while at the slowest process corner, the device speed is slowed down by the process deviation. Changes in these process parameters will cause changes in parameters such as the threshold voltage and transconductance of the transistor, thereby affecting the delay time of basic units such as the inverter in the ring oscillator, and ultimately causing the oscillation frequency to fail to meet the requirements.

[0023] Compared with the existing 8-phase output ring oscillator, under the same power consumption condition, the present invention inserts the adjustable inverters: the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter, so that when the ring oscillator frequency does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by adjusting the adjustable inverters to sacrifice some phase noise to meet the working requirements.

[0024] Example 1 A ring oscillator with adjustable phase noise and maximum oscillation frequency, reference Figure 1 , including: a main passage and a third auxiliary passage; The third auxiliary path is connected to the main path and is used to increase the oscillation frequency; The third auxiliary path includes: a twenty-fourth inverter, a twenty-fifth inverter, a twenty-sixth inverter, a twenty-seventh inverter, a twenty-eighth inverter, a twenty-ninth inverter, a thirtieth inverter and a thirty-first inverter; The input end of the twenty-fourth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-fifth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the twenty-sixth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twenty-seventh inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end of the twenty-seventh inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the twenty-eighth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end of the twenty-eighth inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the twenty-ninth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end of the twenty-ninth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input terminal of the 30th inverter is connected to the output terminal of the 4th inverter and the input terminal of the 5th inverter, and the output terminal of the 30th inverter is connected to the output terminal of the 7th inverter and the input terminal of the 0th inverter; The input terminal of the thirty-first inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal of the thirty-first inverter is connected to the output terminal of the zeroth inverter and the input terminal of the first inverter.

[0025] like Figure 1 As shown, eight inverters D0 to D7 form the main path of the ring oscillator, and inverters D24 to D31 form the third auxiliary path of the ring oscillator. Figure 1 Among them, P0~P3 and N0~N3 are 8 phase oscillation waveforms output by the ring oscillator.

[0026] In the embodiment of the present invention, in the third auxiliary path, a feedback inverter is inserted every five inverters, and the size of the inverter transistor is set smaller than that of the first and second auxiliary paths, so the frequency boosting effect is the weakest.

[0027] The internal inverters of the main path, the first auxiliary path, and the second auxiliary path of the present invention do not need to be enabled, and only the internal inverter of the third auxiliary path uses enable adjustable control. When the maximum output frequency of the oscillator does not meet the requirements under extreme corner conditions, the frequency is further increased by inserting the third adjustable auxiliary path and sacrificing some phase noise.

[0028] Preferably, the main path includes: a zeroth inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter; The input terminal of the zeroth inverter is connected to the output terminal of the seventh inverter, and the output terminal is connected to the input terminal of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output terminal of the second inverter is connected to the input terminal of the third inverter; The output terminal of the third inverter is connected to the input terminal of the fourth inverter; The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter; The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter; The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter; The output terminal of the seventh inverter is connected to the input terminal of the zeroth inverter.

[0029] Preferably, it further comprises: a first auxiliary passage; The first auxiliary path includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter and a fifteenth inverter; The input end of the eighth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the ninth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the tenth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end of the tenth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the eleventh inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end of the eleventh inverter is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twelfth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end of the twelfth inverter is connected to the output end of the second inverter and the input end of the third inverter; The input end of the thirteenth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end of the thirteenth inverter is connected to the output end of the first inverter and the input end of the second inverter; The input end of the fourteenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input terminal of the fifteenth inverter is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the output terminal of the fifteenth inverter is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter.

[0030] like Figure 1 As shown, inverters D8-D15 form a first auxiliary path of the ring oscillator.

[0031] In the embodiment of the present invention, in the first auxiliary path, a feedback inverter is inserted every two inverters, and the size of the inverter transistor is set larger than that of the second and third auxiliary paths, so the frequency boosting effect is the strongest.

[0032] Preferably, it further comprises: a second auxiliary passage; The second auxiliary path includes: a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first inverter, a twenty-second inverter and a twenty-third inverter; The input end of the sixteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the seventeenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the eighteenth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the nineteenth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the twentieth inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-second inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input terminal of the twenty-third inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal of the twenty-third inverter is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter.

[0033] In the embodiment of the present invention, in the second auxiliary path, a feedback inverter is inserted every four inverters, and the size of the inverter transistor is set smaller than that of the first auxiliary path and larger than that of the third auxiliary path, and the frequency boosting effect is second.

[0034] Preferably, reference Figure 2, the zeroth inverter has the same structure as the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter, the fifteenth inverter, the sixteenth inverter, the seventeenth inverter, the tenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter; The zeroth inverter comprises: a first NMOS tube and a first PMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the source of the first NMOS tube, the source is connected to a high level, and the gate is connected to the gate of the first PMOS tube; The source of the first NMOS tube is grounded.

[0035] Preferably, reference Figure 3 , the structure of the twenty-fourth inverter is consistent with the structures of the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter; The twenty-four inverter includes: a plurality of switch branches; Each switch branch is connected in parallel; The switch branch includes: a second NMOS transistor, a second PMOS transistor, a first switch and a second switch; The drain of the second PMOS tube is connected to the first switch, the gate is connected to the gate of the second NMOS tube, and the source is connected to a high level; The drain of the second NMOS tube is connected to the second switch, and the source is grounded.

[0036] In an embodiment of the present invention, a switch branch has two switches, the upper one is a PMOS switch, and the lower one is an NMOS switch. The switch position placed in the present invention introduces smaller parasitic capacitance at the oscillation node.

[0037] Preferably, the driving capabilities of the zeroth inverter, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter are 2-3 times that of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter.

[0038] In the embodiment of the present invention, as the driving capability of the inverter increases, the oscillation frequency output by the ring oscillator will also increase. Inverters D0-D23 are universal inverters. Inverters D24-D31 are internally composed of 5 groups of inverters. S1-S5 are used as switches to control the opening and closing of the inverters. The driving capability of inverters D0-D7 is 2-3 times stronger than that of inverters D8-D15, and the driving capability of inverters D8-D15 is 3-4 times stronger than that of inverters D16-D23. The driving capability of inverters D16-D23 is 1.2-1.6 times stronger than that of inverters D24-D31.

[0039] Preferably, the driving capabilities of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter are 3-4 times that of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter.

[0040] Preferably, the driving capability of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter is 1.2-1.6 times the driving capability of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter.

[0041] In the embodiment of the present invention, in the third auxiliary path composed of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter, because the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are all adjustable inverters, the driving capability of the inverters in the third auxiliary path is adjustable, and the effect of improving the oscillation frequency is adjustable. In order to adapt to the requirements of different corners for the maximum frequency, for example: in the ff corner, the oscillation frequency is very high and the maximum frequency meets the requirements, the inverter of the third auxiliary path can be completely turned off; in the ss corner, the oscillation frequency is very small and the maximum frequency does not meet the requirements, the inverter of the third auxiliary path is completely turned on.

[0042] Example 2 A phase noise and maximum oscillation frequency adjustable ring oscillator control method, applied to a phase noise and maximum oscillation frequency adjustable ring oscillator, comprising: Under the TT, FF corner conditions, the switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are disconnected, that is, the third auxiliary path of the oscillator is disconnected. At this time, the oscillation frequency and phase noise of the oscillator meet the requirements; Under the TT and FF corner conditions, the switches S1 to S5 inside the inverters D24 to D31 are disconnected, which is equivalent to disconnecting the third auxiliary path of the oscillator. At this time, the oscillation frequency and phase noise of the oscillator meet the spec.

[0043] Under the SS corner condition, switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are gradually turned on to increase the frequency to a specified value.

[0044] However, under the SS corner condition, if the internal S1~S5 switches of inverters D24~D31 are disconnected, the oscillator frequency cannot meet the spec, but the phase noise is better than the spec with a certain margin; at this time, the internal S1~S5 switches of inverters D24~D31 are gradually turned on, sacrificing some phase noise to meet the requirement of increasing the frequency to the spec.

[0045] Compared with the existing 8-phase output ring oscillator, under the same power consumption condition, the present invention inserts the adjustable inverters: the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter, so that when the ring oscillator frequency does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by adjusting the adjustable inverters to sacrifice some phase noise to meet the working requirements.

[0046] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A ring oscillator with adjustable phase noise and maximum oscillation frequency, characterized in that: include: Main access and third auxiliary access; The third auxiliary path is connected to the main path and is used to increase the oscillation frequency; The third auxiliary path includes: a twenty-fourth inverter, a twenty-fifth inverter, a twenty-sixth inverter, a twenty-seventh inverter, a twenty-eighth inverter, a twenty-ninth inverter, a thirtieth inverter and a thirty-first inverter; The input end of the twenty-fourth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-fifth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the twenty-sixth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twenty-seventh inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the twenty-eighth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the twenty-ninth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the 30th inverter is connected to the output end of the 4th inverter and the input end of the 5th inverter, and the output end is connected to the output end of the 7th inverter and the input end of the 0th inverter; The input end of the thirty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter.

2. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The main path includes: a zeroth inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter; The input end of the zeroth inverter is connected to the output end of the seventh inverter, and the output end is connected to the input end of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output terminal of the second inverter is connected to the input terminal of the third inverter; The output terminal of the third inverter is connected to the input terminal of the fourth inverter; The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter; The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter; The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter; The output terminal of the seventh inverter is connected to the input terminal of the zeroth inverter.

3. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: Also includes: First auxiliary access; The first auxiliary path includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter and a fifteenth inverter; The input end of the eighth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the ninth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the tenth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the eleventh inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twelfth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the thirteenth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the fourteenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input end of the fifteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the seventh inverter and the input end of the zeroth inverter.

4. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: Also includes: Second auxiliary pathway; The second auxiliary path includes: a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first inverter, a twenty-second inverter and a twenty-third inverter; The input end of the sixteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the seventeenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the eighteenth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the nineteenth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the 20th inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-second inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input terminal of the twenty-third inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal of the twenty-third inverter is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter.

5. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The zeroth inverter has the same structure as the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter, the fifteenth inverter, the sixteenth inverter, the seventeenth inverter, the tenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter; The zeroth inverter comprises: a first NMOS tube and a first PMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the source of the first NMOS tube, the source is connected to a high level, and the gate is connected to the gate of the first PMOS tube; The source of the first NMOS tube is grounded.

6. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The structure of the twenty-fourth inverter is consistent with the structures of the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter; The twenty-four inverters include: a plurality of switch branches; Each of the switch branches is connected in parallel; The switch branch includes: a second NMOS transistor, a second PMOS transistor, a first switch and a second switch; The drain of the second PMOS tube is connected to the first switch, the gate is connected to the gate of the second NMOS tube, and the source is connected to a high level; The drain of the second NMOS tube is connected to the second switch, and the source is grounded.

7. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The driving capabilities of the zeroth inverter, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter are 2-3 times that of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter.

8. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 7, characterized in that: The driving capabilities of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter are 3-4 times that of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter.

9. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 8, characterized in that: The driving capabilities of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter are 1.2-1.6 times the driving capabilities of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter.

10. A method for controlling a ring oscillator with adjustable phase noise and maximum oscillation frequency, applied to a ring oscillator with adjustable phase noise and maximum oscillation frequency as claimed in any one of claims 1 to 9, characterized in that: include: Under the TT, FF corner conditions, the switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are disconnected, that is, the third auxiliary path of the oscillator is disconnected. At this time, the oscillation frequency and phase noise of the oscillator meet the requirements; Under the SS corner condition, switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are gradually turned on to increase the frequency to a specified value.

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