Spread spectrum fractional frequency division control circuit, fractional frequency division phase-locked loop and chip

Abstract

The invention provides a spread spectrum fractional frequency division control circuit, a fractional frequency division phase-locked loop and a chip, the spread spectrum fractional frequency division control circuit comprises a spread spectrum circuit, a signal modulator and a frequency division control signal output circuit, and the spread spectrum circuit correspondingly processes a superposition result according to a corresponding spread spectrum mode. According to the technical scheme of the invention, the method comprises the following steps of: adding a first frequency division control signal to a frequency division circuit to obtain a corresponding first frequency division control signal, and processing the superposition result in a non-spread-spectrum mode and different spread-spectrum modes (including a central spread-spectrum mode and a downward spread-spectrum mode) by the spread-spectrum circuit is different, so that the non-spread-spectrum mode and the different spread-spectrum modes can be supported by the technical scheme of the invention; and an effective spectrum spreading function can be kept when the fractional frequency division ratio is close to 0 or 1, so that a good phase noise suppression effect is achieved while high frequency and high resolution are completed, and relatively high flexible configuration capability is provided.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a spread-spectrum fractional-divide control circuit, a fractional-phase-locked loop, and a chip. Background Art

[0002] High-speed frequency sources are the main sources of electromagnetic interference in electronic circuits, which may have a negative impact on the performance and stability of the system. To effectively suppress the electromagnetic interference brought by high-speed digital systems, various methods can be adopted, such as using high-order filters, power decoupling, good clock line layout, ground wire and power consumption ground isolation, using clock buffers, etc. If the clock of the system is provided by a phase-locked loop, the clock can also be fractionally divided and spread-spectrumed, so that the electromagnetic interference of the output clock is spread over a larger frequency spectrum, effectively reducing the electromagnetic interference and improving the reliability and stability of the system.

[0003] Although some existing spread-spectrum control circuits can implement the superposition of fractional-divide and spread-spectrum functions by using the principle of phase delay compensation, they still have the problem of phase spurs (i.e., the interference degree of fractional spurs), and cannot achieve good phase noise performance while achieving high frequency and high resolution.

[0004] Although some other existing spread-spectrum control circuits can cyclically modulate the spread-spectrum fractional divider used to implement the fractional-divide and spread-spectrum functions through a Σ-Δ modulator, thereby reducing the interference degree of the fractional spurs of the modulation output, they can only perform a small-amplitude center spread-spectrum. When the fractional-divide ratio is close to 0 or close to 1, the center spread-spectrum function will be distorted downward or upward, that is, the spread-spectrum function is lost at this time, and the applicable range is small.

[0005] Therefore, there is an urgent need for a new fractional-divide and spread-spectrum control scheme, which can not only implement the superposition of fractional-divide and spread-spectrum functions to reduce the signal spur problem existing in the existing fractional-divide technology, but also provide a high flexible configuration ability to maintain an effective spread-spectrum function when the fractional-divide ratio is close to 0 or close to 1, and then achieve a good phase noise suppression effect while achieving high frequency and high resolution. Summary of the Invention

[0006] The purpose of the present invention is to provide a spread-spectrum fractional-divide control circuit, a fractional-phase-locked loop, and a chip, which can implement the superposition of fractional-divide and spread-spectrum functions and also provide a high flexible configuration ability.

[0007] To achieve the above purpose, the present invention provides a spread-spectrum fractional-divide control circuit, which includes: A spread spectrum circuit is used to superimpose an (n + 1)-bit fractional division control signal and a corresponding triangular wave signal in a corresponding spread spectrum mode to obtain a first superimposed result, and perform corresponding processing on the first superimposed result according to the spread spectrum mode to obtain a corresponding first frequency division control signal, wherein the processing of the first superimposed result by the spread spectrum circuit in the non-spread spectrum mode and different spread spectrum modes is different from each other; A signal modulator is coupled to the spread spectrum circuit and is used to modulate and shape the first frequency division control signal; and A frequency division control signal output circuit is coupled to the signal modulator and a corresponding fractional frequency divider, and is used to provide a second frequency division control signal to the fractional frequency divider according to the output of the signal modulator, and the fractional frequency divider is used to divide a corresponding clock based on the second frequency division control signal.

[0008] Optionally, the initial value of the first superimposed result is equal to MFN[n:0], and the first superimposed result increases by MODSTEP in each clock cycle of the feedback clock fed back by the fractional frequency divider until the maximum value, and then the first superimposed result decreases by MODSTEP in each clock cycle of the feedback clock until it decreases back to MFN[n:0]; wherein the maximum value is MFN[n:0] + MODSTEP * MODCNT, MFN[n:0] is the (n + 1)-bit fractional division control signal, MODSTEP is the spread spectrum modulation step configured by a register, and MODCNT is the number of spread spectrum modulation steps configured by a register.

[0009] Optionally, the register configuration value of MODCNT is calculated according to the modulation frequency and the reference clock in the spread spectrum mode, and the register configuration value of MODSTEP is calculated according to the modulation depth in the spread spectrum mode, the (n + 1)-bit fractional division control signal, and the corresponding integer division control signal.

[0010] Optionally, the spread spectrum circuit subtracts different first subtraction values from the first superimposed result in the non-spread spectrum mode and different spread spectrum modes to implement the different processing in the non-spread spectrum mode and different spread spectrum modes, and the first subtraction value is configured by a second register or calculated according to the register configuration values of MODSTEP and MODCNT; wherein MODSTEP is the spread spectrum modulation step configured by a register, and MODCNT is the number of spread spectrum modulation steps configured by a register.

[0011] Optionally, the first subtraction value is equal to 0 in the non-spread spectrum mode, equal to MODSTEP * MODCNT / 2 in the center spread spectrum mode, and equal to MODSTEP * MODCNT in the downward spread spectrum mode.

[0012] Optionally, the frequency spreading circuit includes: A triangular wave generator, configured to generate and output the triangular wave signal corresponding to the fractional division control signal of the n+1 bits in the corresponding frequency spreading mode; A second accumulator, coupled to the triangular wave generator and the fractional division control signal of the n+1 bits, and configured to superimpose the output of the triangular wave generator and the fractional division control signal of the n+1 bits to obtain the first superimposed result; A subtractor, coupled to the second accumulator, and configured to subtract the first subtracted value from the first superimposed result output by the second accumulator to obtain the first frequency division control signal.

[0013] Optionally, the frequency spreading circuit is further configured to extend the number of bits of the processed result by k bits to output the first frequency division control signal of n+k+1 bits, where n≥0, k≥2 and both n and k are integers.

[0014] Optionally, n=13 and k=2.

[0015] Optionally, the frequency spreading circuit further includes a first register, where an additional value of n+k+1 bits is configured in the first register, and the frequency spreading circuit is further configured to superimpose the first superimposed result or the processed result with the additional value, thereby extending the number of bits of the processed result by k bits.

[0016] Optionally, the frequency spreading fractional division control circuit further includes: A signal separation circuit, coupled to the frequency spreading circuit, and configured to separate the highest k-bit and the remaining n+1-bit in the first frequency division control signal of n+k+1 bits to obtain a high k-bit signal and a low n+1-bit signal; A high k-bit delay circuit, coupled to the signal separation circuit and the frequency division control signal output circuit, and configured to delay the high k-bit signal output by the signal separation circuit and provide it to the frequency division control signal output circuit; Wherein, the signal modulator modulates and shapes the low n+1-bit signal output by the signal separation circuit, and the output of the signal modulator is synchronized with the output of the high k-bit delay circuit; The frequency division control signal output circuit further superimposes the output of the signal modulator and the output of the high k-bit delay circuit.

[0017] Optionally, the high k-bit delay circuit includes a delay chain, the delay chain includes at least two cascaded first delay units, and the number of stages of the first delay unit matches the modulation time of the signal modulator.

[0018] Optionally, the first delay unit is a k-bit register; and / or, the number of stages of the first delay unit is three, and the signal modulator is a third-order SDM modulator using a MASH structure.

[0019] Optionally, the frequency division control signal output circuit is further configured to: superimpose the output of the high k-bit delay circuit, the output of the signal modulator, and the corresponding integer frequency division control signal, and then subtract a k-bit second subtraction value to obtain the second frequency division control signal after integer frequency division superposition.

[0020] Optionally, the frequency division control signal output circuit includes: A third accumulator, coupled to the signal modulator and the high k-bit delay circuit, and configured to superimpose the output of the high k-bit delay circuit and the output of the signal modulator; A third register, configured to configure the second subtraction value; A fourth accumulator, coupled to the third accumulator, the third register, and the corresponding integer frequency division control signal, and configured to add the output of the third accumulator and the integer frequency division control signal and then subtract the second subtraction value; An output register, coupled to the fourth accumulator, configured to perform clock synchronization on the output of the fourth accumulator and the feedback clock fed back by the fractional frequency divider to output the second frequency division control signal.

[0021] Optionally, the spread spectrum fractional frequency division control circuit further includes a pseudo-random sequence generator for generating and outputting a pseudo-random sequence; the spread spectrum circuit further includes a first accumulator, coupled to the n+1-bit fractional frequency division control signal and the pseudo-random sequence generator, and configured to superimpose the n+1-bit fractional frequency division control signal and the pseudo-random sequence to obtain a second superimposed result, and superimpose the second superimposed result with the triangular wave signal to obtain the first superimposed result.

[0022] Optionally, the spread spectrum circuit is further coupled to an enable signal, a spread spectrum mode control signal, and a spread spectrum direction control signal, and provides the following operating modes according to the enable signal, the spread spectrum mode control signal, and the spread spectrum direction control signal: (1) Only integer frequency division mode: The enable signal is at a first level; (2) Fractional frequency division mode without superimposed spread spectrum: The enable signal is at a second level, and the spread spectrum mode control signal is at a second level; (3) Spread spectrum mode: The enable signal is at a second level, the spread spectrum mode control signal is at a first level, and when the spread spectrum direction control signal is at a first level, it is center spread spectrum, and when the spread spectrum direction control signal is at a second level, it is downward spread spectrum.

[0023] Optionally, the frequency spreading circuit further further divides the frequency spreading mode according to the (n + 1)-bit fractional division control signal MFN[n:0] and the frequency spreading direction control signal into: (3-1) Central frequency spreading mode with integer division: The frequency spreading direction control signal is at the first level, and MFN[n:0] = 0; (3-2) Downward frequency spreading mode with integer division: The frequency spreading direction control signal is at the second level, and MFN[n:0] = 0; (3-3) Central frequency spreading mode with superimposed fractional division: The frequency spreading direction control signal is at the first level, and MFN[n:0] ≠ 0; (3-4) Downward frequency spreading mode with superimposed fractional division: The frequency spreading direction control signal is at the second level, and MFN[n:0] ≠ 0.

[0024] Based on the same inventive concept, the present invention also provides a fractional phase-locked loop, including a prescaler, a frequency discriminator and phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator connected in sequence. The fractional phase-locked loop further includes a fractional divider and a frequency spreading fractional division control circuit as described in the present invention. The output end of the fractional divider is coupled to the feedback input end of the frequency discriminator and phase detector. One input end of the fractional divider is coupled to the output end of the voltage-controlled oscillator, and the other input end of the fractional divider is coupled to the output end of the frequency spreading fractional division control circuit.

[0025] Based on the same inventive concept, the present invention also provides a chip, which includes the phase-locked loop as described in the present invention.

[0026] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects: 1. The spread-spectrum fractional-N control circuit of the present invention includes a spread-spectrum circuit, a signal modulator, and a fractional-N control signal output circuit. The spread-spectrum circuit can superimpose an (n + 1)-bit fractional-N control signal and a corresponding triangular wave signal in a corresponding spread-spectrum mode, and perform corresponding processing on the superimposed result according to the spread-spectrum mode to obtain a corresponding first fractional-N control signal. Moreover, in the non-spread-spectrum mode (such as the integer-only spread-spectrum mode and the non-superimposed spread-spectrum fractional-N mode in the embodiments of the present invention) and different spread-spectrum modes (such as the center spread-spectrum mode and the downward spread-spectrum mode described in the embodiments of the present invention), the processing of the first superimposed result is different. After being modulated and shaped by the signal modulator, the first fractional-N control signal is output as a second fractional-N control signal by the fractional-N control signal output circuit, and then the fractional-N divider divides the corresponding clock based on the second fractional-N control signal. Therefore, the technical solution of the present invention can support the non-spread-spectrum mode and different spread-spectrum modes, and can maintain an effective spread-spectrum function when the fractional-N ratio is close to 0 or close to 1, and can achieve a good phase noise suppression effect while achieving high frequency and high resolution.

[0027] 2. The register configuration values of the spread-spectrum modulation step MODSTEP and the spread-spectrum modulation step count MODCNT can be calculated and configured according to information such as the spread-spectrum modulation frequency and modulation amplitude according to actual requirements, thereby providing a high flexible configuration ability and a wide application range.

[0028] 3. The spread-spectrum fractional-N control circuit of the present invention can also extend the number of bits of the processing result obtained by its spread-spectrum circuit by k bits, thereby avoiding the problem of signal overflow after the superposition of the fractional-N division and the spread-spectrum function. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them: Figure 1 is a schematic circuit diagram of the phase-locked loop according to the first embodiment of the present invention.

[0030] Figure 2 is a schematic diagram of the architecture of the spread-spectrum fractional-N control circuit according to the first embodiment of the present invention.

[0031] Figure 3 is a schematic diagram of an example structure of the spread-spectrum circuit in the spread-spectrum fractional-N control circuit according to the first embodiment of the present invention.

[0032] Figure 4 is a schematic diagram of center spread-spectrum of the spread-spectrum circuit in the spread-spectrum fractional-N control circuit according to the first embodiment of the present invention.

[0033] Figure 5It is a schematic diagram of down - spreading of the spreading circuit in the spread - spectrum fractional - frequency - division control circuit according to the first embodiment of the present invention.

[0034] Figure 6 It is a schematic diagram of an example structure of the signal modulator in the spread - spectrum fractional - frequency - division control circuit according to the first embodiment of the present invention.

[0035] Figure 7 It is a schematic diagram of an example structure of the third delay unit in the signal modulator of the spread - spectrum fractional - frequency - division control circuit according to the first embodiment of the present invention.

[0036] Figure 8 It is a schematic diagram of an example structure of the frequency - division control signal output circuit in the spread - spectrum fractional - frequency - division control circuit according to the first embodiment of the present invention.

[0037] Figure 9 It is a schematic diagram of the architecture of the spread - spectrum fractional - frequency - division control circuit according to the second embodiment of the present invention.

[0038] Figure 10 It is a schematic diagram of an example structure of the spreading circuit in the spread - spectrum fractional - frequency - division control circuit according to the second embodiment of the present invention.

[0039] Figure 11 It is a schematic diagram of an example structure of the high - k bit - delay circuit in the spread - spectrum fractional - frequency - division control circuit according to the second embodiment of the present invention.

[0040] Figure 12 It is a schematic diagram of an example structure of the frequency - division control signal output circuit in the spread - spectrum fractional - frequency - division control circuit according to the second embodiment of the present invention.

[0041] Figure 13 It is a schematic diagram of an example structure of the spread - spectrum fractional - frequency - division control circuit according to the second embodiment of the present invention (n = 13, k = 2, m = 7). Detailed implementation manners

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0043] The following combines the attached Figure 1 to the attached Figure 13 and specific embodiments to detail the technical solution of the present invention.

[0044] First Embodiment Please refer to Figure 1 , an embodiment of the present invention provides a spread-spectrum fractional division control circuit 10 and a fractional division phase-locked loop having the spread-spectrum fractional division control circuit 10. That is, the spread-spectrum fractional division control circuit 10 of this embodiment is provided in the fractional division phase-locked loop.

[0045] In one example, please refer to Figure 1 , the fractional division phase-locked loop of this embodiment not only includes a prescaler (DIVM, also referred to as "front-end prescaler") 11, a phase frequency detector (PFD) 12, a charge pump (CHP) 13, a low-pass filter (LPF, also referred to as "loop filter") 14, and a voltage-controlled oscillator (VCO) 15 connected in sequence, but also includes a fractional divider (DIVN) 16 and a spread-spectrum fractional division control circuit 10. One input terminal of the fractional divider (DIVN) 16 is coupled to the output terminal of the voltage-controlled oscillator 15, and the other input terminal is coupled to the output terminal of the spread-spectrum fractional division control circuit 10.

[0046] Among them, the prescaler 11 prescales an externally input input clock (whose frequency is F clk_in)(Perform frequency division processing to generate a reference clock (not shown), whose frequency is the reference frequency F ref , and this reference clock is fed into the frequency discriminator and phase detector 12.

[0047] The frequency discriminator and phase detector 12 is used to generate a charge and discharge signal (not shown) with a phase difference based on the reference clock (whose frequency is F ref ) output by the prescaler 11 and the feedback clock CLK_DIV fed back by the fractional divider (DIVN) 16.

[0048] The charge pump 13 is used to generate a corresponding bias current based on the control of the charge and discharge signal output by the frequency discriminator and phase detector 12.

[0049] The low-pass filter 14 is used to generate a corresponding control voltage (not shown) based on the bias current provided by the charge pump 13.

[0050] The voltage-controlled oscillator 15 is used to generate a corresponding clock (whose frequency is Fvco) based on the control voltage output by the low-pass filter 14.

[0051] The spread-spectrum fractional division control circuit 10 can enter corresponding working modes (such as only integer division mode, fractional division mode without superimposed spread spectrum, center spread spectrum mode of integer division or downward spread spectrum mode of integer division, center spread spectrum mode of superimposed fractional division or downward spread spectrum mode of superimposed fractional division, etc.) based on the configuration of corresponding control signals (including fractional division control signal MFN[n:0], integer division control signal MFI[m:0], enable signal PLLFRAEN, spread spectrum mode control signal SSCGBYP, spread spectrum direction control signal SPREADCTL, etc.), and based on these control signals and the feedback clock CLK_DIV output by the fractional divider 16, dynamically change the second division control signal MFIS[m:0] generated and output by it, so that the average division ratio of the fractional divider 16 is a preset fractional value.

[0052] The fractional divider 16 is used to divide the clock (whose frequency is Fvco) output by the voltage-controlled oscillator 15 based on the second division control signal MFIS[m:0] output by the spread-spectrum fractional division control circuit 10, and then feedback and output the feedback clock CLK_DIV, where m and n are both integers, and m can be equal to (n + 1) / 2 or any other appropriate value. The desired frequency of the feedback clock CLK_DIV is equal to the phase detection frequency F pfd (which is equal to F ref ). The frequency F ref (i.e., the reference frequency) of the reference clock is as follows: F ref= F clk_in / DIVM.

[0053] Among them, DIVM is the frequency division coefficient of the prescaler 11.

[0054] After the fractional-N PLL is started, the frequency of the feedback clock CLK_DIV gradually approaches the frequency F of the reference clock ref until it is locked. The feedback clock CLK_DIV is used as the reference clock for fractional frequency division and spread spectrum and is provided to the spread spectrum fractional frequency division control circuit 10.

[0055] The output of the frequency discriminator and phase detector 12 is effectively filtered by the low-pass filter 14 to remove phase spurs, and then the control voltage of the voltage-controlled oscillator 15 is adjusted, so that the output frequency F of the voltage-controlled oscillator 15 pll_VCO is locked to the desired frequency point.

[0056] In addition, when the output frequency F of the voltage-controlled oscillator 15 pll_VCO is exactly at the n±(b / A) multiple frequency point of the phase detection frequency F of the frequency discriminator and phase detector 12 pfd (which is equal to F ref ), the spurious frequency is closest to the main signal, and the frequency difference between the two is very small (for example, only 1 / M 3 F pfd ), which usually cannot be filtered by the low-pass filter 14. At this time, the voltage-controlled oscillator 15 may be affected by the strongest fractional spurious interference. In addition, due to the high operating frequency and short period of the fractional-N PLL, it is more likely to become an electromagnetic interference source.

[0057] In this embodiment, in order to effectively suppress the electromagnetic interference of the fractional-N PLL, the spread spectrum fractional frequency division control circuit 10 spreads the spectrum of the feedback clock CLK_DIV of the fractional frequency divider and superimposes the spread spectrum function, thereby dynamically changing the frequency division ratio of the fractional frequency divider 16, so that the average value of the frequency division ratio of the fractional frequency divider 16 is a preset fractional value, and conflicts in the frequency division ratio in the two modes of the fractional frequency division mode and the spread spectrum mode are avoided.

[0058] Please refer to Figure 2 , in one example, the spread spectrum fractional frequency division control circuit 10 includes a pseudo-random sequence generator 100, a spread spectrum circuit 101, a signal modulator 104, and a frequency division control signal output circuit 105. In other examples, if necessary, the spread spectrum fractional frequency division control circuit 10 can also omit the setting of the pseudo-random sequence generator 100.

[0059] Among them, the pseudo-random sequence generator 100 is used to generate and output a pseudo-random sequence PRBS. The pseudo-random sequence PRBS has a "random" characteristic, and the cycle length can be related to the number of bits of the pseudo-random sequence generator 100 (also referred to as the "order of the pseudo-random sequence generator 100"). The larger the number of bits, the larger the cycle length of the pseudo-random sequence PRBS. Within each cycle, the binary numbers "0" and "1" in the pseudo-random sequence PRBS bit stream output by the pseudo-random sequence generator 100 are randomly distributed, and the number of "0" and "1" is equal. Its spectral characteristics are very close to white noise. Adding the pseudo-random sequence 100 can enable the spread-spectrum fractional frequency division control circuit 10 to better spread the quantization noise evenly to a higher frequency band, improve the signal-to-noise ratio, and at the same time reduce the influence of quantization error. Optionally, the pseudo-random sequence generator 100 is a 32-bit linear feedback shift register, which can generate the pseudo-random sequence PRBS through exclusive OR operations and other methods.

[0060] The spread spectrum circuit 101 is coupled to an n + 1-bit fractional division control signal MFN[n:0] and a pseudo-random sequence generator 100, and is used to superimpose the n + 1-bit fractional division control signal MFN[n:0] and the pseudo-random sequence generator 100 in a corresponding spread spectrum mode to obtain a second superimposed result (not shown), and further superimpose the second superimposed result with a corresponding triangular wave signal TEMP to obtain a first superimposed result (not shown), and perform corresponding processing on the first superimposed result according to the spread spectrum mode to obtain an n + 1-bit first division control signal OUT[(n + k):0], where n≥0, k≥2 and both n and k are integers. Among them, in the non-spread spectrum mode, no triangular wave signal TEMP is superimposed on the second superimposed result (that is, in this case, the triangular wave signal TEMP can be regarded as always equal to 0), and in the non-spread spectrum mode and different spread spectrum modes (where the spread spectrum directions of different spread spectrum modes are different, such as the center spread spectrum mode and the downward spread spectrum mode), the spread spectrum circuit 101 can use any suitable method to perform corresponding processing on the first superimposed result, and in the non-spread spectrum mode and different spread spectrum modes, the processing performed by the spread spectrum circuit 101 on the first superimposed result is different from each other. Among them, the non-spread spectrum mode and the spread spectrum mode can be determined by the enable signal PLLFRAEN connected to the spread spectrum circuit 101. For example, when PLLFRAEN = 0 (that is, the enable signal is at a low level), the spread spectrum circuit 101 operates in the non-spread spectrum mode, and the non-spread spectrum mode can be only the integer division mode (that is, the integer division mode without superimposed spread spectrum), or the fractional division mode without superimposed spread spectrum (that is, only the fractional division mode). When PLLFRAEN = 1 (that is, the enable signal is at a high level), the spread spectrum circuit 101 operates in the spread spectrum mode, and the spread spectrum mode can be the spread spectrum mode of only integer division (that is, the integer division mode with superimposed spread spectrum), or the spread spectrum mode of superimposed fractional division (also known as the "spread spectrum mode of superimposed fractional division"), and the spread spectrum mode of superimposed fractional division can be the spread spectrum mode with an integer part equal to 0 (that is, the integer division control signal MFI[m:0] = 0), or the spread spectrum mode with an integer part not equal to 0 (that is, MFI[m:0]≠0).

[0061] Optionally, please refer to Figure 3 , the spread spectrum circuit 101 subtracts different first subtraction values from the first superimposed result in the non-spread spectrum mode and different spread spectrum modes to achieve different processing in the non-spread spectrum mode and different spread spectrum modes. And the first subtraction value is configured by the second register 1013 or calculated according to the register configuration values of MODSTEP and MODCNT. MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the spread spectrum modulation step number configured by the register.

[0062] Please refer to Figure 3, in one example, in the non-spread spectrum mode (for example, when the configuration enables the signal PLLFRAEN = 0, and the spread spectrum mode control signal SSCGBYP = x, where x represents any level state among 0, 1, or other states; or when PLLFRAEN = 1 and the spread spectrum mode control signal SSCGBY = 1), the first decrement value is equal to 0; in the center spread spectrum mode (for example, when PLLFRAEN = 1, SSCGBYP = 0, and the spread spectrum direction control signal SPREADCTL = 0), the first decrement value is equal to MODSTEP * MODCNT / 2, and in the down spread spectrum mode (for example, when PLLFRAEN = 1, SSCGBYP = 0, and SPREADCTL = 1), the first decrement value is equal to MODSTEP * MODCNT.

[0063] In one example, please refer to Figure 3 , the spread spectrum circuit 101 includes a first accumulator U1, a triangular wave generator 1011, a second accumulator U2, a second register 1013, and a subtractor U3.

[0064] Among them, one input terminal of the first accumulator U1 is coupled to the (n + 1)-bit fractional division control signal MFN[n:0], and the other input terminal is coupled to the output terminal of the pseudo-random sequence generator 100. The first accumulator U1 is used to superimpose the (n + 1)-bit fractional division control signal MFN[n:0] and the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100 to obtain a second superimposed result (i.e., the fractional division control signal superimposed with the pseudo-random sequence), and provide the second superimposed result to one input terminal of the second accumulator U2.

[0065] The triangular wave generator 1011 is coupled to the spread spectrum mode control signal SSCGBY and the feedback clock CLK_DIV output by the fractional divider 16, and is used to generate and output a triangular wave signal TEMP corresponding to the (n + 1)-bit fractional division control signal MFN[n:0] based on the feedback clock CLK_DIV in the spread spectrum mode (for example, when PLLFRAEN = 1 and SSCGBY = 0), and output TEMP = 0 in the non-spread spectrum mode (for example, when PLLFRAEN = 0 and SSCGBY = x, or when PLLFRAEN = 1 and SSCGBY = 1). Among them, in the spread spectrum mode (for example, when PLLFRAEN = 1 and SSCGBY = 0), the triangular wave generator 1011 can use the feedback clock CLK_DIV output by the fractional divider 16 as the reference clock and start from an initial value of 0 to generate the triangular wave signal TEMP. Please refer to Figures 1 to 3 , and the specific principle is as follows: The initial value of the triangular wave signal TEMP is 0. Taking the feedback clock CLK_DIV as the reference clock, according to the spread spectrum modulation step MODSTEP configured by the register, when the rising edge of each clock cycle of the feedback clock CLK_DIV arrives, TEMP increments by one MODSTEP, and the number of increment steps is the spread spectrum modulation step number MODCNT configured by the register, until the maximum value MODSTEP * MODCNT that TEMP increments to. After that, when the rising edge of each clock cycle of the feedback clock CLK_DIV arrives, it starts to decrement by one MODSTEP until TEMP decrements back to the initial value 0. The process of incrementing from 0 to the maximum MODSTEP * MODCNT and then decrementing back to 0 forms a cycle of the triangular wave signal TEMP.

[0066] The first input terminal of the second accumulator U2 is coupled to the output terminal of the triangular wave generator 1011, and the second input terminal is coupled to the output terminal of the first accumulator U1 (i.e., coupled to the fractional frequency division control signal MFN[n:0] of the second superposition result of n + 1 bits). The second accumulator U2 is used to superpose the triangular wave signal TEMP output by the triangular wave generator 1011 and the output of the first accumulator U1 (i.e., the fractional frequency division control signal MFN[n:0] of n + 1 bits after superposing the pseudo-random sequence PRBS) to output the first superposition result.

[0067] Based on this, the first superposition result output by the second accumulator U2 in this spread spectrum mode (such as the center spread spectrum mode or the down spread spectrum mode) is also a triangular wave signal, whose initial value is equal to the fractional frequency division control signal MFN[n:0] of n + 1 bits, and this first superposition result increments by MODSTEP in each clock cycle of the feedback clock CLK_DIV fed back by the fractional frequency divider 16 until the maximum value MFN[n:0] + MODSTEP * MODCNT, and the number of increment steps is MODCNT. After that, this first superposition result decrements by MODSTEP in each clock cycle of this feedback clock CLK_DIV until it decrements back to the fractional frequency division control signal MFN[n:0] of n + 1 bits, and the number of decrement steps is also MODCNT. Among them, MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the spread spectrum modulation step number configured by the register.

[0068] That is to say, when the fractional frequency division phase-locked loop of this embodiment operates in the corresponding spread spectrum mode (such as configuring PLLFRAEN = 1 and SSCGBY = 0), its spread spectrum modulation frequency and modulation depth are configured by MODSTEP and MODCNT.

[0069] One input terminal of the subtractor U3 is coupled to the output terminal of the second accumulator U2, and the other input terminal is coupled to the second register 1013. The second register 1013 may be a register bank, which is coupled to the spread spectrum mode control signal SSCGBY and the spread spectrum direction control signal SPREADCTL. The second register 1013 is used to configure the first subtraction value required in the current spread spectrum mode. The subtractor U3 is used to subtract the output of the second accumulator U2 from the first subtraction value configured in the second register 1013 to output the first frequency division control signal OUT[(n + k):0]. Among them, the first subtraction values configured by the second register 1013 in the non-spread spectrum mode and different spread spectrum modes are different from each other.

[0070] In one example, in the non-spread spectrum mode (for example, when PLLFRAEN = 1 and SSCGBY = 1 are configured), the first subtraction value configured by the second register 1013 is equal to 0. In the center spread spectrum mode (for example, when PLLFRAEN = 1, SSCGBY = 0, and SPREADCTL = 0 are configured), the first subtraction value configured by the second register 1013 is equal to MODSTEP * MODCNT / 2; in the down spread spectrum mode (for example, when PLLFRAEN = 1, SSCGBY = 0, and SPREADCTL = 1 are configured), the first subtraction value configured by the second register 1013 is equal to MODSTEP * MODCNT, where MODCNT is the number of spread spectrum modulation steps configured by the register, and MODSTEP is the spread spectrum modulation step size configured by the register.

[0071] Optionally, the register configuration value of MODCNT is calculated according to the modulation frequency f MOD in the current spread spectrum mode and the frequency F ref of the reference clock. The register configuration value of MODSTEP is calculated according to the modulation depth MD in the current spread spectrum mode, the n + 1-bit fractional frequency division control signal MFN[n:0], and the corresponding m + 1-bit integer frequency division control signal MFI[m:0], specifically as follows: MODCNT = F clk_in / (DIVM * 2 * fMOD); MODSTEP = MD * LDF * 2 n+1 / (100 * MODCNT); where m ≥ 0 and is an integer, F clk_in is the frequency of the input clock externally input to the fractional frequency division phase-locked loop, f MOD is the spread spectrum modulation frequency, DIVM is the frequency division coefficient of the prescaler 11, MD is the percentage of the spread spectrum modulation depth, LDF is the frequency division ratio of the fractional frequency division, and there is: LDF = MFN + MFI / 2 n+1 ; Fref = Fclk_in / DIVM。

[0072] Please refer to Figure 2 and Figure 3 such that control signals such as the enable signal PLLFRAEN, the spread spectrum mode control signal SSCGBYP, the spread spectrum direction control signal SPREADCT, the (n + 1)-bit fractional division control signal MFN[n:0], and the integer division control signal MFI[m:0] can be configured through corresponding configuration registers respectively. Among them, the (n + 1)-bit fractional division control signal MFN[n:0] can be provided by an (n + 1)-bit fractional division configuration register.

[0073] Through the configuration of the enable signal PLLFRAEN, the spread spectrum mode control signal SSCGBYP, the spread spectrum direction control signal SPREADCT, the (n + 1)-bit fractional division control signal MFN[n:0], and the integer division control signal MFI[m:0] (where m ≥ 0 and is an integer), the spread spectrum fractional division control circuit 10 of this embodiment can provide the following operating modes: (1) Integer-only mode: MFI[m:0] ≠ 0, MFN[n:0] = 0, PLLFRAEN = 0 (i.e., PLLFRAEN is at the first level), SSCGBYP = x (x represents 0 or 1 or other states, i.e., SSCGBYP is at the second level or the first level or other levels), that is, as long as PLLFRAEN is at the first level, regardless of the state of SSCGBYP, it enters the integer-only mode (i.e., for example, when PLLFRAEN = 0, the entire fractional division and spread spectrum link is turned off). This mode is a type of non-spread spectrum mode, an integer division mode without superimposed spread spectrum, and in this mode, TEMP = 0 continuously (i.e., the triangular wave generator 1011 does not output a triangular wave signal); (2) Non-Frequency modulation Fractional mode (i.e., fractional division only mode): PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level) and SSCGBYP = 1 (i.e., SSCGBYP is at the second level). This mode is also a non-spread spectrum mode, where the fractional division control signal MFN[n:0] ≠ 0, and the integer part MFI[m:0] can be equal to 0 (in this case, the fractional division mode does not have the superimposed integer division function), or can be not equal to 0 (in this case, the fractional division mode only has the superimposed integer division function); (3) Frequency modulation mode: When PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), and the spread spectrum direction control signal SPREADCT = 0 (i.e., at the first level), it is center spread spectrum; when the spread spectrum direction control signal SPREADCT = 1 (i.e., at the second level), it is down spread spectrum. Among them, this spread spectrum mode can be further divided according to the fractional division control signal MFN[n:0] and the spread spectrum direction control signal SPREADCT as follows: (3-1) Center Spread Spectrum modulation integer mode: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 0 (i.e., SPREADCT is at the first level), and MFN[n:0] = 0.

[0074] (3-2) Down Spread Spectrum modulation integer mode: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 1 (i.e., SPREADCT is at the second level), and MFN[n:0] = 0.

[0075] (3-3) Center Spread Spectrum modulation Fractional mode: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 0 (i.e., SPREADCT is at the first level), and MFN[n:0] ≠ 0.

[0076] (3-4) Down Spread Spectrum modulation Fractional mode: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 1 (i.e., SPREADCT is at the second level), and MFN[n:0] ≠ 0.

[0077] It should be noted that in the two spread-spectrum modes of superposition of fractional frequency division (3-3) and (3-4), the integer part MFI[m:0] can be equal to 0 (in this case, only the fractional frequency division function is superimposed, and the integer frequency division function is not superimposed), or it can be not equal to 0 (in this case, both the integer frequency division and fractional frequency division functions are superimposed).

[0078] Please refer to Figures 1 to 5 , when the spread-spectrum fractional frequency division control circuit 10 operates in the integer frequency division mode, the clock frequency F pll_VCO output by the voltage-controlled oscillator 15 is: F pll_VCO =(F clk_in / DIVM)*MFI; When the spread-spectrum fractional frequency division control circuit 10 operates in the fractional frequency division mode (which can be the above (2) mode, (3-3) mode or (3-4) mode), the clock frequency F pll_VCO output to the voltage-controlled oscillator 15 is: F pll_VCO =(F clk_in / DIVM)*[MFI+(MFN+0.5) / 2 n+1 .

[0079] Among them, F clk_in is the frequency of the externally input clock (i.e., the input source clock), MFN is the fractional frequency division control signal of n + 1 bits, DIVM is the division coefficient of the prescaler 11, and MFI is the integer frequency division control signal of m + 1 bits.

[0080] One input end of the signal modulator 104 is coupled to the output end of the spread-spectrum circuit 101. The signal modulator 104 is used to modulate and shape the n + 1-bit first frequency division control signal OUT[n:0] output by the spread-spectrum circuit 101. Among them, the signal modulator 104 can be implemented by any suitable circuit design.

[0081] Optionally, the signal modulator 104 is a third-order SDM modulator (Sigma-Delta Modulator) using the MASH structure, which can also be written as Σ (Sigma)-Δ (Delta) modulator or Δ-Σ modulator. The MASH structure includes but is not limited to MASH1-1 structure, MASH2-1 structure, MASH1-1-1 structure. Among them, the SDM modulator is a modulator that improves the signal resolution through oversampling and noise shaping techniques. Its basic principle generally includes oversampling, noise shaping based on the feedback loop, and digital filtering and decimation.

[0082] In one example, please refer to Figure 6, the signal modulator 104 adopts a third-order MASH 1-1-1 structure and includes first to third-stage accumulators M1 to M3, delayers 1041 to 1043, a delay chain 1044, delayers 1045 to 1047, and accumulators U6 to U7. Each stage of the accumulator has an accumulation output terminal, a carry output terminal, and two input terminals.

[0083] Among them, the accumulation output terminal of the first-stage accumulator M1 is coupled to an input terminal of the second-stage accumulator M2 and an input terminal of the first-stage accumulator M1 through the delayer 1041. The other input terminal of the first-stage accumulator M1 is coupled to the (n + 1)-bit first frequency division control signal OUT[n:0] output by the frequency spreading circuit 101. The carry output terminal of the first-stage accumulator M1 is coupled to the input terminal of the delay chain 1044. The output terminal of the delay chain 1044 is coupled to an input terminal of the accumulator U7, and the delay chain 1044 is also coupled to the feedback clock CLK_DIV. The delay chain 1044 is used to delay the carry C0 output from the carry output terminal of the first-stage accumulator M1 with the feedback clock CLK_DIV as the reference clock, for example, to perform a two-beat delay, and the output terminal of the delay chain 1044 outputs the delayed carry C0D2. The delayer 1041 is also coupled to the feedback clock CLK_DIV, and the delayer 1041 is used to delay the output of the accumulation output terminal of the first-stage accumulator M1 with the feedback clock CLK_DIV as the reference clock. Among them, the output value of the accumulation output terminal of the first-stage accumulator M1 is the added value of the output value delayed by the delayer 1041 and OUT[n:0]. If the added value overflows, the first-stage accumulator M1 performs a carry C0 output operation.

[0084] The accumulation output terminal of the second-stage accumulator M2 is coupled to an input terminal of the third-stage accumulator M3 and the other input terminal of the second-stage accumulator M2 through the delayer 1042. The carry output terminal of the second-stage accumulator M2 is coupled to the input terminal of the delayer 1045. The output terminal of the delayer 1045 is coupled to an input terminal of the accumulator U6, and the delayer 1045 is also coupled to the feedback clock CLK_DIV. The delayer 1045 is used to delay the carry C1 output from the carry output terminal of the second-stage accumulator M2 with the feedback clock CLK_DIV as the reference clock, for example, to perform a one-beat delay. The output terminal of the delayer 1045 outputs the delayed carry C1D1. The delayer 1042 is also coupled to the feedback clock CLK_DIV, and the delayer 1042 is used to delay the output of the accumulation output terminal of the second-stage accumulator M2 with the feedback clock CLK_DIV as the reference clock. Among them, the output value of the accumulation output terminal of the second-stage accumulator M2 is the added value of the output value delayed by the delayer 1042 and the output value of the accumulation output terminal of the first-stage accumulator M1. If the added value overflows, the second-stage accumulator M2 performs a carry C1 output operation.

[0085] The accumulative output terminal of the third-level accumulator M3 is coupled to the input terminal of the delay device 1043, and the output terminal of the delay device 1043 is coupled to another input terminal of the third-level accumulator M3. The carry output terminal of the third-level accumulator M3 is coupled to the input terminal of the delay device 1046, and the output terminal of the delay device 1046 is coupled to another input terminal of the accumulator U6. The delay device 1043 is also coupled to the feedback clock CLK_DIV. The delay device 1043 is used to delay the output of the accumulative output terminal of the third-level accumulator M3 with the feedback clock CLK_DIV as the reference clock. Among them, the output value of the accumulative output terminal of the third-level accumulator M3 is the added value of the output value after being delayed by the delay device 1043 and the output value of the accumulative output terminal of the second-level accumulator M2. If the added value overflows, the third-level accumulator M3 performs a carry C2 output operation.

[0086] In addition, the delay devices 1041 to 1043, the delay chain 1044, and the delay devices 1045 to 1047 can be implemented by any suitable circuit design. For example, the delay devices 1041 to 1043 are all implemented by using n + 1-bit (bit) registers, the delay chain 1044 is implemented by using cascaded 1-bit registers 1044a and 1044b, and the delay device 1045 is implemented by using the 1-bit register 1044a.

[0087] Please refer to Figure 7 , the delay devices 1046 and 1047 are both composed of a register 104a and a subtractor 104b. The register 104a is also coupled to the feedback clock CLK_DIV, and delays the signal received by the register 104a with the feedback clock CLK_DIV as the reference clock (it can also be said to "delay one beat"). One input terminal of the subtractor 104b is coupled to the output terminal of the register 104a, and the other input terminal is coupled to the signal received by the register 104a, and then subtracts the input of the register 104a from the output of the register 104a.

[0088] From Figure 6 as shown, the signal modulator 104 outputs OUTSD[n:0]=C2 - C2D1 + C1D1 - C2D1 + C2D2 - C1D2 + C0D2. When n = 13, the result has 8 different values [-3, -2, -1, 0, 1, 2, 3, 4].

[0089] Please combine Figure 1 and Figure 2, the frequency division control signal output circuit 105 is coupled to the signal modulator 104 and the fractional divider (DIVN) 16 in the fractional-N phase-locked loop (PLL). The frequency division control signal output circuit 105 is configured to superimpose the output OUTSD[n:0] of the signal modulator 104 and the corresponding integer frequency division control signal MFI[m:0], so as to output the second frequency division control signal MFIS[m:0] after integer frequency division superposition to the fractional divider 16. The fractional divider 16 is configured to divide the clock (whose frequency is Fvco) output by the voltage-controlled oscillator 15 based on the second frequency division control signal MFIS[m:0] output by the frequency division control signal output circuit 105.

[0090] In one example, please refer to Figure 8 , the frequency division control signal output circuit 105 includes a fourth accumulator U5 and an output register 1052. One input terminal of the fourth accumulator U5 is coupled to the output terminal of the signal modulator 104, and the other input terminal of the fourth accumulator U5 is coupled to the integer frequency division control signal MFI[m:0]. The fourth accumulator U5 is configured to superimpose the output OUTSD[n:0] of the signal modulator 104 and the integer frequency division control signal MFI[m:0]. The input terminal of the output register 1052 is coupled to the output terminal of the fourth accumulator U5. The output register 1052 is also coupled to the feedback clock CLK_DIV, and is configured to perform clock synchronization on the output of the fourth accumulator U5 and the feedback clock CLK_DIV, so as to output the second frequency division control signal MFIS[m:0] after integer frequency division superposition.

[0091] In the above embodiments, n, k, and m can be any suitable values respectively. Please refer to Figures 1 to 8 , in one example, n = 13, k = 2, m = 7. The working principle of the spread-spectrum fractional frequency division control circuit 10 in this example is as follows: First, the triangular wave generator 1011 in the spread-spectrum circuit 101 uses 0 as the initial value and uses the feedback clock CLK_DIV as the reference clock. In a cycle in the spread-spectrum mode with fractional frequency division (for example, configuring PLLFRAEN = 1, SSCGBY = 0), at the rising edge of each cycle of CLK_DIV, it increments by a step MODSTE, and the number of increment steps is MODCNT, gradually increasing to the maximum value MODSTEP * MODCNT, and then at the rising edge of each cycle of CLK_DIV, it decrements by a step MODSTEP until it decrements back to 0, thereby generating the triangular wave TEMP[13:0]. At the same time, the first accumulator U1 in the spread-spectrum circuit 101 superimposes MFN[13:0] and the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100.

[0092] Next, the second accumulator U2 in the frequency spreading circuit 101 superimposes the triangular wave TEMP and the MFN[13:0] after superimposing the pseudo-random sequence PRBS to generate a first superimposed result, which is a triangular wave signal. Taking the feedback clock CLK_DIV as the reference clock, in the frequency spreading mode of fractional frequency division (for example, configuring PLLFRAEN = 1 and SSCGBY = 0), it increments by a step MODSTE at the rising edge of each cycle of CLK_DIV, and the number of increment steps is MODCNT, gradually increasing to the maximum value MFN[13:0] + MODSTEP * MODCNT, and then decrementing by a step MODSTEP at the rising edge of each cycle of CLK_DIV until it decrements back to MFN[13:0].

[0093] The subtractor U3 in the frequency spreading circuit 101 further subtracts the first subtraction value configured in the second register 1013. Among them, in the center frequency spreading mode, the first subtraction value configured in the second register 1013 is 1 / 2 * MODCNT * MODSTEP, and if it is the downward frequency spreading mode, the first subtraction value configured in the second register 1013 is MODSTEP * MODCNT.

[0094] Next, the 13-bit first frequency division control signal OUT[13:0] output by the frequency spreading circuit 101 is modulated and shaped by the signal modulator 104 and output as OUTSD[13:0], thereby spreading the quantization noise to a higher frequency band, so that the fractional frequency division phase-locked loop can filter out the high-frequency noise through its low-pass filter; Then, the frequency division control signal output circuit 105 adds the output OUTSD[13:0] of the signal modulator 104 and the integer frequency division control signal MFI[7:0]. After the result is synchronized by the clock of the output register 1052, the second frequency division control signal MFIS[7:0] is obtained. The MFIS[7:0] is provided to the fractional frequency divider 16 in the fractional frequency division phase-locked loop. The fractional frequency divider 16 performs fractional frequency division on the clock output by the voltage-controlled oscillator 15 based on MFIS[7:0] to obtain the feedback clock CLK_DIV, and finally makes the frequency of the feedback clock CLK_DIV reach the reference frequency F provided by the prescaler 11 ref , realizing the locking of the fractional frequency division phase-locked loop.

[0095] Accordingly, for the spread-spectrum fractional-N control circuit provided in this embodiment and the fractional-N phase-locked loop having the spread-spectrum fractional-N control circuit, the spread-spectrum circuit can superimpose an (n + 1)-bit fractional-N control signal and a corresponding triangular wave signal in a corresponding spread-spectrum mode, and perform corresponding processing on the superimposed result according to the spread-spectrum mode to obtain a corresponding first frequency division control signal. Moreover, the processing of the first superimposed result by the spread-spectrum circuit is different in the non-spread-spectrum mode and different spread-spectrum modes. The first frequency division control signal is output as a second frequency division control signal by the frequency division control signal output circuit after being modulated and shaped by the signal modulator, and then the fractional-N divider divides the corresponding clock based on the second frequency division control signal. Accordingly, it can support the non-spread-spectrum mode and different spread-spectrum modes (including multiple different center spread-spectrum modes / down spread-spectrum modes), can avoid the problem of downward or upward distortion caused by a large spread-spectrum modulation amplitude when the fractional-N ratio is close to 0 or close to 1, and can effectively reduce spurs by using noise shaping technology, enabling the fractional-N phase-locked loop to achieve good phase noise performance while achieving high frequency and high resolution. In addition, the register configuration values of the spread-spectrum modulation step MODSTEP and the spread-spectrum modulation step count MODCNT can be calculated and configured according to the actual requirements through the spread-spectrum modulation frequency and modulation amplitude, thereby providing a high flexible configuration ability and a wide application range.

[0096] In addition, in an example of this embodiment, please refer to Figure 2 , the enable signal PLLFRAEN can be provided to the pseudo-random sequence generator 100, the spread-spectrum circuit 101, and the signal modulator 104 in the spread-spectrum fractional-N control circuit 10 of this embodiment to control the enabling of these circuits. Accordingly, when PLLFRAEN = 0, the entire fractional-N and spread-spectrum link in the spread-spectrum fractional-N control circuit 10 is turned off to reduce the circuit power consumption in the integer-N-only mode.

[0097] In other examples of this embodiment, on the basis that the spread-spectrum fractional-N control circuit can use PLLFRAEN, SSCGBYP, SPREADCT, MFN[n:0], and MFI[m:0] to implement the required operating mode, PLLFRAEN can also not be input to some links of the fractional-N and spread-spectrum in the spread-spectrum fractional-N control circuit 10, for example, not input to at least one of the pseudo-random sequence generator 100 and the spread-spectrum circuit 101. Accordingly, when PLLFRAEN = 0, only some links of the fractional-N and spread-spectrum in the spread-spectrum fractional-N control circuit 10 (including the signal modulator 104) are turned off.

[0098] Based on the same inventive concept, this embodiment also provides a chip, which includes the fractional-N PLL and internal circuitry as described in this embodiment. The clock input terminal of the internal circuitry is coupled to the output terminal of the voltage-controlled oscillator of the fractional-N PLL, and the fractional-N PLL provides a clock with low spurious rate for the internal circuitry.

[0099] Since the chip integrates the fractional-N PLL of the present invention, it can effectively resist the serious problem of external electromagnetic interference.

[0100] Second Embodiment Please refer to Figures 1 to 9 It should be understood that in the above embodiment, the OUTSD[n:0] output after noise shaping by the signal modulator 104 is added to the integer division control signal MFI[m:0]. The accuracy of the fractional division is n + 1 bits (bit), and the accuracy of each accumulator M1 to M3 in the signal modulator 104 is also n + 1 bits. When the fractional-N PLL operates in the fractional division mode without the spread spectrum function (for example, configuring PLLFRAEN = 1, SSCGBY = 1), the integer plus fractional division coefficient of the fractional-N PLL can be denoted as "DIVN~DIVN + 1". Therefore, when MFN[n:0] is full, it is equivalent to adding 1 to the integer division coefficient of the fractional-N PLL; and when the fractional-N PLL operates in the spread spectrum mode with superimposed fractional division (for example, configuring PLLFRAEN = 1 and SSCGBY = 0), the spread spectrum modulation amplitudes MODSTEP*MODCNT of the center spread spectrum and the downward spread spectrum are at most n + 1 bits. In this case, the accumulators M1, etc. in the signal modulator 104 may overflow.

[0101] To avoid the problem of overflow of the accumulator in the signal modulator 104, this embodiment provides a spread spectrum fractional division control circuit 10 and a fractional-N PLL having the spread spectrum fractional division control circuit 10. Compared with the first embodiment, the spread spectrum circuit 101 of the spread spectrum fractional division control circuit 10 in this embodiment is more used to extend the number of bits of the result of processing its first superimposed result by k bits in the current spread spectrum mode, so as to output a first division control signal OUT[(n + k):0] with n + k + 1 bits. And the spread spectrum fractional division control circuit 10 separates the high k-bit signal OUT[(n + k):(n + 1)] in OUT[(n + k):0], which does not participate in the modulation and shaping of the signal modulator 104, but is added to OUTSD[n:0] processed by the signal modulator 104 in OUT[(n + k):0] after corresponding delay, so as to obtain the corresponding second division control signal. Where n≥0, k≥2 and both n and k are integers.

[0102] Please refer to Figure 1, the basic architecture of the fractional-N PLL in this embodiment is the same as that in the first embodiment, and it includes not only a prescaler (DIVM, also known as "front-end prescaler") 11, a phase frequency detector (PFD) 12, a charge pump (CHP) 13, a low-pass filter (LPF, also known as "loop filter") 14, and a voltage-controlled oscillator (VCO) 15 connected in sequence, but also a fractional divider (DIVN) 16 and a spread-spectrum fractional-divider control circuit 10. One input terminal of the fractional divider (DIVN) 16 is coupled to the output terminal of the voltage-controlled oscillator 15, and the other input terminal is coupled to the output terminal of the spread-spectrum fractional-divider control circuit 10. Among them, the connection relationship and functions among the various modules in this fractional-N PLL are basically the same as those in the first embodiment, which can be referred to the relevant content above and will not be elaborated here.

[0103] Therefore, the technical solution of this embodiment spreads the spectrum of the feedback clock CLK_DIV of the fractional divider through the spread-spectrum fractional-divider control circuit 10, and superimposes the spread-spectrum function, thereby dynamically changing the division ratio of the fractional divider 16, so that the average value of the division ratio of the fractional divider 16 is a preset fractional value, and conflicts in the division ratios in the two modes of the fractional division mode and the spread-spectrum mode and data overflow in the accumulator in the signal modulator are avoided, so as to effectively suppress the electromagnetic interference of the fractional-N PLL.

[0104] Please refer to Figure 10 , in an example of this embodiment, the spread-spectrum fractional-divider control circuit 10 includes a pseudo-random sequence generator 100, a spread-spectrum circuit 101, a signal separation circuit 102, a high-k-bit delay circuit 103, a signal modulator 104, and a division control signal output circuit 105. In other examples, according to actual needs, the setting of the pseudo-random sequence generator 100 can be omitted in the spread-spectrum fractional-divider control circuit 10.

[0105] Among them, the pseudo-random sequence generator 100 is used to generate and output a pseudo-random sequence PRBS. The spread-spectrum circuit 101 is coupled to the (n + 1)-bit fractional-divider control signal MFN[n:0] and the pseudo-random sequence generator 100, and is used to superimpose the (n + 1)-bit fractional-divider control signal MFN[n:0] with the corresponding triangular wave signal TEMP in the corresponding spread-spectrum mode to obtain a second superimposed result, and extend the number of bits of the second superimposed result by k bits to obtain an (n + k + 1)-bit first division control signal OUT[(n + k):0], where n≥0, k≥2 and both n and k are integers.

[0106] Optionally, please refer to Figure 10 , the spread-spectrum circuit 101 includes a first accumulator U1, a triangular wave generator 1011, a first register 1012, a second accumulator U2, a second register 1013, and a subtractor U3.

[0107] Among them, one input terminal of the first accumulator U1 is coupled to the (n + 1)-bit fractional division control signal MFN[n:0], and the other input terminal is coupled to the pseudo-random sequence generator 100. The first accumulator U1 is used to superimpose the (n + 1)-bit fractional division control signal MFN[n:0] and the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100 to obtain a second superimposed result, and provide the second superimposed result to one input terminal of the second accumulator U2.

[0108] The triangular wave generator 1011 is coupled to the spread spectrum mode control signal SSCGBY, and is used to generate and output a triangular wave signal TEMP corresponding to the (n + 1)-bit fractional division control signal MFN[n:0] in the spread spectrum mode (for example, when PLLFRAEN = 1 and SSCGBY = 0), and output 0 in the non-spread spectrum mode (for example, when PLLFRAEN = 1 and SSCGBY = 1). Among them, the specific principle of the triangular wave generator 1011 to generate the triangular wave signal TEMP in the spread spectrum mode (for example, when PLLFRAEN = 1 and SSCGBY = 0) is the same as that of the first embodiment, and will not be elaborated here. The initial value of the triangular wave signal TEMP is 0. Taking the feedback clock CLK_DIV as the reference clock, when the rising edge of each clock cycle of the feedback clock CLK_DIV arrives, TEMP increments by a step size MODSTEP, and the number of increments is MODCNT. The maximum value that TEMP increments to is MODSTEP * MODCNT. After that, when the rising edge of each clock cycle of the feedback clock CLK_DIV arrives, it starts to decrement by a step size MODSTEP until TEMP decrements back to 0. Among them, the register configuration value of MODCNT is calculated according to the modulation frequency f MOD and the reference clock F ref in the current spread spectrum mode, and the register configuration value of MODSTEP is calculated according to the modulation depth MD, the (n + 1)-bit fractional division control signal MFN[n:0], and the (m + 1)-bit integer division control signal MFI[m:0] in the current spread spectrum mode. The calculation formulas of MODCNT and MODSTEP are the same as those of the first embodiment, and will not be elaborated here.

[0109] The first register 1012 is used to configure an additional value of (n + k + 1) bits, and this additional value is, for example, equal to 2 n+k。The first input terminal of the second accumulator U2 is coupled to the output terminal of the triangular wave generator 1011, the second input terminal is coupled to the output terminal of the first accumulator U1 (i.e., coupled to the (n + 1)-bit fractional division control signal MFN[n:0]), and the third input terminal is coupled to the output terminal of the first register 1012. The second accumulator U2 is used to superimpose the output of the triangular wave generator 1011, the additional value configured in the first register 1012, and the output of the first accumulator U1 (i.e., the (n + 1)-bit fractional division control signal MFN[n:0] after superimposing the pseudo-random sequence PRBS), so as to realize the signal bit number expansion by k bits. Here, the function of the first register 1012 is to expand the bit number of the first superimposed result after superimposing MFN[n:0] and TEMP by k bits (i.e., the total of the spread spectrum and the fractional division code value is expanded by k bits) to prevent data overflow.

[0110] One input terminal of the subtractor U3 is coupled to the output terminal of the second accumulator U2, and the other input terminal is coupled to the second register 1013. The second register 1013 can be a register bank, which is coupled to the spread spectrum mode control signal SSCGBY and the spread spectrum direction control signal SPREADCTL. The second register 1013 is used to configure the first subtraction value required for the current (i.e., non-spread spectrum mode, center spread spectrum mode, or down spread spectrum mode). The subtractor U3 is used to subtract the first subtraction value configured in the second register 1013 from the output of the second accumulator U2 to output the first frequency division control signal OUT[(n + k):0] with (n + k + 1) bits. Among them, the first subtraction value configured by the second register 1013 in the non-spread spectrum mode (for example, configuring PLLFRAEN = 0 or 1, and SSCGBY = 1) is equal to 0, the first subtraction value configured in the center spread spectrum mode (for example, configuring PLLFRAEN = 1, SSCGBY = 0, and SPREADCTL = 0) is equal to MODSTEP * MODCNT / 2, and the first subtraction value configured in the down spread spectrum mode (for example, configuring PLLFRAEN = 1, SSCGBY = 0, and SPREADCTL = 1) is equal to MODSTEP * MODCNT, where MODCNT is the spread spectrum modulation step number configured by the register, and MODSTEP is the spread spectrum modulation step size configured by the register.

[0111] Thus, in this example, the frequency spreading circuit 101 first extends the number of bits of the first superposition result (i.e., the result of superposing the second superposition result and the triangular wave information) by k bits, and then the subtractor U3 processes the signal with the extended number of bits in the corresponding current mode (i.e., subtracts the corresponding first subtraction value). Therefore, compared with the first embodiment, the frequency spreading circuit 101 can achieve the effect of extending the number of bits of the result of processing its first superposition result by k bits. In other embodiments of the present invention, the subtractor U3 and the second register 1013 can also be arranged at the front stage of the first register 1012, and a corresponding accumulator can be additionally provided at the first register 1012, so as to achieve the effect of first subtracting the corresponding first subtraction value from the first superposition result output by the second accumulator U2 (i.e., performing corresponding processing on the first superposition result), and then extending the number of bits of the processed result by k bits.

[0112] In addition, control signals such as the frequency spreading mode control signal SSCGBYP, the frequency spreading direction control signal SPREADCT, the (n + 1)-bit fractional division control signal MFN[n:0], and the integer division control signal MFI[m:0] coupled to the frequency spreading circuit 101 can be configured through the configuration register respectively. Among them, the (n + 1)-bit fractional division control signal MFN[n:0] can be provided by the (n + 1)-bit fractional division configuration register.

[0113] By different configurations of the enable signal PLLFRAEN, the frequency spreading mode control signal SSCGBYP, the frequency spreading direction control signal SPREADCT, the (n + 1)-bit fractional division control signal MFN[n:0], and the integer division control signal MFI[m:0], the frequency spreading fractional division control circuit 10 of this embodiment can provide multiple working modes such as only the integer division mode, the frequency spreading mode of integer division (including center frequency spreading or downward frequency spreading), the fractional division mode without superposition frequency spreading, and the frequency spreading mode of superposed fractional division (including center frequency spreading or downward frequency spreading). The specific situations of PLLFRAEN, SSCGBYP, SPREADCT, MFN[n:0], and MFI[m:0] in these modes are the same as those in the first embodiment, and the relevant content described in the above first embodiment can be referred to and will not be elaborated here.

[0114] Please continue to refer to Figure 10, the input end of the signal separation circuit 102 is coupled to the output end of the frequency spreading circuit 101 (i.e., the output end of the subtractor U3). The signal separation circuit 102 is used to cache or register the first frequency division control signal OUT[(n + k):0] of n + k + 1 bits output by the frequency spreading circuit 101, and separate and output the highest k bit positions and the remaining n + 1 bit positions in the first frequency division control signal OUT[(n + k):0] of n + k + 1 bits, so as to obtain a high k bit position signal OUT[(n + k):(n + 1)] and a low n + 1 bit position signal OUT[n:0]. The signal separation circuit 102 can adopt any suitable circuit design such as a signal decoder or a division and remainder operation circuit, and the present invention does not make specific limitations thereon.

[0115] Please refer to Figure 10 , the input end of the high k bit position delay circuit 103 is coupled to an output end of the signal separation circuit 102. The high k bit position delay circuit 103 is used to delay the high k bit position signal OUT[(n + k):(n + 1)] output by the signal separation circuit 102. The high k bit position delay circuit 103 can adopt any suitable circuit design. Optionally, please refer to Figure 11 , the high k bit position delay circuit 103 includes a delay chain. The delay chain includes at least two cascaded first delay units 103a, and the number of stages of the first delay unit 103a matches the modulation time of the signal modulator 104. In one example, the first delay unit 103a is a k-bit register, which can cache and delay the output of the high k bit position signal OUT[(n + k):(n + 1)] output by the signal separation circuit 102.

[0116] Please continue Figure 10 , one input end of the signal modulator 104 is coupled to another output end of the signal separation circuit 102. The signal modulator 104 is used to modulate and shape the low n + 1 bit position signal OUT[n:0] output by the signal separation circuit 102.

[0117] Among them, the delay time of the high k bit position delay circuit 103 for the high k bit position signal OUT[(n + k):(n + 1)] matches the time taken for the signal modulator 104 to modulate and shape the low n + 1 bit position signal OUT[n:0], so that the delayed high k bit position signal OUTD[(n + k):(n + 1)] output by the high k bit position delay circuit 103 and the modulated low n + 1 bit position signal OUTD[n:0] output by the signal modulator 104 are synchronized. Among them, the signal modulator 104 can be implemented by any suitable circuit design.

[0118] In one example, please refer to Figure 11 and Figure 6, the number of stages of the first delay unit 103a in the high-k bit delay circuit 103 is three, and the signal modulator 104 is a third-order Σ-Δ modulator using the MASH structure, which includes but is not limited to the MASH1-1 structure, the MASH2-1 structure, and the MASH1-1-1 structure. Among them, the third-order MASH1-1-1 structure can adopt the same circuit design as the third-order MASH1-1-1 structure in the first embodiment, which will not be elaborated here.

[0119] As can be seen from Figure 6 shown, the output of the signal modulator 104 is OUTSD[n:0]=C2-C2D1+C1D1-C2D1+C2D2-C1D2+C0D2. When n = 13, its result has 8 different values [-3, -2, -1, 0, 1, 2, 3, 4]. In this case, please further combine Figure 10 , when n = 13 and k = 2, the signal (not marked) obtained by adding the output OUTD[(n + k):(n + 1)] of the high-k bit delay circuit 103 and the output OUTSD[n:0] of the signal modulator 104 in the frequency division control signal output circuit 105 has 11 different values [-3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7].

[0120] Please combine Figure 1 and Figure 10 , the frequency division control signal output circuit 105 is coupled to the high-k bit delay circuit 103, the signal modulator 104, and the fractional divider (DIVN) 16 in the fractional-N phase-locked loop (PLL). The frequency division control signal output circuit 105 is used to superimpose the output OUTD[(n + k):(n + 1)] of the high-k bit delay circuit 103, the output OUTSD[n:0] of the signal modulator 104, and the corresponding integer frequency division control signal MFI[m:0] to output the second frequency division control signal MFIS[m:0] after integer frequency division superposition to the fractional divider 16. The fractional divider 16 is used to divide the clock (whose frequency is Fvco) output by the voltage-controlled oscillator 15 based on the MFIS[m:0] output by the frequency division control signal output circuit 105.

[0121] In one example, please refer to Figure 12, the frequency division control signal output circuit 105 includes a third accumulator U4, a third register 1051, a fourth accumulator U5, and an output register 1052. One input terminal of the third accumulator U4 is coupled to the output terminal of the signal modulator 104, and the other input terminal is coupled to the output terminal of the high-k bit delay circuit 103. The third accumulator U4 can be the same accumulator as the accumulator U7 in the signal modulator 104, or can be different from the accumulator U7 in the signal modulator 104. The third accumulator U4 is used to superimpose the output OUTD[(n + k):(n + 1)] of the high-k bit delay circuit 103 and the output OUTSD[n:0] of the signal modulator 104. The output terminal of the third register 1051 is coupled to the first input terminal of the fourth accumulator U5 and is used to configure a k-bit second subtraction value, and the second subtraction value is, for example, equal to 2 k-1 . The second input terminal of the fourth accumulator U5 is coupled to the output terminal of the third accumulator U4, the third input terminal of the fourth accumulator U5 is coupled to the integer frequency division control signal MFI[m:0], and the fourth accumulator U5 is used to add the output of the third accumulator U4 and the integer frequency division control signal MFI[m:0] and then subtract the second subtraction value (for example, 2 k-1 ) configured in the third register 1051. The input terminal of the output register 1052 is coupled to the output terminal of the fourth accumulator U5, and the output register 1052 is also coupled to the feedback clock CLK_DIV and is used to perform clock synchronization on the output of the fourth accumulator U5 and the feedback clock CLK_DIV to output a second frequency division control signal MFIS[m:0] after integer frequency division superposition.

[0122] In the above embodiments, n, k, and m can be any suitable values respectively. Please refer to Figure 1 , Figures 10 to 13 , in an example, n = 13, k = 2, m = 7, and the working principle of the spread spectrum fractional frequency division control circuit 10 in this example is as follows: First, the triangular wave generator 1011 in the spread spectrum circuit 101 uses the feedback clock CLK_DIV as the reference clock. In one cycle in the spread spectrum mode of superimposing fractional frequency division (for example, configuring PLLFRAEN = 1 and SSCGBY = 0), at the rising edge of each clock cycle of CLK_DIV, it increments by a step MODSTEP, the increment step number is MODCNT, and it gradually increments to the maximum value, and then at the rising edge of each CLK_DIV, it decrements by a step MODSTEP until it decrements back to its initial value (for example, equal to 0, or it can be other values), thereby generating a triangular wave TEMP. At the same time, the first accumulator U1 in the spread spectrum circuit 101 superimposes MFN[13:0] and the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100.

[0123] Next, the second accumulator U2 in the frequency spreading circuit 101 adds the triangular wave TEMP and MFN[13:0] after superimposing the pseudo-random sequence PRBS, and further adds the additional value 2 provided by the first register 1012 15 and subtracts the first subtraction value provided by the second register 1013. Among them, in the center frequency spreading mode (for example, configuring PLLFRAEN = 1, SSCGBY = 0, SPREADCT = 0), the first subtraction value provided by the second register 1013 is 1 / 2*MODCNT*MODSTEP. If it is the downward frequency spreading mode (for example, configuring PLLFRAEN = 1, SSCGBY = 0, SPREADCT = 1), then the first subtraction value provided by the second register 1013 is MODSTEP*MODCNT. If it is the non-frequency spreading mode (for example, PLLFRAEN = 1, SSCGBY = 1), then the first subtraction value provided by the second register 1013 is 0, and TEMP = 0 provided by the triangular wave generator.

[0124] Next, the high 2-bit signal OUT[15:14] output by the frequency spreading circuit 101 is sent by the signal separation circuit 102 to the high 2-bit delay circuit 103 for two beats, and the output is OUTD[15:14]; the low 13-bit signal OUT[13:0] output by the frequency spreading circuit 101 is modulated and shaped by the signal modulator 104, and the output is OUTSD[13:0], so as to spread the quantization noise to a higher frequency band. Thus, the fractional-N PLL can filter out the high-frequency noise through its low-pass filter; Then, OUTD[15:14] output by the high 2-bit delay circuit 103 is added to OUTSD[13:0] output by the signal modulator 104 at the third accumulator U4 of the frequency division control signal output circuit 105, and the result of the addition has 11 different values [-3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7]; After that, the fourth accumulator U5 in the frequency division control signal output circuit 105 adds the output of the third accumulator U4 and the integer frequency division control signal MFI[7:0] and then subtracts the second subtraction value (which is equal to 2) provided by the third register 1051. The obtained result is clock-synchronized by the output register 1052 to obtain the second frequency division control signal MFIS[7:0]. This MFIS[7:0] is provided to the fractional divider 16 in the fractional-N PLL. The fractional divider 16 performs fractional frequency division on the clock output by the voltage-controlled oscillator 15 based on MFIS[7:0] to obtain the feedback clock CLK_DIV, and finally makes the frequency of the feedback clock CLK_DIV reach the reference frequency F provided by the prescaler 11 ref to achieve the locking of the fractional-N PLL.

[0125] In this embodiment, the sum of the spread spectrum and the fractional division code value is extended by k bits through the spread spectrum circuit 101 (that is, the signal after superimposing MFN[n:0] and TEMP is further superimposed with the first subtraction value 2 provided by the first register 1012) n+k ), and in the frequency division control signal output circuit 105, a second subtraction value 2 is further subtracted from the integer division coefficient k-1 , and the high k-bit signal OUT[(n + k):(n + 1)] in the extended signal is separated by the signal separation circuit 102, so that these high k bits do not participate in the modulation and shaping of the signal modulator 104, but are directly added to and subtracted from the signal OUTD[n:0] output by the signal modulator 104 after being delayed by the high k-bit delay circuit 103. Thus, the spread spectrum fractional division control circuit of this embodiment and the fractional division phase-locked loop having this spread spectrum fractional division control circuit can not only simultaneously implement the spread spectrum and fractional division functions, enabling the spread spectrum frequency and spread spectrum amplitude to be flexibly configured, so as to avoid the problem of downward or upward distortion due to the too large spread spectrum modulation amplitude when the fractional division ratio is close to 0 or close to 1, but also effectively reduce spurs by using noise shaping technology, enabling the fractional division phase-locked loop to achieve good phase noise performance while completing high frequency and high resolution, and can also avoid the problem of accumulator overflow, with a wide range of applications.

[0126] In addition, in an example of this embodiment, please refer to Figure 9 , the enable signal PLLFRAEN can be provided to the pseudo-random sequence generator 100, spread spectrum circuit 101, signal separation circuit 102, high k-bit delay circuit 103, and signal modulator 104 in the spread spectrum fractional division control circuit 10 of this embodiment to control the enable of these circuits. Thus, when PLLFRAEN = 0, the entire fractional division and spread spectrum link in the spread spectrum fractional division control circuit 10 is turned off to reduce the circuit power consumption in the integer division only mode.

[0127] In other examples of this embodiment, based on the fact that the spread spectrum fractional division control circuit can utilize PLLFRAEN, SSCGBYP, SPREADCT, MFN[n:0], and MFI[m:0] to achieve the required working mode, PLLFRAEN can also not be input to some links of the fractional division and spread spectrum in the spread spectrum fractional division control circuit 10. Thus, when PLLFRAEN = 0, only this part of the fractional division and spread spectrum link connected by PLLFRAEN is turned off. This part of the link can include at least one of the pseudo-random sequence generator 100, signal separation circuit 102, high k-bit delay circuit 103, part of the spread spectrum circuit 101, and part of the signal modulator 104.

[0128] Based on the same inventive concept, an embodiment of the present invention further provides a chip, which includes a fractional-N phase-locked loop as described in the present invention and an internal circuit. The clock input terminal of the internal circuit is coupled to the output terminal of the voltage-controlled oscillator of the fractional-N phase-locked loop. The fractional-N phase-locked loop provides a clock with a low spurious rate for the internal circuit. Since the chip integrates the fractional-N phase-locked loop of the present invention, it can effectively resist the serious problem of external electromagnetic interference.

[0129] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the technical solutions of the present invention.

Claims

1. A spread spectrum fractional frequency division control circuit, characterized in that: include: a spread spectrum circuit, configured to superimpose an n+1-bit fractional frequency division control signal with a corresponding triangular wave signal in a corresponding spread spectrum mode to obtain a first superposition result, and to perform corresponding processing on the first superposition result according to the spread spectrum mode to obtain a corresponding first frequency division control signal, wherein the processing of the first superposition result by the spread spectrum circuit in a non-spread spectrum mode and in different spread spectrum modes is different from each other; a signal modulator, coupled to the spread spectrum circuit, and configured to modulate and shape the first frequency division control signal; and The frequency division control signal output circuit is coupled to the signal modulator and the corresponding fractional frequency divider, and is used to provide a second frequency division control signal to the fractional frequency divider according to the output of the signal modulator, and the fractional frequency divider is used to divide the corresponding clock based on the second frequency division control signal.

2. The spread spectrum fractional frequency division control circuit according to claim 1, characterized in that: The initial value of the first superposition result is equal to MFN[n:0], and the first superposition result increases by MODSTEP in each clock cycle of the feedback clock fed back by the fractional divider until it reaches a maximum value, and then the first superposition result decreases by MODSTEP in each clock cycle of the feedback clock until it decreases back to MFN[n:0]; wherein the maximum value is MFN[n:0]+MODSTEP*MODCNT, MFN[n:0] is the n+1-bit fractional division control signal, MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the number of spread spectrum modulation steps configured by the register.

3. The spread spectrum fractional frequency division control circuit according to claim 2, characterized in that: The register configuration value of MODCNT is calculated based on the modulation frequency and reference clock in the spread spectrum mode, and the register configuration value of MODSTEP is calculated based on the modulation depth in the spread spectrum mode, the n+1-bit fractional frequency division control signal and the corresponding integer frequency division control signal.

4. The spread spectrum fractional frequency control circuit according to any one of claims 1 to 3, characterized in that: The spread spectrum circuit subtracts different first subtrahend values ​​from the first superposition result in a non-spread spectrum mode and in different spread spectrum modes to achieve the different processing in the non-spread spectrum mode and in different spread spectrum modes, and the first subtrahend value is configured by a second register or calculated according to the register configuration values ​​of MODSTEP and MODCNT; wherein MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the number of spread spectrum modulation steps configured by the register.

5. The spread spectrum fractional frequency division control circuit according to claim 4, characterized in that: The first subtraction value is equal to 0 in the non-spread spectrum mode, equal to MODSTEP*MODCNT / 2 in the center spread spectrum mode, and equal to MODSTEP*MODCNT in the downward spread spectrum mode.

6. The spread spectrum fractional frequency division control circuit according to claim 4, characterized in that: The spread spectrum circuit comprises: A triangular wave generator, used for generating and outputting the triangular wave signal corresponding to the n+1-bit fractional frequency division control signal in the corresponding spread spectrum mode; a second accumulator, coupled to the triangular wave generator and the n+1-bit fractional frequency division control signal, and configured to superimpose the output of the triangular wave generator and the n+1-bit fractional frequency division control signal to output the first superposition result; A subtractor is coupled to the second accumulator and is used for subtracting the first subtraction value from the first superposition result output by the second accumulator to obtain the first frequency division control signal.

7. The spread spectrum fractional frequency control circuit according to any one of claims 1 to 3 and 5 to 6, characterized in that: The spectrum spreading circuit is further used for expanding the bit number of the processed result by k bits to output the first frequency division control signal of n+k+1 bits, wherein n≥0, k≥2 and n and k are both integers.

8. The spread spectrum fractional frequency division control circuit according to claim 7, characterized in that: n=13, k=2.

9. The spread spectrum fractional frequency division control circuit according to claim 7, characterized in that: The spectrum spreading circuit further includes a first register, in which an additional value of n+k+1 bits is configured. The spectrum spreading circuit is further used to superimpose the first superposition result or the processed result with the additional value, thereby expanding the number of bits of the processed result by k bits.

10. The spread spectrum fractional frequency division control circuit according to claim 7, characterized in that: The spread spectrum fractional frequency division control circuit further comprises: A signal separation circuit is coupled to the spread spectrum circuit and is used to separate the highest k bits and the remaining n+1 bits in the n+k+1-bit first frequency division control signal to obtain a high k-bit signal and a low n+1-bit signal; A high-k bit delay circuit is coupled to the signal separation circuit and the frequency division control signal output circuit, and is used to delay the high-k bit signal output by the signal separation circuit and then provide it to the frequency division control signal output circuit; The signal modulator is further used to modulate and shape the low n + 1 bit signal output by the signal separation circuit, and the output of the signal modulator is synchronized with the output of the high k bit delay circuit; The frequency division control signal output circuit is further used to superimpose the output of the signal modulator and the output of the high-k bit delay circuit.

11. The spread spectrum fractional frequency division control circuit according to claim 10, characterized in that: The high-k bit delay circuit comprises a delay chain, wherein the delay chain comprises at least two first delay units connected in cascade, and the number of stages of the first delay units matches the modulation time of the signal modulator.

12. The spread spectrum fractional frequency division control circuit according to claim 11, characterized in that: The first delay unit is a k-bit register; and / or the number of stages of the first delay unit is three, and the signal modulator is a third-order SDM modulator using a MASH structure.

13. The spread spectrum fractional frequency division control circuit according to claim 10, characterized in that: The frequency division control signal output circuit is further configured to: superimpose the output of the high-k bit delay circuit, the output of the signal modulator and the corresponding integer frequency division control signal, and then subtract the k-bit second subtrahend value to obtain the second frequency division control signal after integer frequency division superposition.

14. The spread spectrum fractional frequency division control circuit according to claim 13, characterized in that: The frequency division control signal output circuit comprises: a third accumulator, coupled to the signal modulator and the high-k bit delay circuit, and used to superimpose the output of the high-k bit delay circuit and the output of the signal modulator; A third register, used to configure the second subtrahend value; a fourth accumulator, coupled to the third accumulator, the third register and the corresponding integer frequency division control signal, and configured to add the output of the third accumulator and the integer frequency division control signal and then subtract the second subtrahend value; The output register is coupled to the fourth accumulator and is used to synchronize the output of the fourth accumulator with the feedback clock fed back by the fractional frequency divider to output the second frequency division control signal.

15. The spread spectrum fractional frequency control circuit according to any one of claims 1-3, 5-6 and 8-14, characterized in that: The spread spectrum fractional frequency division control circuit also includes a pseudo-random sequence generator, which is used to generate and output a pseudo-random sequence; the spread spectrum circuit also includes a first accumulator, which is coupled to the n+1-bit fractional frequency division control signal and the pseudo-random sequence generator, and is used to superimpose the n+1-bit fractional frequency division control signal and the pseudo-random sequence to obtain a second superposition result, and superimpose the second superposition result with the triangular wave signal to obtain the first superposition result.

16. The spread spectrum fractional frequency control circuit according to any one of claims 1-3, 5-6 and 8-14, characterized in that: The spread spectrum circuit is also coupled to an enable signal, a spread spectrum mode control signal, and a spread spectrum direction control signal, and provides the following working modes according to the enable signal, the spread spectrum mode control signal, and the spread spectrum direction control signal: (1) Integer division mode only: the enable signal is at the first level; (2) Fractional frequency division mode without superimposed spread spectrum: the enable signal is at the second level, and the spread spectrum mode control signal is at the second level; (3) Spread spectrum mode: the enable signal is at the second level, the spread spectrum mode control signal is at the first level, and the center spread spectrum is performed when the spread spectrum direction control signal is at the first level, and the downward spread spectrum is performed when the spread spectrum direction control signal is at the second level.

17. The spread spectrum fractional frequency control circuit according to claim 16, characterized in that: The spectrum spreading circuit further divides the spectrum spreading mode into the following modes according to the n+1-bit fractional frequency division control signal MFN[n:0] and the spectrum spreading direction control signal: (3-1) Integer frequency division center spread spectrum mode: the spread spectrum direction control signal is at the first level, and MFN[n:0]=0; (3-2) Integer frequency division downward spread spectrum mode: the spread spectrum direction control signal is at the second level, and MFN[n:0]=0; (3-3) Center spread spectrum mode with superimposed fractional frequency division: the spread spectrum direction control signal is at the first level, and MFN[n:0]≠0; (3-4) Downward spread spectrum mode with superimposed fractional frequency division: the spread spectrum direction control signal is at the second level, and MFN[n:0]≠0.

18. A fractional frequency phase-locked loop, comprising a pre-divider, a frequency detector, a phase detector, a charge pump, a low-pass filter and a voltage-controlled oscillator connected in sequence, characterized in that: The fractional-frequency phase-locked loop also includes a fractional frequency divider and a spread spectrum fractional frequency division control circuit as described in any one of claims 1-17, the output end of the fractional frequency divider is coupled to the feedback input end of the frequency detector and phase detector, one input end of the fractional frequency divider is coupled to the output end of the voltage-controlled oscillator, and the other input end of the fractional frequency divider is coupled to the output end of the spread spectrum fractional frequency division control circuit.

19. A chip, characterized in that: Comprising the fractional frequency phase locked loop as claimed in claim 18.

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