Detection system, method for performing multiple programming therein, and display device

Abstract

Provided are a detection system, a method for performing multiple programming therein, and a display device. The detection system includes: a display device including a nonvolatile memory; a detection device configured to generate a write voltage for application to the nonvolatile memory; and a protection unit configured to apply the write voltage to the nonvolatile memory when the write voltage is within an allowable voltage range, and not apply the write voltage to the nonvolatile memory when the write voltage is not within the allowable voltage range. Applying the write voltage to the nonvolatile memory enables a multiple programming operation (MTP) in which reference data is written to the nonvolatile memory.

Description

Technical Field

[0001] The present disclosure relates to a detection system and a display device for improving driving reliability, and a method and a display device for performing multiple programming using the detection system. Background Art

[0002] Display devices include liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).

[0003] The LCD device includes a liquid crystal display panel that displays images using the light transmittance of liquid crystals, and a backlight assembly that is disposed under the liquid crystal display panel and provides light to the liquid crystal display panel.

[0004] The OLED device displays images using an organic light emitting diode that emits light through recombination of electrons and holes. The OLED device is more frequently used because it has a fast response time and is driven with low power consumption.

[0005] The display device performs various characteristic tests required for driving the display device during the production process, and writes the reference data for driving obtained in the various characteristic tests into the non-volatile memory. The operation of writing the reference data into the non-volatile memory is called multi-time programming (MTP). The reference data may include data such as correction values ​​according to electrical characteristics and optical characteristics of image data, individual driving voltages of each driving unit of the display device, panel driving voltage, and driving timing.

[0006] During the production process, when reference data is written to the nonvolatile memory by the detection device, an abnormal voltage is applied due to intermittent operation errors of the detection device and the external EDS, thereby writing abnormal reference data. After the abnormal reference data is written to the nonvolatile memory, the abnormal reference data is not erased, which reduces the reliability of the display device. Summary of the invention

[0007] Exemplary embodiments of the present disclosure provide a detection system for improving driving reliability.

[0008] Exemplary embodiments of the present disclosure provide a method of programming reference data to a display device multiple times.

[0009] According to an exemplary embodiment of the present disclosure, a detection system includes: a display device including a nonvolatile memory; a detection device configured to generate a write voltage for application to the nonvolatile memory; and a protection unit configured to apply the write voltage to the nonvolatile memory when the write voltage is within an allowable voltage range, and not apply the write voltage to the nonvolatile memory when the write voltage is not within the allowable voltage range. Applying the write voltage to the nonvolatile memory enables a multiple programming (MTP) operation in which reference data is written to the nonvolatile memory.

[0010] In an exemplary embodiment, the detection device may include a detection controller configured to generate a write voltage, and the protection section may be connected between the detection controller and the nonvolatile memory.

[0011] In an exemplary embodiment, the protection part may be located in the display device.

[0012] In an exemplary embodiment, the protection portion may be located in the detection device.

[0013] In an exemplary embodiment, the protection unit may include: a first comparator configured to compare a first reference voltage and a write voltage; a second comparator configured to compare a second reference voltage and the write voltage; and a logic circuit configured to generate a write control signal for controlling whether the write voltage is applied to the non-volatile memory based on an output signal of the first comparator and an output signal of the second comparator.

[0014] In an exemplary embodiment, the first reference voltage may be a lowest voltage within an allowable voltage range, the second reference voltage may be a highest voltage within the allowable voltage range, and the logic circuit may be a NOR logic operator.

[0015] In an exemplary embodiment, the first reference voltage may be a highest voltage within an allowable voltage range, the second reference voltage may be a lowest voltage within the allowable voltage range, and the logic circuit may be an AND logic operator.

[0016] In an exemplary embodiment, a nonvolatile memory may include: an MTP cell element including a series of one-time programming (OTP) cells; and a voltage controller configured to control whether a write voltage is applied to the MTP cell element in response to a write control signal.

[0017] In an exemplary embodiment, the OTP cell may be configured to initially maintain a “0” state and change from the “0” state to a “1” state when a bias voltage is applied.

[0018] In an exemplary embodiment, the voltage controller may include a transistor including a control electrode configured to receive a write control signal, a first electrode configured to receive a write voltage, and a second electrode connected to the MTP cell element.

[0019] According to an exemplary embodiment of the present disclosure, a method for programming reference data multiple times into a nonvolatile memory in a display device includes: generating a write voltage for writing to the nonvolatile memory; applying the write voltage to the nonvolatile memory when the write voltage is within an allowable voltage range, and not applying the write voltage to the nonvolatile memory when the write voltage is not within the allowable voltage range.

[0020] In an exemplary embodiment, the method may further include: comparing a first reference voltage and a write voltage; comparing a second reference voltage and the write voltage; and generating a write control signal for controlling whether the write voltage is applied to the non-volatile memory based on the comparison of the write voltage with the first reference voltage and the second reference voltage.

[0021] In an exemplary embodiment, the first reference voltage may be a lowest voltage within an allowable voltage range, the second reference voltage may be a highest voltage within the allowable voltage range, and the write control signal may be generated by using a NOR logical operator.

[0022] In an exemplary embodiment, the first reference voltage may be a highest voltage within an allowable voltage range, the second reference voltage may be a lowest voltage within the allowable voltage range, and the write control signal may be generated by using an AND logical operator.

[0023] In an exemplary embodiment, the method may further include controlling whether a write voltage is applied to an MTP cell element in response to a write control signal, wherein the nonvolatile memory includes the MTP cell element, the MTP cell element including a series of one-time programming (OTP) cells.

[0024] In an exemplary embodiment, the OTP cell may initially maintain a "0" state and change from the "0" state to a "1" state when a bias voltage is applied.

[0025] According to an exemplary embodiment of the present disclosure, a display device includes: a display portion including a series of pixels; a nonvolatile memory; and a protection portion configured to receive a write voltage for application to the nonvolatile memory. The protection portion is configured to apply the write voltage to the nonvolatile memory when the write voltage is within an allowable voltage range, and not apply the write voltage to the nonvolatile memory when the write voltage is not within the allowable voltage range. Applying the write voltage to the nonvolatile memory enables a multiple programming (MTP) operation in which reference data is written to the nonvolatile memory.

[0026] In an exemplary embodiment, the protection unit may include: a first comparator configured to compare a first reference voltage and a write voltage; a second comparator configured to compare a second reference voltage and the write voltage; and a logic circuit configured to generate a write control signal for controlling whether the write voltage is applied to the non-volatile memory based on an output signal of the first comparator and an output signal of the second comparator.

[0027] In an exemplary embodiment, a nonvolatile memory may include: an MTP cell element including a series of one-time programming (OTP) cells; and a voltage controller configured to control whether a write voltage is applied to the MTP cell element in response to a write control signal.

[0028] In an exemplary embodiment, the display device may further include: a driving voltage generator configured to generate the first reference voltage and the second reference voltage.

[0029] According to various aspects of the embodiments of the present disclosure, the detection system checks whether the MTP voltage is an abnormal MTP voltage in the multiple programming mode. When the MTP voltage is an abnormal MTP voltage, the abnormal MTP voltage can be prevented from being applied to the non-volatile memory. Therefore, abnormal data can be prevented from being written into the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features and advantages of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram illustrating a detection system according to an exemplary embodiment;

[0032] Figure 2 is a circuit diagram showing a multiple programming (MTP) protection unit according to an exemplary embodiment;

[0033] Figure 3 is a circuit diagram showing a driving voltage generator according to an exemplary embodiment;

[0034] Figure 4A and Figure 4B is a conceptual diagram illustrating an operation of a one time programming (OTP) unit according to an exemplary embodiment;

[0035] Figure 5 is a conceptual diagram illustrating an abnormal operation of an OTP unit according to a comparative exemplary embodiment;

[0036] Figure 6 is a circuit diagram showing an MTP protection unit according to an exemplary embodiment;

[0037] Figure 7 is a block diagram illustrating a detection system according to an exemplary embodiment; and

[0038] Figure 8 is a flowchart illustrating a method of multi-programming a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, the present disclosure will be explained in detail with reference to the accompanying drawings.

[0040] Figure 1 is a block diagram illustrating a detection system according to an exemplary embodiment.

[0041] Reference Figure 1 , the detection system may include a display device 100 and a detection device 200 .

[0042] The detection apparatus 200 may include a detection controller 210. The detection controller 210 is configured to generate various test signals used in various detection modes and generally control the detection operation of the detection apparatus 200.

[0043] In an exemplary embodiment, the detection controller 210 may generate and / or transmit a write voltage as an MTP (Multi-Time Programming) voltage VPP to be applied to the nonvolatile memory 130, and generate and / or transmit various reference data R_DATA to the display device 100 to be written to the nonvolatile memory 130 of the display device 100 in the multi-time programming mode. The multi-time programming mode may be performed in a sleep mode in which the display device 100 does not display an image.

[0044] The display device 100 may include a display part 110 , a timing controller 120 , a nonvolatile memory 130 , an MTP protection part 140 , a driving voltage generator 150 , a memory 160 , a data compensator 170 , a data driver 180 , and a scan driver 190 .

[0045] The display part 110 may include a plurality of data lines DL and a plurality of scan lines SL, and a plurality of pixels P each including a plurality of sub-pixels SP1 , SP2 , and SP3 .

[0046] A plurality of scan lines SL are arranged to be spaced apart from each other in a first direction D1 , and each scan line SL extends in a second direction D2 crossing the first direction D1 .

[0047] A plurality of data lines DL are arranged to be spaced apart from each other in the second direction D2, and each of the data lines DL extends in the first direction D1.

[0048] The plurality of pixels P are arranged in a matrix including a plurality of pixel columns and a plurality of pixel rows. Each of the sub-pixels SP1, SP2 and SP3 may include a display element and at least one transistor and at least one capacitor for driving the display element. The display element may include an organic light emitting diode and a liquid crystal capacitor.

[0049] The timing controller 120 may generally control the operation of the display apparatus 100 .

[0050] In an exemplary embodiment, the timing controller 120 is configured to receive the reference data R_DATA from the detection apparatus 200 so that the received reference data R_DATA is written to the nonvolatile memory 130 in the multi-programming mode.

[0051] In the multi-programming mode, the reference data R_DATA is written to the nonvolatile memory 130 using the MTP voltage VPP. The nonvolatile memory 130 may include a flash memory, an EEPROM, or the like.

[0052] The MTP voltage VPP is a control voltage for controlling the states of a plurality of OTP cells in the nonvolatile memory 130. For example, the OTP cell initially maintains a "0" state and is GS When applied, it changes from the "0" state to the "1" state. The OTP cell can write 1-bit data "0" or "1".

[0053] A register in the nonvolatile memory 130 is allocated for each type of reference data, and a plurality of parameters corresponding to a plurality of levels of reference data may be written in each register.

[0054] For example, with respect to the nonvolatile memory 130, reference data of multiple high-level voltages corresponding to a scan high voltage applied to the scan driver 190 may be written into multiple parameters of a first register, and reference data of multiple low-level voltages corresponding to a scan low voltage applied to the scan driver 190 may be written into multiple parameters of a second register.

[0055] The MTP protection unit 140 is configured to receive the MTP voltage VPP from the detection device 200 in the multi-programming mode. The MTP protection unit 140 is configured to check the MTP voltage VPP based on the allowable voltage range. When the MTP voltage VPP is not within the allowable voltage range, the MTP protection unit 140 may prevent the MTP voltage VPP from being applied to the nonvolatile memory 130.

[0056] The driving voltage generator 150 is configured to generate a plurality of driving voltages.

[0057] According to an exemplary embodiment, the driving voltage may include a plurality of reference voltages for determining an allowable voltage range for checking whether the MTP voltage is abnormal.

[0058] In the multi-programming mode, a plurality of reference voltages generated from the driving voltage generator 150 are provided to the MTP protection part 140 .

[0059] The memory 160 may store reference data provided from the nonvolatile memory 130 during a period in which the display device 100 displays a normal image in the display mode. The reference data stored in the memory 160 may be used as reference data for driving the display device 100. The memory 160 may include a RAM.

[0060] The data compensator 170 is configured to generate compensated image data for compensating the image data stored in the memory 160 using reference data according to the control of the timing controller 120 in the display mode.

[0061] The data driver 180 is configured to generate data voltages corresponding to image data according to the control of the timing controller 120 based on reference data stored in the memory 160 and supply the data voltages to the plurality of data lines DL.

[0062] The scan driver 190 is configured to generate a scan signal according to the control of the timing controller 120 based on the reference data stored in the memory 160 and sequentially supply the scan signal to the plurality of scan lines SL.

[0063] Figure 2 is a circuit diagram illustrating a multiple programming (MTP) protection section according to an exemplary embodiment.

[0064] Figure 3 is a circuit diagram illustrating a driving voltage generator according to an exemplary embodiment.

[0065] Reference Figure 1 and Figure 2The MTP protection unit 140 is configured to apply the MTP voltage VPP to the nonvolatile memory 130 when the MTP voltage VPP is within the allowable voltage range. The MTP protection unit 140 is configured to prevent the MTP voltage VPP from being applied to the nonvolatile memory 130 when the MTP voltage VPP is not within the allowable voltage range.

[0066] The MTP protection part 140 may include a first comparator OP1 , a second comparator OP2 , and a logic circuit NOR.

[0067] The first comparator OP1 may include a first input terminal (+) receiving a first reference voltage VPP-a, a second input terminal (-) receiving an MTP voltage VPP, and an output terminal OT1. The first reference voltage VPP-a may be a low voltage lower than the MTP voltage VPP. The first reference voltage VPP-a may be the lowest voltage within an allowable voltage range. The first comparator OP1 may receive a first power supply voltage VDDI and a second power supply voltage GND.

[0068] The first comparator OP1 is configured to output a low signal L when the MTP voltage VPP is higher than the first reference voltage VPP-a, and to output a high signal H when the MTP voltage VPP is lower than the first reference voltage VPP-a.

[0069] The second comparator OP2 may include a first input terminal (+) receiving the MTP voltage VPP, a second input terminal (-) receiving a second reference voltage VPP+a, and an output terminal OT2, wherein the second reference voltage VPP+a may be a high voltage higher than the MTP voltage VPP. The second reference voltage VPP+a may be the highest voltage within an allowable voltage range. The second comparator OP2 may receive a first power supply voltage VDDI and a second power supply voltage GND.

[0070] The second comparator OP2 is configured to output a low signal L when the MTP voltage VPP is lower than the second reference voltage VPP+a, and to output a high signal H when the MTP voltage VPP is higher than the second reference voltage VPP+a.

[0071] Reference Figure 3 According to an exemplary embodiment, a first reference voltage VPP-a and a second reference voltage VPP+a may be generated by using a variable resistor string RS. The variable resistor string RS may include a plurality of variable resistors VR1, VR2, and VR3. The variable resistor string RS may divide the driving voltage VLIN provided from the driving voltage generator 150 into a first reference voltage VPP-a and a second reference voltage VPP+a using the variable resistors VR1, VR2, and VR3, and output the divided voltages.

[0072] Now refer to Figure 2 , the logic circuit NOR is configured to generate a write control signal MTP_CS based on output signals of the first comparator OP1 and the second comparator OP2 , and output the write control signal MTP_CS to the nonvolatile memory 130 .

[0073] The logic circuit NOR may be a NOR gate of a logic operator.

[0074] The logic circuit NOR may include a first input terminal IN1 connected to the output terminal OT1 of the first comparator OP1 , a second input terminal IN2 connected to the output terminal OT2 of the second comparator OP2 , and an output terminal OT3 connected to the nonvolatile memory 130 .

[0075] The logic circuit NOR is configured to output the write control signal MTP_CS of a high signal H when receiving a low signal L from the first comparator OP1 and receiving a low signal L from the second comparator OP2 .

[0076] The logic circuit NOR is configured to output the write control signal MTP_CS of a low signal L when receiving a high signal H from at least one of the first comparator OP1 and the second comparator OP2 .

[0077] The nonvolatile memory 130 may include a voltage controller 131 and an MTP cell (or referred to as an MTP cell element) 133 .

[0078] The voltage controller 131 may include a control transistor TR.

[0079] The control transistor TR may include a control electrode G connected to the output terminal OT3 of the logic circuit NOR, a first electrode D receiving the MTP voltage VPP, and a second electrode S connected to a voltage terminal of the MTP unit 133. In addition, the second electrode S is connected to the second power supply voltage GND via a resistor R.

[0080] When the output signal of the logic circuit NOR is a high signal H, the control transistor TR is turned on, and the MTP voltage VPP is output through the voltage terminal of the MTP cell 133. Therefore, when the MTP voltage VPP is applied to the MTP cell 133, a plurality of programming processes are performed.

[0081] However, when at least one of the first comparator OP1 and the second comparator OP2 outputs a high signal H, the logic circuit NOR outputs the write control signal MTP_CS of a low signal L. When the MTP voltage VPP is lower than the first reference voltage VPP-a or higher than the second reference voltage VPP+a, the logic circuit NOR outputs the write control signal MTP_CS of a low signal L.

[0082] When the output signal of the logic circuit NOR is a low signal L, the control transistor TR is turned off, and the MTP voltage VPP is not applied to the MTP voltage terminal of the nonvolatile memory 130 .

[0083] According to an exemplary embodiment, when the MTP voltage VPP is between the first reference voltage VPP-a and the second reference voltage VPP+a, the MTP voltage VPP is applied to the MTP voltage terminal of the nonvolatile memory 130. When the MTP voltage VPP is equal to or less than the first reference voltage VPP-a or equal to or greater than the second reference voltage VPP+a, the MTP voltage VPP may be prevented from being applied to the MTP voltage terminal of the MTP cell 133 in the nonvolatile memory 130.

[0084] Therefore, it is possible to prevent abnormal data from being written into the nonvolatile memory 130 .

[0085] The MTP cell 133 may include a plurality of OTP cells corresponding to bits of reference data stored in the nonvolatile memory 130. Each OTP cell may be written with 1 bit of data. When the MTP voltage VPP is applied to the MTP cell 133, a multiple programming process is performed. When the MTP voltage VPP is blocked, the multiple programming process is not performed.

[0086] Figure 4A and Figure 4B is a conceptual diagram illustrating an operation of a one time programming (OTP) unit according to an exemplary embodiment.

[0087] The nonvolatile memory may include a plurality of OTP cells corresponding to a storage capacity of the reference data.

[0088] Reference Figure 4A , the OTP cell maintains "0" in the initial state. When the write value corresponding to the OTP cell is "0", the initial state "0" is maintained.

[0089] However, referring to Figure 4B When the write value corresponding to the OTP cell is "1", the MTP voltage VPP is applied to the OTP cell, and the bias voltage V GS When applied to the OTP cell, the oxide layer of the OTP cell is destroyed, and the OTP cell changes from the "0" state to the "1" state. The OTP cell can write "0" or "1" of 1-bit data.

[0090] Figure 5 is a conceptual diagram illustrating an abnormal operation of an OTP unit according to a comparative exemplary embodiment.

[0091] Reference Figure 5, the write value written into the OTP cell is "0", so the initial state is maintained. At this time, an abnormal voltage is applied to the OTP cell due to an operational error of the detection device and the ESD input, and the OTP cell changes from a "0" state to a "1" state. Therefore, the OTP cell writes abnormal bit data. The abnormal data written into the OTP cell will not be deleted.

[0092] When abnormal data is written to the nonvolatile memory, the reliability of the display device may be reduced due to errors in the reference data.

[0093] In order to solve such a problem, after checking whether the MTP voltage supplied by the detection device is abnormal, a multi-programming process may be controlled in a multi-programming mode of writing reference data into a nonvolatile memory.

[0094] Figure 6 is a circuit diagram illustrating an MTP protection section according to an exemplary embodiment.

[0095] Reference Figure 1 and Figure 6 , the MTP protection unit 140A may include a first comparator OP1, a second comparator OP2, and a logic circuit AND.

[0096] The first comparator OP1 may include a first input terminal (+) receiving a first reference voltage VPP+a, a second input terminal (-) receiving an MTP voltage VPP, and an output terminal OT1. The first reference voltage VPP+a may be a high voltage higher than the MTP voltage VPP. The first reference voltage VPP+a may be the highest voltage within an allowable voltage range. The first comparator OP1 may receive a first power supply voltage VDDI and a second power supply voltage GND.

[0097] The first comparator OP1 is configured to output a high signal H when the MTP voltage VPP is lower than the first reference voltage VPP+a, and to output a low signal L when the MTP voltage VPP is higher than the first reference voltage VPP+a.

[0098] The second comparator OP2 may include a first input terminal (+) receiving the MTP voltage VPP, a second input terminal (-) receiving the second reference voltage VPP-a, and an output terminal OT2, wherein the second reference voltage VPP-a may be a low voltage lower than the MTP voltage VPP. The second reference voltage VPP-a may be the lowest voltage within an allowable voltage range. The second comparator OP2 may receive a first power supply voltage VDDI and a second power supply voltage GND.

[0099] The second comparator OP2 is configured to output a high signal H when the MTP voltage VPP is higher than the second reference voltage VPP-a, and to output a low signal L when the MTP voltage VPP is lower than the second reference voltage VPP-a.

[0100] The logic circuit AND may be an AND gate of a logic operator. The logic circuit AND may include a first input terminal IN1 connected to an output terminal OT1 of the first comparator OP1 , a second input terminal IN2 connected to an output terminal OT2 of the second comparator OP2 , and an output terminal OT3 connected to the nonvolatile memory 130 .

[0101] The logic circuit AND is configured to output the write control signal MTP_CS of a high signal H when receiving a high signal H from the first comparator OP1 and a high signal H from the second comparator OP2 .

[0102] The logic circuit AND is configured to output the write control signal MTP_CS of a low signal L when receiving a low signal L from at least one of the first comparator OP1 and the second comparator OP2 .

[0103] The nonvolatile memory 130 may include a voltage controller 131 and an MTP unit 133 .

[0104] The voltage controller 131 may include a control transistor TR.

[0105] The control transistor TR may include a control electrode G connected to the output terminal OT3 of the logic circuit AND, a first electrode D receiving the MTP voltage VPP, and a second electrode S connected to a voltage terminal of the MTP unit 133. In addition, the second electrode S is connected to the second power supply voltage GND via a resistor R.

[0106] When the output signal of the logic circuit AND is a high signal H, the control transistor TR is turned on, and the MTP voltage VPP is output through the voltage terminal of the MTP cell 133. Therefore, when the MTP voltage VPP is applied to the MTP cell 133, a plurality of programming processes are performed.

[0107] However, when the output signal of the logic circuit AND is a low signal L, the control transistor TR is turned off, and the MTP voltage VPP is blocked from being applied to the MTP voltage terminal of the nonvolatile memory 130 .

[0108] According to an exemplary embodiment, when the MTP voltage VPP is between the first reference voltage VPP+a and the second reference voltage VPP-a, the MTP voltage VPP is applied to the MTP voltage terminal of the nonvolatile memory 130. When the MTP voltage VPP is equal to or less than the second reference voltage VPP-a or equal to or greater than the first reference voltage VPP+a, the MTP voltage VPP may be prevented from being applied to the MTP voltage terminal of the MTP unit 133.

[0109] Therefore, it is possible to prevent abnormal data from being written into the nonvolatile memory 130 .

[0110] Hereinafter, the same reference numerals are used to refer to the same or like components as those described in the previous exemplary embodiment, and the same detailed explanation will not be repeated unless necessary.

[0111] Figure 7 is a block diagram illustrating a detection system according to an exemplary embodiment.

[0112] Reference Figure 7 , the detection system may include a display device 100A and a detection device 200A.

[0113] The detection apparatus 200A may transmit a write voltage as the MTP voltage VPP applied to the nonvolatile memory 130 and various reference data R_DATA to the display apparatus 100A in a multi-programming mode of writing the reference data R_DATA to the nonvolatile memory 130 of the display apparatus 100A.

[0114] The programming mode may be performed a plurality of times in a sleep mode in which the display apparatus 100A does not display an image.

[0115] The display device 100A may include a display part 110 , a timing controller 120 , a nonvolatile memory 130 , a driving voltage generator 150 , a memory 160 , a data compensator 170 , a data driver 180 , and a scan driver 190 .

[0116] The display part 110 may include a plurality of data lines DL, a plurality of scan lines SL, and a plurality of pixels P each including a plurality of sub-pixels SP1 , SP2 , and SP3 .

[0117] The timing controller 120 may generally control the operation of the display apparatus 100A.

[0118] According to an exemplary embodiment, the timing controller 120 is configured to receive the reference data R_DATA from the detection apparatus 200A so that the received reference data R_DATA is written to the nonvolatile memory 130 in the multi-programming mode.

[0119] In the multi-programming mode, the timing controller 120 is configured to write the reference data R_DATA to the nonvolatile memory 130 using the MTP voltage VPP provided from the detection device 200A.

[0120] The MTP voltage VPP is a control voltage for controlling the states of a plurality of OTP cells in the nonvolatile memory 130. For example, the OTP cell initially maintains a "0" state and is GS When applied, it changes from the "0" state to the "1" state. The OTP cell can write 1-bit data "0" or "1".

[0121] The driving voltage generator 150 is configured to generate a plurality of driving voltages.

[0122] The memory 160 may store the reference data provided from the nonvolatile memory 130 during a period in which the display apparatus 100A displays a normal image in the display mode.

[0123] The data compensator 170 is configured to generate compensated image data for compensating the image data stored in the memory 160 using reference data according to the control of the timing controller 120 in the display mode.

[0124] The data driver 180 is configured to generate data voltages corresponding to image data according to the control of the timing controller 120 based on reference data stored in the memory 160 and supply the data voltages to the plurality of data lines DL.

[0125] The scan driver 190 is configured to generate a scan signal according to the control of the timing controller 120 based on the reference data stored in the memory 160 and sequentially supply the scan signal to the plurality of scan lines SL.

[0126] The detection device 200A may include a detection controller 210 and an MTP protection unit 230 .

[0127] In the multi-programming mode, the detection controller 210 is configured to transmit reference data R_DATA for writing to the nonvolatile memory 130 to the timing controller 120 .

[0128] The detection controller 210 is configured to apply the MTP voltage VPP, which is a write voltage of the nonvolatile memory 130 , to the MTP protection part 230 .

[0129] The detection controller 210 is configured to provide the MTP protection part 230 with a plurality of reference voltages for determining an allowable voltage range for checking whether the MTP voltage is abnormal.

[0130] The MTP protection part 230 is configured to check the MTP voltage VPP based on the allowable voltage range. When the MTP voltage VPP is not within the allowable voltage range, the MTP protection part 230 may prevent the MTP voltage VPP from being applied to the nonvolatile memory 130.

[0131] The MTP protection unit 230 may include a reference Figure 2 and Figure 6 The components are the same or similar to the components described in the previous exemplary embodiments.

[0132] According to an exemplary embodiment, the detection device 200A may include an MTP protection part 230. After checking whether the MTP voltage VPP is abnormal, only the normal MTP voltage VPP is applied to the nonvolatile memory 130 of the display device 100A. Therefore, it is possible to prevent the abnormal MTP voltage caused by the error of the detection device from being applied to the nonvolatile memory 130.

[0133] Figure 8 is a flowchart illustrating a method of multi-programming a display device according to an exemplary embodiment.

[0134] Reference Figure 1 and Figure 8 In the multi-programming mode, the detection device 200 is configured to transmit the MTP voltage VPP and the reference data R_DATA to the display device 100 .

[0135] The MTP protection unit 140 receives the MTP voltage VPP from the detection device 200 (step S110 ).

[0136] Then, the MTP protection unit 140 checks the MTP voltage VPP (step S120 ).

[0137] Specifically, refer to Figure 2 The MTP protection unit 140 includes a first comparator OP1, a second comparator OP2, and a logic circuit NOR.

[0138] The first comparator OP1 outputs a low signal L when the MTP voltage VPP is greater than the first reference voltage VPP-a, and outputs a high signal H when the MTP voltage VPP is less than the first reference voltage VPP-a.

[0139] The second comparator OP2 outputs a low signal L when the MTP voltage VPP is less than the second reference voltage VPP+a, and outputs a high signal H when the MTP voltage VPP is greater than the second reference voltage VPP+a.

[0140] When receiving the low signal L from each of the first comparator OP1 and the second comparator OP2 , the logic circuit NOR outputs the write control signal MTP_CS of the high signal H (step S130 ).

[0141] The nonvolatile memory 130 includes a voltage controller 131 and an MTP unit 133. The voltage controller 131 includes a control transistor TR.

[0142] When the output signal of the logic circuit NOR is a high signal H, the control transistor TR is turned on, and the MTP voltage VPP is applied to the voltage terminal of the MTP unit 133 (step S140 ).

[0143] Therefore, when the MTP voltage VPP is applied to the MTP cell 133, a plurality of programming processes are performed (step S150).

[0144] However, when at least one of the first comparator OP1 and the second comparator OP2 outputs a high signal H, the logic circuit NOR outputs the write control signal MTP_CS of a low signal L. When the MTP voltage VPP is lower than the first reference voltage VPP-a or higher than the second reference voltage VPP+a, the logic circuit NOR outputs the write control signal MTP_CS of a low signal L (step S130).

[0145] When the output signal of the logic circuit NOR is a low signal L, the control transistor TR is turned off, and the MTP voltage VPP is not applied to the MTP voltage terminal of the nonvolatile memory 130 (step S160 ).

[0146] According to an exemplary embodiment, when the write control signal MTP_CS is a low signal L, the detection apparatus 200 may initialize the multi-time program mode (step S170 ).

[0147] According to an exemplary embodiment, when the write control signal MTP_CS is a low signal L, the timing controller 120 may change the display apparatus 100 into a turn-off state (step S170 ).

[0148] According to an exemplary embodiment, in the multi-programming mode, the MTP protection unit 140 checks whether the MTP voltage is an abnormal MTP voltage. When the MTP voltage is an abnormal MTP voltage, the abnormal MTP voltage can be prevented from being applied to the nonvolatile memory 130. Therefore, abnormal data can be prevented from being written into the nonvolatile memory 130.

[0149] Therefore, driving reliability of the display device 100 may be improved by writing normal reference data into the nonvolatile memory 130 .

[0150] The present disclosure can be applied to a display device and an electronic device having the display device. For example, the present disclosure can be applied to a computer monitor, a laptop computer, a digital camera, a cellular phone, a smart phone, a smart tablet, a television, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a navigation system, a game console, a video phone, etc.

[0151] The foregoing is an illustration of various aspects of the embodiments of the present disclosure and should not be construed as limiting them. Although some exemplary embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications can be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function term is intended to cover the structure described herein as performing the function, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the inventive concept and is not to be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the claims. The inventive concept is defined by the claims, and the equivalents of the claims are included in the inventive concept.

Claims

1. A detection system, comprising: A display device including a non-volatile memory; a detection device configured to generate a write voltage for application to the nonvolatile memory and reference data obtained in a characteristic test of the display device; as well as a protection unit configured to apply the write voltage to the nonvolatile memory when the write voltage is within an allowable voltage range, and configured not to apply the write voltage to the nonvolatile memory when the write voltage is not within the allowable voltage range, applying the write voltage to the nonvolatile memory enables multiple programming operations, in which the reference data is written to the nonvolatile memory using the write voltage, The multiple programming operations are performed in a sleep mode in which the display device does not display an image.

2. The detection system according to claim 1, wherein: The detection device includes a detection controller configured to generate the write voltage, and Wherein, the protection unit is connected between the detection controller and the non-volatile memory.

3. The detection system according to claim 2, wherein: The protection portion is located in the display device.

4. The detection system according to claim 2, wherein: The protection part is located in the detection device.

5. The detection system according to claim 2, wherein: The protection unit comprises: A first comparator configured to compare a first reference voltage with the write voltage; a second comparator configured to compare a second reference voltage with the write voltage; and A logic circuit is configured to generate a write control signal for controlling whether to apply the write voltage to the nonvolatile memory based on an output signal of the first comparator and an output signal of the second comparator.

6. The detection system according to claim 5, wherein: The first reference voltage is a lowest voltage within the allowable voltage range, the second reference voltage is a highest voltage within the allowable voltage range, and the logic circuit is a NOR logic operator.

7. The detection system according to claim 5, wherein: The first reference voltage is a highest voltage within the allowable voltage range, the second reference voltage is a lowest voltage within the allowable voltage range, and the logic circuit is an AND logic operator.

8. The detection system according to claim 5, wherein: The non-volatile memory comprises: A multiple programming unit element includes a plurality of one-time programming units; and A voltage controller is configured to control whether the write voltage is applied to the multi-programming cell element in response to the write control signal.

9. The detection system according to claim 8, wherein: The one-time programming cell is configured to initially maintain a “0” state, and is configured to change from the “0” state to a “1” state when a bias voltage is applied.

10. The detection system according to claim 8, wherein: The voltage controller includes a transistor including a control electrode configured to receive the write control signal, a first electrode configured to receive the write voltage, and a second electrode connected to the multi-programming cell element.

11. A method for programming reference data obtained during a characteristic test of a display device multiple times into a nonvolatile memory in the display device, the method comprising: generating a write voltage for writing into the nonvolatile memory; as well as When the write voltage is within an allowable voltage range, applying the write voltage to the nonvolatile memory, and when the write voltage is not within the allowable voltage range, not applying the write voltage to the nonvolatile memory, wherein applying the write voltage to the nonvolatile memory enables multiple programming operations, in which the reference data is written to the nonvolatile memory using the write voltage, and The multiple programming operations are performed in a sleep mode in which the display device does not display an image.

12. The method according to claim 11, further comprising: comparing a first reference voltage with the write voltage; comparing a second reference voltage with the write voltage; as well as Based on the comparison of the first reference voltage and the write voltage and the comparison of the second reference voltage and the write voltage, a write control signal for controlling whether the write voltage is applied to the nonvolatile memory is generated.

13. The method according to claim 12, wherein: The first reference voltage is a lowest voltage within the allowable voltage range, the second reference voltage is a highest voltage within the allowable voltage range, and the write control signal is generated by using a NOR logical operator.

14. The method according to claim 12, wherein: The first reference voltage is a highest voltage within the allowable voltage range, the second reference voltage is a lowest voltage within the allowable voltage range, and the write control signal is generated by using an AND logical operator.

15. The method according to claim 12, further comprising: controlling whether the write voltage is applied to the multi-programming cell element in response to the write control signal, The nonvolatile memory includes the multiple programming unit element, and the multiple programming unit element includes a plurality of one-time programming units.

16. The method according to claim 15, the one-time programming cell initially maintains a "0" state, and changes from the "0" state to a "1" state when a bias voltage is applied.

17. A display device, comprising: A display unit including a plurality of pixels; Non-volatile memory; as well as a protection section configured to receive a write voltage for application to the nonvolatile memory, the protection section configured to apply the write voltage to the nonvolatile memory when the write voltage is within an allowable voltage range, and configured not to apply the write voltage to the nonvolatile memory when the write voltage is not within the allowable voltage range, applying the write voltage to the nonvolatile memory enables multiple programming operations in which reference data obtained in a characteristic test of the display device is written to the nonvolatile memory using the write voltage in the multiple programming operations, The multiple programming operations are performed in a sleep mode in which the display device does not display an image.

18. The display device according to claim 17, wherein: The protection unit comprises: A first comparator configured to compare a first reference voltage with the write voltage; a second comparator configured to compare a second reference voltage with the write voltage; and A logic circuit is configured to generate a write control signal for controlling whether to apply the write voltage to the nonvolatile memory based on an output signal of the first comparator and an output signal of the second comparator.

19. The display device according to claim 18, wherein: The non-volatile memory comprises: A multiple programming unit element includes a plurality of one-time programming units; and A voltage controller is configured to control whether the write voltage is applied to the multi-programming cell element in response to the write control signal.

20. The display device according to claim 18, further comprising: The driving voltage generator is configured to generate the first reference voltage and the second reference voltage.

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