Memory Controller, Method of Operating the Memory Controller, and Memory System

Abstract

A method of operating a memory controller for individually controlling a plurality of memory cells includes: reading respective segments from the plurality of memory cells based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when the result of the error correction decoding indicates success, updating at least one of a plurality of cumulative error pattern information respectively corresponding to the plurality of memory cells based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, adjusting at least one of the plurality of control signals based on at least one of the plurality of cumulative error pattern information.

Description

[0001] Cross - reference to related applications

[0002] This disclosure claims priority to Korean Patent Application No. 10 - 2018 - 0091903, filed on August 7, 2018, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Technical field

[0003] This disclosure relates to a semiconductor memory system, and more particularly, to a memory system that performs error correction operations based on error - correcting code (ECC). Background art

[0004] Semiconductor memory devices can be classified into volatile memory devices and non - volatile memory devices, where data stored in volatile memory devices is lost when the power is turned off, and data stored in non - volatile memory devices is retained even when the power is turned off.

[0005] During the process of writing data to or reading data from a semiconductor memory device, errors may occur in the data. Generally, before writing data, an error - correcting code can be added to the data by the semiconductor memory device. When an error is detected in the data during a read operation, the semiconductor memory device can correct the detected error by using the error - correcting code to restore the original data.

[0006] However, in the case where the data includes many error bits, the probability of successfully correcting the data may be low. In addition, in the case of rereading the data for the purpose of performing decoding and / or error correction again, the power consumption increases. Summary of the invention

[0007] Embodiments of the inventive concept provide a memory controller and a memory system that can increase the probability of successfully performing error correction on data and can reduce power consumption according to error correction.

[0008] Embodiments of the inventive concept provide an operation method of a memory controller that separately controls operations of a plurality of memory cells. The method includes: reading respective segments from the plurality of memory cells by the memory controller based on a plurality of control signals; generating an output codeword by the memory controller based on the segments; performing error - correction decoding on the output codeword by the memory controller; when the result of the error - correction decoding indicates success, updating at least one of a plurality of cumulative error pattern information respectively corresponding to the plurality of memory cells by the memory controller based on the result of the error - correction decoding; and when the result of the error - correction decoding indicates failure, adjusting at least one of the plurality of control signals by the memory controller based on at least one of the plurality of cumulative error pattern information.

[0009] An embodiment of the inventive concept also provides a memory controller, including: a codeword circuit configured to generate an output codeword based on a first segment read from a first memory cell according to a first control signal and a second segment read from a second memory cell according to a second control signal; an error correction code (ECC) circuit configured to perform error correction decoding on the output codeword; and a control circuit configured to operate based on a result of the error correction decoding. The control circuit adjusts at least one of the first control signal and the second control signal based on at least one of first cumulative error pattern information corresponding to the first memory cell and second cumulative error pattern information corresponding to the second memory cell.

[0010] An embodiment of the inventive concept also provides a memory system, including: a first memory cell configured to operate in response to a first control signal; a second memory cell configured to operate in response to a second control signal; and a memory controller configured to read a first segment from the first memory cell based on the first control signal and read a second segment from the second memory cell based on the second control signal. The memory controller includes: a codeword circuit configured to generate an output codeword based on the first segment and the second segment; an error correction code (ECC) circuit configured to perform error correction decoding on the output codeword; and a control circuit configured to operate based on a result of the error correction decoding. The control circuit adjusts at least one of the first control signal and the second control signal based on at least one of first cumulative error pattern information corresponding to the first memory cell and second cumulative error pattern information corresponding to the second memory cell.

[0011] An embodiment of the inventive concept also provides a memory controller, including: a codeword circuit configured to generate an output codeword based on a first segment read from a first memory cell according to a first control signal and a second segment read from a second memory cell according to a second control signal; an error correction code (ECC) circuit configured to perform error correction decoding on the output codeword; and a control circuit configured to: when the result of the error correction decoding indicates success, update at least one of first cumulative error pattern information corresponding to the first memory cell and second cumulative error pattern information corresponding to the second memory cell; and when the result of the error correction decoding indicates failure, adjust at least one of the first control signal and the second control signal based on at least one of the first cumulative error pattern information and the second cumulative error pattern information. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the inventive concept will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings.

[0013] Figure 1 A block diagram of a memory system according to an embodiment of the inventive concept is shown.

[0014] Figure 2 shows the Figure 1 block diagram of the memory controller.

[0015] Figure 3 shows the Figure 1 schematic diagram of an example of the memory system adjusting a control signal.

[0016] Figure 4 shows the Figure 3 block diagram of the memory controller according to a successfully decoded operation.

[0017] Figure 5 shows the Figure 4 schematic diagram of an example of the memory controller updating an error mode information table based on a successfully decoded operation.

[0018] Figure 6 shows the Figure 4 schematic diagram of an example of the memory controller adjusting a control signal according to a successfully decoded operation.

[0019] Figure 7A , Figure 7B and Figure 7C shows the schematic diagram of an example in which a control circuit determines a read voltage level according to an embodiment of the inventive concept.

[0020] Figure 8 shows the Figure 4 schematic diagram of an example of the memory controller refreshing data of a memory cell according to a successfully decoded operation.

[0021] Figure 9 shows the Figure 3 block diagram of the memory controller according to a failed decoded operation.

[0022] Figure 10 shows the Figure 9 schematic diagram of an example of the memory controller rereading a segment based on a failed decoded operation.

[0023] Figure 11 shows the Figure 9 schematic diagram of an example of the memory controller performing decoding again according to a failed decoded operation.

[0024] Figure 12 shows the flowchart of the operation of the memory controller according to an embodiment of the inventive concept.

[0025] Figure 13 shows the flowchart of the operation corresponding to the case where the memory controller decodes successfully according to an embodiment of the inventive concept.

[0026] Figure 14A flowchart showing operations corresponding to a case where a memory controller decoding fails according to an embodiment of the inventive concept is shown.

[0027] Figure 15 A block diagram of an application of a memory system according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0028] Embodiments of the inventive concept are described below in detail and clearly to the extent that an ordinary person skilled in the art can implement the inventive concept.

[0029] As is common in the field of the inventive concept, embodiments may be described and illustrated in terms of blocks that perform the described functions. These blocks, which may be referred to herein as units or modules, etc., are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, and may optionally be driven by firmware and / or software. For example, a circuit may be embodied in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuits constituting the blocks may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Without departing from the scope of the inventive concept, each block of an embodiment may be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of the inventive concept, blocks of an embodiment may be physically combined into more complex blocks.

[0030] A memory cell according to an embodiment of the inventive concept described below may mean any memory cell that can operate in response to a separate control signal. In an embodiment of the inventive concept, a memory cell may include, for example, a memory device, a memory chip, a memory die, a memory bank, a memory block, or memory cells connected to one word line. For example, a memory cell according to an embodiment of the inventive concept may indicate a memory device that can individually adjust a read voltage.

[0031] Accordingly, each memory cell according to an embodiment of the inventive concept may be implemented by or implemented as any of the following: a separate memory package, a separate memory device, a separate memory chip, or a separate memory die. Alternatively, a collection of memory cells may be implemented by or implemented as any of the following: one memory package, one memory device, one memory chip, or one memory die.

[0032] A memory cell or a set of memory cells according to an embodiment of the inventive concept may be implemented using at least one of the following: volatile memories (e.g., static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc.) and non-volatile memories (e.g., read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), flash memory, etc.).

[0033] Figure 1 FIG. shows a block diagram of a memory system according to an embodiment of the inventive concept. Referring Figure 1 , the memory system 1000 includes a memory controller 100 and a memory 200. The memory 200 may include a plurality of memory cells MU11, MU12 to MU1n; MU21, MU22 to MU2n; and MUn1, MUn2 to MUnn (hereinafter may be referred to as a plurality of memory cells MU11 to MUnn).

[0034] The memory controller 100 may provide a plurality of control signals CTRL11 to CTRL1n, CTRL21 to CTRL2n, and CTRLn1 to CTRLnn (hereinafter may be referred to as a plurality of control signals CTRL11 to CTRLnn) and a plurality of data DATA11 to DATA1n, DATA21 to DATA2n, and DATAn1 to DATAnn (hereinafter may be referred to as a plurality of data DATA11 to DATAnn) to the memory 200 through a plurality of channels CH1, CH2 to CHn. For example, the memory controller 100 may provide the control signals CTRL11 to CTRL1n and the data DATA11 to DATA1n through the first channel CH1, and may provide the control signals CTRL21 to CTRL2n and the data DATA21 to DATA2n through the second channel CH2.

[0035] The memory controller 100 may control each of the memory cells MU11 to MUnn based on control signals respectively corresponding to the memory cells MU11 to MUnn. For example, the memory controller 100 may control the memory cell MU11 based on the control signal CTRL11 corresponding to the memory cell MU11, and may control the memory cell MU12 based on the control signal CTRL12 corresponding to the memory cell MU12. The memory controller 100 may control the memory cell MU21 based on the control signal CTRL21 corresponding to the memory cell MU21, and may control the memory cell MU22 based on the control signal CTRL22 corresponding to the memory cell MU22.

[0036] In an embodiment, the memory controller 100 may transmit a selection signal for the purpose of individually controlling the memory cells MU11 to MUnn. The selection signal may be a signal indicating one of the memory cells connected to a channel. For example, the memory controller 100 may control the memory cell MU11 based on the control signal CTRL11 and the selection signal indicating the memory cell MU11.

[0037] The memory controller 100 may store data in each of the memory cells MU11 to MUnn, and may read the stored data from each of the memory cells MU11 to MUnn. For example, the memory controller 100 may provide the control signal CTRL11 and the data DATA11 to the first channel CH1 to store the data DATA11 in the memory cell MU11. The memory controller 100 may provide the control signal CTRL21 to the second channel CH2 to store the data DATA21 in the memory cell MU21.

[0038] As described above, the memory system 1000 may include a plurality of memory cells that may operate in response to respective control signals. The memory controller 100 may individually manage the control signals regarding each memory cell. That is, the memory controller 100 may control each memory cell based on different control signals. The memory controller 100 may control each memory cell by transmitting different control signals to different channels. In addition, the memory controller 100 may control each memory cell by transmitting different control signals to one channel.

[0039] As Figure 1 shown, the memory controller 100 includes an error correction code (ECC) circuit 110, a codeword circuit 120, and a control circuit 130. The ECC circuit 110 may generate an input codeword CW’ by performing encoding on the data “DATA” provided from the host. The input codeword CW’ may be a data code added with an error correction code ECC.

[0040] The codeword circuit 120 may divide an input codeword CW' provided from the ECC circuit 110 into a plurality of segments SEG1 to SEGn. The codeword circuit 120 may divide the input codeword CW' according to a predetermined division rule.

[0041] The control circuit 130 may control each of the memory cells MU11 to MUnn based on control signals respectively corresponding to the memory cells MU11 to MUnn. For example, the control circuit 130 may store the first segment SEG1 in the memory cell MU11 based on the control signal CTRL11, and may store the second segment SEG2 in the memory cell MU12 based on the control signal CTRL12.

[0042] The control circuit 130 may distribute and store the segments SEG1 to SEGn in the memory cells MU11 to MUnn. In an embodiment, the control circuit 130 may distribute and store the segments SEG1 to SEGn in the memory cells connected to the same channel. For example, the control circuit 130 may store the segments SEG1 to SEGn in the memory cells MU11 to MU1n respectively. In another embodiment, the control circuit 130 may distribute and store the segments SEG1 to SEGn in the memory cells connected to different channels. For example, the control circuit 130 may store the segments SEG1 to SEGn in the memory cells MU11 to MUn1 respectively. In another embodiment, the control circuit 130 may store the segments SEG1 to SEGn in the memory cells MU11 to MUnn in any order.

[0043] The control circuit 130 may read the segments SEG1 to SEGn distributed and stored in the memory cells MU11 to MUnn based on the control signals respectively corresponding to the memory cells MU11 to MUnn.

[0044] The codeword circuit 120 may generate an output codeword CW based on the segments SEG1 to SEGn read from the memory cells MU11 to MUnn. The codeword circuit 120 may generate the output codeword CW according to a predetermined division rule. In an embodiment, the generated output codeword CW may include error bits generated during the process of writing the segments SEG1 to SEGn into the memory cells MU11 to MUnn or reading the segments SEG1 to SEGn from the memory cells MU11 to MUnn. In this way, the bits of the input codeword CW' may be different from the bits of the corresponding output codeword CW.

[0045] The ECC circuit 110 may perform error correction decoding (hereinafter referred to as "decoding") to correct errors in the generated output codeword CW. For example, the ECC circuit 110 may perform hard decision decoding. The data "DATA" output from the ECC circuit 110 may be provided to the host according to the result of the decoding. For example, in the case where the decoding result indicates that the decoding operation is successful, the ECC circuit 110 may provide the decoded codeword (i.e., the error-corrected codeword) to the host. The ECC circuit 110 may provide the decoding result to the control circuit 130.

[0046] The control circuit 130 may adjust the control signal corresponding to each of the memory cells MU11 to MUnn based on the decoding result from the ECC circuit 110. In an embodiment, the control circuit 130 may adjust the control signal based on the cumulative error pattern information corresponding to each of the memory cells MU11 to MUnn. The cumulative error pattern information may be cumulative information generated based on the error bits of the data output from the memory cell.

[0047] The control circuit 130 may adjust the control signal so that the number of error bits of the segmented data read from the memory cell is reduced. For example, since error bits may occur during the process of writing or reading the segment, the control circuit 130 may adjust the control signal so that the write voltage level or the read voltage level to be provided to the memory cell is changed. However, the inventive concept is not limited to adjusting the control signal to change the write and / or read voltage levels. For example, the control circuit 130 may adjust the control signal according to various conditions associated with the error bits.

[0048] According to the adjusted control signal, the control circuit 130 may store data in the memory cells MU11 to MUnn, or may read data from the memory cells MU11 to MUnn. Since the control signal is adjusted in such a way that the number of error bits of the segmented data read from the memory cell is reduced, the number of error bits of the output codeword CW generated based on the adjusted control signal will be reduced.

[0049] As described above, the memory system 1000 may adjust the control signal corresponding to each of the memory cells MU11 to MUnn so that the number of error bits of the data read from each of the memory cells MU11 to MUnn is reduced. In this way, the original raw bit error rate (RBER) of the memory system 1000 is reduced.

[0050] Figure 1The circuits 110 to 130 included in the memory controller 100 can be implemented in the form of software, hardware, or a combination thereof. In an embodiment, the software can be machine code, firmware, embedded code, and application software. For example, the hardware can include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, an integrated circuit core, a microelectromechanical system (MEMS), a passive component, or a combination thereof.

[0051] Figure 2 A block diagram of a Figure 1 memory controller according to an embodiment of the inventive concept is shown. Referring Figure 2 to, the memory controller 100 includes an ECC circuit 110, a codeword circuit 120, a control circuit 130, a bus 140, a processor 150, a random access memory (RAM) 160, a read only memory (ROM) 170, a host interface 180, and a memory interface 190.

[0052] Referring Figure 1 to, the operations of the ECC circuit 110, the codeword circuit 120, and the control circuit 130 are described, and thus additional descriptions will be omitted to avoid redundancy.

[0053] The bus 140 is configured to provide a channel between the components of the memory controller 100. The processor 150 can control the overall operation of the memory controller 100. For example, the ECC circuit 110, the codeword circuit 120, and the control circuit 130 can be driven by the processor 150.

[0054] The RAM 160 can be used as a buffer memory, a cache memory, or a working memory of the memory controller 100. The RAM 160 can store the code and commands executed by the processor 150, and can store the data processed by the processor 150. The RAM 160 can include a flash translation layer (FTL) 161. The FTL 161 can be software or firmware that performs various management operations between the host and the memory cells so that the memory cells can be effectively used. In an embodiment, the FTL 161 stored in the RAM 160 can be driven by the processor 150.

[0055] In an embodiment, the FTL 161 can assign one of the memory cells to each of the segments. In this way, the FTL 161 can manage the information about the memory cells corresponding to the segments. The control circuit 130 can store the segments in the assigned memory cells, or can read the segments from the assigned memory cells.

[0056] The ROM 170 can store various information required for the memory controller 100 to operate in the form of firmware. In Figure 2In the illustrated embodiment, the FTL 161 is included in the RAM 160. However, in other embodiments, the inventive concept is not limited thereto, and the FTL 161 may be included in the ROM 170.

[0057] The memory controller 100 may communicate with a host through the host interface 180. The memory controller 100 may communicate with the memory cells through the memory interface 190.

[0058] Reference will be made to Figures 3 to 11 describe more comprehensively Figure 1 the operation of the memory controller 100. For ease of description, it is assumed that each of the plurality of channels corresponds to one memory cell. That is, the operation of the memory controller 100 will be described based on an example in which the memory controller 100 controls one memory cell through one channel, but the inventive concept is not limited thereto. In addition, for ease of description, the operation of the memory controller 100 will be described based on an example in which the control circuit 130 adjusts a control signal so that the read voltage level to be provided to the memory cell changes, but the inventive concept is not limited thereto.

[0059] Figure 3 shows Figure 1 a schematic diagram of an example in which a memory system adjusts a control signal. Referring to Figure 3 , the memory system 1000 includes a memory controller 100 and a plurality of memory cells 210, 220 to 2nO (hereinafter may be referred to as memory cells 210 to 2nO). The memory controller 100 may control the memory cells 210 to 2nO based on a plurality of control signals CTRL1, CTRL2 to CTRLn (hereinafter may be referred to as control signals (CTRL1 to CTRLn)). Each of the memory cells 210 to 2nO may operate independently based on the corresponding control signal.

[0060] Each of the memory cells 210 to 2nO may store a corresponding segment among a plurality of segments SEG1, SEG2 to SEGn (hereinafter may be referred to as segments SEG1 to SEGn). For example, the first memory cell 210 may store the first segment SEG1, the second memory cell 220 may store the second segment SEG2, and the nth memory cell 2nO may store the nth segment SEGn.

[0061] The control circuit 130 may read the stored segments SEG1 to SEGn from the memory cells 210 to 2nO. The control circuit 130 may read the segments SEG1 to SEGn based on control signals corresponding to the read voltage levels of each of the memory cells 210 to 2nO. For example, the memory controller 100 may read the first segment SEG1 from the first memory cell 210 based on the control signal CTRL1 corresponding to the read voltage level L1, and may read the second segment SEG2 from the second memory cell 220 based on the control signal CTRL2 corresponding to the read voltage level L2. That is, the first memory cell 210 may output the first segment SEG1 by using the read voltage of the read voltage level L1 in response to the control signal CTRL1, and the second memory cell 220 may output the second segment SEG2 by using the read voltage of the read voltage level L2 in response to the control signal CTRL2. The read voltage level L1 may be different from the read voltage level L2.

[0062] The codeword circuit 120 may generate an output codeword CW based on the first segment SEG1 to the nth segment SEGn read as such.

[0063] The ECC circuit 110 may decode the output codeword CW. The ECC circuit 110 may determine success or failure as a result of decoding the output codeword CW. In an embodiment, in the case where a decoded codeword is generated by decoding the output codeword CW, the ECC circuit 110 may determine that the decoding is successful (i.e., the decoding is successful). In the case where no decoded codeword is generated by decoding the output codeword CW, the ECC circuit 110 may determine that the decoding has failed (i.e., the decoding has failed).

[0064] In the case of outputting the decoding result, the control circuit 130 may adjust the control signals CTRL1 to CTRLn based on the accumulated error pattern information AEPI of the error pattern information table 101. The control circuit 130 may adjust the control signal associated with a specific memory cell based on the accumulated error pattern information AEPI corresponding to the specific memory cell. For example, the error pattern information table 101 may be stored in Figure 2 the RAM 160 or the ROM 170. For example, the error pattern information table 101 may store the accumulated error pattern information AEPI1, AEPI2 to AEPIn for the memory cells 1, 2 to n (i.e., the memory cells 210, 220 to 2nO), respectively. As Figure 3As shown, the control circuit 130 may adjust the control signal CTRL2 based on, for example, the accumulated error pattern information AEPI2 corresponding to the second memory cell 220. The control circuit 130 may adjust the control signal CTRL2 such that the read voltage level L2 of the second memory cell 220 is changed to the read voltage level L2'. In this way, the control circuit 130 may control the second memory cell 220 based on the adjusted control signal CTRL2' instead of the control signal CTRL2. In the case where the adjusted control signal CTRL2' is transmitted or sent to the second memory cell 220, the second memory cell 220 may output the stored data by using the read voltage level L2'.

[0065] The control circuit 130 may manage the control signals CTRL1 to CTRLn corresponding to the memory cells 210 to 2nO based on the control signal management table 102. The control signal management table 102 may store the control signals corresponding to each of the memory cells 210 to 2nO. The control circuit 130 may adjust the control signals based on the accumulated error pattern information AEPI, and may update the control signals stored in the control signal management table 102 based on the adjusted control signals. Thereafter, the control circuit 130 may control the memory cells 210 to 2nO based on the adjusted control signals stored in the control signal management table 102. For example, the control signal management table 102 may be stored in Figure 2 the RAM 160 or the ROM170. For example, as Figure 3 shown, the control signal management table 102 may store the control signals CTRL1, the adjusted control signals CTRL2' to CTRLn for the memory cells 1, 2 to n (i.e., the memory cells 210, 220 to 2nO), respectively.

[0066] As Figure 3 shown, the control circuit 130 may adjust the control signal CTRL2 based on the accumulated error pattern information AEPI2, and may update the control signal CTRL2 corresponding to the second memory cell 220 in the control signal management table 102 based on the adjusted control signal CTRL2'. Thereafter, the control circuit 130 may control the second memory cell 220 based on the adjusted control signal CTRL2' stored in the control signal management table 102.

[0067] In an embodiment, the control circuit 130 may adjust all or part of the control signals CTRL1 to CTRLn according to the accumulated error pattern information AEPI. In this way, the control circuit 130 may update all or part of the control signals CTRL1 to CTRLn in the control signal management table 102.

[0068] Hereinafter, reference will be made toFigures 4 to 11 Describe the operation of the memory controller according to an embodiment of the inventive concept more comprehensively. Specifically, reference will be made to Figures 4 to 8 Describe the memory controller 100 according to the successfully decoded operation, and reference will be made to Figures 9 to 11 Describe the operation of the memory controller 100 according to the decoding failure.

[0069] Figure 4 Illustrates Figure 3 The block diagram of the memory controller according to the successfully decoded operation. Referring to Figure 4 , the memory controller 100 is shown to include an ECC circuit 110, a codeword circuit 120, a control circuit 130, an error mode information table 101, and a control signal management table 102.

[0070] In the case where the decoding result indicates success, the ECC circuit 110 may provide the decoding result "success" including the decoded codeword DCW ( Figure 4 ① of

[0071] to the control circuit 130. The control circuit 130 may receive the decoding result "success" including the decoded codeword DCW from the ECC circuit 110, and may receive the output codeword CW from the codeword circuit 120. The control circuit 130 may detect an error bit ( Figure 4 ② of

[0072] by comparing the output codeword CW with the decoded codeword DCW. The control circuit 130 may determine the memory cell where the detected error bit appears. Figure 4 The control circuit 130 may update the accumulated error pattern information AEPI ( Figure 5 ③ of

[0073] corresponding to the determined memory cell in the error mode information table 101 based on the detected error bit. Reference will be made to Figure 4 Figure 4 Figure 6 Figures 7A to 7C and Figures 7A to 7C Describe the operation of the control circuit 130 detecting the error bit and updating the error mode information table 101 more comprehensively.

[0074] When the updated accumulated error pattern information AEPI satisfies a preset condition, the control circuit 130 can refresh the data stored in the memory cells corresponding to the updated accumulated error pattern information AEPI without adjusting the control signal CTRL. That is, the control circuit 130 can rewrite the data stored in the memory cells. The control circuit 130 can refresh the memory cells by transmitting a control signal CTRL including a refresh command REF to the memory cells ( Figure 4 of ④-2). The control circuit 130 can initialize the accumulated error pattern information AEPI corresponding to the refreshed memory cells in the error pattern information table 101 ( Figure 4 of ⑤-2). Refer to Figure 8 for a more comprehensive description of the operation of the control circuit 130 to refresh the memory cells and initialize the accumulated error pattern information AEPI.

[0075] Figure 5 shows Figure 4 a schematic diagram of an example in which the memory controller of Figure 5 updates the error pattern information table based on successful decoding. Refer to

[0076] As Figure 5 shown, the control circuit 130 can detect error bits by comparing the bits of each segment SEG1 to SEGn of the output codeword CW with the bits of each segment DSEG1 to DSEGn of the decoded codeword DCW. The control circuit 130 can detect the second bit "0" and the third bit "0)" of the bit "0001" included in the second segment SEG2 of the output codeword CW as error bits (i.e., as error bits). The control circuit 130 can determine that the detected error bits are included in the segment SEG2. In this way, the control circuit 130 can determine that error bits occur at the second memory cell 220 (see Figure 3 ).

[0077] For example, the control circuit 130 can determine whether an error bit is included in any segment based on a predetermined partitioning rule used at the codeword circuit 120. Alternatively, the control circuit 130 can partition the output codeword CW and the decoded codeword DCW based on a predetermined partitioning rule, and the control circuit 130 can compare a specific segment of the output codeword CW with a specific segment of the decoded codeword DCW to determine the error bits included in the specific segment. Here, the specific segments of the output codeword CW and the decoded codeword DCW can correspond to each other.

[0078] The control circuit 130 can calculate the number of error bits and the bit error pattern information of each memory cell based on the determined error bits. In the case where the bits of the output codeword CW are decoded into different bit values, the bit error pattern information can be information about the number of errors corresponding to each of the bit error types. In an embodiment, the bit error types can include a first flip error FE1 and a second flip error FE2. In the first flip error FE1, the bit value "0" is flipped to a different bit value "1", and in the second flip error FE2, the bit value "1" is flipped to a different bit value "0". That is, when the first flip error FE1 occurs, the error bit "0" in the output codeword CW can be detected. In addition, when the second flip error FE2 occurs, the error bit "1" in the output codeword CW can be detected.

[0079] As Figure 5 shown, in the case where the second bit value "0" of the second segment SEG2 is decoded into a different bit value "1" (i.e., the second flip error FE2 occurs) and the third bit value "0" of the second segment SEG2 is decoded into a different bit value "1" (i.e., the second flip error FE2 occurs), the control circuit 130 can calculate the number of error bits of the second memory cell 220 as "2". In addition, the control circuit 130 can calculate the number of the second flip errors FE2 as the bit error pattern information. In Figure 5 this example, the number of the second flip errors FE2 can be "2".

[0080] The control circuit 130 can update the error pattern information table 101 based on the number of error bits calculated as such and the bit error pattern information calculated as such. As Figure 5 shown, the error pattern information table 101 can include the cumulative error bit count and the bit error pattern information. That is, the cumulative error pattern information AEPI can include the cumulative error bit count and the bit error pattern information.

[0081] As Figure 5As shown, before updating the error mode information table 101, the cumulative error bit count corresponding to the second memory cell 220 may be "3", the number of first flip errors FE1 may be "1", and the number of second flip errors FE2 may be "2". Accordingly, the control circuit 130 may update the cumulative error bit count corresponding to the second memory cell 220 from "3" to "5" based on the calculated number of error bits. The control circuit 130 may also update the number of second flip errors FE2 from "2" to "4" according to the calculation result.

[0082] Figure 5 Embodiments of illustrate the error mode information table 101 as including a cumulative error bit count and bit error mode information as cumulative error pattern information AEPI. However, other embodiments of the inventive concept are not limited thereto, and the error mode information table 101 may include, for example, various information associated with error bits.

[0083] Figure 6 shows Figure 4 a schematic diagram of an example of a memory controller of

[0082] that adjusts a control signal according to successful decoding. Referring to Figure 6 , the control circuit 130 may receive a decoding result "success" from the ECC circuit 110 and may update (e.g., as described with respect to Figure 5 ) the error mode information table 101. As shown in Figure 6 , the control circuit 130 may update the cumulative error bit count corresponding to the second memory cell 220 from "3" to "5" and may update the number of second flip errors FE2 from "2" to "4".

[0084] The control circuit 130 may determine whether the updated cumulative error bit count is not less than a first threshold and less than a second threshold. In a case where the updated cumulative error bit count is not less than the first threshold and less than the second threshold, the control circuit 130 may adjust the control signal of the associated memory cell. For example, the control circuit 130 may adjust the control signal to adjust the read voltage level of the associated memory cell. In this case, the first threshold may be a reference value for adjusting the read voltage level. The second threshold may be a reference value for performing any other operation (e.g., a refresh operation) without the control circuit 130 adjusting the control signal.

[0085] As Figure 6As shown, when the updated cumulative error bit count is "5", the first threshold is "4", and the second threshold is "9", the updated cumulative error bit count can be not less than the first threshold and can be less than the second threshold. In this case, the control circuit 130 can adjust the control signal CTRL2, thereby adjusting the read voltage level of the second memory cell 220. Thus, the control signal CTRL2 corresponding to the second memory cell 220 in the control signal management table 102 can be updated to the adjusted control signal CTRL2'. In an embodiment, during a read operation associated with the second memory cell 220, the control circuit 130 can read data from the second memory cell 220 by using the adjusted control signal CTRL2'.

[0086] The control circuit 130 can determine the direction and magnitude of adjusting the read voltage level based on the updated cumulative error bit count or the updated bit error pattern information. For example, the control circuit 130 can increase the magnitude of the read voltage level in a preset direction in proportion to the updated cumulative error bit count.

[0087] Hereinafter, reference will be made to Figures 7A to 7C to more comprehensively describe the operation of the control circuit 130 determining the direction and magnitude of adjusting the read voltage level based on the bit error pattern information.

[0088] Figure 7A 、 Figure 7B and Figure 7C are schematic diagrams showing examples of a control circuit determining a read voltage level according to an embodiment of the inventive concept. Specifically, Figure 7A shows an example of the control circuit 130 performing a read operation by using a first voltage V1. Figure 7B shows an example of the control circuit 130 performing a read operation by using a second voltage V2. Figure 7C shows an example of the control circuit 130 performing a read operation by using a third voltage V3. Referring to Figures 7A to 7C , a threshold voltage distribution of memory cells included in a memory cell is shown. In Figures 7A to 7C , the horizontal axis represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells. In Figures 7A to 7C , memory cells in the state "0" included in the first region A1 can be determined as memory cells in the state "1". Memory cells in the state "1" included in the second region A2 can be determined as memory cells in the state "0". That is, the first region A1 can be a region where a first flip error FE1 occurs, and the second region A2 can be a region where a second flip error FE2 occurs.

[0089] Referring to Figure 7A, in the case of performing a read operation based on the first voltage V1, since the size of the first region A1 is the same as the size of the second region A2, the number of first flip errors FE1 can be the same as the number of second flip errors FE2. In this case, the control circuit 130 can maintain the read voltage level. Therefore, the control circuit 130 can maintain the control signal corresponding to the memory cell.

[0090] Reference Figure 7B , in the case of performing a read operation based on the second voltage V2, since the size of the first region A1 is smaller than the size of the second region A2, the number of first flip errors FE1 that will occur in the first region A1 can be smaller than the number of second flip errors FE2 that will occur in the second region A2. In this case, the control circuit 130 can increase the read voltage level. That is, in the case where the number of first flip errors FE1 is smaller than the number of second flip errors FE2, the control circuit 130 can determine that the direction of adjusting the read voltage level is positive. The control circuit 130 can determine the amplitude of adjusting the read voltage level according to the difference between the number of first flip errors FE1 and the number of second flip errors FE2. Therefore, the control circuit 130 can adjust the control signal so that the read voltage level increases according to the determined adjustment amplitude.

[0091] Reference Figure 7C , in the case of performing a read operation based on the third voltage V3, since the size of the first region A1 is larger than the size of the second region A2, the number of first flip errors FE1 that will occur in the first region A1 can be larger than the number of second flip errors FE2 that will occur in the second region A2. In this case, the control circuit 130 can lower the read voltage level. That is, in the case where the number of first flip errors FE1 is larger than the number of second flip errors FE2, the control circuit 130 can determine that the direction of adjusting the read voltage level is negative. The control circuit 130 can determine the amplitude of adjusting the read voltage level according to the difference between the number of first flip errors FE1 and the number of second flip errors FE2. Therefore, the control circuit 130 can adjust the control signal so that the read voltage level decreases according to the determined adjustment amplitude.

[0092] In Figures 7A to 7C the embodiment, a single-level cell (SLC) storing one bit in the memory cell is illustrated. However, other embodiments of the inventive concept are not limited thereto. For example, the inventive concept can be applied to a multi-level cell (MLC) storing multiple bits in the memory cell. In this case, the control circuit 130 can adjust the control signal to adjust multiple read voltage levels.

[0093] As described above, the control circuit 130 can be based on as in Reference Figures 7A to 7CThe read voltage level is determined based on the bit error pattern information described above, and the control signal can be adjusted according to the determined read voltage level. However, the inventive concept is not limited thereto. For example, the control circuit 130 can obtain the read voltage level from the bit error pattern information through machine learning, and can adjust the control signal according to the obtained read voltage level.

[0094] Figure 8 shows Figure 4 a schematic diagram of an example in which a memory controller refreshes data of a memory cell according to successful decoding. Refer to Figure 8 , the control circuit 130 can receive the decoding result "success" from the ECC circuit 110, and can update the error pattern information table 101. As Figure 8 shown, the control circuit 130 can update the cumulative error bit count corresponding to the second memory cell 220 from "3" to "10".

[0095] The control circuit 130 can determine whether the updated cumulative error bit count is not less than a second threshold. In the case where the updated cumulative error bit count is not less than the second threshold, the control circuit 130 can refresh the data stored in the relevant memory cell. As Figure 8 shown, in the case where the updated cumulative error bit count (e.g., 10) is not less than the second threshold (e.g., 9), the control circuit 130 can provide the control signal CTRL2 including the refresh command REF to the second memory cell 220. The second memory cell 220 can perform a refresh operation in response to the refresh command REF. In this way, all the data stored in the second memory cell 220 can be rewritten.

[0096] In the case of rewriting the data of the second memory cell 220, the existing cumulative error pattern information AEPI associated with the second memory cell 220 may not be associated with the second memory cell 220. Therefore, the control circuit 130 can initialize the cumulative error pattern information AEPI corresponding to the second memory cell 220 in the error pattern information table 101. As Figure 8 shown, the control circuit 130 can initialize the cumulative error bit count corresponding to the second memory cell 220 to "0".

[0097] As described above, when the decoding result indicates success, the memory controller 100 may adjust control signals corresponding to memory cells based on the accumulated error pattern information AEPI. The memory controller 100 may adjust the control signals based on the decoding results of the memory cells, thereby adjusting the read voltage levels of the memory cells. As a result, the number of error bits in the data output from the memory cells is reduced, and the probability of decoding failure is decreased. That is, the raw bit error rate (RBER) of the memory system 1000 is decreased.

[0098] In addition, when the accumulated error bit count is not less than a preset value, the memory controller 100 may refresh data of related memory cells. As a result, the reliability of the data stored in the refreshed memory cells is improved.

[0099] Figure 9 illustrates Figure 3 a block diagram of operations of a memory controller according to decoding failure. Refer to Figure 9 , the memory controller 120 is shown to include an ECC circuit 110, a codeword circuit 120, a control circuit 130, an error pattern information table 101, and a control signal management table 102.

[0100] When the decoding result associated with the output codeword CW indicates failure (i.e., decoding failure), the control circuit 130 may receive the decoding result "failure" from the ECC circuit 110 ( Figure 9 ① of ). The control circuit 130 may adjust the control signal CTRL ( Figure 9 ② of ) based on the accumulated error pattern information AEPI in the error pattern information table 101 ( Figure 9 ③ of ). In an embodiment, the control circuit 130 may adjust the control signal CTRL of the memory cells corresponding to the accumulated error pattern information AEPI that meets a preset condition. The control circuit 130 may update the control signal management table 102 according to the adjusted control signal ( Figure 9 ④ of ). The operation of the control circuit 130 adjusting the control signal CTRL based on decoding failure will be described more comprehensively with reference to Figure 10 .

[0101] The control circuit 130 may re-read the segment SEG stored in the memory cells based on the adjusted control signal CTRL ( Figure 9 ⑤ of ). In an embodiment, the control circuit 130 may re-read only the segment SEG stored in the memory cells corresponding to the adjusted control signal among the segments SEG1 to SEGn stored in the memory cells 210 to 2n0. That is, only the segments stored in some of the memory cells among the memory cells 210 to 2n0 may be re-read. Refer to Figure 10Describe more comprehensively the operation of the control circuit 130 to re-read the segmented SEG stored in the memory cell based on the adjusted control signal.

[0102] The codeword circuit 120 can generate a new output codeword NCW based on the re-read segmented SEG ( Figure 9 ⑥). In an embodiment, in the case of only re-reading the segments stored in some memory cells, the codeword circuit 120 can generate a new output codeword NCW based on the re-read segments and the previously read segments. The ECC circuit 110 can perform decoding on the new output codeword NCW ( Figure 9 ⑦). Reference will be made to Figure 11 Describe more comprehensively the operation of the codeword circuit 120 to generate a new output codeword NCW and the operation of the ECC circuit 110 to perform decoding on the new output codeword NCW.

[0103] Figure 10 Illustrates Figure 9 A schematic diagram of an example of a memory controller re-reading segments according to decoding failure. Refer to Figure 10 , the control circuit 130 can receive the decoding result "failure" from the ECC circuit 110 based on the decoding failure. In response to the decoding result "failure", the control circuit 130 can determine whether the cumulative error bit count corresponding to each memory cell in the memory cells 210 to 2nO is less than a first threshold. In the case where the cumulative error bit count is not less than the first threshold (as described in reference Figure 6 ), the control signal of the relevant memory cell can be a pre-adjusted control signal. Thus, in the case where the cumulative error bit count is less than the first threshold, the control circuit 130 can adjust the control signal of the relevant memory cell. For example, the first threshold can be the same as the Figure 6 first threshold. The control circuit 130 can update the control signal management table 102 according to the adjusted control signal.

[0104] As Figure 10 shown, in the error mode information table 101, the cumulative error bit count corresponding to the first memory cell 210 can be "3", the cumulative error bit count corresponding to the second memory cell 220 can be "6", and the cumulative error bit count corresponding to the nth memory cell 2nO can be "5" (see Figure 3the memory cells 210, 220, and 2nO). The control circuit 130 can determine whether the cumulative error bit count corresponding to each of the memory cells 210 to 2nO is less than a first threshold. In the case where the cumulative error bit count corresponding to the first memory cell 210 is "3" and the first threshold is "4", the cumulative error bit count corresponding to the first memory cell 210 is less than the first threshold. In this case, the control circuit 130 can adjust the control signal CTRL1 of the first memory cell 210. As Figure 10 shown, the control circuit 130 can adjust the control signal CTRL1 such that the first memory cell 210 performs a read operation based on the adjusted read voltage level L1'. The control circuit 130 can update the control signal management table 102 according to the adjusted control signal CTRL1'.

[0105] In an embodiment, the control circuit 130 can determine the read voltage level L1' corresponding to the first memory cell 210 based on the cumulative error bit count or the bit error pattern information. As Figure 10 shown, regarding the first memory cell 210, the number of the first flip errors FE1 can be "3", and the number of the second flip errors FE2 can be "0". The control circuit 130 can determine the read voltage level L1' based on the number of the first flip errors FE1 and the number of the second flip errors FE2 associated with the first memory cell 210. As Figures 7A to 7C shown, since the number of the first flip errors FE1 is greater than the number of the second flip errors FE2, the control circuit 130 can determine the read voltage level L1', or in other words, adjust the read voltage level L1' in one direction such that the amplitude of the read voltage level L1' decreases. The control circuit 130 can determine the decrement based on the difference between the number of the first flip errors FE1 and the number of the second flip errors FE2.

[0106] The control circuit 130 can re - read segments from the memory cells based on the adjusted control signal. In an embodiment, the control circuit 130 can only re - read the segments SEG1 to SEGn stored in the memory cells 210 to 2n0 that are associated with the memory cell corresponding to the adjusted control signal. As Figure 10 shown, the control circuit 130 can re - read the first segment SEG1 from the first memory cell 210 based on the adjusted control signal CTRL1'. In response to the adjusted control signal CTRL1', the first memory cell 210 can output the first segment SEG1 by using the read voltage of the read voltage level L1'.

[0107] Figure 11 shows Figure 9Schematic diagram of an example in which a memory controller performs decoding again according to a decoding failure. Refer to Figure 11 , the codeword circuit 120 may generate a new output codeword NCW based on the first segment SEG1 read again from the first memory cell 210. The codeword circuit 120 may generate a new output codeword NCW based on the re-read first segment SEG1 and the previously read second segment SEG2 to nth segment SEGn.

[0108] The ECC circuit 110 may perform decoding on the new output codeword NCW and may output a decoding result. In the case where the decoding result indicates success, the control circuit 130 may operate as described in reference Figures 4 to 8 . In an embodiment, the control circuit 130 may detect an error bit by comparing the decoded codeword DCW with the new output codeword NCW. The control circuit 130 may update the accumulated error pattern information AEPI in the error pattern information table 101 based on the detected error bit. The control circuit 130 may adjust the control signal based on the accumulated error pattern information AEPI and may update the control signal management table 102 based on the adjusted control signal. Alternatively, the control circuit 130 may refresh the segments SEG1 to SEGn stored in the memory cells 210 to 2n0 based on the decoded codeword DCW. That is, the control circuit 130 may rewrite the segments SEG1 to SEGn according to the decoded codeword DCW in which the error bit has been corrected.

[0109] In the case where the decoding result indicates failure, the control circuit 130 may determine that the read operation has failed.

[0110] As described above, in the case where the decoding result indicates failure, the control circuit 130 may adjust the control signal and may re-read the segment based on the adjusted control signal. In this case, the number of error bits of the re-read segment will decrease. Therefore, the probability of successful decoding of the new output codeword NCW generated based on the re-read segment will increase. In addition, the control circuit 130 may not re-read all the segments SEG1 to SEGn stored in the memory cells 210 to 2nO, but the control circuit 130 may only re-read the segment stored in the memory cell corresponding to the adjusted control signal. Therefore, the increase in read latency can be minimized and the power consumption can be reduced.

[0111] Figure 12 Flowchart showing the operation of a memory controller according to an embodiment of the inventive concept. Refer to Figure 3 and Figure 12, in operation S101, the memory controller 100 receives (i.e., reads) a plurality of segments SEG1 to SEGn from a plurality of memory cells 210 to 2nO based on a plurality of control signals CTRL1 to CTRLn. In operation S102, the memory controller 100 generates an output codeword CW based on the plurality of segments SEG1 to SEGn. In operation S103, the memory controller 100 performs error correction decoding on the output codeword CW and generates a decoding result.

[0112] In operation S104, the memory controller 100 adjusts the plurality of control signals CTRL1 to CTRLn based on the decoding result and based on the accumulated error pattern information AEPI corresponding to each of the plurality of memory cells 210 to 2nO. In an embodiment, the memory controller 100 may adjust at least one of the plurality of control signals CTRL1 to CTRLn based on at least one of the plurality of accumulated error pattern information AEPI corresponding to the plurality of memory cells 210 to 2nO.

[0113] Figure 13 FIG. shows a flowchart of operations corresponding to a case where decoding by a memory controller is successful according to an embodiment of the inventive concept. Refer to Figure 4 and Figure 13 , in operation S111, the memory controller 100 detects error bits by comparing the output codeword CW with the decoded codeword DCW. In operation S112, the memory controller 100 updates the accumulated error pattern information AEPI in the error pattern information table 101 based on the detected error bits.

[0114] In operation S113, the memory controller 100 determines whether the updated accumulated error bit count of the updated accumulated error pattern information AEPI is not less than a first threshold. In the case where the updated accumulated error bit count is not less than the first threshold ("Yes" in S113), in operation S114, the memory controller 100 determines whether the updated accumulated error bit count is not less than a second threshold. In the case where the updated accumulated error bit count is less than the second threshold ("No" in S114), in operation S115, the memory controller 100 adjusts the control signal associated with the memory cell corresponding to the updated accumulated error pattern information AEPI.

[0115] When the updated cumulative error bit count is not less than the second threshold (Yes in S114), in operation S116, the memory controller 100 refreshes the data stored in the memory cells corresponding to the updated cumulative error pattern information AEPI. That is, all the data stored in the corresponding memory cells can be rewritten. In operation S117, the memory controller 100 initializes the cumulative error pattern information AEPI corresponding to the refreshed memory cells. For example, the cumulative error bit count corresponding to the refreshed memory cells can be initialized. When the updated cumulative error bit count is less than the first threshold (No in S113), the operation ends.

[0116] Figure 14 FIG. shows a flowchart of operations corresponding to a case where a memory controller decoding fails according to an embodiment of the inventive concept. Refer to Figure 9 and Figure 14 , in operation S121, the memory controller 100 determines whether the cumulative error bit count in the cumulative error pattern information AEPI corresponding to each of the memory cells 210 to 2nO is less than the first threshold. When the cumulative error bit count of the corresponding memory cell is less than the first threshold (Yes in S121), in operation S122, the memory controller 100 adjusts a control signal associated with the memory cell corresponding to the cumulative error pattern information AEPI. In operation S123, the memory controller 100 rereads segments from the associated (i.e., corresponding) memory cell based on the adjusted control signal. In operation S124, the memory controller 100 generates a new output codeword NCW based on the reread segments. In operation S125, the memory controller 100 performs error correction decoding on the new output codeword NCW. When the cumulative error bit count corresponding to each memory cell is not less than the first threshold (No in S121), the operation ends.

[0117] Figure 15 FIG. shows a block diagram of an application of a memory system according to an embodiment of the inventive concept. Refer to Figure 15 , the computer system 2000 includes a host 2100, a user interface 2200, a storage module 2300, a network module 2400, a memory module 2500, and a system bus 2600.

[0118] The host 2100 may drive components and an operating system included in the computer system 2000. In an embodiment, the host 2100 may include, for example, a controller, an interface, a graphics engine, etc. to control components of the computer system 2000. For example, the host 2100 may be implemented using a system-on-chip (SoC).

[0119] The user interface 2200 may include an interface for inputting data or instructions into the host 2100 or outputting data to an external device. In an embodiment, the user interface 2200 may include a user input interface such as a keyboard, keypad, button, touchpad, touch screen, touch pad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric sensor, etc. The user interface 2200 may also particularly include interfaces such as the following: liquid crystal display (LCD), organic light emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, light emitting diode (LED), speaker, and motor.

[0120] The storage module 2300 may store data. For example, the storage module 2300 may store data received from the host 2100. Alternatively, the storage module 2300 may transfer the data stored therein to the host 2100. In an embodiment, the storage module 2300 may be implemented with a non-volatile memory system such as electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), or thyristor RAM (TRAM), etc. The storage module 2300 may include the memory system according to an embodiment of the inventive concept described with reference to Figures 1 to 14 the present invention.

[0121] The network module 2400 may communicate with an external device. In an embodiment, the network module 2400 may support wireless communication such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE TM ), worldwide interoperability for microwave access (Wimax), wireless LAN (WLAN), ultra wideband (UWB), Bluetooth, and wireless display (WI-DI).

[0122] The storage module 2500 may operate as a main memory, working memory, buffer memory, or cache memory of the computer system 2000. The memory module 2500 may include a volatile memory system (e.g., DRAM or SRAM), or a non-volatile memory system (e.g., NAND flash memory, NOR flash memory, PRAM, RoRAM, FeRAM, MRAM, or TRAM). The memory module 2500 may include the memory system according to an embodiment of the inventive concept described with reference to Figures 1 to 14 the present invention.

[0123] The system bus 2600 can electrically connect the host 2100, the user interface 2200, the storage module 2300, the network module 2400, and the memory module 2500 to each other.

[0124] According to the inventive concept, a memory controller and a memory system that can prevent an error correction failure in performing an error correction on data can be provided.

[0125] In addition, a memory controller and a memory system that can increase the probability of successful error correction and can minimize power consumption in a case where the error correction is performed again after an error correction failure can be provided.

[0126] Although the inventive concept has been described with reference to exemplary embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A method for operating a memory controller that individually controls multiple memory units, the method comprising: reading, by the memory controller, respective segments from the multiple memory units based on multiple control signals; generating, by the memory controller, an output codeword based on the segments; performing error correction decoding on the output codeword by the memory controller; when the result of the error correction decoding indicates success, updating, by the memory controller, at least one of multiple cumulative error pattern information respectively corresponding to the multiple memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, adjusting, by the memory controller, at least one of the multiple control signals based on at least one of the multiple cumulative error pattern information; wherein updating at least one of the multiple cumulative error pattern information when the result of the error correction decoding indicates success includes: comparing the output codeword with a decoded codeword generated according to the error correction decoding to detect an error bit corresponding to a first memory unit among the multiple memory units; updating, based on the detected error bit, a first cumulative error pattern information corresponding to the first memory unit among the multiple cumulative error pattern information, and when an updated first cumulative error bit count of the updated first cumulative error pattern information is not less than a first threshold and less than a second threshold, adjusting, by the memory controller, a control signal corresponding to the first memory unit among the multiple control signals.

2. The method according to claim 1, further comprising: when the updated first cumulative error bit count is not less than the second threshold, refreshing, by the memory controller, data stored in the first memory unit; and initializing the updated first cumulative error pattern information.

3. The method according to claim 1, wherein, When the result of the error correction decoding indicates failure and a second cumulative error bit count of a second cumulative error pattern information corresponding to a second memory unit among the multiple memory units is less than the first threshold, adjusting, by the memory controller, a second control signal corresponding to the second memory unit among the multiple control signals.

4. The method according to claim 3, further comprising: re - reading, by the memory controller, one of the segments from the second memory unit based on the adjusted second control signal corresponding to the second memory unit; generating a new output codeword based on the re - read segment; and performing the error correction decoding on the new output codeword.

5. The method according to claim 1, wherein Each of the multiple memory units includes one of the following: a memory device, a memory chip, a memory die, a memory bank, a memory block, and memory cells connected to a word line.

6. The method according to claim 1, further comprising: performing, by the memory controller, error correction encoding on data provided from a host to generate an input codeword added with an error correction code; The input codeword is partitioned by the memory controller to generate the segments; and the segments are stored in the plurality of memory cells by the memory controller based on the plurality of control signals.

7. A memory controller, comprising: a codeword circuit configured to generate an output codeword based on a first segment read from a first memory cell according to a first control signal and a second segment read from a second memory cell according to a second control signal; an error correction code (ECC) circuit configured to perform error correction decoding on the output codeword; and a control circuit configured to operate according to the result of the error correction decoding, wherein the control circuit is configured to adjust at least one of the first control signal and the second control signal based on at least one of first cumulative error pattern information corresponding to the first memory cell and second cumulative error pattern information corresponding to the second memory cell, and wherein when the result of the error correction decoding indicates success: the ECC circuit is configured to generate a decoded codeword, and the control circuit is further configured to: compare the output codeword with the decoded codeword, when at least one error bit is detected from the bits corresponding to the first segment based on the result of the comparison, update the first cumulative error pattern information based on the at least one error bit, and when the updated first cumulative error bit count of the updated first cumulative error pattern information is not less than a first threshold and less than a second threshold, adjust the first control signal.

8. The memory controller according to claim 7, wherein, When the updated first cumulative error bit count is not less than the second threshold, the control circuit is configured to refresh the data stored in the first memory cell and initialize the updated first cumulative error pattern information.

9. The memory controller according to claim 7, wherein, When the result of the error correction decoding indicates failure and the first cumulative error bit count of the first cumulative error pattern information is less than the first threshold, the control circuit is configured to adjust the first control signal.

10. The memory controller according to claim 9, wherein, When the result of the error correction decoding indicates failure, the control circuit is further configured to re-read the first segment from the first memory cell based on the adjusted first control signal, the codeword circuit is further configured to generate a new output codeword based on the re-read first segment and the second segment, and the ECC circuit is further configured to perform the error correction decoding on the new output codeword.

11. The memory controller according to claim 7, wherein, The control circuit is configured to: determine at least one of a first read voltage level of the first memory cell and a second read voltage level of the second memory cell based on at least one of the first cumulative error pattern information and the second cumulative error pattern information; and adjust at least one of the first control signal and the second control signal based on at least one of the determined first read voltage level and the second read voltage level.

12. The memory controller according to claim 11, wherein, The first cumulative error pattern information includes first bit error pattern information, and the first bit error pattern information indicates pattern information of a first bit error in which a first bit value read from the first memory cell is decoded into a bit value different from the first bit value. Wherein, the second cumulative error pattern information includes second bit error pattern information, and the second bit error pattern information indicates pattern information of a second bit error in which a second bit value read from the second memory cell is decoded into a bit value different from the second bit value, and Wherein, the control circuit is configured to adjust at least one of the first read voltage level and the second read voltage level based on at least one of the first bit error pattern information and the second bit error pattern information.

13. A memory system, comprising: A first memory cell configured to operate in response to a first control signal; A second memory cell configured to operate in response to a second control signal; And A memory controller configured to read a first segment from the first memory cell based on the first control signal and read a second segment from the second memory cell based on the second control signal, Wherein, the memory controller includes: A codeword circuit configured to generate an output codeword based on the first segment and the second segment, An error correction code (ECC) circuit configured to perform error correction decoding on the output codeword, and A control circuit configured to operate according to a result of the error correction decoding, Wherein, the control circuit is configured to adjust at least one of the first control signal and the second control signal based on at least one of first cumulative error pattern information corresponding to the first memory cell and second cumulative error pattern information corresponding to the second memory cell, and Wherein, when the result of the error correction decoding indicates success: The ECC circuit is configured to generate a decoded codeword, and The control circuit is further configured to: Compare the output codeword with the decoded codeword, When at least one error bit is detected from bits corresponding to the first segment based on a result of the comparison, update the first cumulative error pattern information based on the at least one error bit, and When an updated first cumulative error bit count of the updated first cumulative error pattern information is not less than a first threshold and less than a second threshold, adjust the first control signal.

14. The memory system according to claim 13, wherein, When the result of the error correction decoding indicates failure and a first cumulative error bit count of the first cumulative error pattern information is less than the first threshold, the control circuit is configured to adjust the first control signal.

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