Power semiconductor module

Abstract

The application discloses a power semiconductor module, comprising a lead frame, a first chip, a second chip, a wire and a mold body, the lead frame comprises a first patch area, a second patch area, a first pin connected with the first patch area and a second pin connected with the second patch area, the first chip is attached to the first patch area, and the second chip is attached to the second patch area; the first chip, the second chip, the first pin and the second pin are connected through the wire; the first patch area, the second patch area, the first chip, the second chip, one end of the first pin connected with the first patch area and one end of the second pin connected with the second patch area are all encapsulated in the mold body, and the surface of the first patch area attached with the first chip is lower than the surface of the second patch area attached with the second chip. The power semiconductor module has the advantages of simplified process, reduced equipment cost, improved product yield and good heat dissipation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to the field of packaging manufacturing of power semiconductor modules. Background Technology

[0002] Traditional smart power semiconductor modules consist of a driver chip, a power chip, a copper-clad ceramic substrate, and a lead frame. The driver chip is typically fixed to the lead frame with silver paste, while the power chip is attached to the copper-clad ceramic substrate with solder paste. The copper-clad ceramic substrate is also connected to the lead frame with solder paste. Smart power semiconductor modules made using this connection method have the following drawbacks:

[0003] 1. Solder paste needs to be heated to melt and then cooled to solidify before it can function as a soldering agent. However, the melting process generates air bubbles, necessitating reflow soldering in a vacuum environment to reduce these bubbles. But in a vacuum, flux evaporates onto the chip and pin surfaces, affecting the reliability of subsequent solder lines. Therefore, a flux cleaning process is required after soldering. This increases the number of processes and related equipment. Furthermore, each additional process step introduces a certain defect rate, leading to a decrease in product yield.

[0004] 2. Poor thermal conductivity of solder paste may cause chip failure during customer applications because the heat generated by the chip cannot be dissipated in time. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention discloses a power semiconductor module to solve the problems of complex processes and high equipment costs caused by the need for reflow soldering in a vacuum equipment and flux cleaning after soldering when using solder paste in existing power semiconductor modules.

[0006] This invention is achieved using the following technical solution:

[0007] A power semiconductor module includes a lead frame, a first chip, a second chip, wires, and a molded enclosure. The lead frame includes a first surface mount area, a second surface mount area disposed on one side of the first surface mount area, a first pin disposed on the side of the first surface mount area away from the second surface mount area and connected to the first surface mount area, and a second pin connected to the second surface mount area. The first chip is mounted on the first surface mount area, and the second chip is mounted on the second surface mount area. The first chip, the second chip, the first pin, and the second pin are connected through the wires. The first surface mount area, the second surface mount area, the first chip, the second chip, the end of the first pin connected to the first surface mount area, and the end of the second pin connected to the second surface mount area are all encapsulated within the molded enclosure. The surface of the first surface mount area on which the first chip is mounted is lower than the surface of the second surface mount area on which the second chip is mounted.

[0008] As an improvement, the side of the lead frame on which the first chip and the second chip are attached is defined as the top surface, and the side opposite to the top surface is defined as the bottom surface. The lead frame also includes a bending connection portion. The first and second patch areas are arranged parallel to each other in a direction perpendicular to the top surface. The bending connection portion bends from the first pin toward the bottom surface and connects to the first patch area. The bottom of the first chip is fixed to the first patch area by solder wire.

[0009] As an improvement, the distance between the surface of the second patch area where the second chip is attached and the surface of the first patch area where the first chip is attached is 900±50um.

[0010] As an improvement, the mold body is divided into an upper mold body located on the top side and a lower mold body located on the bottom side, with the lead frame as the boundary. The upper mold body is provided with a through groove corresponding to the first patch area.

[0011] As an improvement, the through slot is located on the side of the first patch area near the second patch area, or the through slot is located on the side of the first patch area near the first pin.

[0012] As an improvement, the distance from the side of the lower mold seal away from the first patch area to the first patch area is 500±50um.

[0013] As an improvement, the distance from the side of the upper mold body away from the first patch area to the first patch area is 2500±50um.

[0014] As an improvement, the first surface mount area includes a first surface mount pad, a second surface mount pad, a third surface mount pad, and a fourth surface mount pad. The first surface mount pad, the second surface mount pad, the third surface mount pad, and the fourth surface mount pad are arranged side by side with intervals. There are twelve first chips. Six first chips are mounted on the first surface mount pad, and two first chips are mounted on each of the second surface mount pad, the third surface mount pad, and the fourth surface mount pad. The twelve first chips are arranged in an array in the first surface mount area.

[0015] As an improvement, the mold sealing body is provided with shrinkage ejector pin positions arranged along the edge of the through groove on both the front and back sides.

[0016] The total number of the first pin and the second pin is 25 or 26, and the length of the first pin and the second pin is 14mm, 11.7mm or 9.5mm.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] The power semiconductor module disclosed in this invention eliminates the copper-clad ceramic plate compared to existing power semiconductor modules. This eliminates the process step of fixing the copper-clad ceramic plate to the lead frame with solder paste, avoiding the reflow soldering process in vacuum equipment and the flux cleaning process after solder paste soldering. This simplifies the process and reduces the cost of related equipment. Moreover, by eliminating the process steps related to solder paste soldering, it avoids the occurrence of defective products in these process steps, thereby improving the product yield. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the power semiconductor module from the front view as disclosed in Embodiment 1 of the present invention;

[0020] Figure 2 This is a schematic diagram of the power semiconductor module from the rear view as disclosed in Embodiment 1 of the present invention;

[0021] Figure 3 This is a schematic diagram showing the interaction of the lead frame, first chip, second chip, wire, first pin, and second pin as disclosed in Embodiment 1 of the present invention.

[0022] Figure 4 Here is a schematic diagram of section AA in section 3;

[0023] Figure 5 for Figure 4 Enlarged view of a portion of point B in the middle;

[0024] Figure 6This is a schematic diagram of the structure of the first patch area, the second patch area, the first chip, the second chip, and the wires in the prior art;

[0025] Figure 7 This is a schematic diagram of the structure of the first patch area, the second patch area, the first chip, the second chip, and the wires disclosed in Embodiment 1 of the present invention.

[0026] Figure 8 This is a partial cross-sectional schematic diagram of the power semiconductor module disclosed in Embodiment 1 of the present invention;

[0027] Figure 9 This is a partial cross-sectional schematic diagram of the power semiconductor module disclosed in Embodiment 4 of the present invention. Detailed Implementation

[0028] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0029] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0030] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0031] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0032] Example 1:

[0033] Please see Figure 1-8Embodiment 1 of the present invention discloses a power semiconductor module 100, including a lead frame 10, a first chip 20, a second chip 30, a wire 40, and a molded body 50. The lead frame 10 includes a first surface mount area 11, a second surface mount area 12 disposed on one side of the first surface mount area 11, a first pin 13 disposed on the side of the first surface mount area 11 away from the second surface mount area 12 and connected to the first surface mount area 11, and a second pin 14 connected to the second surface mount area 12. The first chip 20 is disposed on the first surface mount area 11, and the second chip 30 is disposed on the side of the first surface mount area 11 away from the second surface mount area 12 and connected to the first surface mount area 11. Chip 30 is attached to the second chip area 12; the first chip 20, the second chip 30, the first pin 13 and the second pin 14 are connected by wires 40; the first chip area 11, the second chip area 12, the first chip 20, the second chip 30, the end of the first pin 13 connected to the first chip area 11, and the end of the second pin 14 connected to the second chip area 12 are all encapsulated in the mold body 50, and the surface of the first chip 20 attached to the first chip area 11 is lower than the surface of the second chip 30 attached to the second chip area 12.

[0034] Preferably, both the first surface mount area 11 and the second surface mount area 12 are copper sheets. The bottom of the first chip 20 is fixed to the first surface mount area 11 by solder wire, and the bottom of the second chip 30 is fixed to the second surface mount area 12 by silver paste. The molding body 50 is an epoxy resin molding body. Preferably, the first chip 20 is a power chip, the second chip 30 is a driver chip, and the operating current of the first chip 20 is greater than the operating current of the second chip 30.

[0035] The power semiconductor module 100 disclosed in this embodiment eliminates the copper-clad ceramic plate compared to existing power semiconductor modules. This eliminates the process step of fixing the copper-clad ceramic plate to the lead frame with solder paste, avoiding the reflow soldering process in vacuum equipment and the flux cleaning process after solder paste soldering. This simplifies the process and reduces the cost of related equipment. Moreover, by eliminating the process steps related to solder paste soldering, it avoids the occurrence of defective products in these process steps, thereby improving the product yield.

[0036] In this embodiment, the first chip 20 is fixed to the first surface mount area 11 by solder wire. Compared with solder paste soldering, heat dissipation is better because the thermal conductivity of solder paste is about 50 W / m*K, while the thermal conductivity of solder wire is about 67 W / m*K, which is about 34% higher. In this embodiment, the first chip 20 is soldered by solder wire, which has a good heat dissipation effect and greatly reduces the risk of chip failure caused by heat accumulation in a short time, thus improving the reliability of the product.

[0037] The side of the lead frame 10 on which the first chip 20 and the second chip 30 are attached is defined as the top surface 101, and the side opposite to the top surface 101 is defined as the bottom surface 102. The mold body 50 includes an upper mold body 51 located on the top surface 101 and a lower mold body 52 located on the bottom surface 102, with the lead frame 10 as the boundary.

[0038] During the wire bonding process, to prevent the wire 40 from contacting the edges of the first chip 20 and the second chip 30, thus causing a short circuit, the arc height of the wire 40 is subject to certain requirements. When the first chip 20 and the second chip 30 are on the same plane, the arc height of the wire 40 needs to be designed to be relatively high. However, the mold enclosure 50 needs to encapsulate the wire 40 within its body, resulting in a relatively thick mold enclosure 50.

[0039] In this embodiment, by setting the surface of the first patch area 11 where the first chip 20 is attached to to be lower than the surface of the second patch area 12 where the second chip 30 is attached, that is, by setting the first patch area 11 to be recessed by a predetermined height relative to the second patch area 12, the arc height of the wire 40 connecting the first patch area 11 and the second patch area 12 can be effectively reduced, thereby reducing the overall thickness of the molded body 50, making it easier for customers to use and adapting to market demands. Furthermore, the reduction in the top surface of the upper molded body 51 decreases the thickness of the upper molded body 51 opposite to the second patch area 12, thereby reducing the material used in the molded body 50 and lowering costs. It should be noted that the thickness of the upper molded body 51 opposite to the second patch area 12 can theoretically be reduced to the point where the wire 40 is not exposed.

[0040] like Figure 6 As shown, in existing power semiconductor modules, the first surface mount area 11' and the second surface mount area 12' are set on the same horizontal plane. When the wire 40' connects the first chip 20' and the second chip 30', the arc of the middle part 40a of the wire 40' is relatively high. During the wire bonding process, the middle part 40a of the wire 40' is prone to collapse.

[0041] In this embodiment, since the first patch area 11 is lowered by a predetermined height relative to the second patch area 12, the arc height of the wire 40 connecting the first patch area 11 and the second patch area 12 is reduced, which can effectively prevent the middle of the wire 40 from collapsing due to being too high, and improve the reliability of the wire bonding.

[0042] The lead frame 10 also includes a bending connection portion 15. The first patch area 11 and the second patch area 12 are arranged parallel to each other in a direction perpendicular to the top surface 101. The bending connection portion 15 bends from the first pin 13 toward the bottom surface 102 and connects to the first patch area 11.

[0043] As an improvement to this embodiment, the distance between the surface of the second patch area 12 where the second chip 30 is attached and the surface of the first patch area 11 where the first chip 20 is attached is S, where S = 900 ± 50 μm. That is, the sinking depth of the first patch area 11 relative to the second patch area 12 is 900 ± 50 μm.

[0044] Preferably, the rated power of the power semiconductor module in this embodiment is less than 6KW. Within this rated power, the high-power chip surface mount area is recessed to be closer to the surface of the mold, thereby enhancing the heat dissipation effect. Combined with the heat dissipation characteristics of epoxy resin itself, the heat dissipation requirements of this type of power semiconductor module can be met.

[0045] As an improvement to this embodiment, the first mounting area 11 includes a first mounting pad 11A, a second mounting pad 11B, a third mounting pad 11C, and a fourth mounting pad 11D. The first mounting pads 11A, 11B, 11C, and 11D are arranged side-by-side with intervals. Twelve first chips 20 are provided. Six first chips are mounted on the first mounting pad 11A, and two first chips 20 are mounted on each of the second, 11B, 11C, and 11D. The twelve first chips 20 are arranged in an array in the first mounting area 11. Specifically, the twelve first chips 20 are arranged in two rows and six columns in the first mounting area 11. This design simplifies the manufacturing process of the first chips 20 and reduces the manufacturing difficulty by arranging the twelve first chips 20 in an array in the first mounting area 11.

[0046] As an improvement to this embodiment, the upper mold seal 51 is provided with a through groove 511 corresponding to the first patch area 11. In this embodiment, during injection molding, the mold seal 50 is provided with a glue inlet on the side of the mold corresponding to the upper mold seal 51 and the side of the mold corresponding to the lower mold seal 52. Since the first patch area 11 is recessed by a predetermined height relative to the second patch area 12, the distance from the surface of the upper mold seal 51 away from the first patch area 11 to the first patch area 11 is greater than the distance from the surface of the lower mold seal 52 away from the first patch area 11 to the second patch area 12. This results in more epoxy resin being injected at the location of the upper mold seal 51 corresponding to the first patch area 11 compared to the location of the lower mold seal 52 corresponding to the first patch area 11. Consequently, the mold flow velocities on the upper and lower surfaces of the first patch area 11 are different, and the two mold flows converge in the upper mold seal 51, causing gas to be unable to escape in time. This makes the injection-molded mold seal 50 prone to problems such as air holes, incomplete sealing, and warping. In this embodiment, by providing a through groove 511 at the first patch area 11 corresponding to the upper mold seal 51, the mold protrusion corresponding to the through groove 511 can block the flow rate of the mold flow during injection molding of the upper mold seal 51, and at the same time reduce the amount of glue injected into the upper mold seal 51 during injection molding, thereby balancing the mold flow speed on the upper and lower surfaces of the first patch area 11, thereby improving the problems of air holes, incomplete mold sealing and warping that are prone to occur in the injection mold seal 50, and improving the molding quality of the product.

[0047] As an improvement to this embodiment, the through slot 511 is located on the side of the first patch area 11 near the second patch area 12. Understandably, the through slot 511 can also be located on the side of the first patch area 11 near the first pin 13. Preferably, the through slot 511 is located in the middle of the corresponding first patch area 11, which can have a greater impact on the mold flow rate, thereby improving the molding quality of the product.

[0048] As an improvement to this embodiment, the distance from the side of the lower mold seal 52 away from the first patch area 11 to the first patch area 11 is H, where H = 500 ± 50 μm. By setting this distance value, on the one hand, the lower mold seal 52 can be insulated and dissipated; on the other hand, it can also avoid the situation where the lower mold seal 52 is easily broken down when the product is powered on due to its thinness at the first patch area 11.

[0049] As an improvement to this embodiment, the distance from the side of the upper mold sealing body 51 away from the first patch area 11 to the first patch area 11 is L, where L = 2500 ± 50 μm.

[0050] As an improvement to this embodiment, the thickness of the lead frame 10 is 380~382um.

[0051] As an improvement to this embodiment, the distance from the side of the upper molded body 51 away from the second patch area 12 to the second patch area 12 is 1700±50um. The distance from the side of the upper molded body away from the second patch area to the second patch area of ​​the existing power semiconductor module is approximately 2300±50um. That is, by setting the surface of the second patch area 12 where the second chip 30 is attached to be higher than the surface of the first patch area 11 where the first chip 20 is attached, the distance from the side of the upper molded body 51 away from the second patch area 12 to the second patch area 12 can be reduced by about 600um compared to the distance from the side of the upper molded body away from the second patch area to the second patch area of ​​the existing upper molded body. This effectively reduces the thickness of the molded body 50 and saves material for the molded body 50.

[0052] As an improvement in this embodiment, the mold enclosure 50 has shrink ejector pin positions 501 arranged along the edge of the through groove 511 on both its front and back sides. These shrink ejector pin positions 501 are used during injection molding of the power semiconductor module 100. The shrink ejector pins of the mold can fix the first patch area 11 at these shrink ejector pin positions 501, preventing the height of the first patch area 11 and / or the second patch area 12 from changing due to mold flow during injection molding of the mold enclosure 50, thus affecting the connection quality of the wires 40. It should be noted that the power semiconductor module 100 disclosed in this embodiment has five shrink ejector pin positions 501 on each of the upper and lower sides of the mold enclosure 50, and both sides function simultaneously. The working principle is that during the initial stage of epoxy resin injection molding, the top and bottom pins fix the lead frame 10 in the middle in the height direction. Before the epoxy resin injection is completed, the epoxy resin is sufficient to fix the lead frame 10. At the same time, the shrinking pins on both sides shrink outward by a certain distance, so that the shrinking pin holes are filled in the later injection process, ensuring the safety and reliability of the power semiconductor module 100 during application. It should be noted that the position of the shrinking pin 501 is determined according to the design of the lead frame 10 and the distribution of its internal structure. Preferably, the pin is set to press exactly at the center of the first patch area 11 and the second patch area 12 to achieve the optimal fixation of the lead frame 10.

[0053] As an improvement to this embodiment, ejector pin positions 502 are provided on the upper and lower sides of the mold sealing body 51. These ejector pin positions 502 are used to assist the product in ejecting from the mold cavity during the demolding process after the mold sealing body 51 has been injected with glue, reducing the problem of film sticking. Preferably, in order to reduce the number of ejector pins while achieving smooth demolding, an ejector pin position 502 is provided at each of the four corners of the mold sealing body 51. As an improvement to this embodiment, the total number of first pins 13 and second pins 14 is 25, and the length of the first pins 13 and second pins 14 is 14mm.

[0054] Example 2:

[0055] The power semiconductor module provided in this embodiment differs from the power semiconductor module provided in Embodiment 1 in that the length of the first pin 13 and the second pin 14 in this embodiment is 11.7 mm. The structure of other components and their interconnections can be referred to in Embodiment 1, and will not be repeated here.

[0056] Example 3:

[0057] The power semiconductor module provided in this embodiment differs from the power semiconductor module provided in Embodiment 1 in that the length of the first pin 13 and the second pin 14 in this embodiment is 9.5 mm. The structure of other components and their interconnections can be referred to in Embodiment 1, and will not be repeated here.

[0058] Example 4:

[0059] Please see Figure 9 The power semiconductor module provided in this embodiment differs from the power semiconductor module provided in Embodiment 1 in that: in this embodiment, the total number of first pins 13' and second pins 14' is 26, and the length of the first pins and second pins is 14mm. The structure of other components and their interconnections can be referred to in Embodiment 1, and will not be repeated here.

[0060] Example 5:

[0061] The power semiconductor module provided in this embodiment differs from the power semiconductor module provided in Embodiment 1 in that: in this embodiment, the total number of first and second pins is 26, and the length of the first and second pins is 11.7 mm. The structure of other components and their interconnections can be referred to in Embodiment 1, and will not be repeated here.

[0062] Example 6:

[0063] The power semiconductor module provided in this embodiment differs from the power semiconductor module provided in Embodiment 1 in that: in this embodiment, the total number of first and second pins is 26, and the length of the first and second pins is 9.5mm. The structure of other components and their interconnections can be referred to in Embodiment 1, and will not be repeated here.

[0064] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A power semiconductor module, characterized in that: The device includes a lead frame, a first chip, a second chip, wires, and a mold. The lead frame includes a first surface mount area, a second surface mount area located on one side of the first surface mount area, a first pin located on the side of the first surface mount area away from the second surface mount area and connected to the first surface mount area, and a second pin connected to the second surface mount area. The first chip is mounted on the first surface mount area, and the second chip is mounted on the second surface mount area. The first chip, the second chip, the first pin, and the second pin are connected through the wires. The first surface mount area, the second surface mount area, the first chip, the second chip, the end of the first pin connected to the first surface mount area, and the end of the second pin connected to the second surface mount area are all encapsulated within the mold. The surface of the first surface mount area where the first chip is mounted is lower than the surface of the second surface mount area where the second chip is mounted. The top surface is defined as the side of the lead frame on which the first chip and the second chip are attached, and the bottom surface is defined as the side opposite to the top surface. The lead frame also includes a bending connection portion. The first patch area and the second patch area are arranged parallel to each other in a direction perpendicular to the top surface. The bending connection portion bends from the first pin toward the bottom surface and connects to the first patch area. The first chip is a power chip, and the second chip is a driver chip; The bottom of the first chip is fixed to the first surface mount area by solder wire; The mold body, with the lead frame as the boundary, includes an upper mold body located on one side of the top surface and a lower mold body located on one side of the bottom surface. The upper mold body is provided with a through groove corresponding to the first patch area. The through slot is located on the side of the first patch area closer to the second patch area, or the through slot is located on the side of the first patch area closer to the first pin.

2. The power semiconductor module according to claim 1, characterized in that, The distance between the surface of the second patch area where the second chip is attached and the surface of the first patch area where the first chip is attached is 900±50um.

3. The power semiconductor module according to claim 1, characterized in that, The distance from the side of the lower mold seal away from the first patch area to the first patch area is 500±50um.

4. The power semiconductor module according to claim 1, characterized in that, The distance from the side of the upper molded body away from the first patch area to the first patch area is 2500±50um.

5. The power semiconductor module according to claim 1, characterized in that, The first surface mount area includes a first surface mount pad, a second surface mount pad, a third surface mount pad, and a fourth surface mount pad. The first surface mount pad, the second surface mount pad, the third surface mount pad, and the fourth surface mount pad are arranged side by side with intervals. There are twelve first chips. Six first chips are mounted on the first surface mount pad, and two first chips are mounted on each of the second surface mount pad, the third surface mount pad, and the fourth surface mount pad. The twelve first chips are arranged in an array in the first surface mount area.

6. The power semiconductor module according to claim 1, characterized in that, Both sides of the mold seal are provided with shrinkage ejector pin positions arranged along the edge of the through groove.

7. The power semiconductor module according to any one of claims 1-6, characterized in that, The total number of the first pin and the second pin is 25 or 26, and the length of the first pin and the second pin is 14mm, 11.7mm or 9.5mm.

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