Integrated circuit including multi-height cells and method of manufacturing the integrated circuit

Abstract

An integrated circuit is provided, comprising: at least one active region extending in a first row along a first direction; at least one active region extending in a second row along the first direction; and a multi-height unit, comprising at least one active region in the first row, at least one active region in the second row, and at least one gate line extending in a second direction intersecting the first horizontal direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by diffusion cutoff.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0093997 filed in the Korean Intellectual Property Office on August 10, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept relate to an integrated circuit, and more particularly, to an integrated circuit including a multi-height cell and a method of manufacturing the integrated circuit. Background Art

[0004] An integrated circuit may include multiple cells arranged in multiple rows. An integrated circuit may include cells that provide similar or identical functions, cells that provide different functions, or cells that provide similar / identical functions and different characteristics at the same time. For example, among multiple cells that provide similar or identical functions, those cells selected based on their characteristics (e.g., operating speed, power consumption, area, etc.) may be included in the integrated circuit. In addition, an integrated circuit may include single-height cells placed in a row or multi-height cells placed continuously in two or more rows. Summary of the invention

[0005] The inventive concept provides an integrated circuit including a plurality of cells, ie, multi-height cells having good characteristics, and a method of manufacturing the same.

[0006] According to one aspect of the present invention, an integrated circuit is provided, comprising: at least one active area extending in a first row along a first direction; at least one active area extending in a second row along the first direction; and a multi-height unit, comprising the at least one active area in the first row, the at least one active area in the second row, and at least one gate line extending along a second direction intersecting the first direction, wherein each of the at least one active area in the first row and the at least one active area in the second row is terminated by diffusion cutoff.

[0007] According to another aspect of the present invention, an integrated circuit is provided, comprising: a multi-height unit, including a plurality of active regions extending along a first direction in two or more rows, wherein the multi-height unit comprises: the plurality of active regions extending along the first direction and terminated by diffusion cut-off; at least one gate line extending along a second direction intersecting the first direction; and a plurality of transistor groups connected in parallel to each other and configured to receive an input signal together, wherein each transistor group of at least two of the plurality of transistor groups comprises transistors sharing a gate line.

[0008] According to another aspect of the present invention, an integrated circuit is provided, comprising: a multi-height unit, including a plurality of active regions extending along a first direction in two or more rows, wherein the multi-height unit comprises: the plurality of active regions extending along the first direction; and at least one gate line extending along a second direction intersecting the first direction, wherein each of the plurality of active regions is terminated by diffusion cutoff. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic diagram showing a portion of an integrated circuit according to some embodiments of the inventive concept;

[0011] Figure 2 An example of diffusion cutoff according to some embodiments of the present inventive concept is shown;

[0012] Figure 3 shows the relationship between diffusion cutoff and elements according to some embodiments of the inventive concept;

[0013] Figure 4A and Figure 4B is a plan view showing an inverter unit according to an embodiment of the inventive concept, Figure 5 According to some embodiments of the present invention, Figure 4A and Figure 4B The circuit diagram corresponding to the inverter unit;

[0014] Fig. 6A and Figure 6B is a plan view showing an inverter unit according to some embodiments of the inventive concept, Fig. 7A and Figure 7B According to some embodiments of the present invention, Fig. 6A and Figure 6B The circuit diagram corresponding to the inverter unit;

[0015] Fig. 8A and Figure 8B is a plan view showing an inverter unit according to some embodiments of the inventive concept;

[0016] Fig.9A and Fig. 9B is a plan view showing units according to some embodiments of the inventive concept;

[0017] Fig.10 is a circuit diagram of a unit according to some embodiments of the inventive concept, Fig.11 is a diagram showing some embodiments of the present invention. Fig.10A plan view of an example of a layout of a unit corresponding to the circuit diagram;

[0018] Fig.12 is a circuit diagram of a unit according to some embodiments of the inventive concept, Fig.13 is a diagram showing some embodiments of the present invention. Fig.12 A plan view of an example of a layout of a unit corresponding to the circuit diagram;

[0019] Fig.14A and Fig. 14B is a plan view showing an inverter unit according to some embodiments of the inventive concept;

[0020] Fig.15A and Fig. 15B is a plan view showing an inverter unit according to some embodiments of the inventive concept;

[0021] Fig.16 is a schematic plan view showing an integrated circuit according to some embodiments of the inventive concept;

[0022] Fig.17 is a flowchart illustrating a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept;

[0023] Fig.18 is a block diagram illustrating a system on chip (SoC) according to some embodiments of the inventive concept; and

[0024] Fig.19 is a block diagram illustrating a computing system including a memory configured to store a program according to some embodiments of the inventive concept.

[0025] The drawings attached to this specification may not be drawn exactly to scale, or elements in the drawings may be enlarged or reduced for convenience of explanation. DETAILED DESCRIPTION

[0026] The inventive concept will now be described more fully below with reference to the accompanying drawings in which example embodiments of the inventive concept are shown. Throughout this application, the same reference numerals may refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items. It should be noted that the various aspects described with respect to one embodiment may be incorporated into different embodiments, although no specific description is given thereto. That is, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination.

[0027] In order to reduce the local layout effect (LLE) between cells in an integrated circuit, a diffusion cutoff (DB) can be inserted into the boundary between cells. In addition to reducing the LLE between cells, the DB can also be advantageous for transistors located near the DB. Specifically, transistors adjacent to the DB can provide a higher current than transistors farther away, which can increase the operating speed. Some embodiments of the present invention may provide an improved integrated circuit, including a multi-height cell having an increased number of transistors adjacent to the DB. The multi-height cell may include an active area terminated by a single DB or a double DB based on the conductivity type. For example, when adjacent to a single DB, the PFET may have improved operating characteristics, and when adjacent to a double DB, the NFET may have improved operating characteristics.

[0028] Figure 1 1 is a schematic diagram showing a portion of an integrated circuit 10 according to some embodiments of the present inventive concept. Specifically, Figure 1 The layout of the integrated circuit 10 is shown on a plane, and the integrated circuit 10 includes a plurality of cells C01 to C05 placed in a first row R11 and a second row R12 along the X-axis and the Y-axis. In this specification, the X-axis direction and the Y-axis direction may be referred to as the first horizontal direction and the second horizontal direction, respectively, and the Z-axis direction may be referred to as the vertical direction. The plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, and a component relatively arranged in the +Z direction compared to another component may be indicated as being above the other component, and a component relatively arranged in the -Z direction compared to another component may be indicated as being below the other component. Unless otherwise indicated in this specification, the height of a component may refer to the length of the component in the Y-axis direction, and the width of a component may refer to the length of the component in the X-axis direction. In addition, the area of ​​a component may refer to the size of the component on a plane parallel to the horizontal plane. In the drawings of this specification, for ease of explanation, only some layers may be shown, and vias may be shown to indicate the connection between the pattern of a metal layer and the conductive pattern below it, and the vias are located below the pattern of the metal layer.

[0029] A cell is a layout unit included in an integrated circuit and may also be referred to as a standard cell. An integrated circuit may include a plurality of different cells. A cell may have a structure that conforms to a preset standard and may be aligned and placed in multiple rows. For example, Figure 1 As shown, the first cell C01 and the third cell C03 may be placed in the first row R11, and the fourth cell C04 and the fifth cell C05 may be placed in the second row R12. The first row R11 and the second row R12 may have equal or substantially equal heights, and the first cell C01 and the fourth cell C04 may have equal or substantially equal heights, that is, equal or substantially equal lengths along the Y-axis direction.

[0030] Reference Figure 1 , the second cell C02 can be placed continuously in the first row R11 and the second row R12, that is, the second cell C02 spans the first row R11 and the second row R12. Therefore, the second cell C02 can have a length corresponding to the sum of the heights of the two rows (that is, the first row R11 and the second row R11). As described above, cells that are continuously placed in two or more consecutive rows or span two or more consecutive rows can be referred to as multi-height cells, and in particular, cells that are continuously placed in two adjacent rows can be referred to as double-height cells. Multi-height cells can have a height corresponding to a multiple of the height of a row (or the height of a single-height cell), while a cell placed in a row (such as the first cell C01) can be referred to as a single-height cell.

[0031] The first to fifth cells C01 to C05 may include active regions extending along the X-axis direction, such as Figure 1 Although Figure 1 , but in some embodiments, the first unit C01 to the fifth unit C05 may also include a fin extending in the X-axis direction and a gate line extending in the Y-axis direction. In some embodiments, the active region may be formed in a substrate, and the substrate may include a semiconductor such as Si or Ge, a compound semiconductor such as SiGe, SiC, GaAs, InAs or InP, or a conductive region such as an impurity-doped well or an impurity-doped structure. In some embodiments, the gate line may include a work function metal-containing layer and a gap filling metal film. For example, the work function metal-containing layer may include one or more metals, including but not limited to Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er and Pd, and the gap filling metal film may be formed by a W film and / or an Al film. In some embodiments, the gate line may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W. In the following figures, for ease of explanation, the fin on the active area may not be shown, but it is understood that the embodiments of the present invention are not only applicable to cells including planar transistors, but also to cells including fin field effect transistors (FinFETs). In addition, in some embodiments, the active area may include at least a portion of the fin structure, and in this case, the fin may be referred to as a fin active area. In addition, in some embodiments, the fin may be referred to as including source / drain regions formed on both sides of the gate line.

[0032] The second cell C02 as a multi-height cell may include first and second active regions RX1 and RX2 extending in a first row R11 along the X-axis direction and third and fourth active regions RX3 and RX4 extending in a second row R12 along the X-axis direction, and the first and third active regions RX1 and RX3 may be adjacent to each other. Figure 1 Although not shown in the figure, the integrated circuit 10 may include a plurality of power supply lines extending at the boundary of the cell along the X-axis direction to supply power to the cell. In some embodiments, a positive power supply voltage may be applied to odd-numbered power supply lines among the plurality of power supply lines, and a ground voltage (or a negative power supply voltage) may be applied to even-numbered power supply lines. In some embodiments, the power supply voltage may be applied to the plurality of power supply lines in a manner opposite to the above description. Thus, as Figure 1 As shown, a pair of active regions of the same conductivity type, i.e., a pair of active regions of an N-channel field effect transistor (NFET) or a pair of active regions of a P-channel field effect transistor (PFET), may be arranged to be adjacent to each other along the Y-axis direction. For example, a power line to which a ground voltage is applied may extend along the X-axis direction on the boundary between the first row R11 and the second row R12, and the first active region RX1 and the third active region RX3 adjacent to the power line may be active regions of the NFET, while the second active region RX2 and the fourth active region RX4 may be active regions of the PFET.

[0033] In some embodiments, the first active region RX1 to the fourth active region RX4 of the second cell C02 may be terminated by diffusion cuts. Diffusion cuts may be inserted to reduce effects between adjacent cells, such as local layout effects (LLE). Diffusion cuts may separate diffusion regions between adjacent cells and may be filled with or include an insulator. In some embodiments, diffusion cuts may separate fins between adjacent cells. In some embodiments, diffusion cuts may separate diffusion regions between adjacent cells by removing a diffusion region and / or at least a portion of a diffusion region. Reference will be made later to Figure 2 An example of diffusion cutting is described. In addition, as will be referred to later Figure 3 As described above, the diffusion cutoff can provide LLE that is beneficial to adjacent transistors, and the closer the transistor is to the diffusion cutoff, the better its characteristics will be, and the second cell C02 can include more transistors than a single-height cell, which performs the same function as the second cell C02 (or corresponds to a circuit similar to or the same as the circuit of the second cell C02), wherein the transistor is adjacent to the diffusion cutoff. Therefore, the second cell C02 can provide better characteristics than the single-height cell, and the integrated circuit 10 can have improved performance.

[0034] In some embodiments, the second cell C02 may include two or more transistors having similar or identical functions and may have a relatively high driving strength or capability. Figure 4A and Figure 4B As described above, for high-speed inversion operation, the inverter unit may include six PFETs connected in parallel to each other and six NFETs connected in parallel to each other. When the high drive strength unit is implemented as a single-height unit and the number of transistors is increased to enhance the drive strength, the number of transistors separated by diffusion cutoffs may be increased. Conversely, when the high drive strength unit is implemented as a double-height unit (e.g., or similar to Figure 1 When a second cell C02 is implemented as a multi-height cell (in which cells span three or more rows or are placed continuously in three or more rows), the number of transistors adjacent to the diffusion cutoff can be increased.

[0035] although Figure 1 The diffusion cutoff is shown to be included in the second cell C02, but in some embodiments, the diffusion cutoff may exist outside the second cell C02, and the second cell C02 may be considered to share the diffusion cutoff with the adjacent cells (i.e., the first cell C01, the third cell C03, the fourth cell C04, and the fifth cell C05). In addition, although the diffusion cutoff is shown as having a length along the Y-axis direction of Figure 1 However, in some embodiments, the length of the diffusion cut along the Y-axis direction may be shorter than that of the second unit C02, and in some embodiments, the diffusion cut may be discontinuously separated into respective parts corresponding to the first to fourth active regions RX01 to RX04, respectively.

[0036] Figure 2 An example of diffusion cutoff according to some embodiments of the present inventive concept is shown. In detail, Figure 2 The upper part is a plan view of the layout including the diffusion cut-off, Figure 2 The lower part is along Figure 2 A cross-sectional view of a diffusion cut taken along the line XX' in the upper part of FIG. Figure 2 No distinction is made in Figure 2 Source / drain regions on both sides of the middle gate line.

[0037] Reference Figure 2, the first active area RX11 to the fourth active area RX14 may be disposed on the substrate SUB, and a plurality of gate lines G11 to G23 may extend parallel to each other along the Y-axis direction on the first active area RX11 to the fourth active area RX14. The spacing between the plurality of gate lines G11 to G23 may be referred to as 1 contact polysilicon spacing (1 CPP). The first active area RX11 to the fourth active area RX14 may be separated from each other via diffusion cutoff. For example, the first active area RX11 and the second active area RX12 may be separated via a first double diffusion cutoff DDB1, the second active area RX12 and the third active area RX13 may be separated via a second double diffusion cutoff DDB2, and the third active area RX13 and the fourth active area RX14 may be separated via a single diffusion cutoff SDB.

[0038] The double diffused cutoff DDB may have a width of approximately 1 CPP or greater, i.e., a length along the X-axis direction. The double diffused cutoff may be formed by etching an active area (e.g., a second double diffused cutoff DDB2, or, for example, a first double diffused cutoff DDB1), by further etching a portion of the substrate in addition to the active area. The gate lines on the double diffused cutoff may be referred to as dummy gate lines, in which active areas and transistors may not be formed, and in some embodiments, the gate lines may be used as conductive paths. For example, the gate lines G12 to G16 on the first double diffused cutoff DDB1 may be dummy gate lines in which transistors will not be formed, and the gate lines G18 and G19 on the second double diffused cutoff DDB2 may also be dummy gate lines in which transistors will not be formed. The single diffused cutoff SDB may have a width approximately equal to the width of the gate line, i.e., a length along the X-axis direction. As Figure 2 As shown, a gate line may not be formed on the single diffusion cutoff SDB. Hereinafter, description of embodiments of the inventive concept will focus on the second double diffusion cutoff DDB2 and a single diffusion cutoff SDB having a width of about 1 CPP similar to the second double diffusion cutoff DDB2.

[0039] Figure 3 1 shows the relationship between diffusion cutoff and components according to some embodiments of the present invention. Figure 3 The upper part is a plan view of the layout including the double diffusion cut-off DDB. Figure 3 The lower part of shows the relationship between the distance of the element from the double diffusion cutoff DDB and the current of the element.

[0040] Reference Figure 3 The first gate line G31 and the second gate line G32 on the double diffusion cut-off DDB may be dummy gate lines, and the third gate line G33 to the sixth gate line G36 may form active regions and NFETs, respectively. Figure 3, the closer a device such as an NFET is to the double-diffused cut-off DDB, the higher the current that the device can provide, and the farther a device such as an NFET is from the double-diffused cut-off DDB, the lower the current that the device can provide. In other words, according to some embodiments conceived by the present invention, a device can provide a current that increases with increasing proximity to the DDB and a current that decreases with increasing distance from the DDB. For example, the NFET closest to the double-diffused cut-off DDB formed via the third gate line G33 can provide a higher current than the NFET formed via the sixth gate line G36. Devices that provide relatively high currents can have relatively high operating speeds, so the greater the number of transistors adjacent to the double-diffused cut-off DDB, the lower the operating speed of the unit including the transistors (e.g., the response time of the output signal relative to the input signal). Although Figure 3 An example of a double diffusion cutoff DDB is shown, but a single diffusion cutoff can provide similar operating characteristics to a DDB, i.e., Figure 3 In a similar manner to the embodiments of the present invention, devices relatively close to a single diffusion cutoff can provide relatively high current and have relatively high operating speeds.

[0041] Figure 4A and Figure 4B is a plan view showing inverter units C40a and C40b according to some embodiments of the inventive concept, Figure 5 According to some embodiments of the present invention, Figure 4A and Figure 4B In detail, Figure 4A and Figure 4B The layout of inverter cells C40a and C40b are shown respectively, which are single-height cells and include six transistors connected in parallel with each other.

[0042] Reference Figure 4A , the inverter unit C40a may include a first active region RX41a and a second active region RX42a extending in the X-axis direction, and the first active region RX41a and the second active region RX42a may be terminated by double diffusion cutoffs DDB1 and DDB2, respectively. Figure 5 As shown, two PFETs and two NFETs of the inverter cell C40 may be disposed adjacent to the double diffused cutoff DDB1 or DDB2.

[0043] Similarly, refer to Figure 4B , the inverter unit C40b may include a first active region RX41b and a second active region RX42b extending in the X-axis direction, and the first active region RX41b and the second active region RX42b may be terminated by single diffusion cutoffs SDB1 and SDB2, respectively. Figure 5 As shown, two PFETs and two NFETs of inverter cell C40 may be disposed adjacent to single diffusion cutoff SDB1 or SDB2.

[0044] Fig. 6A and Figure 6B is a plan view showing inverter units C60a and C60b according to an embodiment of the inventive concept, Fig. 7A and Figure 7B According to some embodiments of the present invention, Fig. 6A and Figure 6B The circuit diagram corresponding to the inverter units C60a and C60b is shown in detail. Fig. 6A and Figure 6B The layout of inverter cells C60a and C60b are shown respectively, which are double-height cells and include six transistors connected in parallel with each other.

[0045] Reference Fig. 6A , the inverter unit C60a can be placed in the first row R61 and the second row R62, and the power line P60a to which the ground voltage GND is applied can extend along the X-axis direction at the boundary between the first row R61 and the second row R62. Therefore, the inverter unit C60a may include an NFET active area adjacent to the power line P60a. In addition, each of the multiple active areas included in the inverter unit C60a may be terminated by double diffusion cutoffs DDB1 and DDB2. Therefore, as Fig. 7A As shown, four PFETs and four NFETs may be arranged adjacent to the double diffused cutoff DDB1 or DDB2 in the inverter cell C60a.

[0046] like Fig. 6A As shown, the inverter unit C60a may include a first pattern M21 in the layer M2 to electrically connect the pattern of the layer M1 corresponding to the output signal Y, and may include a second pattern M22 in the layer M2 to electrically connect the pattern of the layer M1 corresponding to the input signal A. The first pattern M21 and the second pattern M22 may pass through the boundary between the first row R61 and the second row R62 to extend along the Y-axis direction, as shown in FIG. Fig. 6A In addition, the first pattern M21 can be used as an output pin of the inverter unit C60a, and the second pattern M22 can be used as an input pin of the inverter unit C60a. That is, the first pattern M21 and the second pattern M22 can be used to perform signal routing and can also be used as pins of the unit, so the inverter unit C60a can have a relatively simple wiring structure.

[0047] and Figure 4A Compared to the inverter unit C40a, the inverter unit C60a can provide improved routability. Fig.17 As described above, after placing the cell, a wiring operation may be performed to electrically connect the input pins and / or output pins of the cell. Fig. 6A After the inverter unit C60a is formed, the pattern of the layer M3 above the layer M2 can be set to perform wiring for the input pin of the layer M2 corresponding to the input signal A and the output pin of the layer M2 corresponding to the output signal Y. Although the layer M2 may include a pattern extending in the Y-axis direction, the layer M3 may include a pattern extending in the X-axis direction. Therefore, due to Fig. 6A The extension length of the first pattern M21 and the second pattern M22 along the Y-axis direction, Fig. 6A The first pattern M21 and the second pattern M22 of the layer M3 can provide more points at which through holes to be connected to the pattern of the layer M3 can be set. Fig. 6A The inverter unit C60a may have more Figure 4A Therefore, Fig. 6A The inverter unit C60a may provide improved routability and may reduce routing congestion in an integrated circuit including the inverter unit C60a.

[0048] Reference Figure 6B , the inverter unit C60b may be placed in the first row R61 and the second row R62, and the power line P60b to which the power supply voltage VDD is applied may extend in the X-axis direction at the boundary between the first row R61 and the second row R62. Therefore, the inverter unit C60b may include a PFET active region adjacent to the power line P60b. In addition, each of the plurality of active regions included in the inverter unit C60b may be terminated by double diffusion cutoffs DDB1 and DDB2. Therefore, as Figure 7B As shown, four PFETs and four NFETs may be arranged adjacent to the double diffused cutoff DDB1 or DDB2 in the inverter cell C60b.

[0049] Similar to Fig. 6A The inverter unit C60a and Figure 6B The inverter unit C60b may provide two different units having different layouts, each providing the same or similar functions and the same or similar characteristics according to the voltage applied to the power line. Fig.17 As stated, Fig.17 The cell library D72 of FIG. 1 may define two different cells, and one of the two different cells may be selected and placed based on the voltage of the power supply line during the placement and routing process. In addition, it should be understood that although Fig. 6A and Figure 6BInverter cells C60a and C60b including active regions terminated by double-diffused cutoffs are illustrated, but according to some embodiments of the inventive concept, inverter cells including active regions terminated by single-diffused cutoffs may also be included as double-height cells.

[0050] Fig. 8A and Figure 8B is a plan view showing inverter units C80a and C80b according to some embodiments of the present inventive concept. In detail, Fig. 8A and Figure 8B Inverter cells C80a and C80b are shown respectively, which are multi-height cells placed continuously in or across the first to third rows R81, R82 and R83, and include six transistors connected in parallel to each other, as shown in FIG. Figure 4A and Figure 4B The inverter units C40a and C40b and Fig. 6A and Figure 6B In the following, for the sake of brevity, Fig. 8A and Figure 8B The above reference will be omitted in the description of the embodiment of Fig. 6A and Figure 6B A description of an element or feature is provided.

[0051] Reference Fig. 8A , the inverter unit C80a may be placed in the first row R81, the second row R82, and the third row R83 or may span the first row R81, the second row R82, and the third row R83, and the first power line P81a to which the positive power supply voltage VDD is applied may extend along the X-axis direction at the boundary between the first row R81 and the second row R82, and the second power line P82a to which the ground voltage GND is applied may extend along the X-axis direction at the boundary between the second row R82 and the third row R83. Therefore, the inverter unit C80a may include an active region of a PFET adjacent to the first power line P81a and an active region of an NFET adjacent to the second power line P82a. In addition, each of the multiple active regions included in the inverter unit C80a may be terminated by double diffusion cutoffs DDB1 and DDB2. Therefore, six PFETs and six NFETs may be disposed in the inverter unit C80a adjacent to the double diffusion cutoffs DDB1 or DDB2.

[0052] Reference Figure 8B, the inverter unit C80b may be placed in the first row R81, the second row R82, and the third row R83 or may span the first row R81, the second row R82, and the third row R83, and the first power line P81b to which the ground voltage GND is applied may extend along the X-axis direction at the boundary between the first row R81 and the second row R82, and the second power line P82b to which the positive power voltage VDD is applied may extend along the X-axis direction at the boundary between the second row R82 and the third row R83. Therefore, the inverter unit C80b may include an active region of an NFET adjacent to the first power line P81b and an active region of a PFET adjacent to the second power line P82b. In addition, each of the multiple active regions included in the inverter unit C80b may be terminated by double diffusion cutoffs DDB1 and DDB2. Therefore, six PFETs and six NFETs may be disposed in the inverter unit C80b adjacent to the double diffusion cutoffs DDB1 or DDB2.

[0053] As mentioned above FIG. 4A to FIG. 8B As described above, cells corresponding to the same circuit can have different layouts, and the greater the number of transistors adjacent to the diffusion cutoff, the larger the area occupied by the cell and the higher the performance can be provided. Fig. 6A The inverter unit C60a (which is a double height unit) has a ratio Figure 4A The inverter cell C40a (which is a single height cell) has a larger area. Due to the enlarged area of ​​the double diffusion cutout, and also due to the increased number of transistors adjacent to the double diffusion cutout, the inverter cell C60a can provide a larger area than Figure 4A The inverter unit C40a has a higher performance. In addition, as a multi-height unit placed consecutively in three rows or spanning over three rows Fig. 8A The inverter unit C80a has a Fig. 6A The inverter cell C60a (which is a double height cell) has a larger area. Due to the enlarged area of ​​the double diffusion cutout, and also due to the increased number of transistors adjacent to the double diffusion cutout, the inverter cell C80a can provide a larger area than Fig. 6A The inverter unit C60a has higher performance. Therefore, Figure 4A The inverter unit C40a can be used in integrated circuits that require high integration (e.g., Figure 1 a portion of an integrated circuit 10) and Fig. 8A The inverter unit C80a can be used in a part of an integrated circuit requiring high performance, and Fig. 6A The inverter unit C60a can be used in a part of an integrated circuit that requires both high integration and high performance in a balanced manner.

[0054] Fig.9A and Fig. 9Bis a plan view showing cells C90a and C90b according to some embodiments of the inventive concept. In detail, Fig.9A The cell C90a is a multi-height cell and may include an active region terminated by double diffusion cut-offs DDB1 and DDB2, and Fig. 9B The cell C90b is a multi-height cell and may include an active region terminated by single diffusion cut-offs SDB1 and SDB2. In the following, for the sake of brevity, the above-mentioned descriptions of the active region and the active region are omitted. Fig.9A and Fig. 9B Description of the characteristic elements associated with the embodiments.

[0055] Reference Fig.9A , the cell C90a may be placed in the first row R91 and the second row R92 or may span the first row R91 and the second row R92, and may include the first active region to the third active region RX1, RX2, and RX3 extending in the X-axis direction and the gate line extending in the Y-axis direction. The first active region to the third active region RX1, RX2, and RX3 extending in the X-axis direction may be terminated by double diffusion cutoffs DDR1 and DDB2. The first active region RX1 may pass through the boundary between the first row R91 and the second row R92 to extend in the Y-axis direction. That is, the first active region RX1 included in the cell 90a may correspond to Figure 1 The first active region RX1 and the third active region RX3 included in the second cell C02 are at least partially connected to the active region of (i.e., the portions thereof connected to each other), or the active region where the first active region RX1 and the third active region RX3 are merged. Therefore, the length of the active region of the NFET of the cell 90a (i.e., the first active region RX1) along the Y-axis direction may be greater than Figure 1 The sum of the lengths of the active areas of the NFETs of the second cell C02 (ie, the first active area RX1 and the third active area RX3) along the Y-axis direction.

[0056] The unit 90a may include a plurality of fins F01 to F16 extending in the X-axis direction. At least some of the plurality of fins F10 to F16 (e.g., fin F02) may form a transistor with a gate line, and at least some other fins (e.g., fin F04) may be dummy fins. The size or current driving strength of the transistor may be determined based on the number of fins crossing the gate line. As described above, the unit 90a may include an active region of the NFET having an extended length in the Y-axis direction (i.e., a first active region RX1), and thus the number of fins overlapping with the active region of the NFET may be greater than the number of fins overlapping with the active region of the PFET (the second active region RX2 and the third active region RX3). For example, as Fig.9AAs shown, six fins (fins F06 to F11) can overlap with the first active region RX1, and four fins (fins F02, F03, F14, and F15) can overlap with the second active region RX2 (fins F02 and F03) or overlap with the third active region RX3 (fins F014 and F15). Therefore, the cell 90a can have a relatively boosted NFET, and as will be described below with reference to Fig.10 As described above, transistors connected in series in the circuit diagram may be formed in the first active region RX1. Fig.9A An example is shown in which the active region of the NFET (ie, the first active region RX1 ) has an extended length along the Y-axis direction, but it should be understood that in other embodiments of the present invention, the active region of the PFET may also have an extended length along the Y-axis direction.

[0057] Reference Fig. 9B , the cell C90b may be placed in the first row R91 and the second row R92 or may cross the first row R91 and the second row R92, and may include first to third active regions RX1, RX2, and RX3 extending in the X-axis direction, and the first active region RX1 may pass through the boundary between the first row R91 and the second row R92 to extend in the Y-axis direction. In addition, the cell C90b may include a gate line extending in the Y-axis direction and a plurality of fins F01 to F16 extending in the X-axis direction. Fig.9A Compared with the cell 90 a , the first to third active regions RX1 , RX2 , and RX3 extending in the X-axis direction may be terminated by the single diffusion cutoffs SDB1 and SDB2 .

[0058] Based on design rules that can be defined according to semiconductor processes, the first active region RX1 can be spaced apart from the boundary of the cell C90b. The cells adjacent to the cell C90b in the integrated circuit along the X-axis direction can include active regions of NFETs that are merged or combined at the boundary between the first row R91 and the second row R92, such as Figure 1 The space required for forming active regions of different structures in the semiconductor process as described above can be defined based on the design rules. Fig. 9B As shown, the first active region RX1 may be spaced apart from the boundary of the cell C90b facing each other by about 1 CPP in the X-axis direction.

[0059] Fig.10 is a circuit diagram of a unit according to some embodiments of the inventive concept, Fig.11 is a diagram showing some embodiments of the present invention. Fig.10 The circuit diagram corresponds to a plan view of an example of a layout of a unit. In detail, Fig.10 and Fig.11NAND cells C10 and C10' acting as 2-input NAND gates with input signals A and B and an output signal Y are shown.

[0060] refer to Fig.10 , the NAND cell C10 may include a plurality of transistor groups G11 to G18 as high drive strength units. The transistor group and another transistor group may be connected in parallel to each other and may receive input signals in common. For example, transistor groups G11, G13, G15, and G17 including PFETs may be connected in parallel to each other between an output node (i.e., a node corresponding to an output signal Y) and a positive power supply voltage VDD, and may receive input signals A and B in common. In addition, transistor groups G12, G14, G16, and G18 including NFETs may be connected in parallel to each other between an output node and a ground voltage GND, and may receive input signals A and B in common.

[0061] refer to Fig.11 , the NAND cell C10' is a double height cell and may be placed in the first row R111 and the second row R112 or may span the first row R111 and the second row R112, and may include first to fourth active regions RX1, RX2, RX3, and RX4, which are terminated by double diffusion cutoffs DDB1 and DDB2. A power line P11 to which a ground voltage GND is applied at a boundary between the first row R111 and the second row R112 may extend in the X-axis direction, and the first active region RX1 and the third active region RX3 may be disposed adjacent to the power line P11. In order to receive the ground voltage GND through the power line P11, as Fig.11 As shown, the NAND cell C10' may include contacts CT1 and CT2, which are connected to the first active region RX1 and the third active region RX3 and extend by passing through the boundary between the first row R111 and the second row R112. In addition, the NAND cell C10' may include through holes V01 and V02 connected to the power line P11 and placed on the boundary between the first row R111 and the second row R112, and in some embodiments, the through holes V01 and V02 may be strip-type through holes extending in the Y-axis direction, such as Fig.11 As the areas of the vias V01 and V02 increase, the IR drop (or voltage drop) occurring on the current path from the power line P11 of the NAND cell C10' to the element (eg, transistor) can be reduced.

[0062] Fig.12 is a circuit diagram of a unit according to some embodiments of the inventive concept, Fig.13 is a diagram showing some embodiments of the present invention. Fig.12 The circuit diagram corresponds to a plan view of an example of a layout of a unit. In detail, similar to Fig.10 and Fig.11 , Fig.12 and Fig.13 NAND cells C12 and C12' are shown as 2-input NAND gates with input signals A and B and output signal Y. Fig.12 and Fig.13 The above reference will be omitted in the description of the embodiment of Fig.10 and Fig.11 A description of an element or feature is provided.

[0063] refer to Fig.12 , the NAND cell C12 may include a plurality of transistor groups G21 to G26. Fig.10 Compared with NAND cell C10, Fig.12 The NAND cell C12 may include transistor groups G22 and G26 having relatively large NFETs (ie, NFETs having high current driving strength). Therefore, the NFETs of the NAND cell C12 may be boosted, and the operating speed of the NAND cell C12 may be increased.

[0064] refer to Fig.13 , the NAND cell C12' is a double height cell and may be placed in the first row R131 and the second row R132 or may span the first row R131 and the second row R132, and may include first to third active regions RX1, RX2, and RX3 terminated by double diffusion cutoffs DDB1 and DDB2. A power line P13 to which a ground voltage GND is applied at a boundary between the first row R131 and the second row R132 may extend in the X-axis direction, and similarly to the above reference Fig.9A and Fig. 9B According to the description provided, the first active region RX1 as the active region of the NFET may extend along the Y-axis direction across the boundary between the first row R131 and the second row R132. Fig.11 Compared with the NFET included in the NAND cell C10', the transistor (ie, NFET) formed via the first active region RX1 and the gate line may have a relatively high current driving strength and may be boosted, as described above with reference to Fig.12 As described above, transistors to be boosted among transistors included in a cell (eg, transistors connected in series and a transistor group including these transistors) may be formed in an active region (or a merged active region) having an extended length in the Y-axis direction.

[0065] Fig.14A and Fig. 14B 1 is a plan view showing inverter units C14a and C14b according to some embodiments of the present inventive concept. In detail, Fig.14A and Fig. 14BThe layout of the inverter units C14a and C14b is shown, which are double-height units placed in the first row R141 and the second row R142 or spanning the first row R141 and the second row R142 and corresponding to the same circuit. Fig.14A and Fig. 14B Descriptions of elements and features are provided in the description of the embodiments and are included in this description.

[0066] In some embodiments, a cell may include an active region terminated by a single diffusion cutoff or a double diffusion cutoff depending on the conductivity type of the active region. An element (e.g., a transistor) may have characteristics that vary based on the distance between the element and the diffusion cutoff, and may also have different characteristics depending on the type of diffusion cutoff, as described above with reference to Figure 3 For example, a PFET adjacent to a single diffused cutoff may provide better characteristics, such as higher current, than a PFET adjacent to a double diffused cutoff. Additionally, an NFET adjacent to a double diffused cutoff may provide better characteristics, such as higher current, than an NFET adjacent to a single diffused cutoff. Thus, Fig.14A and Fig. 14B As shown, inverter cells C14a and C14b may include an NFET active region terminated by a double diffusion cutoff and a PFET active region terminated by a single diffusion cutoff. As described above, the structure in which the diffusion cutoff of different structures is used may be referred to as a mixed diffusion cutoff (MDB). As described above with reference to the accompanying drawings, inverter cells C14a and C14b as double height cells may include more transistors adjacent to the mixed diffusion cutoff compared to single height cells, and thus may provide relatively high or improved performance.

[0067] Reference Fig.14A , the inverter cell C14a may include an NFET active region (i.e., a first active region RX1 and a third active region RX3) disposed at an inner region and a PFET active region (i.e., a second active region RX2 and a fourth active region RX4) disposed at an outer region. In addition, the inverter cell C14a may include active regions terminated by mixed diffusion cutoffs. For example, the first active region RX1 and the third active region RX3 as NFET active regions may be terminated by double diffusion cutoffs DDB1 and DDB2, while the second active region RX2 and the fourth active region RX4 as PFET active regions may be terminated by two of the single diffusion cutoffs SDB1 to SDB4, respectively. In addition, as Fig.13 Like the first active region RX1 included in the NAND cell C12', it can be understood that the merged active region can also be terminated by single diffusion cutoff or double diffusion cutoff according to the conductivity type of the active region.

[0068] Reference Fig. 14B , the inverter cell C14b may include a PFET active region (i.e., a first active region RX1 and a third active region RX3) disposed at an inner region and an NFET active region (i.e., a second active region RX2 and a fourth active region RX4) disposed at an outer region. In addition, the inverter cell C14b may include an active region terminated by a mixed diffusion cutoff. For example, the first active region RX1 and the third active region RX3 as PFET active regions may be terminated by single diffusion cutoffs DDB1 and DDB2, while the second active region RX2 and the fourth active region RX4 as NFET active regions may be terminated by two double diffusion cutoffs among the double diffusion cutoffs DDB1 to DDB4, respectively.

[0069] Fig.15A and Fig. 15B 1 is a plan view showing inverter units C15a and C15b according to some embodiments of the present inventive concept. In detail, Fig.15A and Fig. 15B The layout of the inverter units C15a and C15b is shown, which are multi-height units that are placed consecutively in the first row R151, the second row R152 and the third row R153 or span the first row R151, the second row R152 and the third row R153 and correspond to the same circuit. Fig.15A and Fig. 15B The above reference will be omitted in the description of the embodiment of Fig.14A and Fig. 14B The embodiments provide a description of the elements and features.

[0070] Reference Fig.15A , the inverter cell C15a may include an active region terminated by a mixed diffusion cutoff. For example, the inverter cell C15a may be arranged along the -(negative) Y direction (ie, Fig.15A In the -Y direction, the active region for NFET, the active region for PFET, the active region for NFET, and the active region for PFET are sequentially included. Therefore, the double diffusion cutoff, the single diffusion cutoff, the double diffusion cutoff, and the single diffusion cutoff can be sequentially arranged along the -Y direction.

[0071] Reference Fig. 15B , the inverter cell C15b may include an active area terminated by a mixed diffusion cutoff. For example, the inverter cell C15b may include an active area for a PFET, a pair of active areas for an NFET, a pair of active areas for a PFET, and an active area for an NFET sequentially along the -Y direction. Therefore, a single diffusion cutoff, a double diffusion cutoff, a single diffusion cutoff, and a double diffusion cutoff may be sequentially provided along the -Y direction.

[0072] Fig.161 is a schematic plan view showing an integrated circuit 16 according to some embodiments of the present invention. Fig.16 An integrated circuit 16 is shown, which includes a first cell C21, a second cell C22, and a third cell C23 placed in or across the first to fifth rows R01 to R05.

[0073] In some embodiments, integrated circuit 16 may include multiple cells corresponding to the same circuit, that is, cells having similar or identical functions but different heights. Fig.16 The first cell C21, the second cell C22, and the third cell C23 may include the same number of NFETs and the same number of PFETs, and may correspond to similar or identical circuits. The first cell C21 may include a diffusion cutoff having a minimum area compared to the second cell C22 and the third cell C23, and thus the first cell C21 may have a smaller area than the second cell C22 and the third cell C23. In addition, the third cell C23 may include the largest number of transistors adjacent to the diffusion cutoff compared to the first cell C21 and the second cell C22, and thus the third cell C23 may provide relatively higher or improved performance compared to the first cell C21 and the second cell C22. In addition, the second cell C22 may have a medium level of area and functional performance compared to the first cell C21 and the third cell C23. Therefore, the integrated circuit 16 may include cells that provide similar or identical functions that are appropriately placed based on requirements such as area, performance, etc., and thus the efficiency, performance, and / or operational reliability of the integrated circuit 16 may be improved.

[0074] Fig.17 is a flow chart illustrating a method of manufacturing an integrated circuit IC according to some embodiments of the inventive concept.

[0075] The cell library (or standard cell library) D72 may include information about the cell, such as function information, component or device characteristic information, layout information, etc. Fig.17 As shown, the cell library D72 may include data defining the layout of multi-height cells (e.g., first to third data D72_1, D72_2, D72_3, etc.). In some embodiments, regarding cells providing similar or identical functions, the first data D72_1 may define a single-height cell, such as Figure 4A and Figure 4B The inverter units C40a and C40b, and the second data D72_2 can define a double height unit, such as Fig. 6A and Figure 6B The inverter units C60a and C60b, and the third data D72_3 can define multi-height units placed continuously in three rows or across three rows, such as Fig. 8A and Figure 8BInverter units C80a and C80b.

[0076] In operation S10, a logic synthesis operation of generating netlist data D73 according to RTL data D71 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis according to RTL data D71 by referring to a cell library D72, thereby generating netlist data D73 including a bitstream or a netlist, the RTL data D71 being written in a hardware description language (HDL) (e.g., VHSIC hardware description language (VHDL) and Verilog). The cell library D72 may include information about the relative high performance capabilities of the multi-height cell, and the multi-height cell may be included in the integrated circuit IC by referring to the information during the logic synthesis process.

[0077] In operation S20, a placement and routing (P&R) operation of generating layout data D74 based on the netlist data D73 may be performed. Fig.17 As shown, the P&R operation S20 may include a plurality of operations S21, S22, and S23.

[0078] In operation S21, an operation of placing a cell may be performed. For example, a semiconductor design tool (e.g., a P&R tool) may be used to place a plurality of cells by referring to a cell library D72 according to the netlist data D73. As described above, single-height cells and multi-height cells may be placed by using semiconductor tools.

[0079] In operation S22, an operation of generating an interconnection may be performed. The interconnection may electrically connect the output pin and the input pin, and may include, for example, at least one through hole and at least one conductive pattern. Fig. 6A As described above, the multi-height cell may have input pins and / or output pins that provide candidate via points, thereby facilitating routing and reducing or preventing routing congestion. In addition, the interconnection may have a relatively simple structure, and signal delays occurring in the interconnection may be reduced.

[0080] In operation S23, an operation of generating layout data D114 may be performed. The layout data D114 may have a format such as GSDII, and may include geometric information of cells and interconnections.

[0081] In operation S30, optical proximity correction (OPC) may be performed. OPC may refer to an operation of forming a desired pattern by correcting distortion (e.g., refraction due to characteristics of light in photolithography included in a semiconductor process for manufacturing the integrated circuit IC), and when OPC is applied to the layout data D74, a pattern on the mask may be determined. In some embodiments, the layout of the integrated circuit IC may be limitedly modified in operation S30, and this limited modification of the integrated circuit IC in operation S30 may be post-processing performed to improve or optimize the structure of the integrated circuit IC, and may be referred to as design polishing.

[0082] In operation S40, an operation of manufacturing a mask may be performed. For example, when OPC is applied to the layout data D74, a pattern on a mask may be defined to form a pattern formed in a plurality of layers, and at least one mask (or photomask) to be used to form the corresponding pattern of the plurality of layers may be manufactured.

[0083] In operation S50, an operation of manufacturing an integrated circuit IC may be performed. For example, the integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S40. Fig.17 As shown, operation S50 may include operations S51 and S52.

[0084] In operation S51, a front-end process (FEOL) operation may be performed. FEOL may refer to an operation of forming various elements such as transistors, capacitors, resistors, etc. on a substrate in a manufacturing process of an integrated circuit IC. For example, FEOL may include, but is not limited to, operations of planarizing and cleaning wafers, operations of forming trenches, operations of forming wells, operations of forming gate lines, operations of forming sources and drains, etc.

[0085] In operation S52, a back-end-of-line (BEOL) operation may be performed. BEOL may refer to an operation of interconnecting various components such as transistors, capacitors, resistors, etc. in a manufacturing process of an integrated circuit IC. For example, BEOL may include, but is not limited to, an operation of silicide gate regions, source regions, and drain regions, an operation of adding a dielectric, an operation of planarization, an operation of forming a hole, an operation of adding a metal layer, an operation of forming a through hole, an operation of forming a passivation layer, etc. Next, the integrated circuit IC may be packaged in a semiconductor package and may be used as a component for various applications.

[0086] Fig.181 is a block diagram showing a system on chip (SoC) 180 according to some embodiments of the inventive concept. The SoC 180 may include an integrated circuit according to some embodiments of the inventive concept as a semiconductor device. The SoC 180 may be a chip on which complex functional blocks such as intellectual property (IP) that perform various functions are implemented, and a multi-height unit according to an embodiment of the inventive concept may be included in one or more functional blocks of the SoC 180, so that the SoC 180 may provide higher efficiency, improved performance, and / or increased operational reliability.

[0087] refer to Fig.18 , SoC 180 may include a modem 182, a display controller 183, a memory 184, an external memory controller 185, a central processing unit (CPU) 186, a transaction unit 187, a power management integrated circuit (PMIC) 188, and a graphics processing unit (GPU) 189, and each functional block of SoC 180 may communicate with each other via a system bus 181.

[0088] The CPU 186 that controls the overall operation of the SoC 180 may control the operation of other functional blocks such as the modem 182, the display controller 183, the memory 184, the external memory controller 185, the transaction unit 187, the PMIC 188, and the GPU 189. The modem 182 may demodulate a signal received from the outside of the SoC 180, and / or may modulate a signal generated within the SoC 180 and send the modulated signal to the outside. The external memory controller 185 may control the operation of sending data to an external memory device connected to the SoC 120 and / or receiving data from an external memory device connected to the SoC 180. For example, a program and / or data stored in an external memory device may be provided to the CPU 186 or the GPU 189 under the control of the external memory controller 185. The CPU 189 may execute program instructions associated with graphics processing. The GPU 189 may receive graphics data via the external memory controller 185, and / or may send graphics data processed using the GPU 189 to the outside of the SoC 180 via the external memory controller 185. The transaction unit 187 may monitor data transactions of each functional block, and the PM1C 188 may control power supplied to each functional block under the control of the transaction unit 187. The display controller 183 may transmit data generated within the SoC 180 to a display (or display device) outside the SoC 180 by controlling the display.

[0089] The memory 184 can be a non-volatile memory, such as but not limited to, electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc., and can be a volatile memory, such as dynamic random access memory (DRAM), static random access memory (SDRAM), mobile DRAM, double data rate synchronous dynamic random access memory (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphic DDR (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), etc.

[0090] Fig.19 1 is a block diagram showing a computing system 190 including a memory configured to store a program according to some embodiments of the inventive concept. The method of manufacturing an integrated circuit according to some embodiments of the inventive concept (eg, Fig.17 At least one of the operations included in the method).

[0091] The computing system 190 may be a stationary computing system, such as a desktop computer, a workstation, and a server, or may be a portable computing system, such as a laptop computer. Fig.19 As shown, the computing system 190 may include a processor 191, an input / output device 192, a network interface 193, a random access memory (RAM) 194, a read-only memory (ROM) 195, and a storage device 196. The processor 191, the input / output device 192, the network interface 193, the RAM 194, the ROM 195, and the storage device 196 may be connected to a bus 197 and may communicate with each other via the bus 197.

[0092] Processor 191 may be referred to as a processing unit and may include at least one core, such as a microprocessor, an application processor (AP), a digital signal processor (DSP), a graphics processing unit (GPU), wherein the at least one core may execute any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extension IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, processor 191 may access a memory, i.e., RAM 194 or ROM 195, via bus 197, and may execute instructions stored in RAM 194 and / or ROM 195.

[0093] The RAM 194 may store a program 194_1 or a portion of the program 194_1 for manufacturing an integrated circuit according to some embodiments of the present inventive concept, and the program 194_1 may enable the processor 191 to perform a method of manufacturing an integrated circuit (eg, Fig.17 That is, the program 194_1 may include a plurality of instructions executable by the processor 191, and the plurality of instructions included in the program 194_1 may cause the processor 191 to perform the above-mentioned reference, for example Fig.17 At least some of the operations included in the described flows.

[0094] Even when power to the computing system 190 is interrupted, the storage device 196 does not lose stored data. For example, the storage device 196 may include a non-volatile storage device or storage medium, such as a tape, an optical disk, a magnetic disk, etc. In addition, the storage device 196 may be attachable to or detachable from the computing system 190. The storage device 196 may store a program 194_1 according to some embodiments of the present inventive concept, or the program 194_1 or at least a portion of the program 194_1 may be loaded from the storage device 196 to the RAM 194 before the processor 191 executes the program 194_1. Alternatively, the storage device 196 may store a file written in a program language, and the program 194_1 or at least a portion of the program 194_1 generated from the file by using a compiler, etc. may be loaded to the RAM 194. In addition, as Fig.19 As shown, the storage device 196 may store a database 196_1, and the database 196_1 may include information used to design an integrated circuit, such as Fig.17 Cell library D72.

[0095] The storage device 196 may store data to be processed by the processor 191 or data processed by the processor 191. That is, according to the program 194_1, the processor 191 may generate data by processing the data stored in the storage device 196, or may store the generated data in the storage device 196. For example, the storage device 196 may store Fig.17 The RTL data D71, netlist data D73 and / or layout data D74 in the.

[0096] The input / output device 192 may include an input device such as a keyboard or a pointing device or an output device such as a display device or a printer. For example, by using the input / output device 192, a user may trigger execution of the program 194_1 via the processor 191 by inputting Fig.17 The RTL data D71 and / or the netlist data D73, and / or determine Fig.17 Layout data D74.

[0097] Network interface 193 may provide access to an external network for computing system 190. For example, a network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

[0098] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: at least one active region extending in a first row along a first direction, including a first active region extending in the first row along the first direction and a second active region extending in the first row along the first direction; at least one active region extending in the second row along the first direction, including a third active region extending in the second row along the first direction and a fourth active region extending in the second row along the first direction; as well as A multi-height cell, comprising: the first active region and the second active region extending in the first row along the first direction, respectively having a first conductivity type and a second conductivity type; the third active region and the fourth active region extending in the second row along the first direction, respectively having the first conductivity type and the second conductivity type; and at least one gate line extending in a second direction intersecting the first direction, wherein the first active region and the third active region are adjacent to each other, and Wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by diffusion cut-off.

2. The integrated circuit according to claim 1, wherein: The diffusion cutoff includes single diffusion cutoff and double diffusion cutoff; wherein the first active region and the third active region are each terminated by the double diffusion cut-off, and The second active region and the fourth active region are each terminated by the single diffusion cutoff.

3. The integrated circuit according to claim 1, wherein: The diffusion cutoff includes single diffusion cutoff and double diffusion cutoff; wherein the first active region and the third active region are each terminated by the single diffusion cut-off, and The second active region and the fourth active region are each terminated by the double diffusion cutoff.

4. The integrated circuit according to claim 1, wherein: Respective portions of the first active region and the third active region are connected to each other.

5. The integrated circuit according to claim 4, wherein: The diffusion cutoff comprises a double diffusion cutoff; and Wherein, the first active region and the third active region are terminated by the double diffusion cut-off.

6. The integrated circuit according to claim 4, wherein: The multi-height unit includes a plurality of fin-shaped portions extending along the first direction, In the plan view of the integrated circuit, the number of fin-shaped portions overlapping with the first active area or the third active area is greater than the number of fin-shaped portions overlapping with the second active area or the fourth active area.

7. The integrated circuit according to claim 6, wherein: The multi-height cell includes transistors which are connected to each other in series and formed in the first active region and the third active region.

8. The integrated circuit of claim 1, wherein: The multi-height cell includes a contact connected to the first active region and the third active region and extending across a boundary between the first row and the second row in the second direction.

9. The integrated circuit of claim 1, wherein: The multi-height unit also includes: a power line extending along the first direction on a boundary between the first row and the second row; and A through hole is on a boundary between the first row and the second row and connected to the power line.

10. The integrated circuit of claim 1, wherein: The multi-height unit comprises: at least one first conductive pattern formed on the first conductive layer; and forming a second conductive pattern on a second conductive layer, the second conductive layer being on the first conductive layer, wherein the second conductive pattern is configured to route an input signal or an output signal, The second conductive pattern extends along the second direction and passes through a boundary between the first row and the second row.

11. The integrated circuit of claim 1 , further comprising: a cell placed in at least one of said first row and said second row; and The multi-height cell is spaced apart from adjacent cells in the cells along the first direction by a contact polysilicon pitch CPP or more.

12. The integrated circuit of claim 1 , further comprising: A single-height cell corresponds to the same circuit as the multiple-height cell and includes at least one active region terminated by a diffusion cutoff.

13. The integrated circuit of claim 12, wherein: The multiple height unit is configured to provide a higher operating speed than the single height unit.

14. The integrated circuit of claim 1, wherein: The multi-height unit includes a plurality of transistor groups connected in parallel to each other and configured to receive an input signal in common, Each transistor group in at least two transistor groups among the plurality of transistor groups includes transistors that share one gate line among the at least one gate line.

15. An integrated circuit comprising: a multi-height cell including a plurality of active regions in two or more rows and extending along a first direction, Wherein, the multi-height unit comprises: the plurality of active regions extending along the first direction and terminated by diffusion cutoff; at least one gate line extending along a second direction intersecting the first direction; a plurality of transistor groups connected in parallel with each other and configured to commonly receive an input signal; a power line extending along the first direction on a boundary between two adjacent rows among the two or more rows; and a through hole on a boundary between two adjacent rows among the two or more rows and connected to the power line, and Each transistor group in at least two transistor groups among the plurality of transistor groups includes transistors that share a gate line.

16. The integrated circuit of claim 15, wherein: The diffusion cutoff includes a single diffusion cutoff and a double diffusion cutoff; and Each of the plurality of active regions is terminated by the single diffusion cutoff or the double diffusion cutoff based on the conductivity type of the active region.

17. The integrated circuit of claim 16, wherein: An active region for an N-channel field effect transistor (NFET) among the plurality of active regions is terminated by the double diffusion cutoff, and Among the plurality of active regions, an active region for a P-channel field effect transistor (PFET) is terminated by the single diffusion cutoff.

18. The integrated circuit of claim 15, wherein: At least one active region among the plurality of active regions extends along the second direction across a boundary between two adjacent rows among the two or more rows.

19. The integrated circuit of claim 15, wherein: The multi-height unit comprises: at least one first conductive pattern formed on the first conductive layer; and forming a second conductive pattern on a second conductive layer, the second conductive layer being on the first conductive layer, wherein the second conductive pattern is configured to route an input signal or an output signal, The second conductive pattern passes through a boundary between at least two consecutive rows among the two or more rows to extend along the second direction.

20. An integrated circuit comprising: a multi-height cell including a plurality of active regions in two or more rows and extending along a first direction, Wherein, the multi-height unit comprises: the plurality of active regions extending along the first direction; at least one gate line extending along a second direction intersecting the first direction, a power line extending along the first direction on a boundary between two adjacent rows among the two or more rows; and a through hole on a boundary between two adjacent rows among the two or more rows and connected to the power line; and Each of the plurality of active regions is terminated by diffusion cut-off.

21. The integrated circuit of claim 20, wherein: The diffusion cutoff includes a single diffusion cutoff and a double diffusion cutoff; and Each of the plurality of active regions is terminated by the single diffusion cutoff or the double diffusion cutoff based on the conductivity type of the active region.

22. The integrated circuit of claim 21, wherein: An active region for an N-channel field effect transistor (NFET) among the plurality of active regions is terminated by the double diffusion cutoff, and An active region for a P-channel field effect transistor (PFET) among the plurality of active regions is terminated by the single diffusion cutoff.

23. The integrated circuit of claim 20, wherein: At least one active region among the plurality of active regions extends along the second direction across a boundary between two adjacent rows among the two or more rows.

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