A Static Var Generator (SVG) Multi-Machine Parallel Control System and Control Method

Abstract

The present invention provides a multi-machine parallel control system and control method for a static var compensator SVG. In the main machine of the static var generator SVG in multi-machine parallel connection, the communication modules of different manufacturers and the same manufacturer are designed, effectively solving the problem of parallel operation of static var generators SVG of the same manufacturer and different manufacturers. According to the different manufacturers of the parallel static var generators SVG, the communication control methods under different working conditions are given, enabling the parallel operation of static var generators SVG of different manufacturers to be realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of multi - machine parallel connection strategies of static var generators (SVG), and relates to a multi - machine parallel control system and control method for SVG of static var generators. Background Art

[0002] SVG (static var generator) is the most advanced reactive power compensation technology in the current power system. It can quickly and continuously output capacitive reactive power or inductive reactive power. By controlling the reactive power of the system, it can stabilize the grid voltage, improve the system power factor, and ensure the stable and efficient operation of the power system.

[0003] Due to the current limitation of power switch (IGBT) technology, the single - unit capacity of SVG equipment is not large. With the continuous increase of the power system capacity, the power system's demand for the capacity of reactive power compensation devices is also increasing. In the field, multiple SVG devices are often connected in parallel to operate on a section of bus. This requires SVG devices to be able to operate in parallel, and each SVG in parallel operation can automatically balance power.

[0004] However, currently in the industry, there is only the fiber - optic communication parallel connection function between the same manufacturers. Due to the different fiber - optic communication protocols of different manufacturers, fast fiber - optic communication cannot be carried out between different manufacturers, and the parallel connection function is limited to the same manufacturer. Summary of the Invention

[0005] The present invention provides a multi - machine parallel control system and control method for SVG of static var generators. This method combines two means of RS485 and fiber - optic communication to simultaneously control the reactive power scheduling of SVG from different manufacturers, overcoming the problem that traditional SVG parallel connection cannot schedule different manufacturers.

[0006] To achieve the above - mentioned purpose, the technical solution adopted by the present invention is as follows:

[0007] A multi - machine parallel control system for SVG of static var generators, which is composed of multiple groups of static var generators SVG from the same manufacturer and different manufacturers and a debugging background host computer. One static var generator SVG in the multiple groups of static var generators SVG is selected as the host, and other groups of static var generators SVG are slaves. The debugging background host computer is connected to RS485 communication #1 on the communication board in the SVG host of static var generators through RS485 communication. The RS485 communication #2 port in the SVG host of static var generators is connected to the RS485 communication interface in the SVG slaves of different manufacturers. Each fiber - optic transceiver module in the SVG host of static var generators is correspondingly connected to each fiber - optic transceiver module in the SVG slaves of the same manufacturer.

[0008] The structures of the multiple sets of static var compensators SVG are the same and are composed of a main control board and a communication board. The main control board is composed of a digital signal processor DSP, a field programmable gate array FPGA on the main control board, and several optical fiber transceiver modules. The digital signal processor DSP and the field programmable gate array FPGA on the main control board are connected by high-speed serial peripheral interface SPI communication. Each optical fiber transceiver module is connected to the field programmable gate array FPGA on the main control board by a data line, and data interaction and transmission are carried out between the optical fiber transceiver module and the field programmable gate array FPGA on the main control board. The communication board is composed of a field programmable gate array FPGA on the communication board, a data processor, RS485 communication #1, and RS485 communication #2. Among them, the field programmable gate array FPGA on the communication board and the data processor are connected by high-speed serial peripheral interface SPI communication. RS485 communication #1 and RS485 communication #2 are connected to the data processor by a data line, and data interaction and transmission are carried out between RS485 communication #1 and RS485 communication #2 and the data processor. The main control board and the communication board in the static var compensator SVG are connected by a dual-port operating memory RAM for communication.

[0009] The digital signal processor DSP in the main control board of the static var compensator SVG is responsible for control algorithms and reactive power calculation. The field programmable gate array FPGA on the main control board is responsible for communication data reception and transmission, including transmitting data to the field programmable gate array FPGA on the communication board and optical fiber communication to the field programmable gate array FPGA on the communication board of other static var compensators SVG. The field programmable gate array FPGA on the communication board in the communication board is responsible for data communication between the inside of the static var compensator SVG and the field programmable gate array FPGA on the main control board. The data processor in the communication board has two RS485 communication ports and is responsible for communication between the static var compensator SVG and the debugging background upper computer, and communication with the RS485 interfaces of static var compensators SVG from different manufacturers.

[0010] A control method for a multi-machine parallel control system of a static var compensator SVG is as follows:

[0011] 1). High-speed communication between static var compensators (SVG) of the same manufacturer: The data processor of the SVG host obtains the reactive power set value required by the upper computer of the debugging background through RS485 communication #1. The data transfer process of the SVG host is as follows: data processor -> communication board field programmable gate array (FPGA) -> main control board FPGA -> digital signal processor (DSP) of the main control board. Then, the DSP of the SVG host is responsible for calculating the total reactive power and distributing the reactive power of each SVG slave. The data distributed by the FPGA of the main control board in the SVG host is distributed to the corresponding optical fiber transceiver module in the SVG slave through the optical fiber transceiver module, and then transmitted by the optical fiber transceiver module to the FPGA of the main control board of the SVG slave. Finally, the FPGA of the main control board notifies the DSP in the SVG slave, and finally controls the reactive power output of the SVG slave.

[0012] 2). High-speed communication between static var compensators (SVG) of different manufacturers: The data processor of the communication board in the SVG host is responsible for communicating between the SVG host and the upper computer of the debugging background and communicating with other manufacturers' SVG through RS485 based on the MODBUS communication protocol. The data processor of the SVG host obtains the reactive power set value from the upper computer of the debugging background through RS485 communication #1, and obtains the status of other manufacturers' SVG through RS485 communication #2. Then, it is transmitted to the DSP in the following order in the SVG host: communication board data processor -> communication board FPGA -> main control board FPGA -> DSP of the main control board. Then, the DSP of the main control board calculates the obtained information and then transmits it back to RS485 communication #2 in the communication board. RS485 communication #2 distributes reactive power to other manufacturers' SVG. The reactive power set value of the SVG host is transmitted to the DSP through the FPGA of the main control board.

[0013] 3). For the case where there are static var compensators SVG from the same manufacturer and those from different manufacturers simultaneously, the data processor of the static var compensator SVG host schedules the reactive power capacities of the static var compensators SVG from different manufacturers and those of all the static var compensators SVG from the same manufacturer. The digital signal processor DSP of the static var compensator SVG host acts as a secondary host to allocate the reactive power capacity of each static var compensator SVG from the same manufacturer.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] 1. By adding communication interfaces and communication methods with the debugging background upper computer, the same manufacturer, and different manufacturers inside the SVG, the present invention realizes the parallel operation of SVGs from different manufacturers, the reactive power allocation operation, and also realizes the high-speed communication between SVGs from the same manufacturer.

[0016] 2. The present invention has standard communication interfaces on the SVG, which is convenient for connecting with other SVGs. And the communication with other SVGs adopts the standard MODBUS communication protocol, so the requirements for other SVGs are relatively low, facilitating connection and control. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a principle block diagram of the control method for multi-machine parallel connection of the static var compensator SVG of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following describes in detail the control method for multi-machine parallel connection of the SVG of the present invention with reference to the drawings:

[0019] As Figure 1 shown, a multi-machine parallel connection control system of a static var compensator SVG of the present invention consists of multiple groups of static var compensators SVG from the same manufacturer and different manufacturers and a debugging background upper computer. One static var compensator SVG is selected as the host from the multiple groups of static var compensators SVG, and the other groups of static var compensators SVG are slaves. The debugging background upper computer is connected to the RS485 communication #1 on the communication board in the static var compensator SVG host through RS485 communication. The RS485 communication #2 port in the static var compensator SVG host is connected to the RS485 communication interface in the static var compensator SVG slave from different manufacturers. Each optical fiber transceiver module in the static var compensator SVG host is correspondingly connected to each optical fiber transceiver module in the static var compensator SVG slave from the same manufacturer.

[0020] The structures of the multiple sets of static var compensators SVG are the same and are composed of a main control board and a communication board. The main control board is composed of a digital signal processor DSP, a field programmable gate array FPGA on the main control board, and several optical fiber transceiver modules. The digital signal processor DSP and the field programmable gate array FPGA on the main control board are connected by high-speed serial peripheral interface SPI communication. Each optical fiber transceiver module is connected to the field programmable gate array FPGA on the main control board by a data line, and data interaction and transmission are carried out between the optical fiber transceiver module and the field programmable gate array FPGA on the main control board. The communication board is composed of a field programmable gate array FPGA on the communication board, a data processor, RS485 communication #1, and RS485 communication #2. Among them, the field programmable gate array FPGA on the communication board and the data processor are connected by high-speed serial peripheral interface SPI communication. RS485 communication #1 and RS485 communication #2 are connected to the data processor by data lines, and data interaction and transmission are carried out between RS485 communication #1 and RS485 communication #2 and the data processor. The main control board and the communication board in the static var compensator SVG are connected by a dual-port operating memory RAM for communication.

[0021] The digital signal processor DSP in the main control board of the static var compensator SVG is responsible for control algorithms and reactive power calculation. The field programmable gate array FPGA on the main control board is responsible for communication data reception and transmission, including transmitting data to the field programmable gate array FPGA on the communication board and optical fiber communication to the field programmable gate array FPGA on the communication board of other static var compensators SVG. The field programmable gate array FPGA on the communication board is responsible for data communication between the inside of the static var compensator SVG and the field programmable gate array FPGA on the main control board. The data processor in the communication board has two RS485 communication ports and is responsible for communicating between the static var compensator SVG and the debugging background upper computer and communicating with the RS485 interfaces of static var compensators SVG from different manufacturers.

[0022] The control method of a multi-machine parallel control system of a static var compensator SVG according to the present invention is as Figure 1 shown, and is specifically as follows:

[0023] 1). High-speed communication between static var compensators (SVG) of the same manufacturer: The data processor of the SVG host obtains the reactive power set value required by the upper computer of the debugging background through RS485 communication #1. The data transfer process of the SVG host is as follows: data processor -> communication board field programmable gate array (FPGA) -> main control board FPGA -> digital signal processor (DSP) of the main control board. Then, the DSP of the SVG host is responsible for the overall reactive power calculation and the reactive power distribution of each SVG slave of the same manufacturer. The data distributed by the FPGA of the main control board in the SVG host is distributed to the corresponding optical fiber transceiver module in the SVG slave through the optical fiber transceiver module, and then transmitted by the optical fiber transceiver module to the FPGA of the main control board of the SVG slave. Finally, the FPGA of the main control board notifies the DSP in the SVG slave, and finally controls the reactive power output of the SVG slave.

[0024] 2). High-speed communication between static var compensators (SVG) of different manufacturers. The data processor ARM on the communication board in the SVG host is responsible for the communication between the SVG host and the upper computer of the debugging background and the RS485 communication with other manufacturers' SVG based on the MODBUS communication protocol. SVG#1 acts as the host, and SVG#3 and SVG#4 of different manufacturers act as slaves. The ARM of SVG#1 obtains the reactive power set value from the upper computer of the debugging background through RS485 communication #1, and the ARM of SVG#1 obtains the status of other manufacturers' SVG through RS485 communication #2. Then, it is transmitted to the DSP in SVG#1 in the following order: communication board ARM -> communication board FPGA -> main control board FPGA -> main control board DSP. Then, the DSP calculates the obtained information and then transmits it back to RS485 communication #2 on the communication board. RS485 communication #2 distributes reactive power to other manufacturers' SVG, and the reactive power set value of the local SVG is transmitted to the DSP through the FPGA.

[0025] 3. For the case where SVG of the same manufacturer and SVG of different manufacturers exist simultaneously, the ARM of SVG#1 schedules the reactive power capacity of SVG of different manufacturers and all SVG of the same manufacturer, and the DSP of SVG#1 acts as a secondary host to distribute the reactive power capacity of each SVG of the same manufacturer.

[0026] The above description is only one implementation manner of the present invention, not all or the only implementation manner. Any equivalent transformation of the technical solution of the present invention adopted by those of ordinary skill in the art by reading the specification of the present invention is covered by the claims of the present invention.

Claims

1. A static var compensator SVG multi-machine parallel control system, characterized in that: The system consists of multiple groups of static var compensators (SVG) from the same manufacturer and different manufacturers, as well as a debugging background host computer. One of the multiple groups of SVG is selected as the host, and the other groups are slaves. The debugging background host computer is connected to the RS485 communication #1 on the communication board in the SVG host through RS485 communication. The RS485 communication #2 port in the SVG host is connected to the RS485 communication interface in the SVG slaves from different manufacturers. Each optical fiber transceiver module in the SVG host is correspondingly connected to each optical fiber transceiver module in the SVG slaves from the same manufacturer; The structures of the multiple groups of SVG are the same, and each consists of a main control board and a communication board. The main control board consists of a digital signal processor (DSP), a field programmable gate array (FPGA) on the main control board, and several optical fiber transceiver modules. The DSP and the FPGA on the main control board are connected through Serial Peripheral Interface (SPI) communication at high speed. Each optical fiber transceiver module is connected to the FPGA on the main control board through a data line, and data interaction and transmission occur between the optical fiber transceiver module and the FPGA on the main control board. The communication board consists of an FPGA on the communication board, a data processor, RS485 communication #1, and RS485 communication #2. The FPGA on the communication board and the data processor are connected through SPI communication at high speed. RS485 communication #1 and RS485 communication #2 are connected to the data processor through data lines, and data interaction and transmission occur between RS485 communication #1 and RS485 communication #2 and the data processor. The main control board and the communication board in the SVG are connected through a dual-port random access memory (RAM) for communication.

2. The multi - machine parallel control system of a static var compensator SVG according to claim 1, characterized in that: The digital signal processor (DSP) in the main control board of the SVG is responsible for control algorithms and reactive power calculation. The FPGA on the main control board is responsible for communication data reception and transmission, including transmitting data to the FPGA on the communication board and optical fiber communication to the FPGA on the communication board of other SVGs. The FPGA on the communication board in the communication board is responsible for data communication between the inside of the SVG and the FPGA on the main control board. The data processor in the communication board has two RS485 communication ports and is responsible for communication between the SVG and the debugging background host computer, as well as communication with the RS485 interface of the SVGs from different manufacturers.

3. The control method of the multi-machine parallel control system of the static var compensator (SVG) as claimed in claim 1 or 2 is as follows: 1). High-speed communication between static var compensators SVG of the same manufacturer: The data processor of the static var compensator SVG host obtains the reactive power set value required by the upper computer of the debugging background through RS485 communication #1. The data transfer process of the static var compensator SVG host is as follows: data processor -> communication board field programmable gate array FPGA -> main control board field programmable gate array FPGA -> digital signal processor DSP of the main control board. Then, the digital signal processor DSP of the static var compensator SVG host is responsible for the overall reactive power calculation and the reactive power distribution of each slave static var compensator SVG. The data distributed by the main control board field programmable gate array FPGA in the static var compensator SVG host is distributed to the corresponding optical fiber transceiver module in the slave static var compensator SVG through the optical fiber transceiver module, and then transmitted by the optical fiber transceiver module to the main control board field programmable gate array FPGA of the slave static var compensator SVG. Finally, the main control board field programmable gate array FPGA notifies the digital signal processor DSP in the slave static var compensator SVG, and finally controls the reactive power output of the slave static var compensator SVG; 2). High-speed communication between static var compensators SVG of different manufacturers: The data processor of the communication board in the static var compensator SVG host is responsible for the communication between the static var compensator SVG host and the upper computer of the debugging background and the RS485 communication with static var compensators SVG of other manufacturers based on the MODBUS communication protocol. The data processor of the static var compensator SVG host obtains the reactive power set value from the upper computer of the debugging background through RS485 communication #1, and obtains the status of static var compensators SVG of other manufacturers through RS485 communication #2. Then, it is transmitted to the digital signal processor DSP in the static var compensator SVG host in the following order: communication board data processor -> communication board field programmable gate array FPGA -> main control board field programmable gate array FPGA -> digital signal processor DSP of the main control board. Then, the digital signal processor DSP of the main control board calculates the obtained information, and then transmits it back to RS485 communication #2 in the communication board. RS485 communication #2 distributes reactive power to static var compensators SVG of other manufacturers. The reactive power set value of the static var compensator SVG host is transmitted to the digital signal processor DSP through the main control board field programmable gate array FPGA; 3). For the case where there are both static var compensators SVG of the same manufacturer and static var compensators SVG of different manufacturers at the same time, the data processor of the static var compensator SVG host schedules the reactive power capacity of static var compensators SVG of different manufacturers and the reactive power capacity of all static var compensators SVG of the same manufacturer. The digital signal processor DSP of the static var compensator SVG host acts as a secondary host to distribute the reactive power capacity of each static var compensator SVG of the same manufacturer.

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