Multi-band network frequency characteristics tester

Abstract

A multi-band network frequency characteristic tester includes a signal source circuit, a gain circuit, a signal conditioning circuit, a programmable attenuation circuit, an analog multiplier circuit, an active low-pass filter circuit, a microprocessor and a display circuit. The signal source circuit outputs a signal source and inputs the signal source into the gain circuit. The signal after gain is transmitted to the signal conditioning circuit for conditioning. The signal conditioned by the signal conditioning circuit is sequentially input into the programmable attenuation circuit and the analog multiplier circuit. The analog multiplier circuit modulates the input signal and outputs the signal to the active low-pass filter circuit. The active low-pass filter circuit filters out the high-frequency signal in the signal to obtain a DC signal. The microprocessor receives the output signal of the active low-pass filter circuit and outputs the signal to the display circuit according to the received signal. The display circuit displays the received signal. The multi-band network frequency characteristic tester described in the present invention has low cost, high integration, good stability, and high application value and practical significance.

Description

Technical Field

[0001] The invention belongs to the technical field of frequency licensing test, and in particular relates to a multi-band network frequency characteristic tester. Background Art

[0002] The frequency characteristic meter is a measuring instrument that can directly measure the amplitude-frequency characteristic curve and phase-frequency characteristic curve of a network and display them intuitively on the display screen. It is mainly used to measure the frequency characteristics or frequency response of a linear two-port network and is widely used in the field of modern electronic measurement.

[0003] At present, foreign advanced frequency characteristic testers are mainly concentrated in the fields of radio frequency and microwave. The most representative and leading industry standards are Agilent in the United States and Rohde & Schwarz in Germany. Most of the frequency characteristic testers produced by these companies are positioned at the high end, with a very wide frequency sweep range, spanning low frequency, medium frequency, high frequency, radio frequency, microwave and other fields, with frequencies up to GHz or even tens of GHz. They have high accuracy but are extremely expensive. Products concentrated in lower frequency bands such as medium frequency or high frequency range are rarely involved, thus limiting the use of low-end customers.

[0004] Although some domestic manufacturers have designed and produced digital frequency characteristic testers for medium and high frequency bands, most designs use peak detection or effective value detection methods to measure the amplitude-frequency characteristic curve of the network under test, and use the phase difference method to measure the phase-frequency characteristic curve of the network under test. The circuit structure is relatively complex, the degree of integration is not high, the stability is relatively poor, the measurement accuracy, especially the phase measurement error, is large, and the price is relatively expensive, which limits its promotion and scope of use.

[0005] The more representative ones are: SA1000 series digital frequency characteristics tester produced by Shijiazhuang Shuying Instrument Co., Ltd. is the first domestic fully digital frequency characteristics tester that uses DDS (direct digital synthesizer) as the frequency source and is controlled by DSP, CPLD, and microprocessor. It can complete dual tests of amplitude-frequency characteristics and phase-frequency characteristics. The sweep output voltage is greater than 0.5V, and the maximum sweep range can reach 20Hz~140MHz. However, there are problems such as poor stability and low measurement accuracy.

[0006] The vector network analyzer GA3623 produced by Nanjing Guorui Antaixin Company mainly uses DDS technology, frequency conversion technology and DSP technology to extract amplitude information and phase information from the output signal of the measurement network, thereby realizing the measurement of network parameters and frequency characteristics. The test instrument has a sweep frequency range of 300KHz~3GHz and is also mainly used in the RF and microwave fields. The price of each unit exceeds 130,000 yuan.

[0007] Frequency characteristic testers are often used in experimental teaching or product development of electronics, communications and other majors in ordinary universities, but most domestic universities are not equipped with such test instruments.

[0008] There are two main reasons for this: First, according to the needs of communication circuit experimental teaching, frequency characteristic testers below 30MHZ usually meet the requirements, while most of the mainstream frequency characteristic meter products on the market have a sweep range of more than 100MHZ, resulting in unnecessary waste of resources and are relatively expensive. For example, the domestically produced Nanjing Sheng SP3060 low-end product has a sweep range of 120MHZ and costs at least RMB 12,000, while foreign products are much more expensive than this; second, many domestic related products do not have the phase-frequency characteristic measurement function, and generally have defects such as low integration and poor measurement accuracy.

[0009] Therefore, it is particularly necessary to design a low-, medium- and high-frequency band frequency characteristic tester with low cost, high integration, good stability and high measurement accuracy to meet the experimental teaching needs of general electronic colleges or scientific research institutions for product development, and it has high application value and practical significance. Summary of the invention

[0010] The invention aims to provide a multi-band network frequency characteristic tester with good use effect and low cost.

[0011] To solve the above technical problems, the present invention provides the following technical solutions: a multi-band network frequency characteristic tester, comprising a signal source circuit, a gain circuit, a signal conditioning circuit, a programmable attenuation circuit, an analog multiplier circuit, an active low-pass filter circuit, a microprocessor and a display circuit, wherein the signal source circuit outputs a signal source and inputs the signal source into the gain circuit, the signal is amplified by the gain circuit, the amplified signal is transmitted to the signal conditioning circuit for conditioning, the signal conditioned by the signal conditioning circuit is input into the programmable attenuation circuit, the programmable attenuation circuit reduces the signal voltage amplitude and then inputs the signal into the analog multiplier circuit, the analog multiplier circuit modulates the input signal and then outputs the signal to the active low-pass filter circuit, the active low-pass filter circuit filters out the high-frequency signal in the signal to obtain a DC signal, the microprocessor receives the output signal of the active low-pass filter circuit, and outputs the signal to the display circuit according to the received signal, and the display circuit displays the received signal.

[0012] The signal source circuit comprises an AD9854 chip, an external clock pin of the AD9854 chip is connected to a clock circuit, a data input pin of the AD9854 chip is connected to a DC power supply via a resistor; a power input end of the AD9854 chip is connected to a DC power supply via an inductor; and an output pin of the AD9854 chip is connected to a filter module.

[0013] There are two filter modules, which are respectively connected to two output pins of the AD9854 chip; the two filter modules have the same structure, both of which include: a first filter resistor, a second filter resistor, a first filter capacitor, a second filter capacitor, a third filter capacitor, a fourth filter capacitor, a fifth filter capacitor, a sixth filter capacitor, a seventh filter capacitor, a first filter inductor, a second filter inductor and a third filter inductor: the output pin of the AD9854 chip is the first filter capacitor, and the first filter capacitor, the second filter capacitor and the third filter capacitor are connected in series; the output pin of the AD9854 chip is also grounded through the first filter resistor; the first filter inductor is connected between the two ends of the first filter capacitor; the two ends of the first filter inductor are also grounded through the fourth and fifth filter capacitors respectively; the second filter inductor is connected between the two ends of the second filter capacitor; the two ends of the second filter inductor are also grounded through the fifth and sixth filter capacitors respectively; the third filter inductor is connected between the two ends of the third filter capacitor; the two ends of the third filter inductor are also grounded through the sixth and seventh filter capacitors respectively; the second end of the third filter capacitor is the output end of the signal source circuit, and the second end of the third filter capacitor is also grounded through the second filter resistor.

[0014] The gain circuit includes a first AD603 chip, a second AD603 chip, an AD8307 chip, a NE5532 chip, an OPA630 chip and an OPA695 chip; the signal output end of the signal source circuit is connected to the operational amplifier input pin of the first AD603 chip through a first gain resistor and a third gain resistor in sequence; the second end of the first gain resistor is also grounded through the second gain resistor; the low voltage control end of the first AD603 chip and the common end of the operational amplifier are grounded; the voltage input end of the first AD603 chip is connected to a DC power supply; the feedback end of the first AD603 chip U201 is connected to the operational amplifier output end and then connected to the second AD603 chip U203 through the third and fourth gain resistors in sequence; the second end of the third gain resistor is also grounded through the eighth gain resistor; the positive voltage control ends of the first and second AD603 chips U203 are grounded through the fourteenth gain resistor.

[0015] The third gain capacitor and the fourth gain capacitor connected in parallel are connected between the positive voltage control terminal of the second AD603 chip and the fourteenth gain resistor; the feedback terminal of the second AD603 chip is connected to the output terminal of the operational amplifier and then connected to the input pin of the OPA695 chip through the first gain capacitor, and the input pin of the OPA695 chip is also grounded through the ninth gain resistor. The output pin of the OPA695 chip is connected to the fifth gain resistor; the fifth gain resistor is connected to the sixth gain resistor, and the sixth gain resistor is connected to the signal output terminal of the gain circuit.

[0016] The output pin of the OPA695 chip is also connected to the ground through the thirteenth gain resistor and the fifteenth gain resistor in sequence; the second end of the thirteenth gain resistor is connected to the in-phase input end of the OPA630 chip, and the twenty-sixth gain resistor is connected between the inverting input end and the output end of the OPA630 chip; the output end of the OPA630 chip is respectively connected to the first variable gain capacitor and the twenty-third gain resistor, the twenty-third gain resistor is respectively grounded and the second variable gain capacitor, the second ends of the first variable gain capacitor and the second variable gain capacitor are respectively connected to the two signal input ends of the AD8307 chip through the twenty-first and twenty-fifth gain resistors, the output end of the AD8307 chip is connected to the twenty-second gain resistor after filtering through the eighth gain capacitor, the second end of the twenty-second gain resistor is connected to the in-phase input end of the first gain NE5532 chip, and the inverting input end and the output end of the first gain NE5532 chip are connected; the in-phase input end of the second gain NE5532 chip is connected to the external interface through the twenty-seventh gain resistor.

[0017] The output end of the first gain NE5532 chip is connected to the inverting input end of the second gain NE5532 chip through the twenty-fourth gain resistor. The second end of the twenty-fourth gain resistor is also connected to the fifth gain capacitor and the seventeenth gain resistor connected in parallel, and the twenty-fourth gain resistor is also connected to the eighteenth gain resistor, and the second end of the eighteenth gain resistor is grounded through the sixteenth gain resistor and the twentieth gain resistor respectively. The fifth gain capacitor and the seventeenth gain resistor connected in parallel are also grounded through the fourteenth gain resistor.

[0018] The fifth gain capacitor and the seventeenth gain resistor connected in parallel are also connected to the forward voltage control terminals of the first AD603 chip and the second AD603 chip.

[0019] The signal conditioning circuit and the programmable attenuation circuit have the same structure, and both include an amplifier circuit and a control circuit; the amplifier circuit includes a first amplifier AD603 chip, a second amplifier AD603 chip and an amplifier OPA690 chip; the signal output end of the gain circuit is connected to the input end of the first amplifier AD603 chip, and the input end of the first amplifier AD603 chip is also grounded through a first amplifier resistor; the input end of the first amplifier AD603 chip is also connected to a deviation adjustment circuit; the signal output end of the first amplifier AD603 chip is connected to the input end of the second amplifier AD603 chip through a fifth amplifier resistor, and the input end of the second amplifier AD603 chip is also connected to a deviation adjustment circuit; the input end of the second amplifier AD603 chip is also grounded through an eighth amplifier capacitor; the voltage control ends of the first and second amplifier AD603 chips are both connected to the output end of the control circuit, and the voltage control ends of the first and second amplifier AD603 chips are also grounded through a sixth amplifier capacitor and a fourth amplifier capacitor respectively; the output end of the second amplifier AD603 chip is connected to the in-phase input end of the amplifier OPA690 chip through a seventh amplifier resistor, and the in-phase input end of the amplifier OPA690 chip is also connected to the eighth amplifier capacitor. The inverting input terminal of the amplified OPA690 chip is grounded through the ninth amplified resistor, and the inverting input terminal of the amplified OPA690 chip is also connected to the output terminal of the amplified OPA690 chip through the tenth amplified resistor, the output terminal of the amplified OPA690 chip is grounded through the twelfth amplified resistor, and the output terminal of the amplified OPA690 chip is also connected to the output pin of the amplifying circuit through the eleventh amplified resistor; the control circuit includes an amplified first NE5532 chip and an amplified second NE5532 chip; the in-phase input terminal of the amplified first NE5532 chip is connected to a DC power supply, the inverting input terminal of the amplified first NE5532 chip is connected to the output terminal of the amplified first NE5532 chip, the output terminal of the amplified first NE5532 chip is connected to the inverting input terminal of the amplified second NE5532 chip through the first control resistor, the inverting input terminal of the amplified second NE5532 chip is also connected to the output terminal of the amplified second NE5532 chip through the second control resistor, and the output terminal of the amplified second NE5532 chip is connected to the voltage control terminals of the first and second amplified AD603 chips through the third control resistor.

[0020] The bias adjustment circuit includes a first bias adjustment resistor, a second bias adjustment resistor, a bias adjustment sliding rheostat, a bias adjustment filter capacitor and a bias adjustment voltage divider resistor; the first bias adjustment resistor and the second bias adjustment resistor are respectively connected to the two ends of the bias adjustment sliding rheostat, the sliding end of the bias adjustment sliding rheostat is connected to the bias adjustment voltage divider resistor, and the bias adjustment voltage divider resistor is connected to the input ends of the first and second amplifier AD603 chips.

[0021] The analog multiplier circuit comprises a first AD835 chip and a second AD835 chip; the inverting input X multiplicand terminal of the first AD835 chip is connected to the first output terminal of the signal source circuit, the non-inverting input Y multiplicand terminal of the first AD835 chip is connected to the signal output terminal of the program-controlled attenuation circuit; the inverting input X multiplicand terminal of the second AD835 chip is connected to the second output terminal of the signal source circuit, wherein the signals outputted from the first output terminal and the second output terminal of the signal source circuit are in an orthogonal relationship; the non-inverting input Y multiplicand terminal of the second AD835 chip is connected to the program-controlled attenuation circuit. The signal output end of the controlled attenuation circuit; the signal output ends of the first and second AD835 chips are respectively connected to the signal output end of the analog multiplier circuit through the first multiplication voltage-dividing resistor; a multiplication filter capacitor is also connected to the multiplication voltage-dividing resistor; the summing input ends of the first AD835 chip and the second AD835 chip are connected to the end of the multiplication adjustable resistor, and the summing input ends of the first and second AD835 chips are also grounded through the second multiplication voltage-dividing resistor; the adjustable end of the multiplication adjustable resistor is connected to the signal output end of the first AD835 chip or the second AD835 chip.

[0022] The non-inverting input Y multiplicand terminal of the first AD835 chip and the second AD835 chip are connected through a short-circuit sleeve.

[0023] There are two active low-pass filter circuits, which are connected to the signal output ends of the first AD835 chip and the second AD835 chip respectively; the active low-pass filter circuit includes a first LM324 chip and a second LM324 chip; the signal output end of the multiplier circuit is connected to the in-phase input end of the first LM324 chip through the first low-pass filter resistor and the second low-pass filter resistor in sequence; the second end of the first low-pass filter resistor and the first end of the second low-pass filter resistor are also connected to a first low-pass filter capacitor, the first low-pass filter capacitor is connected to the output end of the first LM324 chip, and the output end of the first LM324 chip is also connected to The inverting input terminal of the first LM324 chip is connected to the inverting input terminal of the second LM324 chip through the third low-pass filter resistor and the fourth low-pass filter resistor in sequence, the second low-pass filter capacitor is also connected to the second end of the third low-pass filter resistor and the first end of the fourth low-pass filter resistor, the second low-pass filter capacitor is connected to the output terminal of the second LM324 chip, and the output terminal of the second LM324 chip is also connected to the inverting input terminal of the second LM324 chip; the inverting input terminals of the first LM324 chip and the second LM324 chip are also grounded through the third low-pass filter capacitor and the fourth low-pass filter capacitor respectively. The signal output terminal of the second LM324 chip is the signal output terminal of the active low-pass filter circuit; the voltage input terminals of the first and second LM324 chips are both connected to the DC power supply, and the common terminals of the first and second LM324 chips are grounded.

[0024] The display circuit includes an LCD display screen, and the LCD display screen is connected to the signal output terminal of the microprocessor.

[0025] Through the above technical scheme, the beneficial effects of the present invention are as follows: the multi-band network frequency characteristics tester described in the present invention has the advantages of low cost, high integration and good stability, and at the same time, its measurement accuracy is relatively high, which can meet the experimental teaching needs of general electronic colleges and universities or the needs of scientific research institutions; it can test the frequency characteristics of low, medium and high frequency bands, making up for the gap in this type of frequency tester, and has high application value and practical significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is the principle frame of the present invention;

[0027] Figure 2 is the schematic diagram of the signal source circuit;

[0028] Figure 3 is the schematic diagram of the gain circuit;

[0029] Figure 4 This is the schematic diagram of the amplifier circuit;

[0030] Figure 5 This is the control circuit schematic diagram;

[0031] Figure 6 To simulate the multiplier circuit;

[0032] Figure 7 This is the schematic diagram of the filter circuit. DETAILED DESCRIPTION

[0033] Multi-band network frequency characteristics tester, such as Figure 1 As shown, it includes a signal source circuit, a gain circuit, a signal conditioning circuit, a programmable attenuation circuit, an analog multiplier circuit, an active low-pass filter circuit, a microprocessor and a display circuit.

[0034] The signal source circuit outputs the signal source and inputs the signal source to the gain circuit, the signal is amplified by the gain circuit, the amplified signal is transmitted to the signal conditioning circuit for conditioning, the signal conditioned by the signal conditioning circuit is input to the programmable attenuation circuit, the programmable attenuation circuit reduces the signal voltage amplitude and inputs the signal to the analog multiplier circuit, the analog multiplier circuit modulates the input signal and outputs the signal to the active low-pass filter circuit, the active low-pass filter circuit filters out the high-frequency signal in the signal to obtain a DC signal, the microprocessor receives the output signal of the active low-pass filter circuit, and outputs the signal to the display circuit according to the received signal, and the display circuit displays the received signal.

[0035] The microprocessor uses a single-chip microcomputer (model: STM32F103VET6), and the single-chip microcomputer is connected to a minimum system, wherein the minimum system is a mature existing technology and will not be described in detail here.

[0036] like Figure 2 As shown, the signal source circuit includes an AD9854 chip U101, and the external clock pin (port RECLK) of the AD9854 chip U101 is connected to a clock circuit X101. The clock circuit X101 is a mature existing technology, and two crystal oscillators can be selected. The data input pin of the AD9854 chip U101 is connected to a DC power supply through a resistor; the power input terminal of the AD9854 chip U101 is connected to a DC power supply through an inductor; and the output pin of the AD9854 chip U101 is connected to a filter module.

[0037] The filter module is used for filtering, wherein there are two filter modules, which are respectively connected to the two output pins (OUT1 and OUT2) of the AD9854 chip U101; the two filter modules have the same structure, including: a first filter resistor R108, a second filter resistor, a first filter capacitor C105, a second filter capacitor C106, a third filter capacitor C107, a fourth filter capacitor C1012, a fifth filter capacitor C109, a sixth filter capacitor C1010, a seventh filter capacitor C1011, a first filter inductor L102, a second filter inductor L103 and a third filter inductor L101.

[0038] The output pins (IOUT1, IOUT2) of the AD9854 chip U101 are connected to the first filter capacitor C105, and the first filter capacitor C105, the second filter capacitor C106 and the third filter capacitor C107 are connected in series. The output pin of the AD9854 chip U101 is also grounded through the first filter resistor R108; the first filter inductor L102 is connected between the two ends of the first filter capacitor C105; the two ends of the first filter inductor L102 are also grounded through the fourth and fifth filter capacitors C109 respectively; the second filter inductor L103 is connected between the two ends of the second filter capacitor C106; the two ends of the second filter inductor L103 are also grounded through the fifth and sixth filter capacitors C1010 respectively; the third filter inductor L101 is connected between the two ends of the third filter capacitor C107; the two ends of the third filter inductor L101 are also grounded through the sixth and seventh filter capacitors C1011 respectively; the second end of the third filter capacitor C107 is the output end of the signal source circuit, and the second end of the third filter capacitor C107 is also grounded through the second filter resistor.

[0039] like Figure 3The gain circuit shown can make the amplitude value of the signal output within the frequency variation range basically unchanged, so that the signal meets the subsequent requirements. The gain circuit includes a first AD603 chip U201, a second AD603 chip U203, an AD8307 chip U205, a first gain NE5532 chip IC201A and a second gain NE5532 chip IC201B, an OPA630 chip U204 and an OPA695 chip U202.

[0040] The signal output end of the signal source circuit is connected to the operational amplifier input pin of the first AD603 chip U201 through the first gain resistor R201 and the second gain resistor R202 in sequence; the second end of the first gain resistor R201 is also grounded through the seventh gain resistor; the low voltage control end of the first AD603 chip U201 and the common end of the operational amplifier are grounded; the voltage input end of the first AD603 chip U201 is connected to a DC power supply; the feedback end of the first AD603 chip U201 is connected to the operational amplifier output end and then connected to the second AD603 chip U203 through the third and fourth gain resistors R204 in sequence; the second end of the third gain resistor R203 is also grounded through the eighth gain resistor R208; the positive voltage control ends of the first and second AD603 chips U203 are grounded through the fourteenth gain resistor R2014.

[0041] A third gain capacitor C203 and a fourth gain capacitor C204 are connected in parallel between the positive voltage control terminal of the second AD603 chip U203 and the fourteenth gain resistor R2014; the feedback terminal of the second AD603 chip U203 is connected to the output terminal of the operational amplifier and then connected to the input pin of the OPA695 chip U202 through the first gain capacitor C201, and the input pin of the OPA695 chip U202 is also grounded through the ninth gain resistor R209. The output pin of the OPA695 chip U202 is connected to the fifth gain resistor R205; the fifth gain resistor R205 is connected to the sixth gain resistor R206, and the sixth gain resistor R206 is connected to the signal output terminal of the gain circuit.

[0042] The output pin of the OPA695 chip U202 is also connected to the ground through the thirteenth gain resistor R2013 and the fifteenth gain resistor R2015 in sequence; the second end of the thirteenth gain resistor R2013 is connected to the in-phase input end of the OPA630 chip U204, and the twenty-sixth gain resistor R2026 is connected between the inverting input end and the output end of the OPA630 chip U204; the output end of the OPA630 chip U204 is respectively connected to the first variable gain capacitor E201 and the twenty-third gain resistor R2023, the twenty-third gain resistor R2023 is respectively connected to the ground and the second variable gain capacitor E202, the first variable gain capacitor E201 and the second variable gain capacitor The second end of capacitor E202 is connected to the two signal input ends of the AD8307 chip U205 through the twenty-first and twenty-fifth gain resistors R2025 respectively, the output end of the AD8307 chip U205 is connected to the twenty-second gain resistor R2022 after being filtered by the eighth gain capacitor C208, the second end of the twenty-second gain resistor R2022 is connected to the non-inverting input end of the first gain NE5532 chip IC201A, and the inverting input end and output end of the first gain NE5532 chip IC201A are connected; the non-inverting input end of the second gain NE5532 chip IC201B is connected to the external interface JP207 through the twenty-seventh gain resistor R2027.

[0043] The output end of the first gain NE5532 chip IC201A is connected to the inverting input end of the second gain NE5532 chip IC201B through the twenty-fourth gain resistor R2024. The second end of the twenty-fourth gain resistor R2024 is also connected to the fifth gain capacitor C205 and the seventeenth gain resistor R2017 connected in parallel, and the twenty-fourth gain resistor R2024 is also connected to the eighteenth gain resistor R2018, and the second end of the eighteenth gain resistor R2018 is grounded through the sixteenth gain resistor R2016 and the twentieth gain resistor R2020 respectively. The fifth gain capacitor C205 and the seventeenth gain resistor R2017 connected in parallel are also grounded through the fourteenth gain resistor R2014.

[0044] The fifth gain capacitor C205 and the seventeenth gain resistor R2017 connected in parallel are also connected to the forward voltage control terminals of the first AD603 chip U201 and the second AD603 chip.

[0045] The signal after the gain circuit needs to enter the signal conditioning circuit and the programmable attenuation circuit in turn. The signal conditioning circuit and the programmable attenuation circuit have the same structure, both including an amplifier circuit and a control circuit. After the signal conditioning circuit and the programmable attenuation circuit, the signal meets the requirements of the analog multiplier and increases the detection accuracy.

[0046] like Figure 4As shown, the amplifier circuit includes a first amplifier AD603 chip U701, a second amplifier AD603 chip U702 and an amplifier OPA690 chip U703; the signal output end of the gain circuit is connected to the input end of the first amplifier AD603 chip U701, and the input end of the first amplifier AD603 chip U701 is also grounded through a first amplifier resistor R7012; the input end of the first amplifier AD603 chip U701 is also connected to a deviation adjustment circuit; the signal output end of the first amplifier AD603 chip U701 is connected to the input end of the second amplifier AD603 chip U702 through a fifth amplifier resistor R709, and the input end of the second amplifier AD603 chip U702 is also connected to a deviation adjustment circuit.

[0047] Among them, the deviation adjustment circuit includes a first deviation adjustment resistor R702, a second deviation adjustment resistor R703, a deviation adjustment sliding rheostat RP701, a deviation adjustment filter capacitor C1 and a deviation adjustment voltage divider resistor R707; the first deviation adjustment resistor R702 and the second deviation adjustment resistor R703 are respectively connected to the two ends of the deviation adjustment sliding rheostat RP701, the sliding end of the deviation adjustment sliding rheostat RP701 is connected to the deviation adjustment voltage divider resistor R707, and the deviation adjustment voltage divider resistor R707 is connected to the input ends of the first and second amplifier AD603 chips.

[0048] The input end of the second amplifier AD603 chip U702 is also grounded through the eighth amplifier capacitor C704; the voltage control ends of the first and second amplifier AD603 chips are both connected to the output end of the control circuit, and the voltage control ends of the first and second amplifier AD603 chips are also grounded through the sixth amplifier capacitor C703 and the fourth amplifier capacitor C706 respectively; the output end of the second amplifier AD603 chip U702 is connected to the in-phase input end of the amplifier OPA690 chip U703 through the seventh amplifier resistor R7011, and the in-phase input end of the amplifier OPA690 chip U703 is connected to the in-phase input end of the amplifier OPA690 chip U703. The phase input terminal is also grounded through the eighth amplifying resistor R7013 and the first amplifying capacitor C705 respectively; the inverting input terminal of the amplifying OPA690 chip U703 is grounded through the ninth amplifying resistor R706, and at the same time, the inverting input terminal of the amplifying OPA690 chip is also connected to the output terminal of the amplifying OPA690 chip through the tenth amplifying resistor R701, and the output terminal of the amplifying OPA690 chip is grounded through the twelfth amplifying resistor R7014, and the output terminal of the amplifying OPA690 chip is also connected to the output pin of the amplifying circuit through the eleventh amplifying resistor R7010.

[0049] like Figure 5As shown, the control circuit includes an amplifying first NE5532 chip IC701B and an amplifying second NE5532 chip IC701A; the in-phase input terminal of the amplifying first NE5532 chip IC701B is connected to a DC power supply, the inverting input terminal of the amplifying first NE5532 chip IC701B is connected to the output terminal of the amplifying first NE5532 chip IC701B, the output terminal of the amplifying first NE5532 chip IC701B is connected to the inverting input terminal of the amplifying second NE5532 chip IC701A through a first control resistor R7018, the inverting input terminal of the amplifying second NE5532 chip IC701A is also connected to the output terminal of the amplifying second NE5532 chip IC701A through a second control resistor R7020, and the output terminal of the amplifying second NE5532 chip IC701A is connected to the voltage control terminals of the first and second amplifying AD603 chips through a third control resistor R7017.

[0050] like Figure 6 As shown, the analog multiplier circuit includes a first AD835 chip U401 and a second AD835 chip U402; the inverting input X multiplicand terminal (pin X2) of the first AD835 chip U401 is connected to the first output terminal of the signal source circuit, and the non-inverting input Y multiplicand terminal (pin Y1) of the first AD835 chip U401 is connected to the signal output terminal of the programmable attenuation circuit; the inverting input X multiplicand terminal (pin X2) of the second AD835 chip U402 is connected to the second output terminal of the signal source circuit, wherein the signals output from the first output terminal and the second output terminal of the signal source circuit are in an orthogonal relationship; the non-inverting input Y multiplicand terminal (pin Y1) of the second AD835 chip U402 is connected to the signal output terminal of the programmable attenuation circuit.

[0051] The signal output ends (pin W) of the first and second AD835 chips U402 are connected to the two signal output ends (ports JP404 and JP4010) of the analog multiplier circuit through the third multiplication voltage divider resistor R403 and the ninth multiplication voltage divider resistor R409 respectively; the third multiplication voltage divider resistor R403 and the ninth multiplication voltage divider resistor R409 are also grounded through the first multiplication filter capacitor C401 and the second multiplication filter capacitor C402 respectively.

[0052] The summing input terminal (pin Z) of the first AD835 chip U401 and the second AD835 chip U402 are respectively connected to the end of the first multiplication adjustable resistor RP401 and the end of the second multiplication adjustable resistor RP402, and the summing input terminal (pin Z) of the first and second AD835 chips U402 are also grounded through the sixth multiplication voltage-dividing resistor R406 and the thirteenth multiplication voltage-dividing resistor R4013. The adjustable ends of the first multiplication adjustable resistor RP401 and the second multiplication adjustable resistor RP402 are respectively connected to the signal output terminals of the first AD835 chip U401 and the second AD835 chip U402.

[0053] The non-inverting input Y multiplicand terminal (pin Y1) of the first AD835 chip U401 and the second AD835 chip U402 are connected through the short-circuit sleeve SW401, so that the non-inverting input Y multiplicand terminal (pin Y1) of the first AD835 chip U401 and the second AD835 chip U402 share a port, saving wiring.

[0054] At the same time, the inverting input X multiplicand terminal (pin X2) of the first AD835 chip U401 is also grounded through the first multiplication voltage divider resistor R401 and the second multiplication voltage divider resistor R402; the non-inverting input Y multiplicand terminal (pin Y1) of the first AD835 chip U401 is also grounded through the fourth multiplication voltage divider resistor R404 and the fifth multiplication voltage divider resistor R405.

[0055] The inverting input X multiplicand terminal (pin X2) of the second AD835 chip U402 is also grounded through the seventh multiplication voltage divider resistor R407 and the eighth multiplication voltage divider resistor R408; the non-inverting input Y multiplicand terminal (pin Y1) of the second AD835 chip U402 is also grounded through the eleventh multiplication voltage divider resistor R4011 and the twelfth multiplication voltage divider resistor R4012.

[0056] The inverting input X multiplicand terminal (pin X2) of the first AD835 chip U401, the non-inverting input Y multiplicand terminal (pin Y1) of the first AD835 chip U401, the inverting input X multiplicand terminal (pin X2) of the second AD835 chip U402, and the non-inverting input Y multiplicand terminal (pin Y1) of the second AD835 chip U402 are also connected to the first available port JP403, the second available port JP406, the third available port JP409, and the fourth available port JP4012, respectively, so that data can be expanded as needed when in use.

[0057] The active low-pass filter circuit can effectively filter out waveforms above 50MHz, and the simulation result can reach -40dB. In this embodiment, there are two active low-pass filter circuits, which are respectively connected to the signal output ends of the first AD835 chip U401 and the second AD835 chip U402.

[0058] Among them, Figure 7 As shown, the active low-pass filter circuit includes a first LM324 chip U501 and a second LM324 chip U502; the signal output end of the multiplier circuit is connected to the in-phase input end of the first LM324 chip U501 through the first low-pass filter resistor R501 and the second low-pass filter resistor R502 in sequence; the second end of the first low-pass filter resistor R501 and the first end of the second low-pass filter resistor R502 are also connected to a first low-pass filter capacitor C501, the first low-pass filter capacitor C501 is connected to the output end of the first LM324 chip U501, and the output end of the first LM324 chip U501 is also connected to the inverting input end of the first LM324 chip U501; the inverting end of the first LM324 chip U501 The input end is connected to the in-phase input end of the second LM324 chip U502 through the third low-pass filter resistor R503 and the fourth low-pass filter resistor R504 in sequence, and the second low-pass filter capacitor C502 is also connected to the second end of the third low-pass filter resistor R503 and the first end of the fourth low-pass filter resistor R504, and the second low-pass filter capacitor C502 is connected to the output end of the second LM324 chip U502, and the output end of the second LM324 chip U502 is also connected to the inverting input end of the second LM324 chip U502; the in-phase input end of the first LM324 chip U501 and the second LM324 chip U502 are also grounded through the third low-pass filter capacitor C503 and the fourth low-pass filter capacitor C504 respectively. The signal output end of the second LM324 chip U502 is the signal output end of the active low-pass filter circuit; the voltage input ends of the first and second LM324 chips U502 are both connected to a DC power supply, and the common end of the first and second LM324 chips U502 is grounded.

[0059] The signal output end of the active low-pass filter circuit is connected to the signal input end of the microprocessor, and the microprocessor compares the received signal with the threshold value and generates an output signal according to the comparison result. The microprocessor compares the received signal with the threshold value, which is a mature prior art.

[0060] The display circuit comprises an LCD display screen, the LCD display screen is connected to the signal output terminal of the microprocessor, a ground pin of the LCD display screen is grounded, and a power pin of the LCD display screen is connected to a DC power supply.

[0061] When working, firstly, two sinusoidal orthogonal swept frequency signals are output, and after digital-to-analog conversion and filtering by the dual-channel high-speed DAC inside the AD9854 chip, two analog orthogonal signals with equal amplitude, frequency and phase difference of 90 degrees are obtained; the gain circuit ensures that the output swept frequency signal source outputs with equal amplitude in the entire frequency band; after the signal conditioning circuit, a measurement signal with appropriate amplitude can be input to the network under test, and this step can improve the accuracy of the measuring instrument at the same time, and the input amplitude requirement of the analog multiplier circuit can be met through the program-controlled attenuation circuit. After the signal source signal and the output signal of the program-controlled attenuation circuit are modulated by the analog multiplier circuit, the high-frequency signal is filtered out by the low-pass filter circuit to obtain two slowly varying DC signals respectively; the active low-pass filter circuit inputs the two slowly varying DC signals to the microprocessor, and the microprocessor displays the amplitude-frequency characteristic curve and phase-frequency characteristic curve of the network under test through the LCD display.

[0062] The multi-band network frequency characteristics tester described in the present invention has the advantages of low cost, high integration and good stability. At the same time, its measurement accuracy is high and can meet the experimental teaching needs of general electronic colleges and universities or the needs of scientific research institutions; it can test the frequency characteristics of low, medium and high frequency bands, making up for the gap in this type of frequency tester, and has high application value and practical significance.

Claims

1. Multi-band network frequency characteristics tester, characterized by: It includes a signal source circuit, a gain circuit, a signal conditioning circuit, a program-controlled attenuation circuit, an analog multiplier circuit, an active low-pass filter circuit, a microprocessor and a display circuit; The signal source circuit outputs the signal source, and inputs the signal source into the gain circuit, the signal is amplified by the gain circuit, the amplified signal is transmitted to the signal conditioning circuit for conditioning, the signal conditioned by the signal conditioning circuit is input into the program-controlled attenuation circuit, the program-controlled attenuation circuit reduces the signal voltage amplitude and then inputs the signal into the analog multiplier circuit, the analog multiplier circuit modulates the input signal and then outputs the signal to the active low-pass filter circuit, the active low-pass filter circuit filters out the high-frequency signal in the signal to obtain a DC signal, the microprocessor receives the output signal of the active low-pass filter circuit, and outputs the signal to the display circuit according to the received signal, and the display circuit displays the received signal; The signal source circuit comprises an AD9854 chip, an external clock pin of the AD9854 chip is connected to a clock circuit, a data input pin of the AD9854 chip is connected to a DC power supply via a resistor; a power input terminal of the AD9854 chip is connected to a DC power supply via an inductor; and an output pin of the AD9854 chip is connected to a filter module; There are two filter modules, which are connected to two output pins of the AD9854 chip respectively; The two filter modules have the same structure, and both include: a first filter resistor, a second filter resistor, a first filter capacitor, a second filter capacitor, a third filter capacitor, a fourth filter capacitor, a fifth filter capacitor, a sixth filter capacitor, a seventh filter capacitor, a first filter inductor, a second filter inductor and a third filter inductor: the output pin of the AD9854 chip is connected to the first filter capacitor, and the first filter capacitor, the second filter capacitor and the third filter capacitor are connected in series; the output pin of the AD9854 chip is also grounded through the first filter resistor; the first filter inductor is connected between the two ends of the first filter capacitor; the two ends of the first filter inductor are also grounded through the fourth and fifth filter capacitors respectively; The second filter inductor is connected between the two ends of the second filter capacitor; the two ends of the second filter inductor are also grounded through the fifth and sixth filter capacitors respectively; the third filter inductor is connected between the two ends of the third filter capacitor; the two ends of the third filter inductor are also grounded through the sixth and seventh filter capacitors respectively; the second end of the third filter capacitor is the output end of the signal source circuit, and the second end of the third filter capacitor is also grounded through the second filter resistor; The gain circuit comprises a first AD603 chip, a second AD603 chip, an AD8307 chip, a first gain NE5532 chip, a second gain NE5532 chip, an OPA630 chip and an OPA695 chip; the signal output end of the signal source circuit is connected to the operational amplifier input pin of the first AD603 chip through a first gain resistor and a third gain resistor in sequence; the second end of the first gain resistor is also grounded through a second gain resistor; the low voltage control end of the first AD603 chip and the common end of the operational amplifier are grounded; the voltage input end of the first AD603 chip is connected to a DC power supply; the feedback end of the first AD603 chip is connected to the output end of the operational amplifier and then connected to the second AD603 chip through the third and fourth gain resistors in sequence; the The second ends of the three gain resistors are also grounded through the eighth gain resistor; the positive voltage control ends of the first and second AD603 chips are grounded through the fourteenth gain resistor, and the third gain capacitor and the fourth gain capacitor connected in parallel are connected in parallel between the positive voltage control end of the second AD603 chip and the fourteenth gain resistor; the feedback end of the second AD603 chip is connected to the output end of the operational amplifier and then connected to the input pin of the OPA695 chip through the first gain capacitor, the input pin of the OPA695 chip is also grounded through the ninth gain resistor, and the output pin of the OPA695 chip is connected to the fifth gain resistor; the fifth gain resistor is connected to the sixth gain resistor, the sixth gain resistor is connected to the signal output end of the gain circuit, and the output pins of the OPA695 chip are also connected in sequence to the sixth gain resistor. The first variable gain capacitor and the second variable gain capacitor are connected to the ground through the thirteenth gain resistor and the fifteenth gain resistor; the second end of the thirteenth gain resistor is connected to the in-phase input end of the OPA630 chip, and the twenty-sixth gain resistor is connected between the inverting input end and the output end of the OPA630 chip; the output end of the OPA630 chip is respectively connected to the first variable gain capacitor and the twenty-third gain resistor, the twenty-third gain resistor is respectively grounded and connected to the second variable gain capacitor, the second ends of the first variable gain capacitor and the second variable gain capacitor are respectively connected to the two signal input ends of the AD8307 chip through the twenty-first and twenty-fifth gain resistors, the output end of the AD8307 chip is connected to the twenty-second gain resistor after being filtered by the eighth gain capacitor, and the second end of the twenty-second gain resistor is connected to the gain The in-phase input end of the first NE5532 chip, the inverting input end and the output end of the first NE5532 chip are connected; the in-phase input end of the second NE5532 chip is connected to the external interface through the twenty-seventh gain resistor; the output end of the first NE5532 chip is connected to the inverting input end of the second NE5532 chip through the twenty-fourth gain resistor; the second end of the twenty-fourth gain resistor is also connected to the fifth gain capacitor and the seventeenth gain resistor connected in parallel, and the twenty-fourth gain resistor is also connected to the eighteenth gain resistor, the second end of the eighteenth gain resistor is grounded through the sixteenth gain resistor and the twenty-tenth gain resistor respectively, and the fifth gain capacitor and the seventeenth gain resistor connected in parallel are also grounded through the fourteenth gain resistor;The fifth gain capacitor and the seventeenth gain resistor connected in parallel are also connected to the forward voltage control terminals of the first AD603 chip and the second AD603 chip; The analog multiplier circuit comprises a first AD835 chip and a second AD835 chip; the inverting input X multiplicand terminal of the first AD835 chip is connected to the first output terminal of the signal source circuit, the non-inverting input Y multiplicand terminal of the first AD835 chip is connected to the signal output terminal of the program-controlled attenuation circuit; the inverting input X multiplicand terminal of the second AD835 chip is connected to the second output terminal of the signal source circuit, wherein the signals outputted from the first output terminal and the second output terminal of the signal source circuit are in an orthogonal relationship; the non-inverting input Y multiplicand terminal of the second AD835 chip is connected to the program-controlled attenuation circuit. The signal output end of the controlled attenuation circuit; the signal output ends of the first and second AD835 chips are respectively connected to the signal output end of the analog multiplier circuit through the first multiplication voltage-dividing resistor; a multiplication filter capacitor is also connected to the multiplication voltage-dividing resistor; the summing input end of the first AD835 chip and the second AD835 chip is connected to the end of the multiplication adjustable resistor, and the summing input end of the first and second AD835 chips is also grounded through the second multiplication voltage-dividing resistor; the adjustable end of the multiplication adjustable resistor is connected to the signal output end of the first AD835 chip or the second AD835 chip; The display circuit comprises an LCD display screen, and the LCD display screen is connected to the signal output end of the microprocessor.

2. The multi-band network frequency characteristic tester according to claim 1, characterized in that: The signal conditioning circuit and the programmable attenuation circuit have the same structure, and both include an amplifier circuit and a control circuit; the amplifier circuit includes a first amplifier AD603 chip, a second amplifier AD603 chip and an amplifier OPA690 chip; the signal output end of the gain circuit is connected to the input end of the first amplifier AD603 chip, and the input end of the first amplifier AD603 chip is also grounded through a first amplifier resistor; the input end of the first amplifier AD603 chip is also connected to a deviation adjustment circuit; the signal output end of the first amplifier AD603 chip is connected to the input end of the second amplifier AD603 chip through a fifth amplifier resistor, and the input end of the second amplifier AD603 chip is also connected to a deviation adjustment circuit; the input end of the second amplifier AD603 chip is also grounded through an eighth amplifier capacitor; the voltage of the first and second amplifier AD603 chips is connected to the ground. The control ends are connected to the output end of the control circuit, and the voltage control ends of the first and second amplifying AD603 chips are also grounded through the sixth amplifying capacitor and the fourth amplifying capacitor respectively; the output end of the second amplifying AD603 chip is connected to the in-phase input end of the amplifying OPA690 chip through the seventh amplifying resistor, and the in-phase input end of the amplifying OPA690 chip is also grounded through the eighth amplifying resistor and the first amplifying capacitor respectively; the inverting input end of the amplifying OPA690 chip is grounded through the ninth amplifying resistor, and the inverting input end of the amplifying OPA690 chip is also connected to the output end of the amplifying OPA690 chip through the tenth amplifying resistor, and the output end of the amplifying OPA690 chip is grounded through the twelfth amplifying resistor, and the output end of the amplifying OPA690 chip is also connected to the output pin of the amplifying circuit through the eleventh amplifying resistor; The control circuit includes a first amplifying NE5532 chip and a second amplifying NE5532 chip; the in-phase input terminal of the first amplifying NE5532 chip is connected to a DC power supply, the inverting input terminal of the first amplifying NE5532 chip is connected to the output terminal of the first amplifying NE5532 chip, the output terminal of the first amplifying NE5532 chip is connected to the inverting input terminal of the second amplifying NE5532 chip through a first control resistor, the inverting input terminal of the second amplifying NE5532 chip is also connected to the output terminal of the second amplifying NE5532 chip through a second control resistor, and the output terminal of the second amplifying NE5532 chip is connected to the voltage control terminals of the first and second amplifying AD603 chips through a third control resistor.

3. The multi-band network frequency characteristic tester as claimed in claim 2, characterized in that: The bias adjustment circuit includes a first bias adjustment resistor, a second bias adjustment resistor, a bias adjustment sliding rheostat, a bias adjustment filter capacitor and a bias adjustment voltage divider resistor; the first bias adjustment resistor and the second bias adjustment resistor are respectively connected to the two ends of the bias adjustment sliding rheostat, the sliding end of the bias adjustment sliding rheostat is connected to the bias adjustment voltage divider resistor, and the bias adjustment voltage divider resistor is connected to the input ends of the first and second amplifier AD603 chips.

4. The multi-band network frequency characteristic tester as claimed in claim 1, characterized in that: The non-inverting input Y multiplicand terminal of the first AD835 chip and the second AD835 chip are connected through a short-circuit sleeve.

5. The multi-band network frequency characteristic tester according to claim 1, characterized in that: There are two active low-pass filter circuits, which are connected to the signal output ends of the first AD835 chip and the second AD835 chip respectively; the active low-pass filter circuit includes a first LM324 chip and a second LM324 chip; the signal output end of the multiplier circuit is connected to the in-phase input end of the first LM324 chip through the first low-pass filter resistor and the second low-pass filter resistor in sequence; the second end of the first low-pass filter resistor and the first end of the second low-pass filter resistor are also connected to the first low-pass filter capacitor, the first low-pass filter capacitor is connected to the output end of the first LM324 chip, and the output end of the first LM324 chip is also connected to the inverting input end of the first LM324 chip; the inverting input end of the first LM324 chip is connected to the inverting input end of the first LM324 chip in sequence through the third The low-pass filter resistor and the fourth low-pass filter resistor are connected to the in-phase input terminal of the second LM324 chip, the second end of the third low-pass filter resistor and the first end of the fourth low-pass filter resistor are also connected to the second low-pass filter capacitor, the second low-pass filter capacitor is connected to the output terminal of the second LM324 chip, and the output terminal of the second LM324 chip is also connected to the inverting input terminal of the second LM324 chip; the in-phase input terminals of the first LM324 chip and the second LM324 chip are also grounded through the third low-pass filter capacitor and the fourth low-pass filter capacitor respectively, and the signal output terminal of the second LM324 chip is the signal output terminal of the active low-pass filter circuit; the voltage input terminals of the first and second LM324 chips are both connected to a DC power supply, and the common terminals of the first and second LM324 chips are grounded.

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