Device and method for data processing

Abstract

The present application discloses a device and method for data processing. A device includes a processing circuit, a transactional memory support circuit, and a cache. The processing circuit processes a thread of data processing, and the transactional memory support circuit supports execution of transactions within the thread, including tracking address read sets, including addresses accessed by read instructions within the transaction. The transaction includes an instruction, for which the processing circuit is configured to prevent the result of speculatively executing the instruction from being committed until the transaction is completed. The cache has multiple entries, each entry is associated with an address and specifies a replaceable information value for the address, the replaceable information value containing information that can be functionally processed correctly outside the transaction even if the information is incorrect. When a transaction is in a pending state, the transactional memory support circuit identifies read set information based on an encoding of the replaceable information value, and the read set information identifies addresses in the read set tracked for the transaction.

Description

Technical Field

[0001] The present technology relates to the field of data processing and more specifically, to transactional memory. Background Art

[0002] A data processing system may execute multiple data processing threads. At times, a thread may need to access a shared resource, and the nature of the data processing operation may be such that once a thread begins interacting with a shared resource, it may be necessary to complete a set of operations using the resource in an atomic manner without another thread accessing the resource during that time.

[0003] One technique for handling such conflicts between threads may be to use locks to control excessive access to at least one target resource. For example, when a thread begins accessing data in a particular address region, the thread may set a lock variable to claim ownership of the lock, and then, while the lock-owning thread has ownership of the lock, other threads that check the lock variable may determine that the lock has been claimed and therefore may not enter the code segment that interacts with the address region. This lock-based approach may be considered pessimistic because each thread assumes by default that it cannot enter a code segment that accesses a shared resource because a conflict with another thread may occur unless it has ownership of a lock that guarantees that there will be no conflict. However, a lock identifier may generally control exclusive access to multiple resources (e.g., a range of addresses), and therefore, there is no guarantee that when one thread is accessing some of the resources in the set of resources protected by the lock variable, another thread is definitely accessing the same resource. Therefore, in cases where conflicts between threads are rare, the lock-based approach may result in a performance loss because threads may unnecessarily wait for the lock to be released before entering a critical code segment that uses a shared resource.

[0004] A more optimistic approach to handling conflicts between threads accessing shared resources may be to use transactional memory support. A data processing system may have circuitry that supports processing circuitry to execute transactions within a data processing thread. The transaction may be those instructions of the thread executed between a transaction start instruction marking the start of the transaction and a transaction end instruction marking the end of the transaction. Between the transaction start instruction and the transaction end instruction, the processing circuitry may speculatively execute intervening instructions and prevent the commit of those speculatively executed instruction results until the transaction end instruction is reached. An abort event occurring after the transaction start instruction is executed (but before the transaction end instruction is reached) may cause the transaction to be aborted and the speculative results to be discarded. There may be many reasons for aborting a transaction, but one reason may be the detection of a memory access conflict with another thread.

[0005] Thus, with this approach, each thread can optimistically start processing the critical section, assuming no conflicts with other threads, and then commit the results of the transaction if it reaches the end of the critical section without detecting any conflicts. In cases where conflicts are rare, using transactional memory support can improve performance by allowing more threads to process their critical sections simultaneously. Summary of the invention

[0006] At least some embodiments provide an apparatus comprising: a processing circuit for processing a thread of data processing; a transactional memory support circuit for supporting execution of a transaction within the thread processed by the processing circuit, the transaction comprising instructions of the thread speculatively executed between a transaction begin instruction and a transaction end instruction, for which the processing circuit is configured to prevent committing results of the speculatively executed instructions until the transaction end instruction is reached, wherein the transactional memory support circuit is configured to trigger an abort of the transaction in response to detecting a write access from another thread to one of a read set of addresses tracked for the transaction; and a cache having a plurality of entries, each entry being associated with one of a plurality of addresses and specifying an alternative information value associated with the address, the alternative information value containing information that is functionally correct outside of the transaction processing even if the information is incorrect;

[0007] Wherein, when the transaction is in a pending state, the transactional memory support circuit is configured to identify read set information based on the encoding of the replaceable information value, wherein the read set information identifies an address in a read set of addresses tracked for the transaction.

[0008] At least some embodiments provide a data processing method, the method comprising: identifying, in a cache having a plurality of entries, for each entry associated with one of a plurality of addresses, an alternative information value for each address, wherein the alternative information value contains information that is functionally correct outside of the transaction processing even if the information is incorrect; identifying, when the transaction is in a pending state, read set information based on an encoding of the alternative information value, the read set information identifying addresses in a read set of addresses tracked for the transaction; wherein the transaction includes instructions of a thread speculatively executed between a transaction start instruction and a transaction end instruction, for which committing results of the speculatively executed instructions is prevented until the transaction end instruction is reached, and triggering abort of the transaction in response to detecting a write access from another thread to one of the read sets of addresses tracked for the transaction.

[0009] At least some embodiments provide an apparatus comprising: means for processing a data processing thread; means for supporting execution of a transaction within the thread processed by the means for processing, the transaction comprising instructions of the thread speculatively executed between a transaction start instruction and a transaction end instruction, for which the means for processing is configured to prevent committing the speculatively executed instruction results until the transaction end instruction is reached, wherein the means for supporting is configured to trigger an abort of the transaction in response to detecting a write access from another thread to one of a read set of addresses tracked for the transaction; and means for caching data, comprising a plurality of entries, each entry being associated with one of a plurality of addresses and specifying an alternative information value associated with the address, the alternative information value containing information that can be functionally correctly processed outside of the transaction even if the information is incorrect; wherein when the transaction is pending, the means for supporting is configured to identify read set information based on an encoding of the alternative information value, the read set information identifying an address in the read set of addresses tracked for the transaction.

[0010] Other aspects, features and advantages of the present technology will become apparent from the following description of embodiments read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An embodiment of a data processing device having transactional memory support circuitry is schematically illustrated;

[0012] Figure 2 An embodiment of processing transactions in a system with transactional memory support is shown;

[0013] Figure 3 shows the use of lock-based mode Figure 2 An alternative code sequence that performs equivalent operations on a transaction;

[0014] Figure 4 An embodiment of a four-way set associative cache structure is shown, in which the method of the present technology can be applied;

[0015] Figure 5 is a flow chart illustrating an embodiment of a cache eviction policy functioning in a cache structure;

[0016] Figure 6 is a flow chart illustrating the processing of an embodiment of a transaction;

[0017] Figure 7-9 An embodiment of an encoded replaceable information value interpreted as read set information is shown;

[0018] Fig.10An embodiment of a group identifier and a plurality of entry indicators for storing read set information for a cache structure is shown;

[0019] Fig.11 An embodiment is shown that encodes a replaceable information value to be interpreted as read set information including a group identifier and an entry indicator; and

[0020] Fig.12 An embodiment is shown in which alternative information values ​​are encoded as read set information. DETAILED DESCRIPTION

[0021] During the processing of a transaction, addresses may be tracked as part of an address read set or an address write set following accesses triggered by instructions within the transaction. When an instruction reads data from an address in memory, the address is marked as part of a read set; when an instruction writes data to an address in memory, the address is marked as part of a write set. If, at some point between the transaction begin instruction and the transaction end instruction, another instruction from outside the transaction triggers a read or write access to any address in the write set, this may trigger an abort. Similarly, if any instruction outside the transaction performs a write access to any address in the read set, this may also trigger an abort of the transaction. Therefore, it is useful to record read set information that identifies which addresses are in the read set.

[0022] A device according to the present technology includes a processing circuit for processing a data processing thread, and a transaction memory support circuit for supporting the execution of a transaction within the thread processed by the processing circuit. The transaction includes instructions of the thread that are speculatively executed between a transaction start instruction and a transaction end instruction, and the processing circuit is arranged to prevent the results of the speculatively executed instructions from being committed until the transaction end instruction is reached. As described above, the transaction memory support circuit triggers the abort of the transaction in response to detecting a write access from another thread to one of the address read sets tracked for the transaction. The device also includes a cache having a plurality of entries, wherein each entry is associated with one of the plurality of addresses and specifies an alternative information value associated with the address. The alternative information value is information that will be functionally correct outside of the transaction processing even if the information itself is incorrect. When the transaction is in a pending state, the transaction memory support circuit is configured to identify read set information based on the encoding of the alternative information value, and the read set information identifies an address in the address read set tracked for the transaction.

[0023] It should be noted that while the replaceable information values ​​represent information that may be lost without affecting functional correctness when they are not interpreted as read-set information (outside of a transaction), errors in the read-set information may affect functional correctness (and in some embodiments, error detection code may be provided to enable detection of such errors).

[0024] The method may provide an efficient technique for storing read set information in a data cache. This technique does not require a separate memory location to store the read set information or an additional field in the data cache, but requires little or no additional space in the cache to store the read set information. For a technician, replacing the replaceable information value in this way may seem counterintuitive because it means that some information is lost when encoding the read set information. However, as long as the value identified as the replaceable information value outside the transaction does not need to ensure the functional correctness of the processing performed by the processing circuit, that is, the replaceable information value is a value that will be functionally processed correctly even if the value itself is incorrect, re-encoding these values ​​to replace the read set information will not affect the overall functional correctness of the processing performed by the processing circuit. The inventors of the present technology realize that although there may (in some embodiments) be a slight performance impact due to the removal or re-encoding of these values, the improvement in hardware efficiency may outweigh this due to the reduction in the amount of storage required to store the read set information. In any case, some embodiments can avoid performance losses by exploiting redundancy in the encoding of the replaceable information value.

[0025] In some embodiments of the present technology, transactional memory support circuitry responds to a transaction begin instruction (or in response to a subsequent event after the transaction begin instruction, such as a first access to a relevant cache set as a result of the transaction begin instruction) by setting encodings of replaceable information values ​​to identify read set information. In a transaction with multiple nested transactions (e.g., multiple transaction begin instructions are encountered before a transaction end instruction is encountered), setting of encodings of replaceable information values ​​for identifying read set information may occur in response to an additional (e.g., first) transaction begin instruction. Thus, transactional memory support circuitry may update encodings of replaceable information values ​​upon or after entry into a pending transaction to indicate that those values ​​now represent read set information for the transaction instead of (or in addition to) other information previously represented by those values ​​before the transaction became pending.

[0026] In some embodiments, the number of allowed encodings of the replaceable information value outside the transaction is limited to a certain maximum value. Then, after the transaction start instruction, the encoding of the replaceable information value is set to one of the non-allowed encodings to identify the read set information.

[0027] In this way, some encoding of the alternative information value is retained for identifying the read-set information value, a simple technique for encoding the alternative information value is provided, and it is ensured that a valid encoding of the alternative information value outside of a transaction is not mistaken for read-set information within a transaction.

[0028] In some embodiments, the non-permitted encoding selected to identify the read-set information is a redundant encoding that provides a functionally equivalent result to another allowed encoding.

[0029] This exploits redundancy that often exists in the encoding of replaceable information values, thus allowing some encoding to be retained for identifying read-set information without negatively impacting system performance outside of transactions.

[0030] In some embodiments, it is ensured that there is a Hamming distance of at least three between the set of encodings following the transaction start instruction and any allowed encodings outside of the transaction.

[0031] The Hamming distance of a pair of values ​​is the number of bits that need to change state in order to change from one value to another. For example, as required by some embodiments of the present technology, a minimum Hamming distance of 3 means that at least three bits need to be changed or flipped in order to change the value from one value to another. More specifically, in this embodiment, a Hamming distance of at least 3 between the encoding set in response to the transaction start instruction and any allowed encoding outside the instruction means that in order to switch from the first encoding set to the second encoding set, at least three bits need to be changed. This allows double error detection to be implemented, which ensures the safety of the system and allows it to comply with certain functional safety requirements.

[0032] In some embodiments, a non-permitted encoding is an encoding in which more than a predetermined number of alternative information values ​​in the subset of alternative information values ​​have some predetermined values.

[0033] The subset of alternative information values ​​mentioned above may be only a limited number of alternative information values ​​associated with an entry of a set in a set-associated cache, or it may be all alternative information values ​​associated with the set. In these embodiments, when the number of values ​​in a subset that takes a particular value is above a certain threshold, the alternative information value is interpreted as reading set information. Similarly, the processing circuit determines that if the number of alternative information values ​​is lower than or equal to a second threshold (which may be equal to or lower than the first threshold depending on the required level of error detection), the encoding should be interpreted as an alternative information value. Where the first and second thresholds are different, they may be sufficiently different in some embodiments to give a specific expected Hamming distance between the two encodings - such as a Hamming distance of 3. This provides an efficient technique for encoding alternative information values ​​without requiring additional storage space in the cache.

[0034] In some embodiments of the present technology, an encoding indicator field is included in the cache. The field stores an encoding indicator value to indicate to the processing circuit an encoding of the alternative information value.

[0035] This is another embodiment of an efficient encoding form of alternative information values, where a small number of additional bits (i.e., an encoding indicator field) are added to the cache memory to indicate how the encoding of the alternative information value should be interpreted. Although unlike the other embodiments, this does require a small amount of additional storage space in the cache, only a small number of additional bits are required. Furthermore, an advantage of this approach is that it makes all alternative information values ​​available for storing read set information or other useful information when the encoding indicator field indicates that the value should be so interpreted.

[0036] In some embodiments, in response to a transaction start instruction, the transactional memory support circuitry is configured to select an encoding of the alternative information value to reduce the number of bits used for the information so that processing of the information is functionally correct even if the information is incorrect.

[0037] Thus, not all performance benefits associated with alternative information values ​​are lost when changing the encoding of the value, but some performance benefits are still provided even when encoding read set information. That is, by utilizing this approach, even in a pending transaction, in addition to representing the read set information, the alternative information value still indicates some alternative information that existed before the transaction began, but utilizing a smaller number of bits to provide a lower precision.

[0038] In some embodiments, the first portion of the read set information includes error detection information for detecting errors in the read set information.

[0039] By including error detection information in the read set information, robustness against failures may be provided by providing bits that may be used to check the correctness of the read set information.

[0040] When error detection information is included in the read set information, in some embodiments this may mean that there are insufficient bits remaining in the replaceable information value to indicate, for each cache entry, whether the entry corresponds to an address in the read set of the transaction. In some embodiments, this may not be a problem because the allocation of data to the cache can be controlled so that addresses in the read set are allocated to entries that the read set information can identify as part of the read set, and if the read set becomes large enough to include an address for which there is insufficient space in the read set information to indicate the address as part of the read set, the transaction can be aborted. Thus, in some embodiments, the maximum number of cache entries that can be indicated as part of a read set (or the maximum number of cache entries within a given set of a set-associated cache) can be less than the total number of entries (or the total number of entries in a given set of a set-associated cache).

[0041] However, other embodiments may encode the read set information such that whether or not each of the N locations in the cache is associated with an address in the read set may be encoded using fewer than N bits, such that even if a portion of the replaceable information value is used for error detection information, it may still be possible to encode whether each location in the cache is part of the read set.

[0042] In some embodiments, the selected encoding of the second portion of the read set information identifies a group indicator associated with a group of entries in the cache, the group identifier indicating whether the associated group is a complete group including only entries in the read set or an incomplete group including at least one entry that is not in the read set. The second portion also includes at least one entry indicator associated with at least one entry in the incomplete group, the entry identifier indicating whether the associated entry is in the read set.

[0043] In this way, read set information can be provided for all entries in the cache even if there is not enough space in the replaceable information value to provide an indicator for each entry in the cache. This provides a space-saving technique for recording read set information for all entries in the cache.

[0044] In some embodiments, based on an encoding of the replaceable information values, the transactional memory support circuitry may identify read set information for multiple transactions.

[0045] Therefore, the present technique is very general and can be used to provide read set information for multiple transactions while requiring little or no additional storage space in the cache.

[0046] In some embodiments, the read set information of each transaction in the plurality of transactions shares an error detection code.

[0047] This is an efficient way to provide error detection capabilities for multiple transactions using a limited amount of storage.

[0048] In some embodiments, in response to execution of a transaction end instruction or abort of the transaction, the processing circuitry is configured to interpret the alternative information values ​​of the plurality of entries as information that will be processed functionally correctly even though the information is incorrect.

[0049] In this way, the encoding of the replaceable information values ​​identifies that these values ​​will return to their original function after the transaction is completed. Therefore, the same set of values ​​can provide two functions based on their encoding - providing their original function, or identifying the read set information of one or more transactions.

[0050] In some embodiments, after the transaction is completed, the transactional memory support circuitry replaces each replaceable information value in the plurality of entries with a value unrelated to the corresponding replaceable information value.

[0051] Replacing all replaceable information values ​​in this manner allows the security of the system to be ensured by removing any information that can be used by external entities to determine which addresses a transaction has accessed. The value that is unrelated to the corresponding replaceable information value can be, for example, a random value; or, the value can be a default value, for example, all values ​​can be set to 00 or 10, etc.

[0052] In some embodiments, the replaceable information value includes cache eviction policy information.

[0053] Cache eviction policy information is information that allows processing circuitry or cache control circuitry to determine which of a plurality of entries should be evicted when a new entry is allocated to the cache. This means that the replaceable information values ​​may be used to improve the performance of the system, but they are not functionally important with respect to ensuring the functional correctness of the system. That is, if the replaceable information values ​​are incorrect outside of a transaction, the system still operates as required, although there may be some performance impact. Therefore, reusing these values ​​to identify read-set information does not affect the functional correctness of the processing performed by the processing circuitry.

[0054] In some embodiments, when a transaction is pending and the replaceable information value is used to identify read set information of the transaction, the processing circuit selects a cache line from the cache for eviction independent of the replaceable information value.

[0055] If the replaceable information value is cache eviction policy information, then an alternative cache eviction policy may need to be implemented during the processing of a transaction. Many cache eviction policies can be used, one of which involves randomly selecting cache lines to be replaced, and another may be a round-robin replacement policy. This is not the most efficient cache eviction policy because it may result in frequently accessed cache lines being removed from the cache, which has a negative impact on the performance of the system, however, random or round-robin replacements are functionally correct cache eviction policies. Randomly replacing cache lines does not affect the overall functional correctness of the system. Therefore, by defaulting to a random replacement cache policy while a transaction is pending, the replaceable information value can be re-encoded as read set information while still being able to implement some form of cache eviction policy.

[0056] In some embodiments, modified eviction policy information is encoded within the replaceable information value along with the read information while the transaction is pending, and the processing circuitry uses the modified eviction policy information to select a cache line from the cache for eviction when a new entry is allocated.

[0057] In this way, one can still implement a more efficient cache eviction policy than simple random replacement, while also interpreting some replaceable information values ​​as read-set information.

[0058] Figure 1An embodiment of a data processing device 2 with hardware transactional memory (HTM) support is shown. The device has processing logic 4 for executing instructions to perform data processing operations. For example, the processing logic 4 (processing circuit) may include: an execution unit for performing various types of processing operations, such as an arithmetic / logic unit (ALU) for performing arithmetic or logical operations (such as addition, multiplication, and, or, etc.); a floating point unit for performing operations on floating point operands; or a vector processing unit for performing vector processing on vector operands including multiple data elements. A set of architectural registers 6 are provided for storing operands of instructions executed by the processing logic 4 and for storing results of the executed instructions. An instruction decoder 8 decodes instructions taken from an instruction cache 10 to generate control signals for controlling the processing logic 4 or other elements of the data processing device 2 to perform related operations. A load / store unit 12 is also provided to perform load operations (in response to load instructions decoded by the instruction decoder 8) to load data values ​​from the data cache 14 or the main memory 16 into the architectural register 6, and store operations (in response to store instructions decoded by the instruction decoder 8) to store data values ​​from the architectural register 6 to the data cache 14 or the main memory 16.

[0059] The device 2 also has transactional memory support circuitry 20 that provides various resources for supporting hardware transactional memory (HTM). The HTM resources in the transactional memory support circuitry 20 support processing of transactions by the processing logic 4, where a transaction is a series of instructions for which the processing logic 4 does not commit any results of the speculatively executed instructions until the transaction is completed. The transactional memory support circuitry 20 may include: a speculation result memory 22, for example, for storing speculation results of a transaction; an address tracking circuit 24 for tracking addresses accessed by a transaction; a conflict detection circuit 26 for detecting conflicts between data accesses made by a transaction and data accesses made by other threads so that the transaction can be aborted when a conflict is detected; and a recovery state storage circuit 28 for storing a snapshot of architectural state data from the architectural registers 6 at the beginning of a transaction so that when the transaction is aborted, this state can be restored to cover the speculative results of the transaction. In addition, the resources may include a lock storage structure 30 for a strong lock identifier and a nesting depth register 32. Although the address tracking circuit 24 is in Figure 1 As described below, in some embodiments this may be combined with the data cache 14 so that the data cache includes an indication of which addresses are in the read set or write set for transaction tracking.

[0060] During the processing of a transaction by the processing logic 4, the results of some speculatively executed instructions (e.g., store instructions for storing data to the cache 14 or the memory 16) are temporarily stored in the speculative result memory 22 for committing once the transaction is completed (assuming no abort). When the conflict detection circuit 26 determines that an address in the address read set (e.g., the address of a location in the memory that has been subject to a read access triggered by an instruction in the transaction) has been written by an instruction outside the transaction, an abort of the transaction can be triggered. In the event of an abort, the recovery state memory 28 is used to restore the state of the architectural registers 6 to their state before the start of the transaction.

[0061] Transactions can be nested so that another transaction start instruction is received before a transaction end instruction corresponding to a previous transaction start instruction is encountered and while the earlier transaction is still pending and has not been aborted. The nesting depth register 32 can track the current nesting depth of the transaction to distinguish the following situations: when no transaction has been started, when only a single transaction has been started, or when an additional nested transaction has been started within the previous transaction. When no transaction has been started, the nesting depth can be 0. In response to the first transaction start instruction, the nesting depth can be incremented to 1. If an additional nested transaction is started, the nesting depth can be incremented again to 2, and so on. When the transaction is committed, the nesting depth can be decremented. Therefore, as each corresponding nested transaction commits, the nesting depth is gradually expanded until all transactions have been committed and the nesting depth returns to 0 again.

[0062] Figure 2 An embodiment of executing a transaction within a given thread using transactional memory support circuitry 20 and processing logic 4 is shown. A transaction is a section of program code that is defined by a transaction start instruction (tstart) and a transaction end instruction (tend). In some embodiments, the transaction end instruction is instead called tcommit - which is the same as tend. Figure 2As shown, in response to the transaction start instruction, the current architectural state in the architectural register 6 is captured and stored in the recovery state storage circuit 28. The processing logic 4 begins to perform speculative execution of subsequent instructions after the tstart instruction, and when executing these instructions, the addresses accessed by these instructions are tracked by the address tracking circuit 24, and the conflict detection circuit 26 detects conflicts between the tracked addresses and the addresses accessed using the load / store unit 12 in response to other threads. At least some of the speculative results of the instructions in the transaction are stored in the speculative result storage circuit 22. For example, the value stored in the cache or memory in response to the store instruction STR can be retained in the speculative result storage 22 while the transaction remains pending. If the transaction end instruction (tend) is reached without a simultaneous abort event, the speculative results are committed in response to the transaction end instruction. When the transaction is committed, any results stored in the speculative result storage 22 of the thread can be written to the data cache 14 or the memory 16, and the recovery state 28 can be discarded or allowed to be overwritten because it is no longer necessary to rewind the architectural state to the point before the transaction start instruction was encountered.

[0063] On the other hand, if an abort event occurs, such as when a conflict is detected by conflict detection circuit 26 when another thread accesses an address already accessed by a transaction, then abort of the transaction is triggered and the recovery state of recovery state memory 28 is restored to architectural registers 6. Other causes of an abort event may include, for example, execution of an instruction that is not allowed to be executed within a transaction, insufficient resources within speculation result memory 22 or address tracking circuit 24 for processing speculation results or addresses required for a given transaction, or an interrupt received during a transaction.

[0064] Figure 2 FIG. 1 shows how to use the transaction start and end instructions to execute a certain set of processing operations to be performed in transaction mode. Figure 3As shown, the same set of processing operations can also be performed in a non-transactional mode using a lock-based mechanism. In this case, before starting a code segment, at least one lock check instruction 40 checks a lock variable identified by a lock address #addLock and checks whether the lock variable indicates that another thread has already held the lock. If another thread holds the lock, the processing will not exceed the lock check instruction 40 until the lock is released. Once it is determined that the lock is available, the lock is declared by writing a given value (e.g., binary 1) to the lock address #addLock. For example, the lock check instruction 40 can be implemented using an atomic compare and exchange instruction that compares the current value stored at a specified address to determine whether to hold the lock, and updates the lock variable to declare the lock if the lock is not declared. Alternatively, a series of multiple instructions can be used to implement the lock check to read the lock, test the value of the lock, and if the lock has been declared, cause a processing delay, or if the lock is not currently declared, declare the lock by updating the lock variable. After completing the code segment protected by the lock, another instruction 42 can release the lock once exclusive access to the resource protected by the lock is no longer required. For example, the resources protected by the lock may be data locations identified by various addresses accessed during the intervening code segment.

[0065] The lock-based approach described above may be useful in situations where frequent aborts may occur, for example, if a transactional pattern is used. Furthermore, if frequent aborts do occur during a transaction, code written to use transactional memory may default back to a lock-based system in order to allow the instruction sequence to complete. However, when execution of a transactional memory-based code sequence succeeds and the transaction is committed, this is generally more efficient than a lock-based system.

[0066] As mentioned above, it is useful to be able to track the addresses in a read set (the addresses accessed by read requests within a transaction). Figure 4 1 shows an embodiment of how addresses in a read set can be tracked in a four-way set associative cache 44. Figure 4 As shown, each way 46 within a set 48 includes at least one field 50 that specifies cache eviction policy information. This is information that enables the processing circuit 4 to select a cache line to evict from the cache when a new line is allocated, and in this case is a two-bit value. The cache 44 may also be used to track read set information. One way to do this is to include additional fields 52, 54 within each way 46 of each set 48 of the cache 44 to record transaction information, such as read set information. Figure 4 The illustrated embodiment records transaction information for two transactions, transaction 1 (T1) recorded in field 52 and transaction 2 (T2) recorded in field 54. It should be noted that although Figure 3 Only way 0 is shown in FIG. 4 to include the additional fields 52 , 54 , 50 , but all four ways 46 in the four-way set associative cache 44 may include these fields.

[0067] As shown, an advantage of storing transaction information in data cache 44 is that the transaction information is stored in the read set along with the address to which it is tagged. However, a disadvantage is that additional space is required in the cache to store this information. The embodiments described below help reduce the amount of storage required to store read set information in cache 44.

[0068] As mentioned above Figure 4 As mentioned, the cache 44 typically includes a field 50 that records cache eviction policy information for selecting which line of the cache is evicted when a new line is allocated. Figure 5 An embodiment process is shown that uses this information, in this case using a re-reference interval prediction (RRIP) strategy. In such an embodiment, the information stored in field 50 of cache 44 is a RRIP value.

[0069] like Figure 5 As shown, when (at step 56) the processing circuit requests data at a given address, the cache 44 is checked for the given address (step 58). Specifically, the tag of the data stored in the cache 44 is checked for the address provided by the processing circuit. At step 60, it is determined whether the data is available in the cache 44. If the data is available in the cache, the method proceeds to step 62, where the data is extracted from the cache. At this point, the RRIP value in field 50 of the entry is reset to its default value, indicating that the data in this entry has been recently accessed - for example, the default value may be 0 (00, in Figure 4 This reset of the RRIP value indicates that the entry has been recently accessed and therefore should not be a high priority candidate for eviction from the cache.

[0070] On the other hand, if the address is not found in the cache at step 60, the data is instead retrieved from the main memory or from another cache (step 66). For example, if the cache 44 being checked for the address is a level 1 cache, then the level 2 cache may be checked next, followed by any lower level caches. Once all caches have been checked, if the data is still not found, the processing circuitry will retrieve the data from the main memory. This process is applicable to any number of cache levels.

[0071] Figure 5The subsequent steps of illustrate a process for selecting which entry of a cache to allocate for data extracted from a memory or another cache. It is not necessary to wait for the data to actually be returned from the memory or another cache before performing these steps - the entry for storing the returned data can be allocated before the returned data is received. In step 68, the processing circuit determines whether there is an invalid entry in the original cache 44, which invalid entry can be selected to be overwritten by the retrieved data. When selecting an invalid entry to be replaced, if the cache 44 is a set-associated cache, the selected entry must be within a specific set of entries selected based on the address of the data assigned to the cache. If an invalid entry that can be replaced is found, the process proceeds to step 70, where the invalid entry is replaced (overwritten) with the extracted data, and the invalid entry transitions to valid.

[0072] On the other hand, if no appropriate invalid entry is found, the method proceeds to step 72, where the processing circuitry identifies one or more cache entries (within the appropriate set) having the highest RRIP values. In this embodiment, a high RRIP value indicates that the entry has not been accessed for a long time and is therefore a good candidate for replacement within the cache eviction policy. For a two-bit RRIP value, the processing circuitry will seek to identify any entry with a RRIP value of 3 (11). If no entry has this RRIP value, the processing circuitry will look for an entry with the next highest value - 2 (10) - and so on.

[0073] Once one or more entries with the highest value are identified, the method proceeds to step 74, where the number of entries with the highest value is identified. If only one entry has the highest value, that entry is evicted from the cache and replaced with the extracted data (step 76). On the other hand, if multiple cache entries have the same highest RRIP value, the method proceeds to step 78, where the processing circuitry selects an entry to be evicted by randomly selecting one of the entries. However, in other embodiments, rather than randomly selecting an entry, the processing circuitry may select the next entry (i.e., the next way 46 in set 48).

[0074] Multiple entries with the same RRIP value indicate that there is a level of redundancy within the system, since any cache entry with the highest RRIP value is an equally valid choice for the cache to be evicted. Therefore, unnecessary additional redundant information is stored in field 50.

[0075] return Figure 5, after selecting the entry with the highest RRIP value to be evicted in step 78, or after steps 64 or 70 or 76, the method proceeds to step 80, where it is determined whether a predetermined time has passed since the last increment of the RRIP value. As described above, the RRIP value provides an indication of how much time has passed since the processing circuit has accessed the relevant entry - a higher RRIP value means that a longer time has passed since the entry was accessed. Therefore, the value is incremented periodically. After step 80, if the predetermined time has not passed since the last increment, the method returns to step 56 and repeats. On the other hand, if the predetermined time has passed, the method instead proceeds to step 82, where the RRIP value is incremented. Note that although the increment of the RRIP value is shown as part of the method of accessing the cache for ease of explanation, the increment of the RRIP value can be triggered when the predetermined time has passed even if there is no cache access to the data. Therefore, for step 80, it is not a prerequisite that steps 56 to 78 have been performed. Additionally, while step 80 illustrates an embodiment where incrementing is triggered by the passage of a predetermined time, in other embodiments, incrementing may be triggered after a predetermined number of processing cycles, a predetermined number of accesses to the cache, or another measure of elapsed time.

[0076] It should be noted that in some embodiments, the number of values ​​that can be incremented can be limited so that only certain numbers can reach a maximum value (e.g., for a 2-bit RRIP value, the maximum value would be 11). This will be explained in more detail later.

[0077] The following embodiments exploit the above-described redundancy within the encoding of RRIP values ​​in order to efficiently store read set information.

[0078] Figure 6 is a flow chart illustrating a method of processing a transaction. At step 84, a transaction start (tstart) instruction of an external transaction is decoded and executed. The transaction start instruction of the external transaction is a transaction start instruction that has not been encountered in another transaction (i.e., it is not a nested transaction). In response, at step 86, encodings of alternative information values ​​(e.g., cache eviction policy information stored in field 50) are set to identify these values ​​as read set information, thereby identifying addresses that form part of the address read set of the transaction. When a transaction is first started, there will not be any addresses as part of the read set, but, despite this, in response to the tstart instruction of the external transaction, the alternative information values ​​can be set to encodings that are not allowed outside the transaction to indicate that they indicate read set information.

[0079] In some embodiments, instead of setting the encoding to identify the replaceable information value as read set information (step 86) in response to encountering a tstart instruction of a transaction outside (step 84), the replaceable information value may be set on a per-set basis. That is, when a line is assigned to a particular set in the cache, then the encoding of the set is changed. In this case, step 86 will follow step 90. This is also the case with the following figures. Therefore, the encoding may be set directly in response to encountering a tstart instruction, or the encoding of the replaceable information value associated with a particular cache set may be set in response to the first line in the read set assigned to the particular cache set after the transaction start instruction. In such an embodiment, during the processing of a transaction, if at a given time the encoding of the replaceable information value associated with a particular cache set is not set to identify the replaceable information value as read set information, this means that there has been no access to the cache set since the transaction start instruction, and therefore the processing circuit is configured to determine that none of the addresses in the cache set is part of the read set of the transaction at that time.

[0080] Note also that if the same block of replaceable information values ​​associated with a given cache set of a set-associated cache is used to indicate a read set for multiple transactions, it is possible that when the other transaction begins, the other transaction may already be pending (e.g., on a different processing element sharing the same cache), and so the encoding of the replaceable information value may already have an encoding indicating that the replaceable information value represents read set information, in which case step 86 may not need to be performed again.

[0081] In step 88, the recovery state memory 28 captures the current snapshot of the architectural state in the architectural registers 6 as the recovery state to be maintained for the transaction. It should be understood that while in some cases this may result in the captured architectural state being written to a separate register, other embodiments may use a physical register file for the architectural registers 6, the architectural registers having more registers than the number of registers supported in the instruction set architecture, and register renaming is used to remap which specific physical register is considered to store the data value of the specific architectural register required by the architecture. In such a system, register renaming can be used to change the mapping from architectural registers to physical registers when a transaction start instruction is encountered, so that a previously captured checkpoint of the architectural state can be effectively maintained in the same physical register file as the current architectural state itself, which can speed up the recovery of the state when necessary. In this case, the capture of the recovery state can be accomplished by changing the register mapping, so that there may not be any need to actually transfer data to / from the physical registers.

[0082] At step 90, speculative execution of instructions following the transaction start instruction begins. While the instructions are speculatively executed in the transaction, the results of some of the speculative instructions may be distributed to the speculative result storage circuit 22 (e.g., the results of the store instructions for storing data to the memory). The addresses accessed by the read instructions in the speculatively executed instructions are marked as part of the address read set by setting the values ​​in the replaceable information values ​​accordingly (or by updating the encoding of the set of replaceable information values ​​of a set associative cache), and while the transaction remains pending, write accesses to the address read set of the transaction by other threads may be monitored.

[0083] At step 92, the conflict detection circuit 26 detects whether an abort event occurs. For example, the abort event may be another thread (or another thread that reads one of the addresses tracked in the write set of the transaction) writing one of the address read sets tracked by the read set information stored in the cache 44, an interrupt or exception occurs, an instruction type that is not allowed to be executed in the transaction is executed, or the resources available for address tracking or speculation result storage 22 are fully utilized, so that the transaction can no longer be safely executed (because some additional addresses or speculation results that may need to be stored may no longer be tracked). It should be understood that other types of aborts can also be defined according to the constraints of the instruction set architecture. If an abort event occurs, the transaction is aborted at step 94, and the recovery state stored in the recovery state memory 28 is restored to the architecture register 6 representing the current architecture state of the system. Then, the processing can be resumed from the earlier execution point represented by the restored architecture state. In some cases, when a transaction is aborted, the microarchitecture may provide a hint indicating the reason why the transaction was aborted, which can be used by the exception handler in software to determine whether it is worthwhile to attempt to perform the desired operation again as a transaction, or whether it is preferable to fall back to executing the fallback path (not using transactions) to perform the corresponding processing operations.

[0084] If an abort event has not occurred at step 92, then a determination is made at step 96 whether any transaction end (tend) instructions have been decoded and executed (again, due to nesting, step 96 may check for tend instructions of the outer transaction based on the nesting depth register 32). If not, then the method loops back to step 92 to wait for an abort event or to execute a transaction end instruction. It should be understood that the speculative execution of instructions and the tracking of address working sets and potential conflicts continue throughout steps 90 to 96 until an abort event occurs or a transaction end instruction is reached.

[0085] When the outermost transaction end instruction is executed, then any speculative results of the transaction are committed to the state, and the previously captured recovery state is discarded or allowed to be overwritten, in step 98. Once the transaction is complete, in step 100, the encoding of the replaceable information values ​​is set to identify these values ​​according to their original purpose - even if the value is incorrect, the processing of it is functionally correct information, such as cache eviction policy information.

[0086] It should be noted that step 100 need not necessarily be followed immediately by set 94 or step 98. This change in encoding may occur at any time when the processing system is not executing a transaction. If no transaction is pending, but the replaceable information value is still encoded to indicate a transaction read set, cache replacement may be controlled based on the same default replacement policy used during the transaction (e.g., random / round-robin selection when no replacement policy information was encoded at all during the transaction, or when replacement policy information was retained with a reduced number of bits during the transaction, then the replacement policy is modified based on the reduced information). Resetting the encoding of the replaceable information value after the transaction ends may take some time because it may require a cache erase to reset the replaceable information associated with a relatively large number of cache sets, which may take some time and may not be executed in time with the tend instruction. Therefore, typically this may be after the tend instruction, but other instructions after the tend instruction may be processed simultaneously while the encoding of the reset replaceable information value is performed in the background.

[0087] Figure 7 shows how alternative information values ​​(such as cache eviction policy information) can be re-encoded to be interpreted as read-set information. Figure 7 In , the replaceable information value is initially interpreted as the RRIP value 102. For example, by using this encoding, using the RRIP replacement strategy, such as Figure 5 As shown. Figure 7 , 16 fields are shown to identify the replaceable information values ​​for the 16 ways of a 16-way set associative cache. It should be understood that the figure shows the RRIP values ​​for only one cache set, and a similar set of RRIP values ​​will be provided for each other set of set associative caches. When the replaceable information values ​​are interpreted as cache eviction policy information 102, each of the sixteen replaceable information values ​​gives a cache eviction policy for one of the sixteen ways of a given set in the 16-way set associative cache. In this embodiment, although the replaceable information values ​​are considered to represent the RRIP value 102, the values ​​maintained in the subset of entries (in this case, entries 0, 3, 6, 9, and 12) are restricted so that no more than a predetermined maximum number of these entries can have the value 3 (0b11). For example, in this case, the maximum number is 2, and therefore no more than two entries in the subset can store the value 11, and these values ​​represent RRIP values.

[0088] When a cache line corresponding to an address in a read set is first allocated to set 104—or when a tstart instruction is encountered—the encoding of the alternative information value is changed so that it identifies that the value is now interpreted as read set information 106. Figure 7 In the illustrated embodiment, the encoding is set by replacing all entries in the above subset (entries 0, 3, 6, 9, and 12) with the value 11. As long as all 5 entries in the subset show this value, the alternative information value will be interpreted as read set information, and thus replacing all entries in the subset with this value indicates that the alternative information value is to be interpreted as read set information. In an alternative embodiment, the subset of entries may alternatively be the entire set of entries. An encoding that sets a subset of 3 or 4 entries (e.g., 0, 3, 6, 9, and 12) to 0b11 is considered invalid, so if one of these encodings is detected, the transaction is aborted. This ensures that the Hamming distance between the valid replacement strategy encoding used outside the transaction and the valid read set encoding inside the transaction is 3, so that there is double error detection capability (even if two bits in entries 0, 3, 6, 9, and 12 change state due to an alpha particle strike or other single event upset, the error can still be detected, even if entries 0, 3, 6, 9, and 12 are not error protected using an error detection / correction code.

[0089] Once the encoding has been changed to identify the replaceable information value as read set information, Figure 7 In an embodiment, the cache eviction policy switches to a replacement policy that is independent of the content of the replaceable information value, such as a random replacement policy, where cache entries to be evicted are selected randomly or in a round-robin replacement policy, where the entries selected as victim entries cycle through each entry of the set in a particular sequence. This may be less efficient than other replacement policies that take into account information about the recent use of the entries, such as RRIP, but it is still functionally correct.

[0090] like Figure 7 As shown, the additional bits not used to indicate the encoding of the alternative information value will be interpreted as read set information - in this case, the bits in fields 1, 2, 4, 5, 7, 8, 10, 11 and 13 to 15 can now be used to store error check bits 108 and read set information 110. Although in this embodiment, the read set information and error check bits have been described separately, it should be understood that in the context of this application, "read set information" is intended to cover both read set values ​​and error check bits. As shown in the figure, this particular configuration also leaves spare bits 112, which can be used to store additional information.

[0091] In response to the encounter of tend instruction 114, this indicates that the encoding should be reset to identify the value as a RRIP value. This will involve replacing at least some of the replaceable information values ​​in the subset discussed above with those values ​​that are not 11, but may also optionally include other values ​​that change the RRIP value. In the embodiment shown in the figure, all values ​​116 are replaced with the same value 10 to hide any sensitive information that can be determined from the read set information before the replacement. However, in some other embodiments, the read set information can be replaced with a random value set instead (assuming that the number of values ​​that take the highest value is not higher than a predetermined maximum value). At this point, the processing circuit returns to the RRIP replacement strategy, and over time, these values ​​will be updated to more accurately reflect which entries should be replaced within the cache eviction strategy.

[0092] The specific embodiments above present space-saving techniques for storing read set information. This is because no extra bits are needed to store the encoding, as the read set encoding is simply set by setting a certain number of alternative information values ​​to the maximum possible value. However, the tradeoff of this approach is that fewer values ​​are available for storing the read set information, since some of the values ​​are obtained by providing the encoding. On the other hand, Figure 8 The embodiment shown in uses three additional bits 118 to mark the encoding of the replaceable information value. Initially, although the replaceable information value is used for the cache eviction policy information value 120, the additional bits 118 are set to 000. This is an encoding that indicates to the processing circuit 4 that the replaceable information value should be interpreted as such. When the cache line corresponding to the address in the read set is first assigned to the set 122 - or when the tstart instruction is encountered - the additional bits 118 are replaced with bits 111, and the processing circuit 4 is configured to interpret the replaceable information value as read set information when the additional bits 118 are set to 111. In this case 124, each entry identifies the read set information of one of the multiple ways of the 16-way set associative cache. Then, in response to the encounter of the tend instruction 126, the additional bits 118 are reset to 000, and the replaceable information value is interpreted again as the cache eviction policy information 128. The replaceable information value can also be replaced with a random value (or a value that is consistent with the tstart instruction). Figure 7 ) are replaced with the same values ​​as in the example.

[0093] By using three additional bits instead of two additional bits, such as in field 118, double error detection is allowed to be provided. This is because in order to change from code 000 to code 111, a Hamming distance of 3 is required; that is, three bits need to be replaced in order to go from one value to another. Since the probability of 3 bits changing state is likely to be extremely low in practice, this is a particularly secure way to encode alternative information values.

[0094] by Figure 8Encoding alternative information values ​​in the manner shown in requires more space in the cache, but allows storage of additional information. For example, Fig. 9 An embodiment is shown in which some cache eviction policy information is still retained once a tstart instruction 130 is encountered. In this embodiment, the replaceable information value again initially represents a RRIP value 132. However, unlike the previous embodiment, when the cache line corresponding to the address in the read set is first assigned to the set 130 - or when the tstart instruction is encountered - only half of the bits after field 118 are replaced with the read set information (which includes the error checking bit). Therefore, the cache eviction policy information is reduced to a single bit instead of the two bits that were originally 132, so that another bit of each pair of bits can be used to identify the read set information 134. Therefore, the most significant bit of the cache eviction policy information is retained and can be used in the changed RRIP replacement policy to indicate which cache line should be evicted when a new cache line is allocated. At the same time, the read set continues to be identified and error checking codes are provided.

[0095] In response to encountering a tend instruction 136, the bits that had been used as error checking bits and read set information are overwritten, and the returned value is interpreted as the read set information value 138. Of course, this also means that the additional bits 118 return to the value 000.

[0096] Fig. 9 The technique shown in has the advantage that cache eviction policy information can be maintained in a simplified form, but has the disadvantage that fewer bits are available for read set information. This may mean that only some entries in the cache are available for storing information used in a transaction.

[0097] However, Fig.10An embodiment is shown in which only nine bits in total are available for identifying the read set information for all 16 entries of a 16-way set associative cache. In this embodiment, each set 144 is considered to be divided into two groups, with a first group 145 including entries 0 to 7 and a second group 147 including entries 8 to 15. However, this is only one embodiment of how to divide the sets 144 into two groups - other embodiments may also be used. Each entry indicator 142 corresponds to one of the entries in the first set or one of the entries in the second set depending on the value of the group identifier 140. In this embodiment, the processing circuit initially assigns read set addresses to only the first group of caches 144. Therefore, the entry indicators each identify the read set information of one of these first 8 entries. When all 8 of these entries are full, the group identifier is set to a predetermined value (e.g., 1) to identify that all entries in the first group include addresses within the read set. At this point, the entry indicators 142 are reset to their default values ​​(e.g., 0). The processing circuit 4 now begins assigning read set addresses to the second group of entries in the cache 144 - entries 8 to 15. The entry indicator now identifies the read set information of one of the entries in this second group. Thus, by using only 9 bits - 1 bit of the group identifier 140 and 8 bits of the entry indicator 142 - read set information can be provided for all 16 ways of the 16-way set associative cache 144. For example, if the value of the group identifier 140 is 1 and the values ​​in the first two entry indicators are also 1, this indicates that all entries in the first group 145 are in the read set and the first two entries in the second group 147 (entries 8 and 9) are also in the read set. This can also be provided by providing two group identifiers, one for each group, and only seven entry indicators. In this case, if all entries in the first group 145 are in the read set, the seven entry indicators are reset to 0 and the first of the two group identifiers is set to 1.

[0098] Fig.11 Shows how to Fig. 9 In the embodiment of Fig.10 , and the entry indicator 142 and group identifier 140 shown in . In this case, since one bit per entry is reserved for cache eviction policy information, a total of 16 bits remain for storing read set information. To allow four bits to be used as error checking bits 108, only twelve bits may be used to store the remainder of the read set value.

[0099] exist Fig.11 In the embodiment of FIG. 5 , there are eight entry indicators 142 in entries 5 through 12, and a group identifier 140 in entry 4. There are also error check bits 108 in entries 0 through 3, and there are also three spare bits 200 in entries 13 through 15. All of this is done while still allowing one bit from each of these entries to be used as cache eviction policy information.

[0100] In other embodiments, the number of bits used to represent the read set information for each position in a given set can be further reduced by dividing the set into more than 2 groups. For example, the read set information for 4 groups of 4 entries within a set can be represented by 7 bits (4 group identifiers 140 and 3 entry indicators 142, or 3 group identifiers 140 and 4 entry indicators 142). Therefore, in general, the encoded read information for a set of M*N cache entries (including M groups of N entries each) can be represented by M+N-1 bits.

[0101] In some embodiments of the invention, read set information for multiple transactions may be identified within the encoding of the replaceable information value. Fig.12 Such an embodiment is shown. As shown in this embodiment, before the cache line corresponding to the address in the read set is first assigned to the set 201, or before the tstart instruction is encountered, these values ​​again initially identify the RRIP value 202. Then, with Figure 7 In the same manner as in , the encoding of the replaceable information values ​​is changed to identify that these values ​​should be identified as read set information 208.

[0102] In this embodiment, by using group identifiers 210, 212 and Fig.10 With the entry indicators 214, 216 described in the technique, two transactions - transaction 1 (T1) and transaction 2 (T2) - can release their read set information transmitted in these bits by encoding alternative information values, while still leaving room for error check bits 218. In fact, except Figure 7 In addition to the spare bits 220 that have been left in the READ_READ instruction 222, this embodiment leaves two more spare bits 220, i.e., a total of three spare bits 220. In this embodiment, the read set information of the two transactions shares the error code 218, and the read set information of each transaction is represented by four entry indicators 214, 216 and three group identifiers 210, 212, thereby allowing the sixteen ways of the 16-way set-associative cache to be represented by only seven bits in each transaction. Similarly, after encountering the tend instruction 222, the replaceable information values ​​are all reset to the value 10, and they are interpreted as cache eviction policy information 224 again.

[0103] In this application, the phrase "configured to..." is used to mean that an element of a device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0104] Although illustrative embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. A device for data processing, comprising: a processing circuit, the processing circuit being used to process a thread of data processing; transactional memory support circuitry for supporting execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread speculatively executed between a transaction begin instruction and a transaction end instruction, the processing circuitry being configured to prevent committing results of the speculatively executed instructions until the transaction end instruction is reached for the instructions of the thread, wherein the transactional memory support circuitry is configured to trigger an abort of the transaction in response to detecting a write access from another thread to one of the address read sets tracked for the transaction; and a cache having a plurality of entries, each entry being associated with an address of a plurality of addresses and specifying a replaceable information value associated with the address of the plurality of addresses, the replaceable information value comprising cache eviction policy information, wherein processing is functionally correct outside of the transaction even if the cache eviction policy information is incorrect; Wherein, when the transaction is in a pending state, the transactional memory support circuit is configured to identify read set information based on the encoding of the replaceable information value, wherein the read set information identifies an address in a read set of addresses tracked for the transaction.

2. The device according to claim 1, wherein: Following the transaction start instruction, the transactional memory support circuitry is configured to set an encoding of the replaceable information value to identify the read set information.

3. The device according to claim 2, wherein: The transactional memory support circuit is configured to: restricting a number of permissible encodings of said alternative information values ​​outside of said transaction; and After the transaction start instruction, the encoding of the replaceable information value is set to a non-permitted encoding to identify the read set information.

4. The device according to claim 3, wherein: Outside of the transaction, the non-permitted encoding is a redundant encoding that provides a functionally equivalent result to another permitted encoding.

5. The device according to claim 3, wherein: There is a Hamming distance of at least 3 between the set of encodings following the transaction start instruction and any allowed encodings outside of the transaction.

6. The device according to claim 3, wherein: The non-permitted encodings include encodings in which more than a predetermined number of alternative information values ​​in the subset of alternative information values ​​have predetermined values.

7. The device according to claim 1, wherein: The cache includes an encoding indicator field for storing an encoding indicator value to provide an indication to the processing circuit regarding an encoding of the alternative information value.

8. The device according to claim 7, wherein: In response to the transaction start instruction, the transactional memory support circuitry is configured to select an encoding of the alternative information value to reduce a number of bits used for the cache eviction policy information.

9. The device according to claim 1, wherein: The first portion of the read set information includes error detection information for detecting errors in the read set information.

10. The device according to claim 9, wherein: The transactional memory support circuitry is configured to select, after the transactional start instruction, an encoding of the second portion of the read set information to identify: at least one group indicator associated with a set of entries in the cache, the group indicator indicating whether the set of entries is a complete set including only entries in the read set or an incomplete set including at least one entry not in the read set; as well as At least one entry indicator is associated with at least one entry in the incomplete set, the entry indicator indicating whether the at least one entry is in a read set.

11. The device according to claim 1, wherein: The transactional memory support circuitry is configured to identify read set information for each transaction of a plurality of transactions based on an encoding of the replaceable information value.

12. The device according to claim 11, wherein The read set information of each transaction in the plurality of transactions shares an error detection code.

13. The apparatus according to claim 1, wherein: In response to execution of the transaction end instruction or abortion of the transaction, the processing circuit is configured to interpret the replaceable information values ​​of the plurality of entries as the cache eviction policy information.

14. The device according to claim 13, wherein: After executing the transaction end instruction or aborting the transaction, the transactional memory support circuitry is configured to replace each replaceable information value of the plurality of entries with a value unrelated to the replaceable information value.

15. The apparatus according to claim 1, wherein: While the transaction is pending, the processing circuit is configured to select a cache line from the cache for eviction independent of the replaceable information value.

16. The apparatus according to claim 1, wherein: While the transaction is pending, the processing circuit is configured to select a cache line from the cache for eviction based on a modified cache eviction policy based on modified eviction policy information encoded in the replaceable information value and the read set information.

17. The apparatus according to claim 1, wherein: While the transaction is pending, the processing circuitry is configured to, when selecting entries from the cache for eviction, give preference to entries associated with addresses outside a read set of addresses tracked for the transaction.

18. A data processing method, comprising: identifying, in a cache having a plurality of entries, for each entry associated with one of a plurality of addresses, a replaceable information value for each address, wherein the replaceable information value includes cache eviction policy information, wherein processing is functionally correct outside of a transaction even if the cache eviction policy information is incorrect; When a transaction is in a pending state, identifying read set information based on the encoding of the replaceable information value, the read set information identifying an address in a read set of addresses tracked for the transaction; The transaction comprises instructions of a thread speculatively executed between a transaction start instruction and a transaction end instruction, for the instructions of the thread, committing results of the speculatively executed instructions is prevented until the transaction end instruction is reached, and abort of the transaction is triggered in response to detecting a write access from another thread to one of a read set of addresses tracked for the transaction.

19. A device for data processing, comprising: means for handling threads of data processing; means for supporting execution of a transaction within a thread processed by means for processing, the transaction comprising instructions of the thread speculatively executed between a transaction begin instruction and a transaction end instruction, for which instructions the means for processing is configured to prevent committing results of the speculatively executed instructions until the transaction end instruction is reached, wherein the means for supporting is configured to trigger an abort of the transaction in response to detecting a write access from another thread to one of a read set of addresses tracked for the transaction; and an apparatus for caching data, comprising a plurality of entries, each entry being associated with one of a plurality of addresses and specifying a replaceable information value associated with the address of the plurality of addresses, the replaceable information value comprising cache eviction policy information, wherein processing is functionally correct outside of the transaction even if the cache eviction policy information is incorrect; Wherein, when the transaction is in a pending state, the means for supporting is configured to identify read set information based on the encoding of the replaceable information value, the read set information identifying an address in a read set of addresses tracked for the transaction.

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