Application of word line underdrive pulses to improve SRAM stability in low power supply voltage environments

Abstract

Various embodiments of the present disclosure relate to the application of wordline underdrive pulses to improve the stability of SRAM in a low power supply voltage environment. A wordline coupled to a memory cell is selected in association with performing a read / write operation at the memory cell. A wordline signal is asserted on the selected wordline. The assertion of the wordline signal has a leading edge and a trailing edge, and a series of wordline underdrive pulses between the leading edge and the trailing edge. Each wordline underdrive pulse causes the wordline voltage to drop from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level. Both the first and second voltage levels are greater than the ground voltage of the memory cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 726,502, filed September 4, 2018, the contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates to integrated memory circuits, and in particular to a wordline underdrive assist circuit for a static random access memory (SRAM). Background Art

[0004] refer to Figure 1 , which shows a schematic diagram of a standard memory circuit 10 including a plurality of memory cells 12, which are typically arranged in an array including a plurality of columns and rows. Each memory cell 12 in this embodiment is, for example, a conventional six-transistor (6T) static random access memory (SRAM) cell 12. The memory circuit 10 also includes a word line driver 14 for each row and an address decoder 16, which is configured to control the operation of the word line driver.

[0005] Each memory cell 12 includes two cross-coupled CMOS inverters 22 and 24, each of which includes a pair of p-channel and n-channel MOSFET transistors connected in series. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QB. Cell 12 also includes two pass (transmission gate) transistors 26 and 28, whose gate terminals are driven by a word line (WL) that is coupled to the output of word line driver 14. The source-drain of transistor 26 is connected between the true data storage node QT and a node associated with the true bit line (BLT). The source-drain of transistor 28 is connected between the complementary data storage node QB and a node associated with the complementary bit line (BLB). The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high power supply voltage (e.g., Vdd) at a high power supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low power supply voltage (e.g., Gnd) at a low power supply node. The high power supply voltage Vdd at the high power supply node and the low power supply voltage Gnd at the low power supply node constitute a power supply group for the voltages of cell 12.

[0006] Wordline driver circuit 14 includes a pair of p-channel and n-channel MOSFET transistors connected in series, forming a logic inverter. Wordline driver circuit 14 is also coupled to receive a high supply voltage (Vdd) at a high supply node and referenced to a low supply voltage (Gnd) at a low supply node. The input of wordline driver circuit 14 is coupled to the output of address decoder 16, and the wordline (WL) for a row of cells 12 is coupled to the output of the corresponding wordline driver circuit 14. Address decoder 16 receives an address (Addr), decodes the received address, and selectively actuates the wordline through wordline driver circuit 14 to assert a logic high wordline signal.

[0007] In many applications, including system-on-chip (SoC) applications, SRAM cells 12 are preferred memory elements because of their small size and fast data access operations. The memory circuit 10 will include many SRAM cells 12, and therefore the size of each SRAM cell is an important design consideration. Efforts are made to use the smallest possible transistor devices for the SRAM cells 12 in order to reduce die area and control costs. However, the use of small transistor devices increases concerns about variation and stability.

[0008] It is also important to operate the memory circuit 10 at the lowest possible level of high power supply voltage (Vdd). Static noise margin (SNM) is a measure of the stability of the SRAM cell 12 during access, and write margin (WM) is a measure of the ease with which data can be written to the cell. Both SNM and WM decrease as the level of the high power supply voltage Vdd decreases, and therefore stability decreases accordingly as the power supply voltage decreases. In fact, it is known to those skilled in the art that the SRAM cell 12 becomes unstable due to low SNM at lower power supply voltages because the data stored in the cell may flip when accessed.

[0009] Many techniques have been developed to assist the operation of the SRAM cell 12 when using a reduced power supply voltage Vdd level. One technique is known as wordline underdrive (WLUD), in which the logic high voltage on the wordline is pulled down to a voltage below the power supply voltage by the wordline underdrive assist circuit 40 to provide sufficient static noise margin (SNM) for read and write operations. When wordline underdrive is active, the logic high voltage level of the wordline signal applied to the gates of the pass (transfer gate) transistors 26 and 28 is less than the power supply voltage Vdd level. The wordline WL is essentially underdriven by a ΔV voltage, so that the logic high voltage level of the asserted wordline signal is at a voltage level of Vdd-ΔV. The effect of the wordline underdrive technique is to reduce the strength of the pass (transfer gate) transistors 26 and 28. Figure 2A comparison of word line signal voltages for a first case 42 in which the word line under-driving technique is not utilized and a second case 44 in which the word line under-driving technique is utilized is shown.

[0010] The disadvantage of using word line underdrive technology is the reduction of cell current and the corresponding reduction of operating frequency. Figure 3 As shown in , application of a reduced word line voltage increases the flipping time of the cell, where the first case 42 has a flipping time T flip and the second case has a flipping time T flip + ΔT. Summary of the Invention

[0011] In one embodiment, a method includes: decoding an address to select a word line coupled to a memory cell; asserting a word line signal on the selected word line to perform a read / write operation at the memory cell, the asserted word line signal having a leading edge and a trailing edge; and applying a plurality of word line underdrive pulses to the asserted word line signal between the leading edge and the trailing edge, each word line underdrive pulse causing a voltage of the asserted word line signal to drop from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level; wherein both the first and second voltage levels are greater than a ground voltage of the memory cell.

[0012] In one embodiment, a method includes: selecting a word line coupled to a memory cell; and making a single assertion of a word line signal on the selected word line to perform a read / write operation at the memory cell, wherein the single assertion has a leading edge and a trailing edge, and between the leading edge and the trailing edge, the single assertion further includes a plurality of word line underdrive pulses, wherein each word line underdrive pulse causes a word line voltage to drop from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level; wherein both the first and second voltage levels are greater than a ground voltage of the memory cell.

[0013] In one embodiment, a circuit includes: a word line configured to be coupled to a memory cell powered by a power supply voltage; a pull-up transistor having a source-drain path connected between the power supply voltage and the word line, wherein the pull-up transistor is actuated in response to selection of the word line to perform a read / write operation at the memory cell; a pull-down transistor having a source-drain path connected between the word line and a ground node; and a control circuit configured to apply a control signal to a control terminal of the pull-down transistor to provide a word line underdrive comprising a plurality of word line underdrive pulses; wherein each word line underdrive pulse causes a word line voltage to drop from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level; and wherein both the first and second voltage levels are greater than a ground voltage of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For a better understanding of the present invention, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0015] Figure 1 is a schematic diagram of a standard memory circuit with word line underdrive (WLUD) assistance;

[0016] Figure 2 is a timing diagram showing a comparison of word line voltages with and without word line underdriving;

[0017] Figure 3 is a timing diagram showing a comparison of cell flip timing with and without word line underdriving;

[0018] Figure 4 is a schematic diagram of a memory circuit with pulsed word line underdrive (WLUD) assistance;

[0019] Figure 5 is a timing diagram illustrating one embodiment of pulsed word line underdriving;

[0020] Figure 6 is a timing diagram illustrating another embodiment of pulsed word line underdriving;

[0021] Figure 7A-7B is a block diagram of a pulsed word line underdrive assist circuit; and

[0022] Figure 8 The diagram shows the use of conventional word line underdrive (such as Figure 1 ) and pulse word line underdrive (such as Figure 4 ) operations. DETAILED DESCRIPTION

[0023] refer to Figure 4 , which shows a schematic diagram of a memory circuit 110 including a plurality of memory cells 12, which are typically arranged in an array including a plurality of columns and rows. Each memory cell 12 in this embodiment is, for example, a conventional six-transistor (6T) static random access memory (SRAM) cell 12. The memory circuit 110 also includes a word line driver 14 for each row and an address decoder 16, which is configured to control the operation of the word line driver.

[0024] Each memory cell 12 includes two cross-coupled CMOS inverters 22 and 24, each inverter comprising a pair of p-channel and n-channel MOSFET transistors connected in series. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QB. Cell 12 also includes two pass (transfer gate) transistors 26 and 28, whose gate terminals are driven by a word line (WL) coupled to the output of word line driver 14. The source-drain of transistor 26 is connected between the true data storage node QT and a node associated with the true bit line (BLT). The source-drain of transistor 28 is connected between the complementary data storage node QB and a node associated with the complementary bit line (BLB). The source terminals of p-channel transistors 30 and 32 in each of inverters 22 and 24 are coupled to receive a high power supply voltage (e.g., Vdd) at a high power supply node, while the source terminals of n-channel transistors 34 and 36 in each of inverters 22 and 24 are coupled to receive a low power supply voltage (e.g., Gnd) at a low power supply node. The high power supply voltage Vdd at the high power supply node and the low power supply voltage Gnd at the low power supply node constitute a power supply group for the voltages of cell 12.

[0025] Wordline driver circuit 14 includes a pair of p-channel and n-channel MOSFET transistors connected in series, forming a logic inverter. Wordline driver circuit 14 is also coupled to receive a high supply voltage (Vdd) at a high supply node and referenced to a low supply voltage (Gnd) at a low supply node. The input of wordline driver circuit 14 is coupled to the output of address decoder 16, and the wordline (WL) for a row of cells 12 is coupled to the output of the corresponding wordline driver circuit 14. Address decoder 16 receives an address (Addr), decodes the received address, and selectively actuates the wordline through wordline driver circuit 14 to assert a logic high wordline signal.

[0026] The memory circuit 110 supports an improved form of word line underdrive (WLUD) using a pulsed word line underdrive assist circuit 140. The pulsed word line underdrive assist circuit 140 is coupled to the word line WL and can be selectively activated by the address decoder 16.

[0027] Figure 5Shows a timing diagram of a single assertion 144 of a word line (in response to address decoding of a selected word line) being logic high according to an embodiment of a pulsed word line underdrive technique. The address decoder 16 asserts the word line 144 through the word line driver circuit 14 corresponding to a read or write period, and includes a leading edge 150 and a trailing edge 152. In the leading edge 150, the voltage of the word line signal rises from a low supply voltage (Gnd) to a high supply voltage (Vdd), and in the trailing edge 152, the voltage of the word line signal falls from the high supply voltage (Vdd) to the low supply voltage (Gnd). Between the leading edge 150 and the trailing edge 152 of the asserted word line signal, the pulsed word line underdrive assist circuit 140 applies a plurality of underdrive pulses 154 to the word line, which causes the logic high voltage of the word line signal to drop by ΔV (where ΔV < VDD). The value of the ΔV voltage, the duration (Pd) of each underdrive pulse 154, and the value of the interval (Pi) between consecutive underdrive pulses 154 can be configured by the pulsed word line underdrive assist circuit 140.

[0028] Figure 6 Shows a timing diagram of a single assertion 244 of a word line (in response to address decoding of a selected word line) according to another embodiment of the pulsed word line underdrive technique. The address decoder 16 asserts the word line 244 through the word line driver circuit 14 corresponding to a read or write period, and includes a leading edge 250 and a trailing edge 252. In the leading edge 250, the voltage of the word line signal rises from a low supply voltage (Gnd) to a fixed underdrive voltage (Vdd - ΔV1; where ΔV1 < Vdd), and in the trailing edge 252, the voltage of the word line signal falls from the fixed underdrive voltage (Vdd - ΔV1) to the low supply voltage (Gnd). Between the leading edge 250 and the trailing edge 252 of the asserted word line signal, the pulsed word line underdrive assist circuit 140 applies a plurality of underdrive pulses 254 to the word line, which causes the logic high voltage of the word line signal to drop by ΔV2 (where ΔV2 < Vdd; and ΔV1 + ΔV2 < Vdd). The values of the ΔV1 and ΔV2 voltages, the duration (Pd) of each underdrive pulse 254, and the value of the interval (Pi) between consecutive underdrive pulses 254 can be configured by the pulsed word line underdrive assist circuit 140.

[0029] Now refer to Figure 7A, which shows a block diagram of the pulsed wordline underdrive assist circuit 140. Pull-down circuit 160 is coupled between wordline WL and a low power supply voltage (Gnd) node. The conductivity of pull-down circuit 160 is controlled by a first control signal CNTL1. The first control signal CNTL1 is modulated by a pulse circuit 170. The pulse circuit 170 can apply a pulse to pull-down circuit 160 to select a voltage level ΔV or ΔV2 of a pulse for pulsed wordline underdrive assist. Wordline underdrive circuit 162 is coupled between wordline WL and a low power supply voltage (Gnd) node. The conductivity of wordline underdrive circuit 162 is controlled by a second control signal CNTL2. The second control signal CNTL2 is modulated by a bias circuit 172. The bias circuit 172 can apply a bias to pull-down circuit 160 to select a voltage level ΔV1 for a fixed underdrive voltage. The pulsed wordline underdrive assist circuit 140 is enabled for operation by a wordline underdrive enable signal (WLUDen) generated by an address decoder. The pulse circuit 170 may be configured to select the value of the ΔV or ΔV2 voltage, the duration (Pd), and the interval (Pi).The bias circuit 172 may be configured to select the magnitude of the voltage level ΔV1.

[0030] In one embodiment, the pull-down circuit 160 may include an n-channel pull-down transistor whose source-drain is coupled between the word line WL and a low power supply voltage (Gnd) node. A first control signal CNTL1 is applied to the gate of the pull-down transistor. When both the pull-down transistor of the pull-down circuit 160 and the p-channel pull-up transistor 168 of the driver 12 are active, the two transistors form a voltage divider circuit, and the divided voltage sets the voltage level at the word line to implement a pulse for pulsed word line underdrive assist.

[0031] In one embodiment, wordline underdrive circuit 162 may include an n-channel pull-down transistor whose source-drain is coupled between wordline WL and a low power supply voltage (Gnd) node. A second control signal CNTL2 is applied to the gate of the pull-down transistor. When both the pull-down transistor of pull-down circuit 162 and the p-channel pull-up transistor 168 of driver 12 are active, the two transistors form a voltage divider circuit, and this divided voltage sets the voltage level at the wordline to implement wordline underdrive.

[0032] It should be understood that the wordline underdrive circuit 162 may be omitted, or alternatively selectively disabled, such that the pulsed wordline underdrive assist only applies pulses. Figure 7B An example of such an implementation is shown in .

[0033] Now refer to Figure 8 , which illustrates the use of conventional word line underdrive (such as Figure 1 ) and pulse word line underdrive (such as Figure 4 ) operations. Figure 8The upper portion shows the assertion of the word line signal with conventional word line underdrive (reference numeral 400), the assertion of the word line signal with pulsed word line underdrive (reference numeral 402), and the assertion of the word line without any form of word line underdrive (reference numeral 404). In each case, the assertion of the word line signal has a leading edge 250 and a trailing edge 252. Between the edges 250 and 252, the word line signal without any form of word line underdrive (reference numeral 404) is at the voltage level of Vdd. Between the edges 250 and 252, the word line signal with conventional word line underdrive (reference numeral 400) is at the voltage level of Vwlud, where Vwlud < Vdd. Between the edges 250 and 252, the word line signal with pulsed word line underdrive (reference numeral 402) has a maximum voltage of Vdd - ΔV1 (a fixed underdrive voltage, where ΔV1 < Vdd), which is greater than Vwlud, and includes a plurality of underdrive pulses 254, where for each pulse, the asserted word line signal voltage drops to a voltage of Vdd - ΔV2 (where ΔV2 < Vdd; and ΔV1 + ΔV2 < Vdd) below Vwlud.

[0034] Figure 8 The lower portion shows the bit line voltages in response to the assertion of the word line signal with conventional word line underdrive (reference numeral 400) and the assertion of the word line signal with pulsed word line underdrive (reference numeral 402). In particular, it will be noted that there is an increased difference (Vdiff) between the true bit line (BLT) voltage 410 and the complementary bit line (BLB) voltage 412 in the case of using pulsed word line underdrive (reference numeral 402) compared to conventional word line underdrive (reference numeral 400).

[0035] The use of pulsed word line underdrive (reference numeral 402) provides benefits during a write operation. Compared to conventional word line underdrive (reference numeral 400), lower word line underdrive requirements or better word line voltage levels provide an improved write window 420 (between consecutive pulses 254).

[0036] The foregoing description has provided a complete and informative description of exemplary embodiments of the invention by way of example and not limitation. However, various modifications and adaptations will become apparent to those skilled in the art in view of the foregoing description when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications to the teachings of the invention will still fall within the scope of the invention as defined by the appended claims.

Claims

1. A method comprising: decoding an address to select a word line coupled to a memory cell; asserting a word line signal on the selected word line to perform a read / write operation at the memory cell, the asserted word line signal having a leading edge and a trailing edge; as well as applying a plurality of word line under-drive pulses to the asserted word line signal between the leading edge and the trailing edge, each word line under-drive pulse causing the voltage of the asserted word line signal to drop from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level; wherein both the first voltage level and the second voltage level are greater than a ground voltage of the memory cell; as well as During the application of the plurality of word line under-driving pulses, a difference between a real bit line voltage and a complementary bit line voltage of the memory cell is increased. 2 . The method of claim 1 , wherein the first voltage level is equal to a power supply voltage of the memory cell.

3. The method according to claim 2, further comprising: The magnitude of the difference between the second voltage level and the first voltage level is selected. The method of claim 1 , wherein the first voltage level is less than a power supply voltage of the memory cell.

5. The method according to claim 4, further comprising: selecting a magnitude of a difference between the supply voltage and the first voltage level; as well as The magnitude of the difference between the second voltage level and the first voltage level is selected. 6 . The method of claim 1 , wherein there are gaps between consecutive word line under-drive pulses of the plurality of word line under-drive pulses, the method further comprising selecting the gaps. 7 . The method of claim 1 , wherein each wordline underdrive pulse of the plurality of wordline underdrive pulses has a duration, the method further comprising selecting the duration.

8. A method comprising: selecting a word line coupled to the memory cell; as well as making a single assertion of a word line signal on the selected word line in connection with performing a read / write operation at the memory cell, wherein the single assertion has a leading edge and a trailing edge, and between the leading edge and the trailing edge, the single assertion further comprises a plurality of word line underdrive pulses, wherein each word line underdrive pulse causes a word line voltage to drop from a first voltage level to a second voltage level and then to rise from the second voltage level to the first voltage level; wherein both the first voltage level and the second voltage level are greater than a ground voltage of the memory cell; as well as During the application of the plurality of word line under-driving pulses, a difference between a real bit line voltage and a complementary bit line voltage of the memory cell is increased.

9. The method of claim 8, wherein the first voltage level is equal to a supply voltage of the memory cell, and the method further comprises selecting the second voltage level.

10. The method of claim 8, wherein the first voltage level is less than a supply voltage of the memory cell, and further comprising selecting the first voltage level and the second voltage level.

11. The method of claim 8, wherein there are intervals between consecutive word line under-drive pulses of the plurality of word line under-drive pulses, the method further comprising selecting the intervals.

12. The method of claim 8, wherein each wordline underdrive pulse of the plurality of wordline underdrive pulses has a duration, the method further comprising selecting the duration.

13. A circuit comprising: a word line configured to be coupled to a memory cell powered by a power supply voltage; a pull-up transistor having a source-drain path connected between the power supply voltage and the word line, wherein the pull-up transistor is actuated in response to selection of the word line to perform a read / write operation at the memory cell; a pull-down transistor having a source-drain path connected between the word line and a ground node; as well as a control circuit configured to apply a control signal to a control terminal of the pull-down transistor to provide a wordline underdrive comprising a plurality of wordline underdrive pulses; wherein each word line underdrive pulse causes the word line voltage to drop from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level; and wherein both the first voltage level and the second voltage level are greater than a ground voltage of the memory cell; as well as During the application of the plurality of word line under-driving pulses, a difference between a real bit line voltage and a complementary bit line voltage of the memory cell is increased.

14. The circuit of claim 13 , wherein the control circuit comprises: a bias circuit coupled to a control terminal of the pull-down transistor and configured to set an amount of fixed wordline underdrive; as well as A pulse circuit is coupled to the control terminal of the pull-down transistor and is configured to apply the plurality of wordline underdrive pulses.

15. The circuit of claim 13, wherein the first voltage level is equal to the supply voltage of the memory cell.

16. The circuit of claim 13, wherein the first voltage level is less than the supply voltage of the memory cell.

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