Memory chip built-in self-test method and circuit device

Abstract

The present invention discloses a memory chip built-in self-test method and circuit device, the method comprising: inputting an original test vector into a circuit to be tested to generate a test data signal; inputting the original test vector into a register so that the original test vector is synchronized with the test data signal; performing a logical XOR operation on the delayed original test vector and the test data signal to generate a test result indication signal for indicating whether the circuit to be tested is valid; inverting the phase of the delayed original test vector by 180 degrees to generate an inverted test vector, and performing a logical AND-NOT operation on the inverted test vector and the test data signal to output a logic state indication value for indicating the logic state of the test data signal when the circuit to be tested fails; and selecting and outputting one of a valid test result and a logic state indication value for indicating the circuit to be tested according to the test result indication signal. It is possible to judge whether the circuit to be tested is valid, and further obtain the failure form of the circuit to be tested.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a memory chip built-in self-test method and circuit device. Background Art

[0002] As the number of units contained in ultra-large-scale semiconductor integrated circuits increases, the proportion of test costs in the total chip cost is increasing. At present, it is generally believed that the solution that can effectively solve the chip-level test cost is to insert a "built-in self-test (BIST)" structure inside the chip. Through this solution, the controllability and observability of chip testing can be increased, making test vector generation and verification testing easier.

[0003] The usual testing method is to load the test vector to the chip under test, collect the response results and compare them with the expected results to detect whether the chip can work normally. In the current built-in self-test structure, the memory chip comparison circuit performs an XOR logic operation on the test data signal (i.e., the response result) output after the test circuit is tested and the test vector (i.e., the expected result), and judges whether the circuit under test can work normally based on the result of the operation. The specific testing process is: when the test data signal is different from the test vector, the output result is "1", and the judgment result is that the circuit under test is invalid and cannot work normally; when the test data signal is the same as the test vector, the output result is "0", and the judgment result is that the circuit under test is valid and can work normally.

[0004] However, in the current test method, the state of the test data signal cannot be accurately obtained based on the judgment result. The reason is that when the circuit to be tested fails, there are two possibilities: when the state of the test data signal is "1" and the state of the test vector is "0", the judgment result is that the circuit to be tested is invalid; when the state of the test data signal is "0" and the state of the test vector is "1", the judgment result is also that the circuit to be tested is invalid. At this time, the state of the test data signal includes two states "0" and "1" when the circuit to be tested is invalid. Therefore, using the existing test method, the state of the test data signal cannot be known based on the judgment result. Summary of the invention

[0005] The present invention provides a memory chip built-in self-test method and circuit device to overcome or alleviate one or more problems existing in the background technology and at least provide a beneficial choice.

[0006] As one aspect of the present invention, a memory chip built-in self-test method is provided, comprising:

[0007] Inputting the original test vector into the circuit under test to generate a test data signal;

[0008] Inputting the original test vector into a register to delay the transmission time of the original test vector so that the original test vector is synchronized with the test data signal;

[0009] Performing a logical exclusive OR operation on the delayed original test vector and the test data signal to generate a test result indication signal, wherein the test result indication signal is used to indicate whether the circuit to be tested is valid;

[0010] Inverting the phase of the delayed original test vector by 180 degrees to generate an inverted test vector, performing a logic AND operation on the inverted test vector and the test data signal, and outputting a logic state indication value, wherein the logic state indication value is used to indicate the logic state of the test data signal when the circuit to be tested fails;

[0011] According to the test result indication signal, one of the valid test result and the logic state indication value for indicating the circuit to be tested is selectively output.

[0012] Preferably, in the above memory chip built-in self-test method, before inputting the original test vector into the circuit to be tested to generate the test data signal, it also includes:

[0013] The original test vector is generated according to a test control signal generated by a built-in self-test controller.

[0014] Preferably, in the above-mentioned memory chip built-in self-test method, the logic states of the test data signal and the delayed original test vector both include a high level and a low level, and the step of performing a logical XOR operation on the delayed original test vector and the test data signal to generate a test result indication signal includes:

[0015] When the logic state of the test data signal is different from the logic state of the delayed original test vector, the test result indication signal generated after performing a logical XOR operation is at a high level.

[0016] Preferably, in the above-mentioned memory chip built-in self-test method, the step of outputting the logic state indication value when the test result indication signal is at a high level comprises:

[0017] When the test result indication signal is at a high level and the output logic state indication value is at a high level, it indicates that the logic state of the test data signal is at a low level;

[0018] When the test result indication signal is at a high level and the output logic state indication value is at a low level, it indicates that the logic state of the test data signal is at a high level.

[0019] Preferably, in the above-mentioned memory chip built-in self-test method, the logic states of the test data signal and the delayed original test vector both include a high level and a low level, and the step of performing a logical XOR operation on the delayed original test vector and the test data signal to generate a test result indication signal includes:

[0020] When the logic state of the test data signal is the same as the logic state of the delayed original test vector, the test result indication signal generated after performing a logical XOR operation indicates a low level.

[0021] Preferably, in the above-mentioned memory chip built-in self-test method, when the test result indication signal is at a low level, the output valid test result is represented as a high impedance state.

[0022] The present invention also provides a memory chip built-in self-test circuit device, including a circuit to be tested, a register, a comparison circuit and a test result output module;

[0023] The circuit to be tested is used to generate a test data signal according to an original test vector;

[0024] The register is used to delay the transmission time of the original test vector so that the delayed original test vector is output synchronously with the test data signal;

[0025] The comparison circuit is connected to the circuit to be tested and the register, and the comparison circuit includes an XOR gate, an inverter and a NAND gate;

[0026] The XOR gate comprises a first input terminal, a second input terminal and a first signal output terminal, the first input terminal is used to input the original test vector after delay, the second input terminal is used to receive the test data signal, and the first signal output terminal is used to output a test result indication signal, and the test result indication signal is used to indicate whether the circuit to be tested is valid;

[0027] The inverter comprises an inverter input end and an inverter output end, wherein the inverter input end is used to receive the delayed original test vector, and the inverter output end is used to output an inverted test vector generated by inverting the phase of the delayed original test vector by 180 degrees;

[0028] The NAND gate comprises a third input terminal, a fourth input terminal and a second signal output terminal, the third input terminal is used to receive the test data signal, the fourth input terminal is connected to the inverter output terminal, the fourth input terminal is used to receive the inverted test vector, and the second signal output terminal is used to output a logic state indication value, and the logic state indication value is used to indicate the logic state of the test data signal when the circuit to be tested fails;

[0029] The test result output module is connected to the XOR gate and the NAND gate, and is used to selectively output one of a valid test result indicating that the circuit under test is valid and the logic state indication value according to the test result indication signal.

[0030] Preferably, in the above-mentioned memory chip built-in self-test circuit device, the circuit device further includes a test vector generation module, and the test vector generation module includes:

[0031] Built-in self-test controller for generating test control signals;

[0032] A test vector generator is used to generate the original test vector according to the test control signal, the input end of the measurement vector generator is connected to the built-in self-test controller, and the multiple output ends of the measurement vector generator are respectively connected to the circuit under test and the register.

[0033] Preferably, in the above-mentioned memory chip built-in self-test circuit device, the test result output module is a multiplexer and includes a selection control terminal, a first signal input terminal, a second signal input terminal and a test result output terminal;

[0034] The selection control terminal is connected to the first signal output terminal of the XOR gate, and is used to receive the test result indication signal;

[0035] The first signal input terminal is connected to the second signal output terminal of the NAND gate, and is used to receive the logic state indication value;

[0036] The second signal input terminal is used to input a valid test result indicating that the circuit to be tested is valid;

[0037] The test result output terminal is used to connect to the second signal input terminal and output the valid test result when the test result indication signal is at a low level, and to connect to the first signal input terminal and output the logic state indication value when the test result indication signal is at a high level.

[0038] The present invention adopts the above technical scheme, which has the following advantages: the scheme improves the function of the comparison circuit. Specifically, the original test vector and the test data signal are input into the comparison circuit. In the comparison circuit, the original test vector and the test data signal are subjected to a logical XOR operation to generate a test result indication signal. In addition, the phase of the original test vector is reversed by 180 degrees to generate an inverted test vector, and the inverted test vector and the test data signal are subjected to a logical AND-NOT operation to output a logic state indication value. Finally, the multiplexer selects the output logic state indication value or the valid test result according to the test result indication signal, wherein the logic state indication value indicates the logic state of the test data signal when the circuit to be tested fails. The scheme can not only determine whether the circuit to be tested is valid, but also further obtain the failure form of the circuit to be tested, that is, the logic state of the test data signal and the logic state of the original test vector can be directly obtained from the test result. Not only does it improve the test efficiency, but it is also convenient for the subsequent maintenance of the circuit to be tested.

[0039] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present invention and should not be regarded as limiting the scope of the present invention.

[0041] Figure 1 A flow chart of a memory chip built-in self-test method provided by an embodiment of the present invention is shown.

[0042] Figure 2 A structural diagram of a memory chip built-in self-test circuit device provided by an embodiment of the present invention is shown.

[0043] Figure 3 A comparison circuit structure diagram of a memory chip built-in self-test circuit device according to an embodiment of the present invention is shown.

[0044] Figure 4 A schematic diagram of signals during a memory chip built-in self-test process provided by an embodiment of the present invention is shown. Description of the drawings:

[0046] 100-test vector generation module;

[0047] 101-Built-in self-test controller;

[0048] 102-test vector generator;

[0049] 111-input terminal of the test vector generator;

[0050] 110- output terminal of the test vector generator;

[0051] 200-circuit to be tested;

[0052] 300 - register;

[0053] 400-comparison circuit;

[0054] 401-XOR gate;

[0055] 411 - a first input terminal of an XOR gate;

[0056] 421 - the second input terminal of the XOR gate;

[0057] 431-a first signal output terminal of the XOR gate;

[0058] 402-inverter;

[0059] 412-inverter input terminal;

[0060] 422-inverter output terminal;

[0061] 403-NAND gate;

[0062] 433-the third input terminal of the NAND gate;

[0063] 443-the fourth input terminal of the NAND gate;

[0064] 413 - a second signal output terminal of the NAND gate;

[0065] 500-test result output module;

[0066] 501-first signal input terminal;

[0067] 502- second signal input terminal;

[0068] 503-test result output terminal;

[0069] 504-Select the control terminal. DETAILED DESCRIPTION

[0070] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0071] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0073] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0074] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0075] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0076] Embodiment 1

[0077] In a specific embodiment, a memory chip built-in self-test method is provided, such as Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, including:

[0078] Step S100: inputting the original test vector into the circuit under test 200 to generate a test data signal.

[0079] A functional test is performed on the circuit under test 200 to determine whether the function of the circuit under test 200 is valid. For example, the circuit under test 200 reads the original test vector and outputs a test data signal. By determining whether the test data signal is consistent with the original test vector, it is determined whether the circuit under test 200 can correctly read the original test vector. If they are consistent, it means that the reading function of the circuit under test 200 is valid. If they are inconsistent, it means that the reading function of the circuit under test 200 is invalid.

[0080] Step S200: inputting the original test vector into the register 300 to delay the transmission time of the original test vector so that the original test vector is synchronized with the test data signal.

[0081] Since it takes time for the circuit under test 200 to read the original test vector and output the test data signal, the original test vector is input into the register 300 and cached for a period of time to ensure that the original test vector and the test data signal are output synchronously.

[0082] Step S300: performing a logical exclusive OR operation on the delayed original test vector and the test data signal to generate a test result indication signal, where the test result indication signal is used to indicate whether the circuit under test 200 is valid.

[0083] The XOR gate 401 can perform a logical XOR operation on the original test vector and the test data signal received at the same time to generate a test result indication signal. Figure 4As shown, the test result indication signal is output from path a, and the test result indication signal is in logic state 1 or 0. When the test result indication signal is 1, it indicates that the circuit under test 200 fails. When the test result indication signal is 0, it indicates that the circuit under test 200 is valid. Of course, the test result indication signal can also be represented by other types of signals, all of which are within the protection scope of this embodiment.

[0084] Step S400: Invert the phase of the delayed original test vector by 180 degrees to generate an inverted test vector, perform a logical AND operation on the inverted test vector and the test data signal, and output a logic state indication value, which is used to indicate the logic state of the test data signal when the circuit under test 200 fails.

[0085] like Figure 4 As shown, after the original test vector and the test data signal undergo the above logic operation, the obtained logic state indication value may include a logic state of 1 or 0.

[0086] Step S500: According to the test result indication signal, output one of a valid test result and a logic state indication value for indicating the circuit under test 200.

[0087] like Figure 4 As shown, when the test result indication signal is 0, a valid test signal is output, and the valid test signal can be represented by the high impedance state Hi-Z input in advance. When the test result indication signal is 1, a logic state indication value is output. If the output logic state indication value is finally selected, it means that the circuit under test 200 fails, and the logic state of the test data signal is obtained by detecting the output logic state indication signal. For example, when the logic state indication value is 0, the original test vector is 0, and the logic state of the test data signal is 1; when the logic state indication value is 1, the original test vector is 1, and the logic state of the test data signal is 0.

[0088] In one embodiment, the original test vector is input to the circuit under test 200 for testing, and before the test data signal is generated, the method further includes:

[0089] The original test vector is generated according to the test control signal generated by the built-in self-test controller 101 .

[0090] The built-in self-test controller 101 generates a test control signal, the test vector generator 102 receives the test control signal, and generates an original test vector according to the test control signal. Of course, the generation of the original test vector includes but is not limited to the above-mentioned method, and can also be other generation methods, all within the protection scope of this embodiment.

[0091] In one embodiment, the logic states of the test data signal and the delayed original test vector both include a high level and a low level, and the step of performing a logical XOR operation on the delayed original test vector and the test data signal to generate a test result indication signal includes:

[0092] When the logic state of the test data signal is different from the logic state of the delayed original test vector, the test result indication signal generated after the logical XOR operation is performed is at a high level.

[0093] For example, the logic state of the test data signal is 0, and the logic state of the delayed original test vector is 1, or the logic state of the test data signal is 1, and the logic state of the delayed original test vector is 0, and the test result indication signal generated after the XOR operation is 1, indicating that the circuit under test 200 has failed.

[0094] In one embodiment, when the test result indication signal is at a high level, the step of outputting a logic state indication value includes:

[0095] When the test result indication signal is at a high level and the output logic state indication value is at a high level, it indicates that the logic state of the test data signal is at a low level;

[0096] When the test result indication signal is at a high level and the output logic state indication value is at a low level, it indicates that the logic state of the test data signal is at a high level.

[0097] For example, the logic state of the test data signal is 0, the logic state of the original test vector is 1, and the test result indication signal is 1, indicating that the circuit under test 200 fails. According to the high-level test result indication signal, a logic state indication value that can indicate the logic state of the test data signal is output. The process of generating the logic state indication value is: the phase of the original test vector with a logic state of 1 is reversed by 180 degrees to generate an inverted test vector, and the logic state of the inverted test vector is 0. The inverted test vector with a logic state of 0 and the test data signal with a logic state of 0 are subjected to a logical AND operation, and the logic state of the output logic state indication value is 1. Therefore, it can be known that when the detected logic state indication value is 1, it indicates that the logic state of the test data signal is 0 and the logic state of the original test vector is 1. Similarly, when the detected logic state indication value is 0, it indicates that the logic state of the test data signal is 1 and the logic state of the original test vector is 0. The above method can be used to directly obtain the logic state of the test data signal and the logic state of the original test vector when the circuit under test 200 fails, so as to facilitate efficient judgment of the failure state.

[0098] In one embodiment, the logic states of the test data signal and the delayed original test vector both include a high level and a low level, and the step of performing a logical XOR operation on the delayed original test vector and the test data signal to generate a test result indication signal includes:

[0099] When the logic state of the test data signal is the same as the logic state of the delayed original test vector, the test result indication signal generated after the logical XOR operation is performed is represented as a low level.

[0100] For example, the logic state of the test data signal is 0, and the logic state of the original test vector after delay is 0, or the logic state of the test data signal is 1, and the logic state of the original test vector after delay is 1, and the test result indication signal generated after the XOR operation is 0, indicating that the circuit under test 200 is valid, that is, the circuit under test 200 can correctly read the original test vector.

[0101] In one implementation, when the test result indication signal is at a low level, the output valid test result is represented as a high impedance state.

[0102] For example, the high impedance state is pre-inputted, so that when the test result indication signal is 0, a valid test result of the high impedance state is directly output, indicating that the circuit under test 200 can correctly read the original test vector. Of course, when the test result indication signal is 0, other types of signals can also be output, all within the protection scope of this embodiment.

[0103] Embodiment 2

[0104] In another specific embodiment, a memory chip built-in self-test circuit device is provided, such as Figure 2 and Figure 3 As shown, it includes a test vector generation module 100, a circuit to be tested 200, a register 300, a comparison circuit 400 and a test result output module 500. The test vector generation module 100 includes a built-in self-test (BIST) controller 101 and a test vector (TPG) generator 102.

[0105] Among them, the built-in self-test controller 101 is used to generate a test control signal, the test vector generator 102 is used to generate an original test vector according to the test control signal, the input terminal 111 of the measurement vector generator is connected to the built-in self-test controller 101, and the output terminal 110 of the measurement vector generator is respectively connected to the circuit under test 200 and the register 300.

[0106] The circuit under test 200 is used to generate a test data signal according to an original test vector. The register 300 is used to delay the transmission time of the original test vector so that the delayed original test vector is output synchronously with the test data signal.

[0107] The comparison circuit 400 is connected to the circuit under test 200 and the register 300. The comparison circuit 400 includes an XOR gate 401, an inverter 402, and a NAND gate 403. The XOR gate 401 includes a first input terminal 411, a second input terminal 421, and a first signal output terminal 431. The first input terminal 411 is used to input the original test vector, the second input terminal 421 is used to receive the test data signal, and the first signal output terminal 411 is used to output a test result indication signal, which is used to indicate whether the circuit under test 200 is valid; the inverter 402 includes an inverter input terminal 412 and an inverter output terminal 422. The inverter input terminal 412 is used to receive the delayed original test vector, and the inverter output terminal 422 is used to output an inverted test vector generated by reversing the phase of the delayed original test vector by 180 degrees; the NAND gate 403 It includes a third input terminal 433, a fourth input terminal 443 and a second signal output terminal 413, the third input terminal 433 is used to receive a test data signal, the fourth input terminal 443 is connected to the inverter output terminal 422, the fourth input terminal 443 is used to receive an inverted test vector, and the second signal output terminal 413 is used to output a logic state indication value, and the logic state indication value is used to indicate the logic state of the test data signal when the circuit under test 200 fails; a test result output module 500, connected to the XOR gate 401 and the NAND gate 403, is used to select one of the valid test result and the logic state indication value for outputting according to the test result indication signal.

[0108] In one embodiment, the test result output module 500 is a multiplexer, which includes a selection control terminal 504, a first signal input terminal 501, a second signal input terminal 502 and a test result output terminal 503; the selection control terminal 504 is connected to the first signal output terminal 431 of the XOR gate 401, for receiving a test result indication signal; the first signal input terminal 501 is connected to the second signal output terminal 413 of the NAND gate 403, for receiving a logic state indication value; the second signal input terminal 502 is used to input a valid test result indicating that the circuit under test 200 is valid; the test result output terminal 503 is used to connect to the second signal input terminal 502 when the test result indication signal is at a low level, and output a valid test result; when the test result indication signal is at a high level, connect to the first signal input terminal 501, and output a logic state indication value.

[0109] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A memory chip built-in self-test method, characterized in that: include: Inputting the original test vector into the circuit under test to generate a test data signal; Inputting the original test vector into a register to delay the transmission time of the original test vector so that the original test vector is synchronized with the test data signal; Performing a logical exclusive OR operation on the delayed original test vector and the test data signal to generate a test result indication signal, wherein the test result indication signal is used to indicate whether the circuit to be tested is valid; Inverting the phase of the delayed original test vector by 180 degrees to generate an inverted test vector, performing a logic AND operation on the inverted test vector and the test data signal, and outputting a logic state indication value, wherein the logic state indication value is used to indicate the logic state of the test data signal when the circuit to be tested fails; According to the test result indication signal, one of the test result indicating that the circuit to be tested is valid and the logic state indication value is selectively output.

2. The memory chip built-in self-test method according to claim 1, wherein: Before inputting the original test vector into the circuit under test to generate the test data signal, it also includes: The original test vector is generated according to a test control signal generated by a built-in self-test controller.

3. The memory chip built-in self-test method according to claim 1, wherein: The logic states of the test data signal and the delayed original test vector both include a high level and a low level, and the step of performing a logical exclusive OR operation on the delayed original test vector and the test data signal to generate a test result indication signal includes: When the logic state of the test data signal is different from the logic state of the delayed original test vector, the test result indication signal generated after performing a logical XOR operation is at a high level.

4. The memory chip built-in self-test method according to claim 3, wherein: When the test result indication signal is at a high level, the step of outputting the logic state indication value comprises: When the test result indication signal is at a high level and the output logic state indication value is at a high level, it indicates that the logic state of the test data signal is at a low level; When the test result indication signal is at a high level and the output logic state indication value is at a low level, it indicates that the logic state of the test data signal is at a high level.

5. The memory chip built-in self-test method according to claim 1, wherein: The logic states of the test data signal and the delayed original test vector both include a high level and a low level, and the step of performing a logical exclusive OR operation on the delayed original test vector and the test data signal to generate a test result indication signal includes: When the logic state of the test data signal is the same as the logic state of the delayed original test vector, the test result indication signal generated after performing a logical XOR operation is represented as a low level.

6. The memory chip built-in self-test method according to claim 5, characterized in that: When the test result indication signal is at a low level, the output valid test result is represented as a high impedance state.

7. A memory chip built-in self-test circuit device, characterized in that: It includes a circuit to be tested, a register, a comparison circuit and a test result output module; The circuit to be tested is used to generate a test data signal according to an original test vector; The register is used to delay the transmission time of the original test vector so that the delayed original test vector is output synchronously with the test data signal; The comparison circuit is connected to the circuit to be tested and the register, and the comparison circuit includes an XOR gate, an inverter and a NAND gate; The XOR gate comprises a first input terminal, a second input terminal and a first signal output terminal, the first input terminal is used to input the original test vector after delay, the second input terminal is used to receive the test data signal, and the first signal output terminal is used to output a test result indication signal, and the test result indication signal is used to indicate whether the circuit to be tested is valid; The inverter comprises an inverter input end and an inverter output end, wherein the inverter input end is used to receive the delayed original test vector, and the inverter output end is used to output an inverted test vector generated by inverting the phase of the delayed original test vector by 180 degrees; The NAND gate comprises a third input terminal, a fourth input terminal and a second signal output terminal, the third input terminal is used to receive the test data signal, the fourth input terminal is connected to the inverter output terminal to receive the inverted test vector, and the second signal output terminal is used to output a logic state indication value, and the logic state indication value is used to indicate the logic state of the test data signal when the circuit to be tested fails; The test result output module is connected to the XOR gate and the NAND gate, and is used to selectively output one of a valid test result indicating that the circuit under test is valid and the logic state indication value according to the test result indication signal.

8. The memory chip built-in self-test circuit device as claimed in claim 7, characterized in that: It also includes a test vector generation module, the test vector generation module includes: Built-in self-test controller for generating test control signals; A test vector generator is used to generate the original test vector according to the test control signal, the input end of the test vector generator is connected to the built-in self-test controller, and the multiple output ends of the test vector generator are respectively connected to the circuit to be tested and the register.

9. The memory chip built-in self-test circuit device as claimed in claim 7, characterized in that: The test result output module is a multiplexer and includes a selection control terminal, a first signal input terminal, a second signal input terminal and a test result output terminal; The selection control terminal is connected to the first signal output terminal of the XOR gate, and is used to receive the test result indication signal; The first signal input terminal is connected to the second signal output terminal of the NAND gate, and is used to receive the logic state indication value; The second signal input terminal is used to input a valid test result indicating that the circuit to be tested is valid; The test result output terminal is used to connect to the second signal input terminal and output the valid test result when the test result indication signal is at a low level, and to connect to the first signal input terminal and output the logic state indication value when the test result indication signal is at a high level.

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