Storage device, semiconductor device, and method for manufacturing the same

Abstract

The present disclosure provides a storage device, a semiconductor device, and a method for manufacturing a semiconductor device. The manufacturing method includes: providing a first chip and a plurality of second chips, the first chip having a first pad, and each second chip having a second pad; stacking the second chips on the first chip, the second pads belonging to different second chips being arranged in a stepped manner with respect to the first pad, and the projections of the second pads belonging to any two adjacent second chips on the first chip partially overlapping; forming connection holes passing through the second chips, the connection holes exposing the first pad, the connection holes including a plurality of hole segments, each hole segment being located in a corresponding second chip, and any hole segment exposing a partial area of the second pad of the second chip where it is located; forming a conductor in the connection holes, and the first pad corresponding to the connection holes and each second pad being connected to the conductor. The manufacturing method of the present disclosure can simplify the process and reduce costs.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a storage device, a semiconductor device, and a method for manufacturing a semiconductor device. Background Art

[0002] With the development of semiconductor technologies, chip stacking technologies have been widely applied to various memories, such as DRAM (Dynamic Random Access Memory), etc. Currently, for multiple stacked chips, the TSV (Through Silicon Vias) technology is required to connect each chip with the shortest path. Specifically, in the prior art, generally, silicon channels need to be formed on each chip first, and conductive members are formed in the silicon channels, and then the chips are stacked, so that the conductive members in each silicon channel are connected, thereby connecting each chip.

[0003] However, performing the TSV process on each chip will make the entire manufacturing process time-consuming, with many processes and high costs.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a storage device, a semiconductor device, and a method for manufacturing a semiconductor device, which can simplify the process and reduce costs.

[0006] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, including:

[0007] providing a first chip and a plurality of second chips, the first chip having a first pad, and each of the second chips having a second pad;

[0008] stacking each of the second chips on the first chip, the second pads belonging to different second chips and the first pad being arranged in a stepped manner, and the projections of the second pads belonging to any two adjacent second chips on the first chip partially overlapping;

[0009] forming connection holes passing through each of the second chips, the connection holes exposing the first pad, the connection holes including a plurality of hole segments, each of the hole segments being correspondingly located in each of the second chips, and any one of the hole segments exposing a partial area of the second pad of the second chip where it is located;

[0010] A conductor is formed in the connection hole, and the first pad corresponding to the connection hole and each of the second pads are connected to the conductor.

[0011] In an exemplary embodiment of the present disclosure, the connection hole is formed by a single opening process.

[0012] In an exemplary embodiment of the present disclosure, forming the connection holes passing through each of the second chips includes:

[0013] Cover a photoresist layer on the second chip farthest from the first chip;

[0014] Expose and develop the photoresist layer to form a developed area. The projection of the developed area on the first chip coincides with the first pad, and a partial area of the second pad covered by the photoresist layer is exposed;

[0015] Etch from the developed area towards the first pad until the first pad is exposed;

[0016] Strip the photoresist layer.

[0017] In an exemplary embodiment of the present disclosure, forming the conductor in the connection hole includes:

[0018] Form an isolation layer on the inner wall of the connection hole. The isolation layer exposes the surface of the second pad away from the first chip and the first pad;

[0019] Form the conductor in the isolation layer. The conductor is connected to the areas of each of the second pads not covered by the isolation layer.

[0020] In an exemplary embodiment of the present disclosure, forming the isolation layer on the inner wall of the connection hole includes:

[0021] Form an isolation material layer in the connection hole. The isolation material layer covers the first pad and the areas of the second pads located in the connection hole;

[0022] Remove the isolation material layer on the first pad and the isolation material layer on the surface of the second pad away from the first chip.

[0023] In an exemplary embodiment of the present disclosure, forming the conductor in the isolation layer includes:

[0024] Cover a conductive layer on the second chip farthest from the first chip. The conductive layer fills the connection hole;

[0025] Remove the area of the conductive layer outside the connection hole.

[0026] In an exemplary embodiment of the present disclosure, the materials of the first pad and the second pad are metals.

[0027] In an exemplary embodiment of the present disclosure, the material of the first pad is any one of copper, aluminum, and tungsten, and the material of the second pad is any one of copper, aluminum, and tungsten.

[0028] In an exemplary embodiment of the present disclosure, the first chip includes:

[0029] A first substrate;

[0030] A first insulating layer disposed on the first substrate, and the first pad is embedded in a surface of the first insulating layer away from the first substrate;

[0031] The second chip includes:

[0032] A second substrate;

[0033] A second insulating layer disposed on a surface of the second substrate away from the first chip, and the second pad is embedded in a surface of the second insulating layer away from the second substrate;

[0034] The second substrate of the second chip closest to the first chip is disposed on a surface of the first insulating layer away from the first substrate, and the second substrates and the second insulating layers of the second chips are alternately stacked.

[0035] According to one aspect of the present disclosure, there is provided a semiconductor device, including:

[0036] A first chip having a first pad;

[0037] A plurality of second chips, each of the second chips having a second pad, the second chips are stacked on the first chip, the second pads belonging to different second chips are distributed in a stepped manner with respect to the first pad, and the projections of the second pads belonging to any two adjacent second chips on the first chip partially overlap;

[0038] Via holes passing through the second chips, the via holes exposing the first pad, the via holes including a plurality of hole segments, each of the hole segments is correspondingly located in each of the second chips, and a partial area of the second pad of the second chip where any one of the hole segments is located is exposed;

[0039] A conductor disposed in the via holes, and the first pad corresponding to the via holes and each of the second pads are connected to the conductor.

[0040] In an exemplary embodiment of the present disclosure, the semiconductor device further includes:

[0041] An isolation layer is disposed between the inner wall of the connection hole and the conductor, and the isolation layer exposes the surfaces of the first pad and the second pad that are away from the first chip.

[0042] In an exemplary embodiment of the present disclosure, the materials of the first pad and the second pad are metals.

[0043] In an exemplary embodiment of the present disclosure, the material of the first pad is any one of copper, aluminum, and tungsten, and the material of the second pad is any one of copper, aluminum, and tungsten.

[0044] In an exemplary embodiment of the present disclosure, the first chip includes:

[0045] A first substrate;

[0046] A first insulating layer is disposed on the first substrate, and the first pad is embedded in the surface of the first insulating layer away from the first substrate;

[0047] The second chip includes:

[0048] A second substrate;

[0049] A second insulating layer is disposed on the surface of the second substrate away from the first chip, and the second pad is embedded in the surface of the second insulating layer away from the second substrate;

[0050] The second substrate of the second chip closest to the first chip is disposed on the surface of the first insulating layer away from the first substrate, and the second substrates and the second insulating layers of the second chips are alternately stacked.

[0051] According to one aspect of the present disclosure, there is provided a storage device including the semiconductor device described in any one of the above.

[0052] In the method for manufacturing the semiconductor device of the present disclosure, the second chips can be first stacked on the first chip so that the first pads and the second pads belonging to different second chips are distributed in a stepped manner, and then connection holes are formed in the direction close to the first chip. Each hole segment of the connection hole exposes a partial area of the second pad of the second chip where it is located. Then, the second chips and the first chip are connected by a conductor. Compared with the existing scheme of separately opening holes for each chip, the number of hole-opening processes can be reduced, so that the entire manufacturing process can be simplified and the time consumption can be reduced, which is beneficial to reducing the manufacturing cost.

[0053] In the storage device and semiconductor device of the present disclosure, since the first pads and the second pads belonging to different second chips are arranged in a stepped manner, and the projections of the second pads belonging to two adjacent second chips on the first chip partially overlap. During manufacturing, the second chips can be stacked on the first chip, and then connection holes are formed in the direction close to the first chip. Each hole segment of the connection hole exposes a partial area of the second pad of the second chip where it is located, and then the second chips and the first chip are connected by a conductor. It is possible to avoid opening holes for each second chip separately, which is beneficial to reducing the number of hole-opening processes, simplifying the entire manufacturing process, reducing the time consumption, and lowering the manufacturing cost.

[0054] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0056] Figure 1 It is a flowchart of the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0057] Figure 2 It is a schematic diagram of the first chip in the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0058] Figure 3 It is a schematic diagram of the second chip in the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0059] Figure 4 It is a schematic diagram after completing step S120 in the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0060] Figure 5 It is a flowchart of step S130 in the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0061] Figure 6 It is a schematic diagram after completing step S1320 in the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0062] Figure 7 It is a schematic diagram after completing step S1340 in the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.

[0063] Figure 8Flow chart of step S140 in the manufacturing method of the semiconductor device according to the present disclosure implementation mode.

[0064] Figure 9 Flow chart of step S1410 in the manufacturing method of the semiconductor device according to the present disclosure implementation mode.

[0065] Figure 10 Schematic diagram after completing step S14110 in the manufacturing method of the semiconductor device according to the present disclosure implementation mode.

[0066] Figure 11 Schematic diagram after completing step S14120 in the manufacturing method of the semiconductor device according to the present disclosure implementation mode.

[0067] Figure 12 Flow chart of step S1420 in the manufacturing method of the semiconductor device according to the present disclosure implementation mode.

[0068] Figure 13 Schematic diagram after completing step S14210 in the manufacturing method of the semiconductor device according to the present disclosure implementation mode.

[0069] Figure 14 Schematic diagram of an implementation mode of the semiconductor device according to the present disclosure.

[0070] Figure 15 Schematic diagram of another implementation mode of the semiconductor device according to the present disclosure.

[0071] Figure 16 Schematic diagram of still another implementation mode of the semiconductor device according to the present disclosure.

[0072] In the figure: 1, the first chip; 11, the first pad; 12, the first substrate; 13, the first insulating layer; 2, the second chip; 21, the second pad; 22, the second substrate; 23, the second insulating layer; 3, the via hole; 4, the conductor; 5, the isolation layer; 100, the photoresist layer; 101, the developed area; 200, the conductive layer. Detailed implementation mode

[0073] Now, the exemplary implementation modes will be described more comprehensively with reference to the accompanying drawings. However, the exemplary implementation modes can be implemented in various forms and should not be construed as limited to the implementation modes set forth herein; rather, these implementation modes are provided so that the present invention will be complete and comprehensive, and the concept of the exemplary implementation modes will be fully conveyed to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0074] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is flipped so that it is upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0075] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second" are used only as labels and are not a limitation on the quantity of their objects.

[0076] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, which can be used to manufacture a semiconductor device. The semiconductor device may be a stacked chip, such as a DRAM, etc., and will not be listed one by one here.

[0077] As Figure 1 shown, the manufacturing method of the embodiments of the present disclosure may include:

[0078] Step S110: Provide a first chip and a plurality of second chips. The first chip has a first pad, and each of the second chips has a second pad;

[0079] Step S120: Stack each of the second chips on the first chip. The second pads of each of the second chips are arranged in a stepped manner with the first pad, and the projection parts of the second pads belonging to adjacent second chips on the first chip overlap;

[0080] Step S130: Form connection holes passing through each of the second chips. The connection holes expose the first pad. The connection holes include a plurality of hole segments. Each of the hole segments is correspondingly located in each of the second chips, and any one of the hole segments exposes a partial area of the second pad of the second chip where it is located;

[0081] Step S140: Form a conductor in the connection holes. The first pad corresponding to the connection holes and each of the second pads are connected to the conductor.

[0082] In the method for manufacturing a semiconductor device according to the present disclosure, first, each second chip is stacked on the first chip, such that the first pads and the second pads belonging to different second chips are arranged in a stepped manner. Then, connection holes are formed in a direction approaching the first chip, and partial regions of the second pads of the second chips where the respective hole segments of the connection holes are located are exposed. Subsequently, the respective second chips and the first chip are connected by a conductor. Compared with the existing solution where holes are opened for each chip separately, the number of hole-opening processes can be reduced, thereby simplifying the entire manufacturing process and reducing the time consumption, which is beneficial to reducing the manufacturing cost.

[0083] The following will detail each step of the manufacturing method according to the embodiments of the present disclosure:

[0084] As Figure 2 and Figure 3 shown, in step S110, a first chip 1 and second chips 2 are provided. The number of the first chips 1 can be one, and it has first pads 11, and the first pads 11 can be connected to the circuits on the first chip 1.

[0085] For example, as Figure 2 shown, the first chip 1 may include first pads 11, a first substrate 12, and a first insulating layer 13, where:

[0086] The material of the first substrate 12 can be silicon or other semiconductor materials, and its shape and size are not particularly limited herein.

[0087] The first insulating layer 13 can be disposed on the surface of the first substrate 12, and its material can be silicon oxide, silicon nitride, etc., or a mixture of multiple insulating materials.

[0088] The first pads 11 can be disposed on the surface of the first insulating layer 13 away from the first substrate 12, and the first pads 11 can be embedded in the first insulating layer 13 and be flush with the surface of the first insulating layer 13 away from the first substrate 12. At the same time, the material of the first pads 11 can be a metal, such as copper, aluminum, or tungsten, etc. Of course, it can also be other metal conductive materials, which will not be listed one by one here. The shape of the first pads 11 can be rectangular, and of course, it can also be circular or other shapes. In addition, the number of the first pads 11 can be one or more.

[0089] As Figure 3 shown, the number of the second chips 2 can be multiple, and each second chip 2 has second pads 21. For example, the second chip 2 may include second pads 21, a second substrate 22, and a second insulating layer 23, where:

[0090] The structure and material of the second substrate 22 can be the same as those of the first substrate 12.

[0091] The second insulating layer 23 may be disposed on the surface of the second substrate 22, and the material of the second insulating layer 23 may be the same as that of the first insulating layer 13.

[0092] The second pad 21 may be disposed on the surface of the second insulating layer 23 away from the second substrate 22, and the second pad 21 may be embedded in the second insulating layer 23 and flush with the surface of the second insulating layer 23 away from the second substrate 22. At the same time, the material of the second pad 21 may be a metal, such as copper, aluminum or tungsten. Of course, it may also be other metal materials, which will not be enumerated one by one here. The shape of the second pad 21 may be rectangular, circular or other shapes. The number of second pads 21 of each second chip 2 may be the same as the number of first pads 11 of the first chip 1.

[0093] As Figure 4 shown, in step S120, the second chips 2 are stacked on the first chip 1, and the second pads 21 belonging to different second chips 2 and the first pads 11 are distributed in a stepped manner, and the projections of the second pads 21 belonging to adjacent second chips 2 on the first chip 1 partially overlap.

[0094] One second chip 2 may be disposed on the first chip 1, and then other second chips 2 are stacked layer by layer on this second chip 2 to form a stacked structure. At the same time, during the successive stacking process, the adjacent first chip 1 and second chip 2 may be bonded, and the adjacent second chips 2 may be bonded. For example, the second insulating layers 23 and the second substrates 22 are alternately stacked on the surface of the first insulating layer 13 away from the first substrate 12, and the second substrate 22 of the second chip 2 closest to the first chip 1 is bonded to the surface of the first insulating layer 13 away from the first substrate 12; among two adjacent second chips 2, the second insulating layer 23 of the lower second chip 2 is bonded to the second substrate 22 of the upper second chip 2.

[0095] Of course, in another embodiment, the shapes and sizes of the second chips 2 and the first chip 1 are the same, but the positions of the second pads 21 on each second chip 2 are different. The second chips 2 may be disposed opposite to the first chip 1, that is, the edges are flush. Since the positions of the second pads 21 belonging to different second chips 2 are different, they may also be distributed in a stepped manner, so as to finally form Figure 15 the semiconductor device shown.

[0096] If each second chip 2 has a plurality of second pads 21 and the first chip 1 has a plurality of first pads 11, multiple sets of stepped distributed pads may be formed. The formation method of the stepped distribution may refer to the above, and will not be elaborated here. For any two sets of stepped distributed pads, they may be arranged in a mirror image, that is, Figure 16 the semiconductor device shown in. Of course, any two sets of stepped distributed pads may also be offset in the same direction.

[0097] AsFigure 1 As shown, in step S130, connection holes 3 are formed to sequentially pass through each second chip 2. The connection holes 3 expose the first pads 11. The connection holes 3 include a plurality of hole segments, and each hole segment is correspondingly located within each second chip 2, and any one hole segment exposes a partial area of the second pad 21 of the second chip 2 where it is located.

[0098] The connection holes 3 can be formed by a single opening process, such as by a single etching process. Of course, the connection holes 3 can also be formed by multiple opening processes, but the number of opening processes can be less than the number of second chips 2. Thus, compared with the method of opening holes for each chip in the prior art, the number of opening processes can be reduced and the process can be simplified.

[0099] For example, as Figure 5 shown, step S130 may include steps S1310 - S1340, where:

[0100] In step S1310, a photoresist layer 100 is covered on a second chip 2 that is farthest from the first chip 1.

[0101] The photoresist layer 100 can be a positive photoresist or a negative photoresist, and no special limitation is made here.

[0102] As Figure 6 shown, in step S1320, the photoresist layer 100 is exposed and developed to form a developed area 101. The projection of the developed area 101 on the first chip 1 coincides with the first pad 11, and a partial area of the second pad 21 covered by the photoresist layer 100 is exposed.

[0103] The photoresist layer 100 can be exposed through a mask and developed to form a developed area 101. The developed area 101 faces the first chip 1, and the projection of the developed area 101 on the first chip 1 coincides with the first pad 11. At the same time, since the second pads 21 and the first pads 11 are distributed in a stepped manner, the developed area 101 can expose a partial area of the second pad 21 covered by the photoresist layer 100, that is, a partial area of the second pad 21 of the second chip 2 that is farthest from the first chip 1 is exposed.

[0104] In step S1330, etching is performed towards the first pad 11 within the developed area 101 until the first pad 11 is exposed.

[0105] The area of the second chip 2 exposed in the development area 101 can be etched by dry etching. The etched area gradually extends towards the first pad 11 opposite to the development area 101 until the first pad 11 is exposed, so as to form the connection holes 3 passing through each perforation 211 through one etching. The materials of the first pad 11 and the second pad 21 can both be copper. When performing dry etching, the copper will not be removed, but only the materials in the area opposite to the development area 101 will be etched. Of course, other etching methods can also be used as long as the above-mentioned connection holes 3 can be formed, and they will not be listed one by one here.

[0106] The connection holes 3 formed by etching may include multiple hole segments. Each hole segment is located in each second chip 2 one by one, and a partial area of the second pad 21 of the second chip 2 where each hole segment is located is exposed. Since the second pad 21 and the first pad 11 are distributed in a stepped manner and each pad will not be etched during the above etching process, the sizes of the hole segments are different from each other and gradually decrease towards the exposed first pad 11, that is, the hole diameter of the connection holes 3 gradually shrinks towards the first pad 11. The inner wall on the side of the connection holes 3 close to the second pad 21 is a stepped structure, and the inner wall on the other side is a linearly extending structure.

[0107] As Figure 7 shown, in step S1340, the photoresist layer 100 is peeled off.

[0108] The remaining photoresist layer 100 can be removed by a stripping solution, or the photoresist layer 100 can also be removed by an ashing process or other processes, and no special limitation is made here.

[0109] As Figure 1 shown, in step S140, a conductor 4 is formed in the connection holes 3, and the first pad 11 corresponding to the connection holes 3 and each second pad 21 are connected to the conductor 4.

[0110] The material of the conductor 4 can be a metal, such as copper, aluminum or tungsten. Of course, it can also be other metal materials, which will not be listed one by one here. In order to make the conductivity of the conductor 4 consistent with that of the first pad 11 and the second pad 21, the conductor 4 and the first pad 11 and the second pad 21 can adopt the same material, such as copper. Through the conductor 4, the first pad 11 and each second pad 21 distributed in a stepped manner with it can be connected, so as to realize the connection between the first chip 1 and each second chip 2.

[0111] For example, as Figure 8 shown, step S140 may include step S1410 and step S1420, where:

[0112] In step S1410, an isolation layer 5 is formed on the inner wall of the connection holes 3, and the isolation layer 5 exposes the surfaces of the first pad 11 and the second pad 21 away from the first chip 1.

[0113] The isolation layer 5 can be a single-layer structure, and its material can be silicon oxide, silicon nitride or other insulating materials. Of course, the isolation layer 5 can also be a multi-layer structure. For example, the isolation layer 5 can include an insulating material layer and a barrier layer. Among them, the insulating material layer is formed on the inner wall of the connection hole 3. The barrier layer can be formed on the inner wall of the insulating material layer, which can prevent the conductor 4 from diffusing outward, so as to improve the electrical reliability and stability of the chip. The material of the barrier layer can be determined according to the material of the conductor 4. For example, if the material of the conductor 4 is copper, the material of the barrier layer can be titanium, tantalum, or other materials, as long as it can play a blocking role.

[0114] In one embodiment, the isolation layer 5 is a single-layer structure, as Figure 9 shown, step S1410 may include step S14110 and step S14120, where:

[0115] As Figure 10 shown, in step S14110, an isolation material layer is formed in the connection hole 3, and the isolation material layer covers the regions of the first pad 11 and the second pad 21 located in the connection hole 3.

[0116] The material of the isolation material layer can be silicon oxide, and the isolation material layer can be directly deposited on the second insulating layer 23 of the second chip 2 farthest from the first chip 1. The isolation material layer falls into the connection hole 3 and covers the regions of the first pad 11 and the second pad 21 located in the connection hole 3, so that the inner wall of the connection hole 3 is completely covered.

[0117] As Figure 11 shown, in step S14120, the isolation material layer on the first pad 11 and the isolation material layer on the surface of the second pad 21 away from the first chip 1 are removed.

[0118] The isolation material layer covering the region on the first pad 11 can be removed by an etching solution, so as to at least expose part of the first pad 11 for the conductor 4 to be connected to the first pad 11. At the same time, the isolation material layer on the surface of each second pad 21 away from the first chip 1 can be removed, so as to expose the surface of the second pad 21 away from the first chip 1 in the connection hole 3, which is convenient for the conductor 4 to be connected to each second pad 21.

[0119] As Figure 8 shown, in step S1420, a conductor 4 is formed in the isolation layer 5, and the conductor 4 is connected to the regions of the second pads 21 not covered by the isolation layer 5.

[0120] A conductive material can be filled in the isolation layer 5, and the conductive material covers the exposed regions of the first pad 11 and each second pad 21, so as to obtain the conductor 4, and the shape of the conductor 4 matches the shape of the connection hole 3. For example, as Figure 12As shown, step S1420 may include step S14210 and step S14220, where:

[0121] As Figure 13 shown, in step S14210, a conductive layer 200 is covered on the second chip 2 that is the farthest from the first chip 1, and the conductive layer 200 fills the connection hole 3.

[0122] The conductive layer 200 may be formed by sputtering or electroplating, but is not limited thereto. It may also be formed by evaporation or other processes, which are not specifically limited herein. The portion of the conductive layer 200 filled in the connection hole 3 may cover the exposed areas of the first pad 11 and each second pad 21, so that the first pad 11 and each second pad 21 are connected through the conductive layer 200.

[0123] As Figure 12 shown, in step S14220, the area of the conductive layer 200 located outside the connection hole 3 is removed.

[0124] The area of the conductive layer 200 located outside the connection hole 3 may be removed by chemical mechanical polishing or other processes. The area inside the connection hole 3 is the conductor 4, but the conductor 4 should be connected to the second pad 21 of the second chip 2 that is the farthest from the first chip 1.

[0125] The embodiment of the present disclosure also provides a semiconductor device. As Figure 14 shown, the semiconductor device may include a first chip 1, a second chip 2, a connection hole 3, and a conductor 4, where:

[0126] The first chip 1 has a first pad 11;

[0127] The number of the second chips 2 is multiple. Each second chip 2 has a second pad 21. The second chips 2 are stacked on the first chip 1. The second pads 21 belonging to different second chips 2 are arranged in a stepped manner with respect to the first pad 11, and the projected portions of the second pads 21 belonging to any two adjacent second chips 2 on the first chip 1 overlap.

[0128] The connection hole 3 passes through each second chip 2, exposes the first pad 11, and includes a plurality of hole segments. Each hole segment is correspondingly located in each second chip 2, and the portion of any hole segment that exposes the second pad 21 of its corresponding second chip 2 is a partial area.

[0129] The conductor 4 is disposed in the connection hole 3, and the first pad 11 corresponding to the connection hole 3 and each second pad 21 are connected to the conductor 4.

[0130] As Figure 15 shown, Figure 15 This is another embodiment of the semiconductor device of the present disclosure. As Figure 16 shown,Figure 16 This is yet another embodiment of the semiconductor device disclosed herein.

[0131] In the semiconductor device of the embodiment of the present disclosure, since the second pads 21 of different second chips 2 and the first chip 1 are arranged in a stepped manner, and the projected portions of the second pads 21 of two adjacent second chips 2 on the first chip 1 overlap. During manufacturing, each second chip 2 can be stacked on the first chip 1, and then connection holes 3 are formed in the direction close to the first chip 1. Each hole segment of the connection holes 3 exposes a partial area of the second pad 21 of the corresponding second chip 2, and then each second chip 2 and the first chip 1 are connected by a conductor 4. It is possible to avoid opening holes for each second chip 2 separately, which is beneficial to reducing the number of hole-opening processes, simplifying the entire manufacturing process, reducing the time consumption, and lowering the manufacturing cost.

[0132] The semiconductor device of the embodiment of the present disclosure may further include an isolation layer 5. The isolation layer 5 can be disposed between the inner wall of the connection hole 3 and the conductor 4, and the isolation layer 5 exposes the surfaces of the first pad 11 and the second pad 21 away from the first chip 1.

[0133] Details of the components of the semiconductor device of the embodiment of the present disclosure have been described in detail in the steps of the corresponding manufacturing method, and will not be repeated here.

[0134] The embodiment of the present disclosure also provides a storage device, which may include the semiconductor device of the above embodiment. For example, the storage device may be a memory such as a DRAM or a NAND flash memory.

[0135] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, comprising: providing a first chip and a plurality of second chips, the first chip having a first pad, and each of the second chips having a second pad; stacking each of the second chips on the first chip, with a dislocation at the edge between any two adjacent second chips, and also having the dislocation at the edge between the first chip and an adjacent second chip; the second pads belonging to different second chips and the first pad are arranged in a stepped manner, and the projections of the second pads belonging to any two adjacent second chips on the first chip partially overlap, and the projection of any one of the second pads on the first chip partially overlaps with the first pad; covering a photoresist layer on the second chip farthest from the first chip; exposing and developing the photoresist layer to form a developed area, the projection of the developed area on the first chip coincides with the first pad, and a partial area of the second pad covered by the photoresist layer is exposed; etching from the developed area towards the first pad until the first pad is exposed; stripping the photoresist layer to form a connection hole passing through each of the second chips, the connection hole exposing the first pad, the connection hole including a plurality of hole segments, each of the hole segments corresponding to and located in each of the second chips, and any one of the hole segments exposing a partial area of the second pad of the second chip where it is located; forming a conductor in the connection hole, and the first pad corresponding to the connection hole and each of the second pads are connected to the conductor.

2. The manufacturing method according to claim 1, characterized in that, the connection hole is formed by a single opening process.

3. The manufacturing method according to claim 1, characterized in that, forming a conductor in the connection hole includes: forming an isolation layer on the inner wall of the connection hole, the isolation layer exposing the surface of the second pad away from the first chip and the first pad; forming the conductor in the isolation layer, and the conductor is connected to the areas of the second pads not covered by the isolation layer.

4. The manufacturing method according to claim 3, characterized in that, forming an isolation layer on the inner wall of the connection hole includes: forming an isolation material layer in the connection hole, the isolation material layer covering the first pad and the areas of the second pads located in the connection hole; removing the isolation material layer on the first pad and the isolation material layer on the surface of the second pad away from the first chip.

5. The manufacturing method according to claim 3, characterized in that, forming the conductor in the isolation layer includes: covering a conductive layer on the second chip farthest from the first chip, the conductive layer filling the connection hole; removing the area of the conductive layer outside the connection hole.

6. The manufacturing method according to any one of claims 1-5, characterized in that, the materials of the first pad and the second pad are metals.

7. The manufacturing method according to claim 6, characterized in that, the material of the first pad is any one of copper, aluminum and tungsten, and the material of the second pad is any one of copper, aluminum and tungsten.

8. The manufacturing method according to any one of claims 1-5, characterized in that, the first chip includes: a first substrate; a first insulating layer disposed on the first substrate, and the first pad is embedded in a surface of the first insulating layer away from the first substrate; the second chip includes: a second substrate; a second insulating layer disposed on a surface of the second substrate away from the first chip, and the second pad is embedded in a surface of the second insulating layer away from the second substrate; the second substrate of the second chip closest to the first chip is disposed on the surface of the first insulating layer away from the first substrate, and the second substrates and the second insulating layers of the second chips are alternately stacked.

9. A semiconductor device, characterized in that, it includes: a first chip having a first pad, and the first chip further includes: a first substrate and a first insulating layer, the first insulating layer is disposed on the first substrate, and the first pad is embedded in a surface of the first insulating layer away from the first substrate; a plurality of second chips, each of the second chips having a second pad, and each of the second chips includes: a second substrate and a second insulating layer, the second insulating layer is disposed on a surface of the second substrate away from the first chip, and the second pad is embedded in a surface of the second insulating layer away from the second substrate; each of the second chips is stacked on the first chip, and there are dislocations at the edges of any two adjacent second chips, and there are also the dislocations at the edge of the first chip and the adjacent second chip; the second pads belonging to different second chips and the first pad are arranged in a stepped manner, and the projections of the second pads belonging to any two adjacent second chips on the first chip partially overlap, and the projection of any second pad on the first chip partially overlaps with the first pad; a connection hole passing through each of the second chips, the connection hole exposing the first pad, the connection hole including a plurality of hole segments, each of the hole segments corresponding to one of the second chips, and a partial area of the second pad of the second chip where any of the hole segments is located is exposed; a conductor disposed in the connection hole, and the first pad corresponding to the connection hole and each of the second pads are connected to the conductor.

10. The semiconductor device according to claim 9, characterized in that, the semiconductor device further includes: an isolation layer disposed between the inner wall of the connection hole and the conductor, and the isolation layer exposes the surfaces of the first pad and the second pad away from the first chip.

11. The semiconductor device according to claim 10, characterized in that, the materials of the first pad and the second pad are metals.

12. The semiconductor device according to claim 11, characterized in that, the material of the first pad is any one of copper, aluminum and tungsten, and the material of the second pad is any one of copper, aluminum and tungsten.

13. The semiconductor device according to claim 9, characterized in that, The second substrate of the second chip closest to the first chip is disposed on the surface of the first insulating layer away from the first substrate, and the second substrates and the second insulating layers of the second chips are alternately stacked.

14. A storage device, characterized in that it includes the semiconductor device according to any one of claims 9-13.

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