Substrate panel structure and manufacturing process

Abstract

A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is positioned between the sub-panels.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a substrate panel structure and a manufacturing process, and more particularly, to a substrate panel structure including a plurality of sub-panels, and a method of manufacturing the substrate panel structure. BACKGROUND

[0002] In electronic devices, functional improvements and size reductions can be achieved by changing their materials or by changing their structural designs. When the materials of electronic devices are changed, the settings or parameters of production equipment and manufacturing methods must be modified accordingly, which is more complicated and expensive than simply adjusting their structural designs. Recently, one of the most effective ways to improve the functionality of electronic devices and reduce the size of electronic devices is achieved by structural designs with reduced line width / line space (L / S). SUMMARY

[0003] In some embodiments, according to an aspect, a substrate panel structure includes a plurality of sub-panels and dielectric portions. Each of the sub-panels includes a plurality of substrate units. The dielectric portions are located between the sub-panels.

[0004] In some embodiments, according to another aspect, a manufacturing process includes: (a) providing a plurality of intermediate panels, each intermediate panel including a circuit structure, wherein each of the intermediate panels includes a plurality of panel units, and the intermediate panels are separate and spaced apart from each other; (b) providing a dielectric material to form a plurality of first dielectric layers and dielectric portions, wherein each of the first dielectric layers is on a respective one of the intermediate panels, and the dielectric portions are located between and connecting the dielectric layers; and (c) forming a plurality of redistribution layers on the first dielectric layers, wherein each of the redistribution layers is connected to a respective one of the circuit structures of the intermediate panels. BRIEF DESCRIPTION OF DRAWINGS

[0005] When read with the accompanying Figure 1 Aspects of some embodiments of the present disclosure can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that the various structures can not be drawn to scale, and the dimensions of the various structures can be arbitrarily increased or decreased for the clarity of discussion.

[0006] Figure 1FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0007] Figure 2 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0008] Figure 3 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application. Figure 2 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0009] Figure 4 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0010] Figure 5 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0011] Figure 6 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0012] Figure 7 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0013] Figure 8 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0014] Figure 9 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0015] Figure 10 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0016] Figure 11 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0017] Figure 12 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0018] Figure 13 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0019] Figure 14 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0020] Figure 15 FIG. 1 is a top view of an example of a substrate panel structure according to some embodiments of the application.

[0021] Figure 16 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the application.

[0022] Figure 17 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the application.

[0023] Figure 18 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the application.

[0024] Figure 19 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the application.

[0025] Figure 20 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0026] Figure 21 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0027] Figure 22 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0028] Figure 23 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0029] Figure 24 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0030] Figure 25 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0031] Figure 26 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0032] Figure 27 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0033] Figure 28 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0034] Figure 29 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0035] Figure 30 One or more stages of an example of a manufacturing process are illustrated according to some embodiments of the application.

[0036] Figure 31 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0037] Figure 32 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0038] Figure 33 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0039] Figure 34 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0040] Figure 35 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0041] Figure 36 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0042] Figure 37 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0043] Figure 38 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0044] Figure 39 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0045] Figure 40 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0046] Figure 41 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0047] Figure 42 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0048] Figure 43 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0049] Figure 44 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0050] Figure 45 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0051] Figure 46 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0052] Figure 47 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0053] Figure 48 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0054] Figure 49 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0055] Figure 50 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0056] Figure 51 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0057] Figure 52 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0058] Figure 53 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0059] Figure 54 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0060] Figure 55 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0061] Figure 56 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0062] Figure 57 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0063] Figure 58 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0064] Figure 59 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated.

[0065] Figure 60 According to some embodiments of the application one or more stages of an example of a manufacturing process are illustrated. DETAILED DESCRIPTION

[0066] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of the present application will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0067] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to provide a thorough description of aspects of the application. These are simply examples and are not intended to be limiting. For example, examples in which a first feature is formed over or on a second feature as described below can include embodiments in which the first and second features are formed or disposed in direct contact with each other, and can also include embodiments in which additional features can be formed or disposed between the first and second features such that the first and second features can not be in direct contact. Additionally, the present application can refer to reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not itself serve as indication of a relationship between the various embodiments and / or configurations discussed.

[0068] In the semiconductor-related industry, as the line width / line space (L / S) of a substrate panel gradually decreases, the precision of the substrate panel product is challenged. Manufacturing tolerances, including warpage caused by material differences and errors caused by manufacturing machines, usually occur in each single layer of the substrate panel. For example, when the substrate panel includes three layers, the total tolerance will be the sum of the tolerances in the first, second, and third layers. That is, as the amount of layers (including protective layers) of the substrate panel increases, the total tolerance of the substrate panel accumulates.

[0069] Notably, in the same layer of the substrate panel, the tolerance, which can be expressed as a value of pattern shift, is different between different locations. The value of pattern shift can be defined as the distance between the actual location of a pattern and the predetermined location of the pattern. Generally, the value of pattern shift is relatively small at locations close to the center (e.g., the centroid) of the substrate panel, and is relatively large at locations far from the center. The value of pattern shift at a particular location is proportional to the distance between the particular location and the center. Thus, the maximum value of pattern shift occurs at the edge of the substrate panel, and can increase as the size of the substrate panel increases. For example, in a comparative substrate panel having a single circuit layer with an area of 450 mm*450 mm and an L / S of 2 pm / 2 pm, the value of pattern shift measured at the edge of the substrate panel is at least 3 pm to 5 pm. In addition to the amount of pattern shift, the warpage of the substrate panel also increases as the size of the substrate panel increases. Due to the pattern shift and warpage of the substrate panel, semiconductor dies cannot be precisely mounted onto the substrate.

[0070] To address at least the above concerns, embodiments of the present disclosure provide a substrate panel structure including a plurality of sub-panels. At least portions of each of the sub-panels can be formed separately and then combined into the substrate panel structure. For example, one or more circuits of the sub-panels can be formed separately at a relatively small scale, and thus a maximum value of pattern shift of the substrate panel structure can be reduced.

[0071] Figure 1 A top view of an example of a substrate structure 1' according to some embodiments of the present disclosure is illustrated. The substrate panel structure 1' includes a plurality of sub-panels 2' and a dielectric portion 14' between the sub-panels 2'. Each of the sub-panels 2' includes a plurality of substrate units 20'. The sub-panels 2' are arranged in an "m*n" manner, and "m" and "n" are integers equal to or greater than 2. For example, as shown in Figure 1 The substrate panel structure 1' includes 2*2 sub-panels 2'. However, the number of sub-panels 2' in the substrate panel 1' can be greater than 2*2, and "m" and "n" can not be equal to each other. Similarly, the substrate units 20' of the sub-panels 2' can be arranged in an "o*p" manner, where "o" and "p" are integers, and at least one of "o" and "p" is greater than 1. For example, as shown in Figure 1 Each of the sub-panels 2' includes 5*5 substrate units 20'. In some embodiments, each of the sub-panels 2' has a size less than 500mm*500mm. That is, each side edge of the sub-panels 2' can be shorter than 500mm, such as shorter than 400mm, shorter than 300mm, or shorter than 200mm. In some embodiments, all of the sub-panels 2' are known good sub-panels.

[0072] Figure 2 A top view of an example of a substrate panel structure 1 according to some embodiments of the present disclosure is illustrated. Figure 3 A cross-sectional view taken along line 3-3 of the substrate panel structure 1 shown in Figure 2 Similar to the substrate panel structure 1' shown in Figure 1 The substrate panel structure 1 also includes a plurality of sub-panels 2 and a dielectric portion 14. The dielectric portion 14 is between and can surround the sub-panels 2. Each of the sub-panels 2 includes a plurality of substrate units 20. Each of the substrate units 20 corresponds to one package unit, such as the package unit 7 shown in Figure 12 However, for simplicity and clarity of explanation, each of the sub-panels 2 shown in Figure 2 and 3 Each of the sub-panels 2 shown in Figure 1 Each of the sub-panels 2 shown in

[0073] The sub-panels 2 can include a first sub-panel 2a and a second sub-panel 2b, and a gap “g” is formed between two adjacent ones of the sub-panels 2 (e.g., the first sub-panel 2a and the second sub-panel 2b). As shown in Figure 2 As can be seen in

[0074] Each of the substrate units 20 in the sub-panels 2 is proximate to one another. For example, two adjacent ones of the substrate units 20 in the first sub-panel 2a can be physically connected to one another, or can be separated by a cutting line or a saw street. That is, the substrate units 20 in the first sub-panel 2a can be defined by the cutting line or the saw street. After a plurality of semiconductor dies are mounted onto each of the sub-panels 2 and / or packages are formed on each of the sub-panels 2, these substrate units 20 can be separated by a singulating process along the cutting line or the saw street to form a plurality of package units (e.g., the package units 7 shown in Figure 12 As shown in Figure 2 and 3 As can be seen in

[0075] Referring to Figure 3 , each of the sub-panels 2 has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least a portion of the side surface 23 is an imaginary surface or an imaginary plane. The side surface 23 can be an open cutting line or a saw street for separating the sub-panels 2 from the substrate panel structure 1. As shown in Figure 3As shown, the first surface 21 is the upper surface, and the second surface 22 is the lower surface. Each of the sub-panels 2 includes a first dielectric layer 3, a redistribution layer 4, a protective layer 25, at least one solder connector 26, a circuit structure 5, and a second dielectric layer 6. Similarly, each of the substrate units 20 may include at least a portion of the first dielectric layer 3, at least a portion of the redistribution layer 4, at least a portion of the protective layer 25, at least one solder connector 26, at least a portion of the circuit structure 5, and at least a portion of the second dielectric layer 6. For illustrative purposes, Figure 2 The components of substrate unit 20 are not shown in the image.

[0076] Figure 3 A first sub-panel 2a and a second sub-panel 2b are shown that are substantially identical to each other. However, the first sub-panel 2a and the second sub-panel 2b may be different from each other. For example, the components, arrangement, material, size, and position relative to the dielectric portion 14 of the first sub-panel 2a may be different from those of the second sub-panel 2b.

[0077] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. For example... Figure 3 As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The first dielectric layer 3 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 may comprise, or be formed from, a cured photoimageable dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The first dielectric layer 3 defines at least one via 30 extending through the first dielectric layer 3 and between the first surface 31 and the second surface 32. In some embodiments, the thickness of the first dielectric layer 3 may be from about 3 μm to about 20 μm, preferably from about 3 μm to about 15 μm. The material of the first dielectric layer 3 in the first sub-panel 2a may be substantially the same as the material of the dielectric layer 3 in the second sub-panel 2b. However, the thickness of the first dielectric layer 3 in the first sub-panel 2a may be substantially the same as or slightly different from the thickness of the dielectric layer 3 in the second sub-panel 2b.

[0078] A redistribution layer 4 is on the first dielectric layer 3. The redistribution layer 4 can be on the second surface 32 of the first dielectric layer 3 and in the via 30. The redistribution layer 4 can include a seed layer 41 on the first dielectric layer 3, and a conductive layer 42 on the seed layer 41. The material of the seed layer 41 can be, for example, titanium or copper. In some embodiments, the seed layer 41 can include a titanium layer and a copper layer. The material of the conductive layer 42 can be, for example, a conductive metal such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 can be omitted, and the conductive layer 42 can directly contact the first dielectric layer 3. The redistribution layer 4 can include at least one conductive via 43 in the via 30 of the first dielectric layer 3, and at least one conductive pad 44 on the second surface 32 of the first dielectric layer 3. In some embodiments, the redistribution layer 4 can further include at least one trace (not shown). In some embodiments, the line width / line spacing (L / S) of the redistribution layer 4 can be equal to or greater than 10 pm / 10 pm. The material and L / S of the redistribution layer 4 in the first sub-panel 2a can be substantially the same as the material and L / S of the redistribution layer 4 in the second sub-panel 2b.

[0079] A protection layer 25 is on the second surface 32 of the first dielectric layer 3 and on the redistribution layer 4. The protection layer 25 has a first surface 251 and a second surface 252 opposite the first surface 251. The first surface 251 contacts the lower surface (i.e., the second surface 32) of the first dielectric layer 3. The second surface 252 can be part of the lower surface (i.e., the second surface 22) of each of the sub-panels 2. In some embodiments, the protection layer 25 further includes a portion 254 that extends into the gap “g” between the sub-panels 2 and is on the dielectric portion 14. The protection layer 25 can include or be formed from, for example, a cured photoimageable dielectric (PID) material including a photoinitiator, or a solder mask. The protection layer 25 covers the redistribution layer 4, and at least a portion of the redistribution layer 4 (e.g., the conductive pads 44) is exposed from the protection layer 25 for external connection. In some embodiments, the thickness of the protection layer 25 is from about 10 pm to about 30 pm. The material of the protection layer 25 in the first sub-panel 2a can be substantially the same as the material of the protection layer 25 in the second sub-panel 2b. However, the thickness of the protection layer 25 in the first sub-panel 2a can be substantially the same or slightly different from the thickness of the protection layer 25 in the second sub-panel 2b.

[0080] A solder connector 26 is on the exposed portion of the redistribution layer 4, such as the conductive pads 44 of the redistribution layer 4. The material of the solder connector 26 can be a conductive metal such as tin, or another metal or combination of metals.

[0081] The circuit structure 5 is adjacent to the first surface 31 of the first dielectric layer 3. For example, as shown in FIG. 1, the circuit structure 5 is on the first surface 31 of the first dielectric layer 3. The circuit structure 5 can include, for example, a semiconductor die 50, a plurality of conductive pads 51 on the semiconductor die 50, and a plurality of conductive pads 52 on the first surface 31 of the first dielectric layer 3. The semiconductor die 50 can be, for example, a flip chip semiconductor die. The semiconductor die 50 can include a plurality of conductive pads 51 on the semiconductor die 50. The plurality of conductive pads 51 on the semiconductor die 50 can be electrically connected to the plurality of conductive pads 52 on the first surface 31 of the first dielectric layer 3. The plurality of conductive pads 52 on the first surface 31 of the first dielectric layer 3 can be electrically connected to the redistribution layer 4. In some embodiments, the plurality of conductive pads 51 on the semiconductor die 50 can be electrically connected to the plurality of conductive pads 52 on the first surface 31 of the first dielectric layer 3 through the redistribution layer 4. In some embodiments, the plurality of conductive pads 51 on the semiconductor die 50 can be electrically connected to the plurality of conductive pads 52 on the first surface 31 of the first dielectric layer 3 through the solder connector 26. In some embodiments, the plurality of conductive pads 51 on the semiconductor die 50 can be electrically connected to the plurality of conductive pads 52 on the first surface 31 of the first dielectric layer 3 through the solder connector 26 and the redistribution layer 4. Figure 3As shown, circuit structure 5 is embedded in first dielectric layer 3 and exposed from first surface 31 of first dielectric layer 3. Circuit structure 5 may include a seed layer 51 and a conductive layer 52. Seed layer 51 is exposed from first surface 31 of first dielectric layer 3. The material of seed layer 51 may be, for example, titanium or copper. In some embodiments, seed layer 51 may include titanium layer and copper layer. Conductive layer 52 covers seed layer 51. For example, the material of conductive layer 52 may be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, seed layer 51 may be omitted, and conductive layer 52 may be exposed from first surface 31 of first dielectric layer 3. Circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. Conductive pad 53, conductive via 54, and trace 55 may be formed integrally and concurrently. In some embodiments, conductive via 54 is located on and integrally formed with conductive pad 53. Conductive via 54 protrudes from first dielectric layer 3. The conductive via 54 can be adapted to connect to a semiconductor die (e.g., as shown in the image). Figure 12 (As shown in the diagram). The conductive via 54 has an upper surface 541 that is at a level higher than the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The trace 55 has an upper surface 551 that is substantially coplanar with the upper surface 31 of the first dielectric layer 3. In some embodiments, the L / S ratio of the circuit structure 5 may be equal to or less than 2 μm / 2 μm. The redistribution layer 4 is electrically connected to the circuit structure 5. For example, a portion of the redistribution layer 4 (e.g., the conductive via 43) is embedded in the first dielectric layer 3 and contacts and is electrically connected to the circuit structure 5. For example, the conductive via 43 penetrates the first dielectric layer 3 to contact the circuit structure 5. The material and L / S ratio of the circuit structure 5 in the first sub-panel 2a may be the same as or different from the material and L / S ratio of the circuit structure 5 in the second sub-panel 2b.

[0082] The second dielectric layer 6 is located on the first dielectric layer 3. The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. Figure 3 As shown, the first surface 61 is the upper surface, and the second surface 62 is the lower surface. The first surface 61 of the dielectric layer 6 is a portion of the upper surface (i.e., the first surface 21) of the sub-panel 2. The side surface 63 is a portion of the side surface 23 of the sub-panel 2. The second dielectric layer 6 may be located on the first surface 31 of the first dielectric layer 3 and on the circuit structure 5. The lower surface (i.e., the second surface 62) of the second dielectric layer 6 may contact the upper surface (i.e., the first surface 31) of the first dielectric layer 3. Figure 3As shown in FIG. 1, the seed layer 51 of the circuit structure 5 is located between the conductive layer 52 and the second dielectric layer 6 of the circuit structure 5. The upper surface 551 of the trace 55 of the circuit structure 5 contacts a lower surface (i.e., the second surface 62) of the second dielectric layer 6. The second dielectric layer 6 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It is noted that the second dielectric layer 6 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI). The material of the second dielectric layer 6 can be the same as or different from the material of the first dielectric layer 3. The thickness of the second dielectric layer 6 can be 5 pm to 20 pm. The material and thickness of the second dielectric layer 6 in the first sub-panel 2a can be the same as or different from the material and thickness of the second sub-panel 2b.

[0083] The conductive via 54 of the circuit structure 5 can be embedded in and exposed from the second dielectric layer 6. For example, the second dielectric layer 6 can define at least one via 60 that extends through the second dielectric layer 6 between the first surface 61 and the second surface 62. The conductive via 54 of the circuit structure 5 can be located in the via 60 of the second dielectric layer 6 and exposed from the first surface 61 of the second dielectric layer 6. The seed layer 51 of the conductive via 54 of the circuit structure 5 is located in the via 60 of the second dielectric layer 6 and between the conductive layer 52 and the second dielectric layer 6. In some embodiments, the portion of the seed layer 51 of the conductive via 54 of the circuit structure 5 adjacent to the first surface 61 of the second dielectric layer 6 is omitted, and the conductive layer 52 of the conductive via 54 of the circuit structure 5 is exposed from the first surface 61 of the second dielectric layer 6. Thus, the upper surface 541 of the conductive via 54 is recessed from the upper surface (i.e., the first surface 61) of the second dielectric layer 6. As shown in FIG. 1, the conductive via 54 of the circuit structure 5 is located in the via 60 of the second dielectric layer 6 and exposed from the first surface 61 of the second dielectric layer 6. Figure 3 As shown in FIG. 1, the second dielectric layers 6 of the sub-panels 2 are not connected to each other, and the material and structure of the second dielectric layers 6 can be different among the sub-panels 2.

[0084] The dielectric portion 14 is located between the sub-panels 2. For example, the dielectric portion 14 fills a gap “g” formed between adjacent two of the sub-panels 2 (e.g., the first sub-panel 2a and the second sub-panel 2b). The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. As shown in FIG. 1, the dielectric portion 14 has the upper surface 141 and the lower surface 142. Figure 3 As shown in FIG. 1, the dielectric portion 14 has at least one side surface 143 corresponding to each of the sub-panels 2.

[0085] In some embodiments, the dielectric portion 14 covers and contacts at least a portion of the side surface 23 of each of the sub-panels 2. For example, a side surface 143 of the dielectric portion 14 contacts and is substantially coplanar with a side surface 63 of the second dielectric layer 6 of each of the sub-panels 2. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2 is integrally and simultaneously formed with the dielectric portion 14. For example, the dielectric layers 3 of the sub-panels 2 and the dielectric portion 14 can be integrally and simultaneously formed as a unitary structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panels 2.

[0086] In some embodiments, as shown in FIG. 1A, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface (i.e., the first surface 21) of each of the sub-panels 2 and / or the first surface 61 of the second dielectric layer 6. Thus, the dielectric portion 14 has an inner surface 145 to define a cavity 140 above the upper surface (i.e., the first surface 21) of each of the sub-panels 2. The cavity 140 fully exposes the second dielectric layer 6, e.g., the first surface 61 of the second dielectric layer 6, of each of the sub-panels 2. The upper surface 541 of the conductive via 54 is exposed in the cavity 140. The inner surface 145 can be a portion of the side surface 143 of the dielectric portion 14. The side surface 63 of the second dielectric layer 6 is substantially coplanar with the inner surface 145 of the cavity 140. Figure 3

[0087] The dielectric portion 14 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It is noted that the dielectric portion 14 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI). The material of the dielectric portion 14 can be the same as the material of the first dielectric layer 3 of each of the sub-panels 2. In some embodiments, the thickness of the dielectric portion 14 can be about 100 pm to about 300 pm. As shown in FIG. 1A, the thickness of the first dielectric layer 3 is less than the thickness of the dielectric portion 14. However, in other embodiments, the thickness of the first dielectric layer 3 can be substantially equal to or greater than the thickness of the dielectric portion 14. Figure 3

[0088] ​​In the substrate panel structure 1, the layers with smaller L / S, i.e. the circuit structures 5 and the second dielectric layers 6, are formed in each of the sub-panels 2, respectively, while the layers with larger L / S, i.e. the redistribution layers 4 and the first dielectric layers 3, are formed simultaneously across the entire substrate panel structure 1. The layers with smaller L / S are more sensitive to pattern shift than the layers with larger L / S. Since the layers with smaller L / S are formed separately at a smaller scale, i.e. each of the sub-panels 2 has a smaller size or area, the maximum value of the pattern shift of each of the circuit structures 5, for example, is rather small. The effect of the pattern shift on the layers with smaller L / S can thus be reduced. Moreover, the warpage of the second dielectric layers 6 can also be reduced. On the other hand, the layers with larger L / S, which are more tolerant to pattern shift, can be formed simultaneously at a larger scale to reduce the time and cost of production. The larger pattern shift of the layers with larger L / S does not affect the layers with smaller L / S. Therefore, the substrate panel structure 1 formed from the sub-panels 2 has the same maximum pattern shift value as the sub-panels 2.

[0089] For example, in a sub-panel 2 having an area of 300mm*300mm, the value of the pattern shift measured at the edge thereof can be about 1-2pm. The substrate panel structure 1, comprising at least 2*2 such sub-panels 2, thus provides a maximum pattern shift value of about 1-2pm. That is, the value of the pattern shift of the sub-panels 2 will not accumulate. Therefore, although the substrate panel structure 1 according to the present application has an area larger than 600mm*600mm, its maximum pattern shift value (e.g. about 1-2pm) is significantly less than that of the comparative substrate having an area of 450mm*450mm (e.g. at least 3-5pm). As both the maximum values of the pattern shift and warpage are reduced, the semiconductor dies can be accurately mounted to the predetermined positions on the sub-panels 2, i.e. on the circuit structures 5.

[0090] Figure 4 A cross-sectional view illustrating an example of a substrate panel structure la according to some embodiments of the present application is shown. The substrate panel structure la also comprises a plurality of sub-panels 2, including a first sub-panel 2a and a second sub-panel 2b, and a dielectric portion 14 positioned between the sub-panels 2. Each of the sub-panels 2 comprises a plurality of substrate units 20. The components and arrangement of the substrate panel structure la, including the sub-panels 2 and the substrate units 20, are similar to those of the substrate panel structure 1 shown in Figure 2 and 3 except for the dielectric portion 14, as described below.

[0091] As shown in Figure 4 the upper surface 141 of the dielectric portion 14 is at a level lower than the upper surface, i.e. the first surface 21, of each of the sub-panels 2. The upper surface 141 of the dielectric portion 14 is omitted Figure 2 and 3The cavity 140 of the substrate panel structure 1 as shown in

[0092] Figure 5 A cross-sectional view of an example of a substrate panel structure lb according to some embodiments of the present disclosure is illustrated. The substrate panel structure lb includes a plurality of sub-panels 2c and a dielectric portion 14 positioned between the sub-panels 2c. Each of the sub-panels 2c includes a plurality of substrate units 20c. The substrate panel structure lb is similar to the substrate panel structure lb as shown in Figure 2 and 3 except for the dielectric portion 14 as described below.

[0093] As shown in Figure 5 the second dielectric layer 6 as shown in Figure 2 and 3 is omitted. Furthermore, the conductive vias 54 of the circuit structure 5 are also omitted. Thus, the first surface 57 of the circuit structure 5, which is shown as an upper surface in Figure 5 is fully exposed, e.g. in the cavity 140 defined by the dielectric portion 14. The entire upper surface of the circuit structure 5, i.e. the first surface 57, can be substantially coplanar with the upper surface of the first dielectric portion 3, i.e. the first surface 31. Thus, the conductive pads 53 and traces 55 are exposed in the cavity 140. The conductive pads 53 can be adapted to connect with semiconductor dies. Figure 5 The circuit structure 5 is shown with only one layer, i.e. a conductive layer, of a seedless layer. However, the circuit structure 5 can also include one or more seed layers.

[0094] Figure 6 A cross-sectional view of an example of a substrate panel structure lc according to some embodiments of the present disclosure is illustrated. The substrate panel structure lc also includes a plurality of sub-panels 2c and a dielectric portion 14 positioned between the sub-panels 2c. Each of the sub-panels 2c includes a plurality of substrate units 20c. The components and arrangement of the substrate panel structure lc, including the sub-panels 2c and the substrate units 20c, are similar to the substrate panel structure lb as shown in Figure 5 except for the dielectric portion 14 as described below.

[0095] As shown in Figure 6 the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface, i.e. the first surface 21, of each of the sub-panels 2c. The second dielectric layer 6 as shown in Figure 5The cavity 140 of the substrate panel structure 1b shown in the figure. The upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 31) of the first dielectric layer 3 of each of the sub-panels 2c and / or the upper surface (i.e., the first surface 57) of the circuit structure 5.

[0096] Figure 7 A cross-sectional view illustrating an example of a substrate panel structure 1d according to some embodiments of the present invention is provided. The substrate panel structure 1d also includes a plurality of sub-panels 2d and dielectric portions 14 located between the sub-panels 2d. Each of the sub-panels 2d includes a plurality of substrate units 20d. The substrate panel structure 1d is similar to... Figure 6 The substrate panel structure 1c shown in the figure, except for the following.

[0097] like Figure 7 As shown, circuit structure 5 is not embedded in the first dielectric layer 3. Circuit structure 5 protrudes from the first dielectric layer 3. For example, circuit structure 5 is located on the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The first surface 57 (which is as follows) Figure 7 The lower surface shown in the figure contacts the upper surface of the first dielectric layer 3 (i.e., the first surface 31) and is substantially coplanar with it.

[0098] Figure 8 A cross-sectional view illustrating an example of a substrate panel structure 1e according to some embodiments of the present invention is shown. The substrate panel structure 1e also includes a plurality of sub-panels 2e and dielectric portions 14 located between the sub-panels 2e. Each of the sub-panels 2e includes a plurality of substrate units 20e. The substrate panel structure 1e is similar to... Figure 2 and 3 The substrate panel structure 1 shown in the figure further includes an additional dielectric layer 3e and an additional redistribution layer 4e.

[0099] Figure 8 The structure, configuration, materials, and relative positions of the first dielectric layer 3, the redistribution layer 4, the circuit structure 5, the second dielectric layer 6, and the dielectric portion 14 in the substrate panel structure 1e shown are similar to those in [the original text]. Figure 2 and 3 The structure, configuration, materials, and relative positions of the first dielectric layer 3, the redistribution layer 4, the circuit structure 5, the second dielectric layer 6, and the dielectric portion 14 in the substrate panel structure 1 shown in the figure are not described redundantly.

[0100] An additional dielectric layer 3e is on the first dielectric layer 3 and covers the redistribution layer 4. The additional layer 3e can further include portions 34e that extend into the gaps "g" between the sub-panels 2e and are on the dielectric portions 14. The additional dielectric layer 3e can be made of an insulating or dielectric material, for example, polypropylene (PP). It is noted that the additional dielectric layer 3e can include or be formed of a cured photoimageable dielectric (PID) material, for example, an epoxy resin including a photoinitiator or a polyimide (PI). The material of the additional dielectric layer 3e can be the same as or different from the material of the first dielectric layer 3. The material of the additional dielectric layer 3e in each of the sub-panels 2e can be the same and can be formed integrally and simultaneously. The additional dielectric portions 3e of the sub-panels 2e can be connected to each other by the extending portions 34e. The additional dielectric layer 3e defines at least one via 30e to expose at least a portion of the redistribution layer 4, for example, a conductive pad 44 of the redistribution layer 4.

[0101] An additional redistribution layer 4e is on the additional dielectric layer 3e and in the via 30e. The additional redistribution layer 4e can also include a seed layer 41e on the additional dielectric layer 3e and a conductive layer 42e on the seed layer 41e. The materials of the seed layer 41e and the conductive layer 42e of the additional redistribution layer 4e can be the same as the materials of the seed layer 41 and the conductive layer 42 of the redistribution layer 4. The additional redistribution layer 4e can include at least one conductive via 43e in the via 30e of the additional dielectric layer 3e and at least one conductive pad 44e on the additional dielectric layer 3e. The additional redistribution layer 4e is electrically connected to the redistribution layer 4, for example, through the conductive via 43e. In some embodiments, the additional redistribution layer 4e can further include at least one trace (not shown). The L / S of the additional redistribution layer 4e can be substantially equal to or greater than 10 pm / 10 pm. The L / S of the additional redistribution layer 4e can be substantially the same as the L / S of the redistribution layer 4. The materials and L / S of the additional redistribution layer 4e in each of the sub-panels 2e can be the same and can be formed integrally and simultaneously.

[0102] A protective layer 25 is on the additional dielectric layer 3e and the additional redistribution layer 4e. The protective layer 25 has a first surface 251 and a second surface 252 opposite the first surface 251. The first surface 251 contacts the additional dielectric layer 3e. The second surface 252 can be part of the lower surface (i.e., the second surface 22) of each of the sub-panels 2e. The second surface 252 can be part of the lower surface (i.e., the second surface 22) of each of the sub-panels 2e. In some embodiments, the protective layer 25 further includes a portion 254 that extends into the gap "g" between adjacent two of the sub-panels 2e and is on the extended portion 34e of the additional dielectric layer 3e. The protective layer 25 can include or be formed of, for example, a cured photoimageable dielectric (PID) material including an epoxy resin or a polyimide (PI) including a photoinitiator, or a solder mask. The protective layer 25 covers the additional redistribution layer 4e. At least a portion of the additional redistribution layer 4e (e.g., the conductive pads 44e) is exposed from the protective layer 25 for external connection. The solder connectors 26 are on the exposed portions of the additional redistribution layer 4e, e.g., the conductive pads 44e of the additional redistribution layer 4e. In some embodiments, the panel structure 1e can include more than one additional dielectric layer 3e and more than one additional redistribution layer 4e.

[0103] Figure 9 A cross-sectional view illustrating an example of a substrate panel structure 1f according to some embodiments of the present disclosure is shown. The substrate panel structure 1f also includes a plurality of sub-panels 2f and a dielectric portion 14 between the sub-panels 2f. Each of the sub-panels 2f includes a plurality of substrate units 20f.

[0104] Reference is made to Figure 9 Each of the sub-panels 2f has a first surface 21, a second surface 22 opposite the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least a portion of the side surface 23 is an imaginary surface or an imaginary plane. As shown, Figure 9 The first surface 21 is an upper surface and the second surface 22 is a lower surface. Each of the sub-panels 2f includes a first dielectric layer 3, a circuit layer 27, a redistribution layer 4, a second dielectric layer 6, a circuit structure 5, a protective layer 25, and at least one solder connector 26. Similarly, each of the substrate units 20f can include at least a portion of the first dielectric layer 3, at least a portion of the circuit layer 27, at least a portion of the redistribution layer 4, at least a portion of the second dielectric layer 6, at least a portion of the circuit structure 5, at least a portion of the protective layer 25, and at least one solder connector 26.

[0105] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite the first surface 31. As shown, Figure 9As shown in the middle, the first surface 31 is an upper surface, and the second surface 32 is a lower surface. The first surface 31 of the first dielectric layer 3 can be part of the upper surface (i.e., the first surface 21) of each of the sub-panels 2f. The first dielectric layer 3 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or polyimide (PI).

[0106] The circuit layer 27 is adjacent to the second surface 32 of the first dielectric layer 3. The circuit layer 27 can be embedded in the first dielectric layer 3 and exposed from the second surface 32 of the first dielectric layer 3. The circuit layer 27 can include a seed layer 271 and a conductive layer 272. The seed layer 271 is between the conductive layer 272 and the first dielectric layer 3. The material of the seed layer 271 can be, for example, titanium or copper. In some embodiments, the seed layer 271 can include a titanium layer and a copper layer. For example, the material of the conductive layer 272 can be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 271 can be omitted, and the conductive layer 272 can directly contact the first dielectric layer 3. The circuit layer 27 can contain at least one conductive pad 274, and can further include at least one trace (not shown). The circuit layer 27 including the conductive pad 274 and the trace can be formed by patterning a metal layer.

[0107] The first dielectric layer 3 can further define a via 30 exposing a portion of the circuit layer 27, such as the conductive pad 274 of the circuit layer 27. The redistribution layer 4 is on the first dielectric layer 3 and in the via 30. The redistribution layer 4 can include a seed layer 41 and a conductive layer 42. The seed layer 41 is between the conductive layer 42 and the first dielectric layer 3. The material of the seed layer 41 can be, for example, titanium or copper. In some embodiments, the seed layer 41 can include a titanium layer and a copper layer. For example, the material of the conductive layer 42 can be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 can be omitted, and the conductive layer 42 can directly contact the first dielectric layer 3. The redistribution layer 4 can contain at least one conductive via 43, and can further include at least one trace (not shown). The conductive via 43 is in the via 30 and contacts and electrically connects the circuit layer 27. The solder material 77 is on the conductive via 43 of the redistribution layer 4 for external connection. The solder material 77 can be made of tin, or another metal or combination of metals.

[0108] The second dielectric layer 6 is on the second surface 32 of the first dielectric layer 3 and covers the circuit layer 27. The second dielectric layer 6 has a first surface 61, a second surface 62 opposite the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. As shown in the middle, the first surface 61 of the second dielectric layer 6 is an upper surface, and the second surface 62 is a lower surface. The second dielectric layer 6 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 6 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or polyimide (PI). Figure 9As shown in the middle, the first surface 61 is an upper surface, and the second surface 62 is a lower surface. The first surface 61 of the second dielectric layer 6 contacts the first dielectric layer 3 and the circuit layer 27. The side surface 63 of the second dielectric layer 6 is part of the side surface 23 of each of the sub-panels 2f. The second dielectric layer 6 can phase at least one via 60 to expose a portion of the circuit layer 27, such as a conductive pad 274 of the circuit layer 27. The second dielectric layer 6 can be made of an insulating material or a dielectric, such as polypropylene (PP). It should be noted that the second dielectric layer 6 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or polyimide (PI).

[0109] The circuit structure 5 is on the second surface 62 of the second dielectric layer 6 and in the via 60 of the second dielectric layer 6. The circuit structure 5 can include a seed layer 51 and a conductive layer 52. The seed layer 51 is on the second dielectric layer 6, in the via 60 of the second dielectric layer 6, and on the redistribution layer 4. The conductive layer 52 is on the seed layer 51. For example, the material of the seed layer 51 can be titanium or copper. In some embodiments, the seed layer 51 can include a titanium layer and a copper layer. For example, the material of the conductive layer 52 can be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 51 can be omitted, and the conductive layer 52 can directly contact the second dielectric layer 6 and / or the redistribution layer 4. The circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. The conductive pad 53, the conductive via 54, and the trace 55 can be formed integrally and simultaneously. In some embodiments, the conductive via 54 is on and integrally formed with the conductive pad 53. The conductive via 54 is in the via 60 of the second dielectric layer 6 to contact and electrically connect to the circuit layer 27 embedded in the first dielectric layer 3. Thus, the redistribution layer 4 is electrically connected to the circuit structure 5 via the circuit layer 27. That is, each of the redistribution layers 4 is electrically connected to a respective one of the circuit structures 5 via a respective one of the circuit layers 27. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm.

[0110] A protective layer 25 is on the second dielectric layer 6 and covers the circuit structure 5. That is, the second dielectric layer 6 is sandwiched between the first dielectric layer 3 and the protective layer 25. The protective layer 25 has a first surface 251 and a second surface 252 opposite the first surface 251. The first surface 251 contacts a lower surface (i.e., the second surface 62) of the second dielectric layer 6. The second surface 252 can be part of a lower surface (i.e., the second surface 22) of each of the sub-panels 2f. In some embodiments, the protective layer 25 further includes a portion 254 that extends into the gap "g" between the sub-panels 2f and is on the dielectric portion 14. The extended portion 254 of the protective layer 25 can contact a portion of the side surface 63 of the second dielectric layer 6. The protective layer 25 exposes portions of the circuit structure 5, such as the conductive pads 53 of the circuit structure 5, for external connections. The protective layer 25 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI), or a solder mask.

[0111] A solder connector 26 is on the exposed portions of the circuit structure 5, such as the conductive pads 53 of the circuit structure 5. The material of the solder connector 26 can be a conductive metal, such as tin, or another metal or combination of metals.

[0112] The dielectric portion 14 is between the sub-panels 2f. For example, the dielectric portion 14 is in the gap "g" between the sub-panels 2f. The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. As shown in FIG. 1, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 21) of each of the sub-panels 2f and / or the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The lower surface 142 of the dielectric portion 14 is at a level lower than the lower surface (i.e., the second surface 32) of the first dielectric layer 3 and the upper surface (i.e., the first surface 61) of the second dielectric layer 6 and higher than the lower surface (i.e., the second surface 62) of the second dielectric layer 6. However, in other embodiments, the lower surface 142 of the dielectric portion 14 can be substantially coplanar with the lower surface (i.e., the second surface 32) of the first dielectric layer 3 and the upper surface (i.e., the first surface 61) of the second dielectric layer 6, or can be substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. Figure 9

[0113] ​In some embodiments, the dielectric portion 14 covers and contacts at least part of the side surface 23 of each of the sub-panels 2f. For example, a side surface 143 of the dielectric portion 14 is in contact with and substantially co-planar with a side surface 63 of the second dielectric layer 6 of each of the sub-panels 2f. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2f is formed integrally and simultaneously with the dielectric portion 14. For example, the dielectric layers 3 of the sub-panels 2f and the dielectric portion 14 can be formed integrally and simultaneously as a monolithic structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panels 2f.

[0114] The dielectric portion 14 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It is noted that the dielectric portion 14 can comprise or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI). The material of the dielectric portion 14 can be the same as the material of the first dielectric layer 3 of each of the sub-panels 2f. As Figure 9 As shown in FIG. 1, the thickness of the first dielectric layer 3 is less than the thickness of the dielectric portion 14. However, in other embodiments, the thickness of the first dielectric layer 3 can be substantially equal to or greater than the thickness of the dielectric portion 14.

[0115] Figure 10 A cross-sectional view illustrating an example of a substrate panel structure 1g according to some embodiments of the present disclosure is shown. The substrate panel structure 1g also comprises a plurality of sub-panels 2g and a dielectric portion 14 between the sub-panels 2g. Each of the sub-panels 2g comprises a plurality of substrate units 20g.

[0116] Referring to Figure 10 each of the sub-panels 2g has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least part of the side surface 23 is an imaginary surface or an imaginary plane. As Figure 10 shown, the first surface 21 is an upper surface and the second surface 22 is a lower surface. Each of the sub-panels 2g comprises a first dielectric layer 3, a circuit structure 5, a redistribution layer 4, and at least one solder connector 26. Similarly, each of the substrate units 20g can comprise at least part of the first dielectric layer 3, at least part of the circuit structure 5, at least part of the redistribution layer 4, and at least one solder connector 26.

[0117] The first dielectric layer 3 comprises a first surface 31, a second surface 32 opposite to the first surface 31, and a side surface 33 extending between the first surface 31 and the second surface 32. As Figure 10As shown in FIG. 1, the first surface 31 is an upper surface, and the second surface 32 is a lower surface. The first surface 31 of the first dielectric layer 3 can be part of an upper surface (i.e., the first surface 21) of each of the sub-panels 2g, the second surface 32 of the dielectric layer 3 can be part of a lower surface (i.e., the second surface 22) of each of the sub-panels 2g, and the side surface 33 of the first dielectric layer 3 can be part of a side surface 23 of the sub-panels 2g. The first dielectric layer 3 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or polyimide (PI).

[0118] The circuit structure 5 is adjacent to the first surface 31 of the first dielectric layer 3. For example, as shown in FIG. 1, the circuit structure 5 is embedded in the first dielectric layer 3 and exposed from the first surface 31 of the first dielectric layer 3. Figure 10 As shown in FIG. 1, the circuit structure 5 is embedded in the first dielectric layer 3 and exposed from the first surface 31 of the first dielectric layer 3. The material of the circuit structure 5 can be, for example, a conductive metal, such as copper, or another metal or combination of metals. Figure 10 The circuit structure 5 is shown as consisting of a single layer. However, in some embodiments, the circuit structure 5 can also include other layers, such as one or more seed layers. The circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 can be formed integrally and simultaneously. The trace 55 has an upper surface 551 that is at a level lower than the upper surface 31 of the first dielectric layer 3. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm.

[0119] The first dielectric layer 3 can further define at least one via 30 such that a portion of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5, can be exposed in the via 30 and exposed from the second surface 32 of the dielectric layer 3.

[0120] The redistribution layer 4 is electrically connected to the circuit structure 5. For example, the redistribution layer 4 includes at least one conductive via 43 that is positioned in the via 30 of the first dielectric layer 3 and embedded in the first dielectric layer 3. The conductive via 43 penetrates through the first dielectric layer 3 to contact and electrically connect the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. In some embodiments, the redistribution layer 4 can further include at least one trace (not shown). For example, the material of the redistribution layer 4 can be a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, one or more seed layers can be positioned between the redistribution layer 4 and the first dielectric layer 3. In some embodiments, the line width / line spacing (L / S) of the redistribution layer 4 can be equal to or greater than 10 pm / 10 pm.

[0121] The solder connectors 26 are positioned on and electrically connected to the conductive vias 43 of the redistribution layer 4. The material of the solder connectors 26 can be a conductive metal, such as tin, or other metal or combination of metals. An under bump metallization (UBM) 46 can be positioned between the conductive vias 43 and the solder connectors 26.

[0122] The dielectric portion 14 is positioned between the sub-panels 2g. For example, a gap “g” is defined between two adjacent ones of the sub-panels 2g, and the dielectric portion 14 is positioned in the gap “g”. The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least portions of the side surface 143 are imaginary surfaces or imaginary planes. As shown in FIG. 1, the dielectric portion 14 has the at least one side surface 143 corresponding to each of the sub-panels 2g. The upper surface 141 of the dielectric portion 14 is at a level lower than the upper surface (i.e., the first surface 21) of each of the sub-panels 2g and / or the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 22) of each of the sub-panels 2g and / or the lower surface (i.e., the second surface 32) of the first dielectric layer 3. Figure 10

[0123] In some embodiments, the dielectric portion 14 covers and contacts at least portions of the side surfaces 23 of each of the sub-panels 2g. For example, the side surface 143 of the dielectric portion 14 contacts and is substantially coplanar with the side surface 23 of the first dielectric layer 3 and / or the side surface 33 of the first dielectric layer 3 of each of the sub-panels 2g. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2g is integrally and simultaneously formed with the dielectric portion 14. For example, the dielectric layer 3 of the sub-panels 2g and the dielectric portion 14 can be integrally and simultaneously formed as a unitary structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panels 2g.

[0124] The dielectric portion 14 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the dielectric portion 14 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI). The material of the dielectric portion 14 can be the same as the material of the first dielectric layer 3 of each of the sub-panels 2g. The thickness of the first dielectric layer 3 can be greater than the thickness of the dielectric portion 14.

[0125] As shown in FIG. 1, the dielectric portion 14 has the at least one side surface 143 corresponding to each of the sub-panels 2g. The upper surface 141 of the dielectric portion 14 is at a level lower than the upper surface (i.e., the first surface 21) of each of the sub-panels 2g and / or the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 22) of each of the sub-panels 2g and / or the lower surface (i.e., the second surface 32) of the first dielectric layer 3. Figure 10 ​As shown in the middle, at least one semiconductor die 74 is connected to each of the substrate units 20g. That is, a plurality of semiconductor dies 74 is connected to each of the sub-panels 2g. The semiconductor dies 74 can include bumps 75 and UBMs 76. The bumps 75 are on a lower surface 741 of the semiconductor dies 74, and the UBMs 76 are on the bumps 75. The material of the bumps 75 can be copper. The UBM 76 can include a first layer 761, a second layer 762, and a third layer 763 sequentially on the bump 75. For example, the material of the first layer 761 can be nickel, the material of the second layer 762 can be palladium, and the material of the third layer 763 can be gold, but not limited thereto. The UBM 76 of the semiconductor die 74 can be electrically connected to the conductive pads 53 of the circuit structure 5 through the solder material 77 therebetween. The solder material 77 can be made of tin, or another metal or combination of metals.

[0126] An encapsulant 78 is on and covers the substrate panel structure 1g. For example, the encapsulant 78 is on the first dielectric layer 3 of each of the sub-panels 2g, and covers and encapsulates the semiconductor dies 74. The encapsulant 78 can further include a portion 784 in the gap “g” between the sub-panels 2g and on the dielectric portion 14. The portion 784 of the encapsulant 78 contacts the side surface 33 of the first dielectric layer 3. The encapsulant 78 can be a molding compound. The substrate panel structure 1g and the encapsulant 78 can be separated into a plurality of package units, for example Figure 16 The package unit 7g shown in the middle.

[0127] Figure 11 A cross-sectional view illustrating an example of a substrate panel structure 1h according to some embodiments of the present disclosure is described. The substrate panel structure 1h also includes a plurality of sub-panels 2h and a dielectric portion 14 between the sub-panels 2h. Each of the sub-panels 2h includes a plurality of substrate units 20h.

[0128] Referring to Figure 11 each of the sub-panels 2h has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least part of the side surface 23 is an imaginary surface or an imaginary plane. As Figure 11 shown in the middle, the first surface 21 is an upper surface, and the second surface 22 is a lower surface. Each of the sub-panels 2h includes a second dielectric layer 6, a plurality of conductive pillars 28, a circuit structure 5, a first dielectric layer 3, a redistribution layer 4, and at least one solder connector 26. Similarly, each of the substrate units 20h can include at least part of the second dielectric layer 6, the plurality of conductive pillars 28, at least part of the circuit structure 5, at least part of the first dielectric layer 3, at least part of the redistribution layer 4, and the at least one solder connector 26.

[0129] The second dielectric layer 6 has a first surface 61, a second surface 62 opposite the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. As shown in Figure 11 The first surface 61 is an upper surface, and the second surface 62 is a lower surface. The first surface 61 of the dielectric layer 6 is part of an upper surface (i.e., the first surface 21) of the sub-panel 2h. The side surface 63 is part of a side surface 23 of the sub-panel 2h. The second dielectric layer 6 defines a plurality of vias 60 through the second dielectric layer 6 and between the first surface 61 and the second surface 62. The second dielectric layer 6 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It is noted that the second dielectric layer 6 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or polyimide (PI).

[0130] The conductive pillars 28 are located in the vias 60 of the second dielectric layer 6, and both ends of each of the conductive pillars 28 are exposed from the second dielectric layer 6. The material of the conductive pillars 28 can be, for example, a conductive metal, such as copper, or another metal or combination of metals.

[0131] The circuit structure 5 is adjacent to the first surface 61 of the second dielectric layer 6 and electrically connected to the conductive pillars 28. For example, as shown in Figure 11 The circuit structure 5 is located on the first surface 61 of the second dielectric layer 6, and portions of the circuit structure 5 can extend into the vias 60 to contact the conductive pillars 28. The circuit structure 5 can include a seed layer 51 and a conductive layer 52. The seed layer 51 is located between the conductive layer 52 and the second dielectric layer 6, and between the conductive layer 52 and the conductive pillars 28. The material of the seed layer 51 can be, for example, titanium or copper. In some embodiments, the seed layer 51 can include a titanium layer and a copper layer. The material of the conductive layer 52 can be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 51 can be omitted, and the conductive layer 52 can directly contact the second dielectric layer 6 and / or the conductive pillars 28. The circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 can be formed integrally and simultaneously. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm.

[0132] The redistribution layer 4 is adjacent to the second surface 62 of the second dielectric layer 6. For example, as shown in Figure 11As shown in the middle, the redistribution layer 4 is on the second surface 62 of the second dielectric layer 6, and a portion of the redistribution layer 4 can extend into the via 60 to contact the conductive post 28. The redistribution layer 4 is electrically connected to the circuit structure 5 via the conductive post 28. The redistribution layer 4 can include a seed layer 41 and a conductive layer 42. The seed layer 41 is between the conductive layer 42 and the second dielectric layer 6, and between the conductive layer 42 and the conductive post 28. The material of the seed layer 41 can be, for example, titanium or copper. In some embodiments, the seed layer 41 can include a titanium layer and a copper layer. For example, the material of the conductive layer 42 can be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 can be omitted, and the conductive layer 42 can directly contact the second dielectric layer 6 and the conductive post 28. The redistribution layer 4 can include at least one conductive pad 44 and at least one trace 45. In some embodiments, the line width / line space (L / S) of the redistribution layer 4 can be equal to or greater than 10 pm / 10 pm.

[0133] The first dielectric layer 3 is on the second surface 62 of the second dielectric layer 6 and covers the redistribution layer 4. The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. As shown in the middle, the first surface 31 is an upper surface, and the second surface 32 is a lower surface. The upper surface of the first dielectric layer 3 (i.e., the first surface 31) can contact the lower surface of the second dielectric layer 6 (i.e., the second surface 62). Figure 11

[0134] The first dielectric layer 3 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It is noted that the first dielectric layer 3 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI). The first dielectric layer 3 defines at least one via 30 to expose at least a portion of the redistribution layer 4, such as a conductive pad 44 of the redistribution layer 4.

[0135] The solder connector 26 is in the via 30 of the first dielectric layer 3 and on and electrically connected to the exposed portion of the redistribution layer 4, such as the conductive pad 44. The material of the solder connector 26 can be a conductive metal, such as tin, or other metal or combination of metals. A barrier layer 47 and a wetting layer 48 can be between the conductive pad 44 and the solder connector 26. The material of the barrier layer 47 can be nickel, and the material of the wetting layer can be gold.

[0136] The dielectric portion 14 is between the sub-panels 2h. For example, a gap “g” is defined between two adjacent ones of the sub-panels 2h, and the dielectric portion 14 is in the gap “g”. The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. As shown in the middle, the dielectric portion 14 is between the sub-panels 2h.​Figure 11 As shown in FIG. 1H, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 31) of the first dielectric layer 3 and the lower surface (i.e., the second surface 62) of the second dielectric layer 6 of each of the sub-panels 2h, and is lower than the upper surface (i.e., the first surface 21) of each of the sub-panels 2h. The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 22) of each of the sub-panels 2h and / or the lower surface (i.e., the second surface 32) of the first dielectric layer 3. The side surface 143 of the dielectric portion 14 is substantially coplanar with the side surface 63 of the second dielectric layer 6 of each of the sub-panels 2h.

[0137] In some embodiments, the dielectric portion 14 covers and contacts at least a portion of the side surface 23 of each of the sub-panels 2. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2h is integrally and simultaneously formed with the dielectric portion 14. For example, the dielectric layer 3 of the sub-panels 2h and the dielectric portion 14 can be integrally and simultaneously formed as a monolithic structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panels 2h.

[0138] As shown in FIG. 1H, the dielectric portion 14 is electrically connected to the circuit structure 5. For example, the dielectric portion 14 is electrically connected to the conductive pads 53 of the circuit structure 5 through the solder material 77. The solder material 77 can be made of tin, or another metal or combination of metals. Figure 17 As shown in FIG. 1H, at least one semiconductor die 74 is connected to each of the substrate units 20h. That is, a plurality of semiconductor dies 74 is connected to each of the sub-panels 2h. The semiconductor die 74 can include a bump 75 and a UBM 76. The bump 75 is on a lower surface 741 of the semiconductor die 74, and the UBM 76 is on the bump 75. The material of the bump 75 can be copper. The UBM 76 can include a first layer 761 and a second layer 762 sequentially on the bump 75. For example, the material of the first layer 761 can be nickel, and the material of the second layer 762 can be palladium, but not limited thereto. In some embodiments, the UBM 76 can include three layers made of nickel, palladium, and gold. The UBM 76 of the semiconductor die 74 can be electrically connected to the conductive pads 53 of the circuit structure 5 through the solder material 77 therebetween. The solder material 77 can be made of tin, or another metal or combination of metals.

[0139] An encapsulant 78 is on and covers the substrate panel structure 1h. For example, the encapsulant 78 is on the second dielectric layer 6 of each of the sub-panels 2h, and covers and encapsulates the semiconductor dies 74. The encapsulant 78 includes a portion 784 that is in the gap “g” formed between two adjacent sub-panels 2h and on the dielectric portion 14. The encapsulant 78 can contact and cover the side surface 63 of the second dielectric layer 6. The encapsulant 78 can be a molding compound. The substrate panel structure 1h and the encapsulant 78 can be separated into a plurality of package units, for example, the package unit 7h shown in FIG. 1H, by a singulation process. Figure 12 As shown in FIG. 1H, the dielectric portion 14 is electrically connected to the circuit structure 5. For example, the dielectric portion 14 is electrically connected to the conductive pads 53 of the circuit structure 5 through the solder material 77. The solder material 77 can be made of tin, or another metal or combination of metals.

[0140] Figure 3 A cross-sectional view illustrating an example of a package unit 7 according to some embodiments of the application is shown. The package unit 7 corresponds to each of the substrate units 20 shown in Figs. 1-3. That is, the package unit 7 includes a substrate unit 20, and further includes a semiconductor die 74 and an encapsulant 78. Figure 4 or Figure 13 The package unit 7 includes a substrate unit 20, and further includes a semiconductor die 74 and an encapsulant 78. The substrate unit 20 corresponds to each of the substrate units 20 shown in Figs. 1-3. That is, the package unit 7 includes a substrate unit 20, and further includes a semiconductor die 74 and an encapsulant 78.

[0141] The semiconductor die 74 is connected to the substrate unit 20. The semiconductor die 74 can include bumps 75 on a lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to the conductive vias 54 of the circuit structure 5 of the substrate unit 20 via solder material 77 between the bumps and the conductive vias. The solder material 77 can be made of tin, or another metal or combination of metals.

[0142] The encapsulant 78 is on the substrate unit 20, and covers at least part of the substrate unit 20 and / or the semiconductor die 74. For example, the encapsulant 78 is between the second dielectric layer 6 of the substrate unit 20 and the semiconductor die 74, and encapsulates the bumps 75 and the solder material 77. The encapsulant 78 can be an underfill or a mold compound.

[0143] Figure 5 A cross-sectional view illustrating an example of a package unit 7c according to some embodiments of the application is shown. The package unit 7c corresponds to each of the substrate units 20c shown in Figs. 4-6. That is, the package unit 7c includes a substrate unit 20c, and further includes a semiconductor die 74 and an encapsulant 78. Figure 6 or Figure 14 The package unit 7c includes a substrate unit 20c, and further includes a semiconductor die 74 and an encapsulant 78. The substrate unit 20c corresponds to each of the substrate units 20c shown in Figs. 4-6. That is, the package unit 7c includes a substrate unit 20c, and further includes a semiconductor die 74 and an encapsulant 78.

[0144] The semiconductor die 74 is connected to the substrate unit 20c. The semiconductor die 74 can include bumps 75 on a lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to the conductive pads 53 of the circuit structure 5 of the substrate unit 20c via solder material 77 between the bumps and the conductive vias. The solder material 77 can be made of tin, or another metal or combination of metals.

[0145] The encapsulant 78 is on the substrate unit 20c, and covers at least part of the substrate unit 20c and / or the semiconductor die 74. For example, the encapsulant 78 is between the first dielectric layer 3 of the substrate unit 20c and the semiconductor die 74, and encapsulates the bumps 75, the solder material 77, and part of the circuit structure 5. The encapsulant 78 can be an underfill or a mold compound.

[0146] Figure 7 A cross-sectional view illustrating an example of a semiconductor package 7d according to some embodiments of the application is shown. The package unit 7d corresponds to each of the substrate units 20d shown in Figs. 7-9. That is, the package unit 7d includes a substrate unit 20d, and further includes a semiconductor die 74 and an encapsulant 78. Figure 15Each of the substrate units 20d shown in FIG. 1. That is, the package unit 7d includes the substrate unit 20d, and further includes the semiconductor die 74 and the encapsulant 78.

[0147] The semiconductor die 74 is connected to the substrate unit 20d. The semiconductor die 74 can include bumps 75 on a lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to the conductive pads 53 of the circuit structure 5 of the substrate unit 20d via the solder material 77 between the bumps 75 and the conductive pads 53. The solder material 77 can be made of tin, or another metal or combination of metals.

[0148] The encapsulant 78 is on the substrate unit 20d, and covers at least part of the substrate unit 20d and / or the semiconductor die 74. For example, the encapsulant 78 is between the first dielectric layer 3 of the substrate unit 20d and the semiconductor die 74, and encapsulates the bumps 75, the solder material 77, and part of the circuit structure 5. The encapsulant 78 can be underfill or mold compound.

[0149] Figure 9 A cross-sectional view of an example of a semiconductor package 7f according to some embodiments of the present disclosure is illustrated. The package unit 7f corresponds to Figure 16 Each of the substrate units 20f shown in FIG. 2. That is, the package unit 7f includes the substrate unit 20f, and further includes the semiconductor die 74 and the encapsulant 78.

[0150] The semiconductor die 74 is connected to the substrate unit 20f. The semiconductor die 74 can include bumps 75 on a lower surface 741 of the semiconductor die 74, and UBMs 76 on the bumps 75. The UBM 76 can include a first layer 761 and a second layer 762 sequentially on the bump 75. For example, the material of the first layer 761 can be nickel, and the material of the second layer 762 can be palladium, but not limited thereto. In some embodiments, the UBM 76 can include three layers made of nickel, palladium, and gold. The UBM 76 of the semiconductor die 74 is connected to the redistribution layer 4 of the substrate unit 20f, such as the conductive via 43 of the redistribution layer 4, through the solder material 77.

[0151] The encapsulant 78 is on the substrate unit 20f, and covers at least part of the substrate unit 20f and / or the semiconductor die 74. For example, the encapsulant 78 is on the first dielectric layer 3 of the substrate unit 20f, and covers and encapsulates the semiconductor die 74, the bumps 75 and the UBMs 76 of the semiconductor die 74, the solder material 77, and the redistribution layer 4 of the substrate unit 20f. The encapsulant 78 can be underfill or mold compound.

[0152] Figure 10A cross-sectional view of an example of a package unit 7g according to some embodiments of the application is illustrated. The package unit 7g corresponds to each of the substrate units 20g illustrated in Figure 10 . That is, the package unit 7g includes the substrate unit 20g, and further includes a semiconductor die 74 and an encapsulant 78. The semiconductor 74 and the encapsulant 78 are the same as those described in Figure 17 . Thus, they are not repeated here.

[0153] Figure 11 A cross-sectional view of an example of a semiconductor package 7h according to some embodiments of the application is illustrated. The package unit 7h corresponds to each of the substrate units 20h illustrated in Figure 11 . That is, the package unit 7h includes the substrate unit 20h, and further includes a semiconductor die 74 and an encapsulant 78. The semiconductor 74 and the encapsulant 78 are the same as those described in Figure 18 . Thus, they are not repeated here.

[0154] Figure 3 A cross-sectional view of an example of a semiconductor package 7k according to some embodiments of the application is illustrated. The package unit 7k corresponds to each of the substrate units 20 illustrated in Figure 4 or Figure 12 . That is, the package unit 7 includes the substrate unit 20, and further includes a semiconductor die 74 and an encapsulant 78. The package unit 7k is similar to the package unit 7 illustrated in Figures 19 to 26 , except that the encapsulant 78 of the package unit 7k completely covers the semiconductor die 74.

[0155] Figure 2 A manufacturing process according to some embodiments of the application is illustrated. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as Figure 12 and 3 illustrated in Figure 19 , and / or a package unit of a package unit 7 illustrated in

[0156] Referring to Figure 19 , an intermediate carrier 81 is provided. The intermediate carrier 81 can include a releasing film 82 thereon. A seed layer is formed or disposed on the intermediate carrier 81 by, for example, sputtering. As illustrated in Figure 20 , the seed layer includes a titanium layer 83 and a copper layer 84 in sequence on the releasing film 82 of the intermediate carrier 81.

[0157] Referring to Figure 20second dielectric layer 6 is formed on the seed layer (e.g., copper layer 84). The second dielectric layer 6 has a first surface 61, a second surface 62 opposite the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. As shown in Figure 12 the first surface 61 is an upper surface and the second surface 62 is a lower surface. The first surface 61 contacts the seed layer (e.g., copper layer 84). The second dielectric layer 6 defines at least one via 60 that extends through the second dielectric layer 6 and between the first surface 61 and the second surface 62 to expose a portion of the seed layer (e.g., copper layer 84). Then, a circuit structure 5 is formed on the second surface 62 of the second dielectric layer 6 and in the via 60 of the second dielectric layer 6. The circuit structure 5 includes a seed layer 51 and a conductive layer 52. The seed layer 51 is between the conductive layer 52 and the second dielectric layer 6 and between the conductive layer 52 and the seed layer (e.g., copper layer 84) in the via 60. For example, the seed layer 51 can be formed by sputtering and the conductive layer 52 can be formed by electroplating. The material of the seed layer 51 can be, for example, titanium or copper. In some embodiments, the seed layer 51 can include a titanium layer and a copper layer. For example, the material of the conductive layer 52 can be a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. The conductive pad 53, the conductive via 54, and the trace 55 can be formed integrally and simultaneously. In some embodiments, the conductive via 54 is on and integrally formed with the conductive pad 53. The conductive via 54 of the circuit structure 5 can be in the via 60 of the second dielectric layer 6. That is, each of the circuit structures 5 includes a respective one of the vias 60 of the second dielectric layer 6. The trace 55 has an upper surface 551 that contacts and is substantially coplanar with the lower surface 62 of the second dielectric layer 6. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm. Thus, the intermediate panel 8 is formed. The intermediate panel 8 includes a plurality of panel units 80 connected to each other. Each of the panel units 80 corresponds to a package unit, such as the package unit 7 shown in Figure 19 .

[0158] For illustrative purposes, Figure 21 and 20 only one intermediate panel 8 is shown. However, a plurality of intermediate panels 8 can be provided or formed via the above-mentioned processes. Each of the intermediate panels 8 includes one circuit structure 5, and these intermediate panels 8 are separated from each other. That is, a plurality of intermediate carriers 81 can be provided, and the second dielectric layer 6 can be formed on each of the intermediate carriers 81. Similarly, the circuit structure 5 can be formed on each of the intermediate carriers 81, e.g., on the second dielectric layer 6, thus forming each intermediate panel 8. Since the intermediate panels 8 can be formed individually, the materials and structures of each of the intermediate panels 8 can be different from each other.

[0159] Referring to Figure 21 , a main carrier 91 is provided. The main carrier 91 includes a soft releasing film 92 disposed thereon. The intermediate panels 8 are disposed on the main carrier 91 and partially embedded in the soft releasing film 92. The intermediate carrier 81 is located between the main carrier 91 and the circuit structure 5. The lower surface 921 of the soft releasing film 92 is at a level higher than the upper surface (i.e., the first surface 61) of the second dielectric layer 6. The intermediate panels 8 are spaced apart from each other, and a gap “g” is defined between two adjacent ones of the intermediate panels 8. For illustrative purposes, Figure 22 only two intermediate panels 8 are shown. However, the number of the intermediate panels 8 can be more than two.

[0160] Referring to Figure 22 , a dielectric material is provided on the main carrier 91 to form a plurality of first dielectric layers 3 and one dielectric portion 14. The dielectric material covers the intermediate panels 8 and the soft releasing film 92. Each of the first dielectric layers 3 is on a respective one of the intermediate panels 8. The dielectric portion 14 is in the gap “g” between two adjacent intermediate panels 8 and on the soft releasing film 92. The dielectric portion 14 is between the first dielectric layers 3 and connects the first dielectric layers 3. The first dielectric layers 3 and the dielectric portion 14 are simultaneously and integrally formed as an integral structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layers 3. The dielectric material can be an insulating material or a dielectric material such as polypropylene (PP). It should be noted that the dielectric material can include or be formed of a cured photoimageable dielectric (PID) material such as an epoxy resin including a photoinitiator or a polyimide (PI). Thus, the first dielectric layers 3 and the dielectric portion 14 can be made of or include an insulating material or a dielectric material such as polypropylene (PP), or can be formed of or include a cured photoimageable dielectric (PID) material such as an epoxy resin including a photoinitiator or a polyimide (PI).

[0161] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. As Figure 23 shown in FIG. 1, the first surface 31 is an upper surface, and the second surface 32 is a lower surface. The upper surface (i.e., the first surface 31) of the first dielectric layer 3 contacts the lower surface (i.e., the second surface 62) of the second dielectric layer 6, thus substantially coplanar with the upper surface 551 of the trace 55 of the circuit structure 5. In some embodiments, the thickness of the first dielectric layer 3 can be about 3 pm to about 20 pm, preferably about 3 pm to about 15 pm.

[0162] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. The upper surface 141 contacts the lower surface 921 of the soft release film 92, and is thus at a level higher than the upper surface (i.e., the first surface 61) of the second dielectric layer 6. At least portions of the side surface 143 are imaginary surfaces or imaginary planes. The side surface 143 can contact and be substantially coplanar with the side surface 63 of the second dielectric layer 6, and can further contact the release film 82 and the intermediate carrier 81.

[0163] With reference to Figure 24 At least one via 30 is formed through each of the first dielectric layers 3 by, for example, lithography or drilling. The via 30 exposes a portion of the circuit structure 5, such as a conductive pad 53 of the circuit structure 5. A plurality of redistribution layers 4 is then formed on the first dielectric layers 3, and each of the redistribution layers 4 is electrically connected to a respective one of the circuit structures 5 of the intermediate panel 8. The redistribution layers 4 are on the second surface 32 of the first dielectric layers 3, and in the via 30. The redistribution layers 4 can include a seed layer 41 on the first dielectric layers 3, and a conductive layer 42 on the seed layer 41. The material of the seed layer 41 can be, for example, titanium or copper. In some embodiments, the seed layer 41 can include a titanium layer and a copper layer. For example, the seed layer 41 can be formed by sputtering, and the conductive layer 42 can be formed by electroplating. For example, the material of the conductive layer 42 can be a conductive metal, such as copper, or another metal or combination of metals. The redistribution layer 4 can include at least one conductive via 43 in the via 30 of the first dielectric layers 3, and at least one conductive pad 44 on the second surface 32 of the first dielectric layers 3. The redistribution layer 4 is electrically connected to the circuit structure 5 via the conductive via 43. In some embodiments, the redistribution layer 4 can further include at least one trace (not shown). In some embodiments, the line width / line space (L / S) of the redistribution layer 4 can be equal to or greater than 10 pm / 10 pm.

[0164] With reference to Figure 25A protective layer 25 is formed on the first dielectric layer 3 and covers the reel layer 4. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The first surface 251 contacts the second surface 32 of the first dielectric layer 3. In some embodiments, the protective layer 25 further includes a portion 254 extending into the gap “g” between the intermediate panels 8 and located on the dielectric portion 14. The protective layer 25 may comprise, for example, a curable photoimageable dielectric (PID) material comprising an epoxy resin or polyimide (PI) including a photoinitiator, or a solder resist layer, or formed therefrom. The protective layer 25 covers the reel layer 4, and at least a portion of the reel layer 4 (e.g., a conductive pad 44) ​​is exposed from the protective layer 25 for external connection. In some embodiments, the thickness of the protective layer 25 is from about 10 μm to about 30 μm. At least one solder connector 26 is then formed on the exposed portion of the reel layer 4, such as the conductive pad 44 of the reel layer 4. The material of the solder connector 26 may be a conductive metal, such as tin, or another metal or combination of metals.

[0165] refer to Figure 2 The main carrier 91, including the soft release layer 92, is removed. Then, the intermediate carrier 81, including the release film 82, is removed, exposing the seed layer (e.g., titanium layer 83). The seed layer (e.g., titanium layer 83 and copper layer 84) is then removed, for example, by etching, thus forming... Figure 26 and 3 The substrate panel structure 1 shown is illustrated. Each of the intermediate panels 8 corresponds to a corresponding one of the sub-panels 2. During the etching process, a portion of the seed layer 51 of the circuit structure 5 adjacent to the first surface 61 of the second dielectric layer 6 may also be removed, thus exposing the conductive layer 52 of the conductive via 54 from the first surface 61 of the second dielectric layer 6. Consequently, the upper surface 541 of the conductive via 54 is recessed from the upper surface (i.e., the first surface 61) of the second dielectric layer 6.

[0166] refer to Figure 12The plurality of semiconductor dies 74 are then connected or mounted to the circuit structure 5 (i.e., the sub-panel 2 in the substrate panel structure 1) of each of the intermediate panels 8. For example, at least one semiconductor die 74 is connected to each of the substrate cells 20. The semiconductor dies 74 can include bumps 75 on a lower surface 741 of the semiconductor dies 74. The bumps 75 of the semiconductor dies 74 are electrically connected to the conductive vias 54 of the circuit structure 5 of the substrate cells 20 via a solder material 77 between the bumps 75 and the conductive vias 54. The solder material 77 can be made of tin, or another metal or combination of metals. A plurality of encapsulants 78 are then formed on each of the substrate cells 20 to cover a respective one of the semiconductor dies 74. For example, the encapsulants 78 are between the second dielectric layer 6 and the semiconductor dies 74, and encapsulate the bumps 75 and the solder material 77. Each of the singulated sub-panels 2 is then singulated. That is, each of the intermediate panels 8 (e.g., including the second dielectric layer 6 and the circuit structure 5), each of the first dielectric layers 3, and each of the redistribution layers 4 are singulated to form a plurality of packaged units, such as the packaged units 7 shown in FIG. 1. Figure 27 For example, the edges of each sub-panel 2 can be cut along the side surfaces 23 to remove portions of the dielectric portions 14 and the portions 254 of the protective layers 25 during the singulation process.

[0167] In a comparative manufacturing process (e.g., a reconstitution process), the intermediate panel is first cut into a plurality of panel units that are separated from each other. The panel units are then picked up and placed on a master carrier. Other layers, such as dielectric layers and redistribution layers, are then formed on the master carrier, and a plurality of semiconductor dies are then connected to the panel units. The reason for cutting the intermediate panel into panel units is that the intermediate panel is typically a circular wafer, so the cutting process can effectively reduce the wasted area of the wafer. However, these panel units are placed on the master carrier by a machine, which can cause the positions of these units to be shifted by about 1-3 pm. That is, the pitches of these panel units are not consistent, so the semiconductor dies cannot be precisely bonded to the panel units.

[0168] In contrast, since the intermediate panel 8 in the above-described manufacturing process of the present application includes a plurality of panel units 80 that are connected to each other, the pitches between the plurality of panel units 80 are not affected by the pick-and-place process. That is, the pitches between the panel units in the same intermediate panel are substantially consistent, so the semiconductor dies can be precisely mounted on the panel units.

[0169] Figure 2 A manufacturing process according to some embodiments of the present application is described. In some embodiments, the manufacturing process is also used to manufacture, for example, Figure 12 and 3the substrate panel structure 1 shown in Figures 19 to 20 the packaging unit 7 shown in Figure 27 the stages explained in Figure 20 explained Figure 27 the stages explained in

[0170] Figure 21 the stages shown in Figure 27 the stages shown in Figure 21 shown in Figure 22 the soft releasing film 92 shown in. Thus, the intermediate panels 8 are positioned on the hard releasing film 92a, instead of being embedded therein. A gap "g" is defined between adjacent two of the intermediate panels 8. A resin material 93, e.g. photoresist, is applied in the gap "g" defined between adjacent two of the intermediate panels 8. The resin material 93 can be applied on the hard releasing film 92a before the intermediate panels 8 are disposed, so that the intermediate panels 8 can be embedded in the resin material 93. Alternatively, the resin material 93 can be applied in the gap "g" after the intermediate panels 8 are disposed. A lower surface 931 of the resin material 93 is at a level higher than an upper surface (i.e. the first surface 61) of the second dielectric layer 6. In a subsequent stage similar to Figure 27 the stage shown in

[0171] the stages explained in Figures 22 to 25 the stages shown in Figure 2 the stages explained in Figure 2 and 3 the substrate panel structure 1 shown in. The substrate panel structure 1 can then be subjected to, e.g. Figure 26 and 3 the substrate panel structure 1 shown in. The substrate panel structure 1 can then be subjected to, e.g. Figure 12 other stages of the stages shown in Figure 28 the packaging unit 7 shown in

[0172] Figure 4 and 29 A manufacturing process according to some embodiments of the present application is explained. In some embodiments, the manufacturing process is used for manufacturing, e.g. Figure 12 the substrate panel structure 1 shown inFigures 19 to 20 The encapsulation unit of the package unit 7 shown in Figure 28 The initial stage of the illustrated process is the same as, or similar to, the stage illustrated in Figure 20 The stage illustrated in Figure 28 The stage following the stage illustrated in

[0173] Figure 21 The stage shown in is similar to the stage shown in Figure 28 The stage shown in is similar to the stage shown in Figure 21 As shown in, the main carrier 91 comprises a soft release film 92b having a thickness greater than the thickness of the soft release film 92 shown in Figure 22 The lower surface 921b of the soft release film 92b is substantially coplanar with the lower surface of the second dielectric layer 6 (i.e. the second surface 62). In a subsequent stage similar to the stage shown in Figure 4 In a subsequent stage similar to the stage shown in Figure 28 The stage shown in is similar to the stage shown in

[0174] The stage following the stage shown in Figures 22 to 25 The stage following the stage shown in Figure 4 The stage following the stage illustrated in is similar to the process illustrated in Figure 4 The substrate face structure 1 shown in is thus formed. Each of the intermediate panels 8 corresponds to a respective one of the sub-panels 2.

[0175] Referring to Figure 29 The plurality of semiconductor dies 74 are then connected or mounted to the circuit structure 5 of each of the intermediate panels 8 (i.e. the sub-panels 2 in the substrate face structure 1). For example, at least one semiconductor die 74 is connected to each of the substrate units 20. The semiconductor dies 74 can comprise bumps 75 on a lower surface 741 of the semiconductor dies 74. The bumps 75 of the semiconductor dies 74 are electrically connected to the conductive vias 54 of the circuit structure 5 of the substrate units 20 via solder material 77 between the bumps 75 and the conductive vias 54. The solder material 77 can be made of tin, or another metal or combination of metals. A plurality of encapsulants 78 are then formed on each of the substrate units 20 to cover a respective one of the semiconductor dies 74. For example, the encapsulants 78 are between the second dielectric layer 6 and the semiconductor dies 74, and encapsulate the bumps 75 and the solder material 77. Each of the sub-panels 2 is then singulated. That is, each of the intermediate panels 8 (e.g. comprising the second dielectric layer 6 and the circuit structure 5), each of the first dielectric layers 3 and each of the redistribution layers 4 are singulated to form a plurality of package units, for example Figure 12The encapsulation unit 7 shown in the figure. For example, the edge of each sub-panel 2 can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0176] Figures 31 to 33 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is also used to manufacture, for example... Figure 5 The substrate panel structure 1a shown herein, and / or for example, the substrate panel structure of the substrate panel structure 1a ... shown herein. Figure 13 The packaging unit 7 shown is the packaging unit. The initial stage of the process described is related to... Figure 19 The stages described herein are the same or similar. Figure 31 illustrate Figure 19 The stage following the stage described in the text.

[0177] Figure 31 The stages shown in the text are similar to Figure 13 The stages shown herein, except as described below. Figure 32 As shown, the main carrier 91 includes a hard release membrane 92a rather than... Figure 32 The soft release film 92b is shown in the diagram. Therefore, the intermediate panel 8 is positioned on, rather than embedded in, the hard release film 92a. A gap "g" is defined between adjacent panels in the intermediate panel 8. A resin material 93a, for example photoresist, is applied to the gap "g" defined between adjacent panels in the intermediate panel 8. The resin material 93a can be applied to the hard release film 92a before the intermediate panel 8 is placed, so that the intermediate panel 8 can be embedded in the resin material 93a. Alternatively, the resin material 93a can be applied to the gap "g" after the intermediate panel 8 is placed. The lower surface 931a of the resin material 93a is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. Similar to... Figure 32 In a subsequent stage shown, the lower surface 931a of the resin material 93a contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6, as shown... Figure 22 As shown in the image.

[0178] The process described is in Figure 5 The stages shown in the text are similar to the stages that follow. Figure 5 The process described in the document thus forms Figure 32 The substrate face structure 1a is shown in the figure. Then, the... Figures 22 to 25 The substrate face structure 1a shown in the figure is used for example Figure 5 Other stages shown in the diagram are used to form multiple packaging units, such as... Figure 33 The packaging unit 7 shown in the image.

[0179] Figure 13 A manufacturing process according to some embodiments of the application is illustrated. In some embodiments, the manufacturing process is for manufacturing, for example Figure 34 a substrate panel structure as illustrated in Figure 5 a packaging unit as illustrated in Figure 13 The initial stages of the illustrated process are the same, or similar, to the stages illustrated in Figure 19 A stage following the stages illustrated in Figure 34 A stage following the stages illustrated in

[0180] Referring to Figure 31 , a circuit structure 5 is formed on the seed layer (e.g., copper layer 84). A first surface 57 of the circuit structure 5 contacts the seed layer (e.g., copper layer 84). For example, the material of the circuit structure 5 can be, for example, an electrically conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one electrically conductive pad 53 and at least one trace 55. The electrically conductive pad 53 and the trace 55 can be formed integrally and simultaneously. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm. Thus, an intermediate panel 8c is formed. The intermediate panel 8c includes a plurality of panel units 80c connected to one another. Each of the panel units 80c corresponds to a packaging unit, such as Figure 34 the packaging unit 7c illustrated in

[0181] Referring to Figure 32 , a main carrier 91 is provided. The main carrier 91 includes a soft release film 92 positioned thereon. The intermediate panel 8c is disposed on the main carrier 91 and is partially embedded in the soft release film 92. A lower surface 921 of the soft release film 92 is at a level higher than a first surface 57 of the circuit structure 5. As illustrated in Figure 34 , the first surface 57 of the circuit structure 5 is an upper surface. The intermediate panel 8c are spaced apart from one another, and a gap “g” is defined between two adjacent ones of the intermediate panel 8c. As illustrated in Figure 32 , an intermediate carrier 81 is positioned between the main carrier 91 and the circuit structure 5. In a subsequent stage similar to the stage illustrated in Figure 22 , the lower surface 921 of the soft release film 92 contacts an upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is at a level higher than an upper surface (i.e., first surface 57) of the circuit structure 5, as illustrated in Figure 5 . Furthermore, a first dielectric layer 3 formed on each of the intermediate panel 8c contacts the seed layer (e.g., copper layer 84), and thus an upper surface (i.e., first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., first surface 57) of the circuit structure 5, as illustrated in Figure 5 .

[0182] A stage following the stages illustrated in Figure 34The stages following those illustrated in Figures 22 to 25 The process of the stages illustrated in Figure 5 The substrate panel structure lb illustrated in. Each of the intermediate panels 8c corresponds to a respective one of the sub-panels 2c.

[0183] Referring to Figure 5 The plurality of semiconductor dies 74 is then connected or mounted to the circuitry 5 of each of the intermediate panels 8c (i.e., the sub-panels 2c in the substrate panel structure lb). For example, at least one semiconductor die 74 is connected to each of the substrate units 20c. The semiconductor dies 74 can include bumps 75 on a lower surface 741 of the semiconductor dies 74. The bumps 75 of the semiconductor dies 74 are electrically connected to the conductive pads 53 of the circuitry 5 of the substrate units 20c via solder material 77 between the bumps 75 and the conductive pads 53. The solder material 77 can be made of tin, or another metal or combination of metals. A plurality of encapsulants 78 is then formed on each of the substrate units 20c to cover a respective one of the semiconductor dies 74. For example, the encapsulants 78 are between the first dielectric layers 3 and the semiconductor dies 74, and cover and encapsulate the bumps 75, the solder material 77, and portions of the circuitry 5. Each of the singulated sub-panels 2c is then singulated. That is, each of the intermediate panels 8c (e.g., including the circuitry 5), each of the first dielectric layers 3, and each of the redistribution layers 4 are singulated to form a plurality of package units, e.g., Figure 33 The package units 7c illustrated in. For example, edges of each of the sub-panels 2c can be cut along the side surfaces 23 to remove portions of the dielectric portions 14 and the portions 254 of the protective layers 25 during the singulation process.

[0184] Figure 13 A manufacturing process according to some embodiments of the application is described. In some embodiments, the manufacturing process is also used to manufacture, for example, Figure 35 The substrate panel structure lb illustrated in. For example, the substrate panel structure lb illustrated in Figure 6 The package units 7c illustrated in. For example, the package units 7c illustrated in Figure 13 and 31 The stages following those illustrated in Figure 19 The stages following those illustrated in Figure 35 The stages following those illustrated in

[0185] Figure 31 The stages following those illustrated in Figure 35 The stages following those illustrated in, except that, as illustrated in Figure 32 The main carrier 91 includes the hard release film 92a instead of the hard release film 92b illustrated in Figure 35The soft release film 92 is shown in FIG. 8B. The intermediate panels 8c are positioned on the hard release film 92a, rather than being embedded therein. A gap "g" is defined between adjacent two of the intermediate panels 8c. The resin material 93 (e.g., photoresist) is applied in the gap "g" defined between adjacent two of the intermediate panels 8c. The resin material 93 can be applied on the hard release film 92a before the intermediate panels 8c are disposed, such that the intermediate panels 8c can be embedded in the resin material 93. Alternatively, the resin material 93 can be applied in the gap "g" after the intermediate panels 8c are disposed. A lower surface 931 of the resin material 93 is at a level higher than an upper surface (i.e., the first surface 57) of the circuit structure 5. In a stage similar to the stage shown in FIG. 8A, the lower surface 931 of the resin material 93 contacts the upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8B. In addition, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts the seed layer (e.g., the copper layer 84), thus the upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8B. Figure 32 In a stage subsequent to the stage shown in FIG. 8B, the lower surface 931 of the resin material 93 contacts the upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8C. In addition, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts the seed layer (e.g., the copper layer 84), thus the upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8C. Figure 22 In a stage subsequent to the stage shown in FIG. 8B, the lower surface 931 of the resin material 93 contacts the upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8C. In addition, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts the seed layer (e.g., the copper layer 84), thus the upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8C. Figure 6 In a stage subsequent to the stage shown in FIG. 8B, the lower surface 931 of the resin material 93 contacts the upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8C. In addition, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts the seed layer (e.g., the copper layer 84), thus the upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 8C.

[0186] The stages of the process described above are shown in FIG. 8D. Figure 6 The stages of the process described above are shown in FIG. 8D. Figure 35 The stages of the process described above are shown in FIG. 8D. Figures 22 to 25 The stages of the process described above are shown in FIG. 8D. Figure 6 The stages of the process described above are shown in FIG. 8D. Figure 36 The stages of the process described above are shown in FIG. 8D. Figure 13 The stages of the process described above are shown in FIG. 8D.

[0187] Figure 37 The stages of the process described above are shown in FIG. 8D. 36 A process for manufacturing, e.g., a substrate panel structure such as the substrate panel structure 1c shown in FIG. 9A, and / or a package unit such as the package unit 7c shown in FIG. 9B, according to some embodiments of the present application is described. In some embodiments, the process is used for manufacturing, e.g., a substrate panel structure such as the substrate panel structure 1c shown in FIG. 9A, and / or a package unit such as the package unit 7c shown in FIG. 9B. Figure 6 The stages of the process described above are shown in FIG. 9B. Figure 13 The stages of the process described above are shown in FIG. 9B. Figure 19 The stages of the process described above are shown in FIG. 9B. 31 The stages of the process described above are shown in FIG. 9B. Figure 27 The stages of the process described above are shown in FIG. 9B. Figure 31 The stages of the process described above are shown in FIG. 9B.

[0188] Figure 37 The stages of the process described above are shown in FIG. 9B. Figure 35 The stages of the process described above are shown in FIG. 9B. Figure 37As shown in FIG. 9, the main carrier 91 includes a soft release film 92b having a thickness greater than the thickness of the soft release film 92 shown in FIG. 8. Figure 35 The thickness of the soft release film 92b shown in FIG. 9. The lower surface 921b of the soft release film 92b is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5. In a stage similar to the stage shown in FIG. 8, Figure 22 the lower surface 921b of the soft release film 92b contacts the upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in FIG. 10. Figure 6 As shown in FIG. 10. Furthermore, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts the seed layer (e.g., the copper layer 84), thus the upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5 and the upper surface 141 of the dielectric portion 14, as shown in FIG. 10. Figure 6 As shown in FIG. 10.

[0189] The stage following the stage shown in FIG. 11 is similar to the stage shown in FIG. 10, thus the substrate panel structure 1c shown in FIG. 11 is formed. Figure 37 The stage following the stage shown in FIG. 11 is similar to the stage shown in FIG. 10, thus the substrate panel structure 1c shown in FIG. 11 is formed. Figures 22 to 25 The stage following the stage shown in FIG. 11 is similar to the stage shown in FIG. 10, thus the substrate panel structure 1c shown in FIG. 11 is formed. Figure 6 As shown in FIG. 11. Each of the intermediate panels 8c corresponds to a respective one of the sub-panels 2c.

[0190] Referring to FIG. 12, Figure 6 The plurality of semiconductor dies 74 are then connected or mounted to the circuit structure 5 of each of the intermediate panels 8c (i.e., the sub-panels 2c in the substrate panel structure 1c). For example, at least one semiconductor die 74 is connected to each of the substrate units 20c. The semiconductor dies 74 can include bumps 75 positioned on a lower surface 741 of the semiconductor dies 74. The bumps 75 of the semiconductor dies 74 are electrically connected to the conductive pads 53 of the circuit structure 5 of the substrate units 20c via solder material 77 positioned between the bumps 75 and the conductive pads 53. The solder material 77 can be made of tin, or another metal or combination of metals. A plurality of encapsulants 78 are then formed on each of the substrate units 20c to cover a respective one of the semiconductor dies 74. For example, the encapsulants 78 are positioned between the first dielectric layer 3 and the semiconductor dies 74, and cover and encapsulate the bumps 75, the solder material 77, and portions of the circuit structure 5. Each of the sub-panels 2c is then singulated. That is, each of the intermediate panels 8c (e.g., including the circuit structure 5), each of the first dielectric layers 3, and each of the redistribution layers 4 are singulated to form a plurality of package units, for example, the package units 7c shown in FIG. 13. Figure 36 For example, the edges of each sub-panel 2c can be cut along the side surfaces 23 to remove portions 254 of the dielectric portion 14 and the protection layer 25 during the singulation process.

[0191] Figure 13 A manufacturing process according to some embodiments of the application is illustrated. In some embodiments, the manufacturing process is also used to manufacture a substrate panel structure, such as the substrate panel structure 1c shown in Figures 38 to 41 , and / or a packaging unit, such as the packaging unit 7c shown in Figure 7 . The initial stages of the illustrated process are the same as, or similar to, the stages illustrated in Figure 14 and 31 . Figure 19 Stages following the stages illustrated in Figure 38 are illustrated.

[0192] Figure 31 The stages shown in are similar to the stages shown in Figure 38 , except that, as shown in Figure 14 , the main carrier 91 comprises a hard release film 92a instead of the soft release film 92b shown in Figure 31 . Thus, the intermediate panels 8c are positioned on the hard release film 92a instead of being embedded therein. A gap “g” is defined between adjacent two of the intermediate panels 8c. A resin material 93a (e.g., a photoresist) is applied in the gap “g” defined between adjacent two of the intermediate panels 8c. The resin material 93a can be applied on the hard release film 92a before the intermediate panels 8c are disposed, such that the intermediate panels 8c can be embedded in the resin material 93a. Alternatively, the resin material 93a can be applied in the gap “g” after the intermediate panels 8c are disposed. A lower surface 931a of the resin material 93a is substantially coplanar with an upper surface (i.e., the first surface 57) of the circuit structure 5. In a subsequent stage similar to the stage shown in Figure 38 , the lower surface 931a of the resin material 93a contacts an upper surface 141 of the dielectric portion 14. Thus, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5, as shown in Figure 27 . Furthermore, a first dielectric layer 3 formed on each of the intermediate panels 8c contacts the seed layer (e.g., the copper layer 84), thus an upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5 and the upper surface 141 of the dielectric portion 14, as shown in Figure 39 .

[0193] The stages following the stage shown in Figure 40 of the illustrated process are similar to the stages illustrated in Figure 22 , thus forming the substrate panel structure 1c shown in Figure 23 . Further stages can be performed on the substrate panel structure 1c shown in Figure 24 , such as the stages shown in Figure 24The stages shown in FIG. 8A form a plurality of package units, such as Figure 7 The package units 7c shown in FIG. 8A.

[0194] Figure 40 A manufacturing process according to some embodiments of the present application is described. In some embodiments, the manufacturing process is for manufacturing, for example, a substrate panel structure 1d shown in FIG. 8A, and / or a package unit 7d shown in FIG. 8B. The initial stages of the described process are the same as, or similar to, the stages described in Figure 40 Figure 7 The package units 7d shown in FIG. 8B. Figure 40 and 31 The stages described in FIG. 8B are the same as, or similar to, the stages described in Figure 41 The stages described in FIG. 8B are the same as, or similar to, the stages described in Figure 14 The stages after the stages described in FIG. 8B are described.

[0195] Referring to FIG. 9A, a main carrier 91 is provided. The main carrier 91 includes a soft release film 92 positioned thereon. An intermediate panel 8d is disposed on the main carrier 91 and partially embedded in the soft release film 92. The intermediate panel 8d includes a plurality of panel units 80d connected to each other. Each of the panel units 80d corresponds to a package unit, such as the package units 7d shown in FIG. 8B. The formation of the intermediate panel 8d can be the same as, or similar to, the formation of the intermediate panel 8c shown in FIG. 8A. The circuit structure 5 of the intermediate panel 8d is between the main carrier 91 and the intermediate carrier 81. The circuit structure 5 is embedded in the soft release film 92. A first surface 57 of the circuit structure 5 is a lower surface, as shown in FIG. 8A. A lower surface 921 of the soft release film 92 is substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structure 5. The intermediate panel 8d are spaced apart from each other, and a gap “g” is defined between two adjacent ones of the intermediate panel 8d. In another manufacturing process, the soft release film 92 can be replaced with a hard release film 92a and a resin material 93, such as those shown in FIG. 8B. Figure 40 Figure 41 Figure 14 Referring to FIG. 9B, the intermediate carrier 81, including the release film 82, is removed so that the seed layers (e.g., the titanium layer 83 and the copper layer 84) are exposed. Figures 42 to 48 Figure 9 Referring to FIG. 9C, the seed layers (e.g., the titanium layer 83 and the copper layer 84) can be removed by, for example, etching. Then, a dielectric material can be provided on the main carrier 91 to form a plurality of first dielectric layers 3 and one dielectric portion 14. The formation of the first dielectric layers 3 and the dielectric portion 14 can be similar to the formation of the first dielectric layers 3 and the dielectric portion 14 described in FIG. 8B.

[0196] Referring to FIG. 9D, the main carrier 91 is removed so that the first dielectric layers 3 and the dielectric portion 14 are exposed. Figure 15 Referring to FIG. 9E, the first dielectric layers 3 and the dielectric portion 14 are separated from each other to form a plurality of package units 7d, such as those shown in FIG. 8B.

[0197] Figure 42 Referring to FIG. 10A, a main carrier 91 is provided. The main carrier 91 includes a soft release film 92 positioned thereon. An intermediate panel 8d is disposed on the main carrier 91 and partially embedded in the soft release film 92. The intermediate panel 8d includes a plurality of panel units 80d connected to each other. Each of the panel units 80d corresponds to a package unit, such as the package units 7d shown in FIG. 8B. The formation of the intermediate panel 8d can be the same as, or similar to, the formation of the intermediate panel 8c shown in FIG. 8A. The circuit structure 5 of the intermediate panel 8d is between the main carrier 91 and the intermediate carrier 81. The circuit structure 5 is embedded in the soft release film 92. A first surface 57 of the circuit structure 5 is a lower surface, as shown in FIG. 8A. A lower surface 921 of the soft release film 92 is substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structure 5. The intermediate panel 8d are spaced apart from each other, and a gap “g” is defined between two adjacent ones of the intermediate panel 8d. In another manufacturing process, the soft release film 92 can be replaced with a hard release film 92a and a resin material 93, such as those shown in FIG. 8B. Figure 42 ​​​​​those shown in FIG. 1. Each of the first dielectric layers 3 is on a respective one of the intermediate panels 8d and contacts the soft release film 92. Thus, the upper surface (i.e., the first surface 31) of the first dielectric layers 3 is substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structures 5. The dielectric portions 14 are in the gaps "g" between two adjacent intermediate panels 8d and the soft release film 92. The upper surface 141 of the dielectric portions 14 is thus substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structures 5 and / or the upper surface (i.e., the first surface 31) of the first dielectric layers 3.

[0198] Then, at least one via 30 is formed through each of the first dielectric layers 3, by, for example, lithography or drilling. The via 30 exposes a portion of the circuit structure 5, such as a conductive pad 53 of the circuit structure 5. Then, a plurality of redistribution layers 4 is formed on the first dielectric layers 3, and each of the redistribution layers 4 is electrically connected to a respective one of the circuit structures 5 of the intermediate panels 8d. The formation of the vias 30 of the first dielectric layers 3 and the redistribution layers 4 can be similar to those shown in FIG. 1. Figure 43

[0199] Then, a protective layer 25 is formed on the first dielectric layers 3 and covers the redistribution layers 4. The formation of the protective layer 25 can be similar to those shown in FIG. 1. Figure 15 Figure 44 The protective layer 25 has a first surface 251 and a second surface 252 opposite the first surface 251. The first surface 251 contacts the second surface 32 of the first dielectric layers 3. In some embodiments, the protective layer 25 further includes a portion 254 that extends into the gaps "g" between the intermediate panels 8d and is on the dielectric portions 14. The protective layer 25 covers the redistribution layers 4, and at least portions of the redistribution layers 4, such as the conductive pads 44, are exposed from the protective layer 25 for external connections. Then, at least one solder connector 26 can be formed on the exposed portions of the redistribution layers 4, such as the conductive pads 44 of the redistribution layers 4. The formation of the protective layer 25 and the solder connectors 26 can be similar to those shown in FIG. 1.

[0200] Then, the main carrier 91, including the soft release layer 92, is removed, thereby forming a substrate panel structure 2d shown in FIG. 1. Each of the intermediate panels 8d corresponds to a respective one of the sub-panels 2d. In an alternative manufacturing process, the main carrier 91 can be removed before the solder connectors 26 are formed, thereby forming a structure shown in FIG. 1. Figure 27 Figure 45 The structure shown in FIG. 1 includes a plurality of sub-panels 2d, each of which includes a circuit structure 5, a first dielectric layer 3 on the circuit structure 5, and a redistribution layer 4 on the first dielectric layer 3. The circuit structures 5 are electrically connected to each other through the first dielectric layers 3 and the redistribution layers 4. Figure 46 The structure shown in FIG. 1 includes a plurality of sub-panels 2d, each of which includes a circuit structure 5, a first dielectric layer 3 on the circuit structure 5, and a redistribution layer 4 on the first dielectric layer 3. The circuit structures 5 are electrically connected to each other through the first dielectric layers 3 and the redistribution layers 4.​​​Figure 46 The sub-panel 2d shown is similar to sub-panel 2d', but without solder connector 26. Figure 47 The structure shown can also be used as a substrate panel structure.

[0201] refer to Figure 9 Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8d (i.e., sub-panels 2d in the substrate panel structure 1d). For example, at least one semiconductor die 74 is connected to each of the substrate units 20d. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to conductive vias 54 of the circuit structure 5 of the substrate unit 20d via solder material 77, which is located between the bumps 75 and the conductive vias 54. The solder material 77 may be made of tin, or another metal or combination of metals. Then, an encapsulant 78 is formed on and covers each of the first dielectric layer 3 and the dielectric portions 14, and covers the semiconductor die 74. The encapsulant 78 covers and encapsulates the bumps 75, the solder material 77, and portions of the circuit structure 5. Then, each of the sub-panels 2d is monomerized. That is, each of the monomerized intermediate panels 8d (e.g., containing circuit structure 5), each of the first dielectric layer 3, each of the redistribution layer 4, and the encapsulant 78 form a plurality of encapsulation units, for example Figure 48 The packaging unit 7d shown in the figure. For example, the edge of each sub-panel 2d can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0202] Similarly, it can also be used for Figure 15 The structure shown in the document performs the above-mentioned stages (for example, refer to...). Figures 49 to 54 (stage) to form Figure 10 The encapsulation unit 7d is shown in the figure. In some embodiments, the solder connector 26 may be formed after the encapsulation agent 78 is formed.

[0203] Figure 16 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture a substrate panel structure, for example... Figure 19 The substrate panel structure 2f shown in the figure, and / or Figure 49 The packaging unit 7f shown in the figure is the packaging unit.

[0204] refer to ​ An intermediate carrier 81 is provided. The intermediate carrier 81 may include a release membrane 82 disposed thereon. A metal layer 85 is formed or disposed on the intermediate carrier 81. ​As shown in the middle, the metal layer 85 can include a seed layer 851 and a conductive layer 852 sequentially on the release film 82 of the intermediate carrier 81. For example, the seed layer 851 can be formed by sputtering, and the conductive layer 852 can be formed by electroplating. The material of the seed layer 851 can be, for example, titanium or copper. In some embodiments, the seed layer 851 can include a titanium layer and a copper layer. For example, the material of the conductive layer 852 can be a conductive metal, such as copper, or another metal or combination of metals. However, in other embodiments, the metal layer 85 can be a metal foil that is pressed and attached to the release film 82.

[0205] Reference is made to ​ A second dielectric layer 6 is formed on the metal layer 85, for example, on the conductive layer 852 of the metal layer 85. The second dielectric layer 6 has a first surface 61, a second surface 62 opposite the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. The first surface 61 contacts the conductive layer 852 of the metal layer 85. The second dielectric layer 6 defines at least one via 60 through the second dielectric layer 6 and between the first surface 61 and the second surface 62 to expose a portion of the conductive layer 852 of the metal layer 85. Then, a circuit structure 5 is formed on the second surface 62 of the second dielectric layer 6 and in the via 60 of the second dielectric layer 6. The circuit structure 5 includes a seed layer 51 and a conductive layer 52. The seed layer 51 is between the conductive layer 52 and the second dielectric layer 6, and in the via 60 between the conductive layer 52 and the conductive layer 852 of the metal layer 85. The material of the seed layer 51 can be, for example, titanium or copper. In some embodiments, the seed layer 51 can include a titanium layer and a copper layer. For example, the material of the conductive layer 52 can be a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. The conductive pad 53, the conductive via 54, and the trace 55 can be formed integrally and simultaneously. In some embodiments, the conductive via 54 is on and integrally formed with the conductive pad 53. The conductive via 54 of the circuit structure 5 can be in the via 60 of the second dielectric layer 6 to connect the metal layer 85. That is, each of the circuit structures 5 includes a conductive via 54 in the via 60 of a respective one of the second dielectric layers 6. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm. Thus, the intermediate panel 8f is formed. The intermediate panel 8f includes a plurality of panel units 80f connected to each other. Each of the panel units 80f corresponds to a package unit, such as ​ the package unit 7f shown in the middle.

[0206] Reference is made to ​, the main carrier 91 is provided. The main carrier 91 comprises a soft release film 92 disposed thereon. The intermediate panels 8f are disposed on the main carrier 91 and partially embedded in the soft release film 92. The circuit structures 5 of the intermediate panels 8f are located between the main carrier 91 and the intermediate carrier 81. The circuit structures 5 and the second dielectric layers 6 are embedded in the soft release film 92. The upper surface 921 of the soft release film 92 is at a level lower than the upper surface of the second dielectric layers 6 (i.e., the first surface 61) and higher than the lower surface of the second dielectric layers 6 (i.e., the second surface 62). The intermediate panels 8f are spaced apart from each other, and a gap "g" is defined between two adjacent ones of the intermediate panels 8f. In another manufacturing process, the soft release film 92 can be replaced with a hard release film 92a and a resin material 93, as shown in ​

[0207] Referring to ​ , the intermediate carrier 81, including the release film 82, is removed so that the metal layers 85 are exposed. Then, the metal layers 85 are patterned to form the circuit layers 27 on the first surface 61 of the second dielectric layers 6. The circuit layers 27 can include seed layers 271 formed from the seed layers 851 of the metal layers 85, and conductive layers 272 formed from the conductive layers 852 of the metal layers 85. The circuit layers 27 can include at least one conductive pad 274, and can further include at least one trace (not shown). The conductive vias 54 of the circuit structures 5 contact and electrically connect the circuit layers 27.

[0208] Referring to ​ , a dielectric material is provided on the main carrier 91 to form a plurality of first dielectric layers 3 and dielectric portions 14, the dielectric material covering the intermediate panels 8f and the soft release film 92. Each of the first dielectric layers 3 is on a respective one of the intermediate panels 8f. The dielectric portions 14 are in the gaps "g" between two adjacent intermediate panels 8f and on the soft release film 92. The dielectric portions 14 are between and connect the first dielectric layers 3. The first dielectric layers 3 and the dielectric portions 14 are simultaneously and integrally formed as an integral structure. That is, there is no boundary or interface between the dielectric portions 14 and the first dielectric layers 3. The dielectric material can be an insulating material or a dielectric material, for example, polypropylene (PP). It should be noted that the dielectric material can include or be formed from a cured photoimageable dielectric (PID) material, for example, an epoxy resin including a photoinitiator or a polyimide (PI). Thus, the first dielectric layers 3 and the dielectric portions 14 can be made of, or can include, an insulating material or a dielectric material, for example, polypropylene (PP), or can be formed from a cured photoimageable dielectric (PID) material, for example, an epoxy resin including a photoinitiator or a polyimide (PI).

[0209] The first dielectric layers 3 include first surfaces 31 and second surfaces 32 opposite the first surfaces 31. As ​ ​As shown in the middle, the first surface 31 is an upper surface, and the second surface 32 is a lower surface. The first dielectric layer 3 is on the second dielectric layer 6 and covers the circuit layer 27. The lower surface (i.e., the second surface 32) of the first dielectric layer 3 contacts the upper surface (i.e., the first surface 61) of the second dielectric layer 6.

[0210] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. The lower surface 142 contacts the upper surface 921 of the soft release film 92, and is thus at a level lower than the lower surface (i.e., the second surface 32) of the first dielectric layer 37 and the upper surface (i.e., the first surface 61) of the second dielectric layer 6, while being at a level higher than the lower surface (i.e., the second surface 62) of the second dielectric layer 6. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. The side surface 143 can contact and be substantially coplanar with the side surface 63 of the second dielectric layer 6.

[0211] Referring to ​ At least one via 30 is formed through each of the first dielectric layers 3 by, for example, photolithography or drilling. The via 30 exposes a portion of the circuit layer 27, such as a conductive pad 274 of the circuit layer 27. Then, a plurality of redistribution layers 4 is formed on the first dielectric layers 3, and each of the redistribution layers 4 is electrically connected to a respective one of the circuit structures 5 via a respective one of the circuit layers 27 of the intermediate panel 8f. The redistribution layers 4 are on the first dielectric layers 3 and in the via 30. The redistribution layers 4 can include a seed layer 41 and a conductive layer 42. The seed layer 41 is between the conductive layer 42 and the first dielectric layer 3. The material of the seed layer 41 can be, for example, titanium or copper. In some embodiments, the seed layer 41 can include a titanium layer and a copper layer. For example, the material of the conductive layer 42 can be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 can be omitted. The redistribution layers 4 can include at least one conductive via 43, and can further include at least one trace (not shown). The conductive via 43 is in the via 30 and contacts and electrically connects the circuit layer 27. A solder material 77 is formed on or is on the conductive via 43 of the redistribution layer 4 for external connection. The solder material 77 can be made of tin, or another metal or combination of metals.

[0212] Then, the main carrier 91, including the soft release layer 92, is removed. A protective layer 25 is formed on the second dielectric layer 6 and covering the circuit structure 5. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The protective layer 25 exposes portions of the circuit structure 5, such as conductive pads 53 of the circuit structure 5, for external connections. The protective layer 25 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or a polyimide (PI), or a solder resist layer. Then, at least one solder connector 26 is formed on the exposed portions of the circuit structure 5, such as the conductive pads 53 of the circuit structure 5. The material of the solder connector 26 can be a conductive metal, such as tin, or another metal or combination of metals. Thus, a package unit 7 is formed as shown in ​ The substrate panel structure 1f is shown in FIG. 1f. Each of the intermediate panels 8f corresponds to a respective one of the sub-panels 2f.

[0213] Referring to ​ Then, a plurality of semiconductor dies 74 are connected or mounted to the redistribution layer 4 of each of the intermediate panels 8f (i.e., the sub-panels 2f in the substrate panel structure 1f). For example, at least one semiconductor die 74 is connected to each of the substrate units 20f. The semiconductor die 74 can include bumps 75 on a lower surface 741 of the semiconductor die 74, and UBMs 76 on the bumps 75. The UBM 76 can include a first layer 761 and a second layer 762 sequentially on the bump 75. For example, the material of the first layer 761 can be nickel, and the material of the second layer 762 can be palladium, but not limited thereto. The UBM 76 of the semiconductor die 74 is connected to the redistribution layer 4 of the substrate unit 20f, such as the conductive via 43 of the redistribution layer 4, by a solder material 77. Then, an encapsulant 78 is formed on and covering each of the first dielectric layer 3 and the dielectric portion 14, and covering the semiconductor die 74. For example, the encapsulant 78 is on the first dielectric layer 3 of the substrate unit 20f, and covers and encapsulates the semiconductor die 74, the bumps 75 and the UBMs 76 of the semiconductor die 74, the solder material 77, and the redistribution layer 4 of the substrate unit 20f. The encapsulant 78 can be an underfill or a molding compound. Then, each of the sub-panels 2f is singulated. That is, each of the intermediate panels 8f (e.g., including the circuit layer 27, the second dielectric layer 6, and the circuit structure 5), each of the first dielectric layer 3, each of the redistribution layer 4, and the encapsulant 78 are singulated, forming a plurality of package units, such as ​ The package units 7f are shown in FIG. 1f. For example, the edges of each sub-panel 2f can be cut along the side surface 23 to remove portions 254 of the dielectric portion 14 and the protective layer 25 during the singulation process.

[0214] In an alternative manufacturing process, the main carrier 91 can be removed after the semiconductor die 74 is connected to the circuit structure 5, and the encapsulant 78 is formed. Then, the protective layer 25 and the solder connectors 26 can be formed after the encapsulant 78 is formed and the main carrier 91 is removed.

[0215] ​ A manufacturing process according to some embodiments of the present application is illustrated. In some embodiments, the manufacturing process is for manufacturing, for example ​ a substrate panel structure of the substrate panel structure lg shown in ​ , and / or a package unit, for example the package unit 7g shown in ​ The initial stages of the illustrated process are the same, or similar, to the stages illustrated in ​ The stages following the stages illustrated in Figure 19 are illustrated.

[0216] Referring to Figure 49 , a patterned photoresist 86 is formed or disposed on the photoresist on the seed layer (e.g., the copper layer 84). The patterned photoresist 86 has an upper surface 861 and defines a plurality of openings 860. Then, the circuit structure 5 is formed in the openings 860 of the patterned photoresist 86 and on the seed layer (e.g., the copper layer 84). For example, the material of the circuit structure 5 can be, for example, an electrically conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one electrically conductive pad 53 and at least one trace 55. The electrically conductive pad 53 and the trace 55 can be formed integrally and simultaneously. The trace 55 has an upper surface 551 that is at a level lower than the upper surface 861 of the patterned photoresist 86. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm. Thus, an intermediate panel 8g is formed. The intermediate panel 8g includes a plurality of panel units 80g connected to each other. Each of the panel units 80g corresponds to a package unit, for example Figure 16 the package unit 7g shown in

[0217] Referring to Figure 50 , the main carrier 91 is provided. The main carrier 91 includes a soft release film 92 on it. The intermediate panel 8g is disposed on the main carrier 91 and partially embedded in the soft release film 92. As shown in Figure 50 , the intermediate carrier 81 is located between the main carrier 91 and the circuit structure 5. The upper surface 921 of the soft release film 92 is at a level lower than the upper surface 86 of the patterned photoresist 86. The intermediate panel 8g is spaced apart from each other, and a gap "g" is defined between two adjacent ones of the intermediate panel 8g.

[0218] Referring to Figure 51The plurality of semiconductor dies 74 are then connected or mounted to the circuitry 5 of each of the intermediate panels 8g. For example, at least one semiconductor die 74 is connected to each panel unit 80g. The semiconductor dies 74 can include bumps 75 on a lower surface 741 of the semiconductor dies 74, and UBMs 76 on the bumps 75. The material of the bumps 75 can be copper. The UBMs 76 can include a first layer 761, a second layer 762, and a third layer 763 sequentially on the bumps 75. For example, the material of the first layer 761 can be nickel, the material of the second layer 762 can be palladium, and the material of the third layer 763 can be gold, but not limited thereto. The UBMs 76 of the semiconductor dies 74 can be electrically connected to the conductive pads 53 of the circuitry 5 through a solder material 77 therebetween. The solder material 77 can be made of tin, or another metal or combination of metals. An encapsulant 78 is then formed on the patterned photoresist 85, and covers and encapsulates the semiconductor dies 74 on each of the intermediate panels 8g. A first lower surface 781 of the encapsulant is substantially coplanar with an upper surface 861 of the patterned photoresist 86. The encapsulant 78 can further include a portion 784 in a gap “g” between the intermediate panels 8g and contacting an upper surface 921 of the soft release film 92. A second lower surface 782 of the portion 784 in the gap “g” is substantially coplanar with the upper surface 921 of the soft release film 92. The second lower surface 782 is at a level lower than the first lower surface 781. The encapsulant 78 can be a molding compound.

[0219] Referring to Figure 52 The main carrier 9, including the soft release layer 921, is then removed. Then, the intermediate carrier 81, including the release film 82, is removed, such that the seed layer (e.g., the titanium layer 83) and the second lower surface 782 of the encapsulant 78 are exposed.

[0220] Referring to Figure 53 The seed layer (e.g., the titanium layer 83 and the copper layer 84) is removed by, for example, etching. Then, the patterned photoresist 86 is removed by, for example, stripping. The first lower surface 781 of the encapsulant 78 and the circuitry 5 are thus exposed.

[0221] Referring to Figure 54The dielectric material is provided on the encapsulant 78 and the intermediate panels 8g (e.g., the circuit structure 5) to form a plurality of first dielectric layers 3 and one dielectric portion 14. The dielectric material covers the intermediate panels 8g (e.g., the circuit structure 5). Each of the first dielectric layers 3 corresponds to a respective one of the intermediate panels 8g. The dielectric portion 14 is located in the gap “g” between two adjacent intermediate panels 8g and on the portion 784 of the encapsulant 78 in the gap “g”. The dielectric portion 14 is located between and connects the first dielectric layers 3. The first dielectric layers 3 and the dielectric portion 14 are simultaneously and integrally formed as a unitary structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layers 3. The dielectric material can be an insulating material or a dielectric material such as, for example, polypropylene (PP). It is noted that the dielectric material can comprise or be formed of a cured photoimageable dielectric (PID) material such as, for example, an epoxy resin including a photoinitiator or a polyimide (PI). Thus, the first dielectric layers 3 and the dielectric portion 14 can be made of an insulating material or a dielectric material such as, for example, polypropylene (PP), or can comprise or be formed of a cured photoimageable dielectric (PID) material such as, for example, an epoxy resin including a photoinitiator or a polyimide (PI).

[0222] The first dielectric layer 3 comprises a first surface 31, a second surface 32 opposite the first surface 31, and a side surface 33 extending between the first surface 31 and the second surface 32. As shown in Figure 54 The first surface 31 is an upper surface and the second surface 32 is a lower surface. The upper surface of the first dielectric layer 3 (i.e., the first surface 31) is in contact with and substantially coplanar with the first lower surface 781 of the encapsulant 78, thus at a level higher than the upper surface 551 of the traces 55 of the circuit structure 5. The side surface 33 is in contact with the portion 784 of the encapsulant 78.

[0223] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least part of the side surface 143 is an imaginary surface or an imaginary plane. The upper surface 141 of the dielectric portion 14 is in contact with and substantially coplanar with the second lower surface 782 of the portion 784 of the encapsulant 78, thus at a level lower than the upper surface of the first dielectric layer 3 (i.e., the first surface 31). The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 32) of the first dielectric layer 3.

[0224] Then, at least one via 30 is formed through the first dielectric layer 3 such that a portion of the circuit structure 5, such as a conductive pad 53 of the circuit structure 5, is exposed in the via 30 and from the second surface 32 of the dielectric layer 3. Then, a redistribution layer 4 is formed electrically connected to the circuit structure 5. For example, the redistribution layer 4 includes at least one conductive via 43 positioned in the via 30 of the first dielectric layer 3 and embedded in the first dielectric layer 3. The conductive via 43 extends through the first dielectric layer 3 to contact and electrically connect to the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. In some embodiments, the redistribution layer 4 can further include at least one trace (not shown). For example, the material of the redistribution layer 4 can be a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, the line width / line space (L / S) of the redistribution layer 4 can be equal to or greater than 10 pm / 10 pm.

[0225] Then, at least one solder material 26a is formed or disposed on and electrically connected to the conductive via 43 of the redistribution layer 4. The solder material 26 can be a conductive metal, such as tin, or another metal or combination of metals. A UBM 46 can be disposed between the conductive via 43 and the solder connector 26. Then, a reflow process can be performed to form the solder material 26a into a solder connector 26, thus forming a substrate panel structure 1g as shown in FIG. 1G. Each of the intermediate panels 8g corresponds to a respective one of the sub-panels 2g. Then, each of the sub-panels 2g is singulated. That is, each of the intermediate panels 8g (e.g., the circuit structure 5), each of the first dielectric layers 3, each of the redistribution layers 4, and the encapsulant 78 is singulated, forming a plurality of package units, such as the package units 7g shown in FIG. 1G. Figure 10 Then, at least one solder material 26a is formed or disposed on and electrically connected to the conductive via 43 of the redistribution layer 4. The solder material 26 can be a conductive metal, such as tin, or another metal or combination of metals. A UBM 46 can be disposed between the conductive via 43 and the solder connector 26. Then, a reflow process can be performed to form the solder material 26a into a solder connector 26, thus forming a substrate panel structure 1g as shown in FIG. 1G. Each of the intermediate panels 8g corresponds to a respective one of the sub-panels 2g. Then, each of the sub-panels 2g is singulated. That is, each of the intermediate panels 8g (e.g., the circuit structure 5), each of the first dielectric layers 3, each of the redistribution layers 4, and the encapsulant 78 is singulated, forming a plurality of package units, such as the package units 7g shown in FIG. 1G. Figure 16 Then, at least one solder material 26a is formed or disposed on and electrically connected to the conductive via 43 of the redistribution layer 4. The solder material 26 can be a conductive metal, such as tin, or another metal or combination of metals. A UBM 46 can be disposed between the conductive via 43 and the solder connector 26. Then, a reflow process can be performed to form the solder material 26a into a solder connector 26, thus forming a substrate panel structure 1g as shown in FIG. 1G. Each of the intermediate panels 8g corresponds to a respective one of the sub-panels 2g. Then, each of the sub-panels 2g is singulated. That is, each of the intermediate panels 8g (e.g., the circuit structure 5), each of the first dielectric layers 3, each of the redistribution layers 4, and the encapsulant 78 is singulated, forming a plurality of package units, such as the package units 7g shown in FIG. 1G.

[0226] Figures 55 to 60 A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in Figure 11 A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in Figure 17 A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in Figure 19 A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in Figure 55 A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in Figure 19 A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in

[0227] A manufacturing process according to some embodiments of the present disclosure is described. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure, such as the substrate panel structure 1h shown in FIG. 1H, and / or a package unit, such as the package units 7h shown in FIG. 1H. The initial stages of the described process are the same as, or similar to, the stages described in Figure 55, a second dielectric layer 6 is formed on the seed layer (e.g., copper layer 84). The second dielectric layer 6 has a first surface 61, a second surface 62 opposite the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. As shown in Figure 55 , the first surface 61 is an upper surface and the second surface 62 is a lower surface. The second surface 62 contacts the seed layer (e.g., copper layer 84). The second dielectric layer 6 can be made of an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 6 can include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin including a photoinitiator or polyimide (PI). Then, a plurality of vias 60a are formed through the second dielectric layer 6 and between the first surface 61 and the second surface 62. A plurality of conductive pillars 28 are then formed in the vias 60a of the second dielectric layer 6 by, for example, electroplating. For example, the material of the conductive pillars 28 can be a conductive metal, such as copper, or another metal or combination of metals. Thus, an intermediate panel 8h is formed. The intermediate panel 8h includes a plurality of panel units 80h connected to one another. Each of the panel units 80h corresponds to a package unit, such as the package unit 7h shown in Figure 17

[0228] Referring to Figure 56 , a circuit structure 5 is formed adjacent to the first surface 61 of the second dielectric layer 6 and electrically connected to the conductive pillars 28. For example, as shown in Figure 56 , the circuit structure 5 is on the first surface 61 of the second dielectric layer 6, and portions of the circuit structure 5 can extend into the vias 60a to contact the conductive pillars 28. The circuit structure 5 can include a seed layer 51 and a conductive layer 52. The seed layer 51 is between the conductive layer 52 and the second dielectric layer 6, and between the conductive layer 52 and the conductive pillars 28. The material of the seed layer 51 can be, for example, titanium or copper. In some embodiments, the seed layer 51 can include a titanium layer and a copper layer. For example, the material of the conductive layer 52 can be a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 are formed integrally and simultaneously. In some embodiments, the L / S of the circuit structure 5 can be equal to or less than 2 pm / 2 pm. Forming the circuit layer 5 can include forming a patterned photoresist on the second dielectric layer 6, and forming the circuit layer 5 in the patterned photoresist and on the second dielectric layer 6. It should be noted that the patterned photoresist can be removed in the stage shown in Figure 56 , or can alternatively be removed after the intermediate panel 8h is disposed on the main carrier (e.g., the stage shown in Figure 57

[0229] Referring to Figure 57 ​​, the main carrier 91 is provided. The main carrier 91 includes a soft release film 92 disposed thereon. The middle panels 8h are disposed on the main carrier 91 and partially embedded in the soft release film 92. The middle carrier 81 is located between the main carrier 91 and the circuit structure 5. The upper surface 921 of the soft release film 92 is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. The middle panels 8h are spaced apart from each other, and a gap "g" is defined between two adjacent ones of the middle panels 8h.

[0230] Referring to Figure 58 The plurality of semiconductor dies 74 are then connected or mounted to the circuit structure 5 of each of the middle panels 8h. For example, at least one semiconductor die 74 is connected to each panel unit 80h. The semiconductor die 74 can include bumps 75 disposed on a lower surface 741 of the semiconductor die 74, and UBMs 76 disposed on the bumps 75. The material of the bumps 75 can be copper. The UBM 76 can include a first layer 761 and a second layer 762 disposed on the bumps 75 in sequence. For example, the material of the first layer 761 can be nickel, and the material of the second layer 762 can be palladium, but not limited thereto. The UBM 76 of the semiconductor die 74 can be electrically connected to the conductive pads 53 of the circuit structure 5 through a solder material 77 disposed therebetween. The solder material 77 can be made of tin, or another metal or combination of metals.

[0231] The encapsulant 78 is then formed on the second dielectric layer 6 and covers and encapsulates the semiconductor dies 74 on each of the middle panels 8h. The encapsulant 78 includes a portion 784 disposed in the gap "g" between two adjacent sub-panels 2h and on the soft release film 92. The lower surface 782 of the portion 784 of the encapsulant 78 is in contact with and substantially coplanar with the upper surface 921 of the soft release film 92, and thus, also substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. The encapsulant 78 can contact and cover the side surfaces 63 of the second dielectric layer 6. The encapsulant 78 can be a molding compound.

[0232] Referring to Figure 59 The main carrier 91, including the soft release layer 92, is then removed, such that the surface 782 of the portion 784 of the encapsulant 78 is exposed. Then, the middle carrier 81, including the release film 82, is removed, such that the seed layer (e.g., the titanium layer 83) is exposed. The seed layer (e.g., the titanium layer 83 and the copper layer 84) is then removed by, for example, etching. A laser drilling process can be performed to enlarge portions of the through holes 60a, forming the shape of the through holes 60 as shown in Figure 59 The redistribution layer 4 is then formed adjacent to the second surface 62 of the second dielectric layer 6. For example, as shown in Figure 59As shown in FIG. 1, redistribution layer 4 is on second surface 62 of second dielectric layer 6, and portions of redistribution layer 4 can extend into vias 60 to contact conductive pillars 28. Redistribution layer 4 is electrically connected to circuit structure 5 via conductive pillars 28. Redistribution layer 4 can include a seed layer 41 and a conductive layer 42. Seed layer 41 is between conductive layer 42 and second dielectric layer 6, and between conductive layer 42 and conductive pillars 28. The material of seed layer 41 can be, for example, titanium or copper. In some embodiments, seed layer 41 can include a titanium layer and a copper layer. The material of conductive layer 42 can be, for example, a conductive metal such as copper, or another metal or combination of metals. Redistribution layer 4 can include at least one conductive pad 44 and at least one trace 45. In some embodiments, the line width / line spacing (L / S) of redistribution layer 4 can be equal to or greater than 10 pm / 10 pm.

[0233] Referring to Figure 60 , a dielectric material is provided on encapsulant 78 and intermediate panels 8h (e.g., second dielectric layer 6) to form a plurality of first dielectric layers 3 and a dielectric portion 14. The dielectric material covers redistribution layer 4. Each of first dielectric layers 3 is on a respective one of intermediate panels 8h. Dielectric portion 14 is in gap “g” between two adjacent intermediate panels 8h and on portions 784 of encapsulant 4. Dielectric portion 14 is between and connects first dielectric layers 3. First dielectric layers 3 and dielectric portion 14 are simultaneously and integrally formed as a unitary structure. That is, there is no boundary or interface between dielectric portion 14 and first dielectric layers 3. The dielectric material can be an insulating material or a dielectric material such as, for example, polypropylene (PP). It should be noted that the dielectric material can include or be formed from a cured photoimageable dielectric (PID) material such as, for example, an epoxy resin including a photoinitiator or a polyimide (PI). Thus, first dielectric layers 3 and dielectric portion 14 can be made of, or can include, or be formed from, an insulating material or a dielectric material such as, for example, polypropylene (PP), or a cured photoimageable dielectric (PID) material such as, for example, an epoxy resin including a photoinitiator or a polyimide (PI).

[0234] First dielectric layers 3 include a first surface 31 and a second surface 32 opposite first surface 31. As Figure 60 shown in FIG. 1, first surface 31 is an upper surface and second surface 32 is a lower surface. The upper surface of first dielectric layers 3 (i.e., first surface 31) contacts the lower surface of second dielectric layer 6 (i.e., second surface 62).

[0235] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. The upper surface 141 contacts a surface 782 of a portion 784 of the encapsulant 78, and thus is substantially coplanar with a lower surface (i.e., the second surface 62) of the second dielectric layer 6 and / or an upper surface (i.e., the first surface 31) of the dielectric layer 3. At least a portion of the surface 143 is an imaginary surface or an imaginary plane. The side surface 143 can be substantially coplanar with a side surface 63 of the second dielectric layer 6.

[0236] Then, at least one via 30 is formed through the first dielectric layer 3 to expose at least a portion of the redistribution layer 4, such as a conductive pad 44 of the redistribution layer 4. At least one solder connector 26 is formed in the via 30 of the first dielectric layer 3 and on and electrically connected to the exposed portion of the redistribution layer 4, such as the conductive pad 44. The material of the solder connector 26 can be a conductive metal, such as tin, or other metal or combination of metals. A barrier layer 47 and a wetting layer 48 can be disposed between the conductive pad 44 and the solder connector 26. The material of the barrier layer 47 can be nickel, and the material of the wetting layer can be gold. Thus, a substrate panel 1h is formed as shown in Figure 11 Each of the intermediate panels 8h corresponds to a respective one of the sub-panels 2h.

[0237] Then, each of the sub-panels 2h is singulated. That is, each of the intermediate panels 8h (e.g., including the second dielectric layer 6 and the circuit structure 5), each of the first dielectric layers 3, each of the redistribution layers 4, and the encapsulant 78 are singulated, forming a plurality of packaged units, such as the packaged units 7h shown in Figure 17 For example, an edge of each sub-panel 2h can be cut along the side surface 23 to remove the dielectric portion 14 and the portion 784 of the encapsulant 78 during the singulation process.

[0238] Spatial descriptions, such as, for example, "on," "under," "above," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "over," "below," and the like, are indicated relative to the orientation shown in the figures. It should be understood that spatial descriptions used herein are for purposes of illustration only and that practical embodiments of the structures described herein can be oriented in any direction or manner, as long as the orientation does not depart from the advantages of the embodiments of the present invention.

[0239] As used herein, the terms "about," "substantially," "essentially," and "approximately" are used to describe and account for small variations. When used in connection with a description of an event or circumstance, the terms can refer to instances in which the event or circumstance occurs exactly as well as instances in which the event or circumstance occurs approximately. For example, when used in connection with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be considered substantially the same or equal if the difference between the two values is less than or equal to ±10% of the average of the values (such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0240] Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no more than 5 μιη, no more than 2 μιη, no more than 1 μιη, or no more than 0.5 μιη.

[0241] Additionally, quantities, ratios and other numerical values are sometimes presented in a range format. It is to be understood that such range format is used for convenience and brevity and that the upper value of the range is intended to be substantially the same as the lower value of the range, unless otherwise specified. It is to be further understood that individual values within the range are also intended to be encompassed.

[0242] While the application has been described and illustrated with reference to specific examples thereof, it is not intended that the application be limited thereto, as variations and modifications exist which fall within the true spirit and scope of the present application as defined by the appended claims. The illustrations are not necessarily drawn to scale. There can be many variations to the figures and implementations described and illustrated herein, and it will be apparent to those of ordinary skill in the art that the scope of the present application and its teachings are not limited to a single implementation. For example, the present application can be used in a variety of applications, including but not limited to the applications described and illustrated herein. Accordingly, other implementations are within the scope of the following claims and their equivalents. Although reference has been made to the present application as being applicable to specific examples, it is to be understood that the application can be applied to other examples without departing from the true spirit and scope of the present application. The specification and drawings are, accordingly to be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, process or method to the purpose, spirit and scope of the present application. All such modifications are intended to be within the scope of the claims. While the present application has been described with reference to particular operations performed by particular devices, it is to be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present application. Accordingly, unless specifically indicated otherwise, the order and grouping of operations is not a limitation of the present application.

Claims

1. A substrate panel structure, comprising: Multiple sub-panels, each of which comprises multiple substrate units; and Dielectric portions are located between the sub-panels; Each of the sub-panels includes a first dielectric layer integrally and simultaneously formed with the dielectric portion. Each of the sub-panels includes a circuit structure embedded in the first dielectric layer and a second dielectric layer located on the circuit structure. The circuit structure includes a conductive via embedded in and exposed from the second dielectric layer. The dielectric portion has an inner surface that defines a cavity to fully expose the second dielectric layer of each of the sub-panels. The side surface of the second dielectric layer is substantially coplanar with the inner surface of the dielectric portion, and the upper surface of the conductive via is exposed in the cavity.

2. The substrate panel structure of claim 1, wherein the dielectric portion covers at least a portion of the side surface of each of the sub-panels.

3. The substrate panel structure according to claim 1, wherein the sub-panel comprises a first sub-panel and a second sub-panel, and the spacing between two adjacent substrate units in the first sub-panel is less than the spacing between one of the substrate units of the closest first sub-panel and one of the substrate units of the second sub-panel.

4. The substrate panel structure according to claim 1, wherein the gap between adjacent sub-panels has an inconsistent width.

5. The substrate panel structure according to claim 1, wherein the sub-panels are arranged in an "m*n" manner, and "m" and "n" are integers equal to or greater than 2.

6. The substrate panel structure of claim 1, wherein the upper surface of the dielectric portion is at a level higher than the upper surface of each of the sub-panels, and the dielectric portion defines a cavity above the upper surface of each of the sub-panels.

7. The substrate panel structure according to claim 1, wherein the line width / line spacing of the circuit structure is equal to or less than 2μm / 2μm.

8. The substrate panel structure of claim 1, wherein each of the sub-panels further comprises a redistribution layer electrically connected to the circuit structure, wherein a portion of the redistribution layer is embedded in the first dielectric layer and contacts the circuit structure, and the L / S of the redistribution layer is equal to or greater than 10µm / 10µm.

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