Organic light-emitting diode display device

Abstract

The present disclosure relates to an organic light-emitting diode display device, which includes a substrate, a first oxide transistor, a second oxide transistor, and a sub-pixel structure. The substrate has a display area including a plurality of sub-pixel areas and a peripheral area located next to the display area. The first oxide transistor is arranged in the peripheral area on the substrate and includes a first oxide semiconductor pattern, the first oxide semiconductor pattern including tin (Sn). The second oxide transistor is arranged in each of the sub-pixel areas on the substrate and includes a second oxide semiconductor pattern. The sub-pixel structure is arranged on the second oxide transistor.

Description

Technical Field

[0001] Example embodiments generally relate to an organic light emitting diode display device and a method of manufacturing the same. More particularly, embodiments of the inventive concept relate to an organic light emitting diode display device including a gate driver and a method of manufacturing the same. Background Art

[0002] Flat panel display ("FPD") devices are widely used as display devices in electronic devices because FPD devices are lightweight and thin compared to cathode ray tube ("CRT") display devices. Typical examples of FPD devices include liquid crystal display ("LCD") devices and organic light emitting diode ("OLED") display devices. Compared to LCD devices, OLED display devices can have higher brightness and a wider viewing angle. In addition, because OLED display devices do not require a backlight unit, OLED display devices can be made thinner. In an OLED display device, electrons and holes are injected into an organic thin layer through a cathode and an anode, and then recombine in the organic thin layer to generate excitons, thereby emitting light of a specific wavelength.

[0003] An OLED display device may include a display area for displaying an image and a peripheral area surrounding the display area, as well as a gate driver, a data driver unit, and a plurality of wirings arranged in the peripheral area. A plurality of transistors may be provided in the gate driver, and a plurality of transistors may be provided in the display area. As OLED display devices become larger and have higher brightness, the number of transistors included in the gate driver may be relatively increased, and the gate driver may be arranged in the peripheral area (e.g., dead space). In this case, the area of ​​the peripheral area can be increased. Summary of the Invention

[0004] Some example embodiments provide an organic light emitting diode (OLED) display device including a gate driver, a dead space of which may be reduced and a manufacturing cost of which may be lowered.

[0005] Some example embodiments provide a method of manufacturing an OLED display device including a gate driver, a dead space of the OLED display device may be reduced and a manufacturing cost of the OLED display device may be lowered.

[0006] According to some example embodiments, an OLED display device includes a substrate, a first oxide transistor, a second oxide transistor, and a sub-pixel structure. The substrate has a display area including a plurality of sub-pixel areas, and the substrate includes a peripheral area located next to the display area. The first oxide transistor is disposed in the peripheral area on the substrate and includes a first oxide semiconductor pattern, the first oxide semiconductor pattern including tin (Sn). The second oxide transistor is disposed in each of the sub-pixel areas on the substrate and includes a second oxide semiconductor pattern. The sub-pixel structure is disposed on the second oxide transistor.

[0007] In example embodiments, the second oxide semiconductor pattern may not include Sn.

[0008] In example embodiments, the first oxide transistor and the second oxide transistor may be located in the same layer.

[0009] In example embodiments, the first oxide transistor may further include a first gate electrode disposed on the first oxide semiconductor pattern, and a first source electrode and a first drain electrode disposed on the first gate electrode.

[0010] In an example embodiment, the OLED display device may further include a gate driver that generates a gate signal. The gate driver may be disposed in the peripheral region on the substrate and may include a transistor. The transistor included in the gate driver may correspond to the first oxide transistor.

[0011] In an example embodiment, the OLED display device may further include a third oxide transistor disposed in each of the sub-pixel regions on the substrate. The third oxide transistor includes a third oxide semiconductor pattern, which may include Sn. The second oxide transistor may correspond to a driving transistor, and the third oxide transistor may correspond to a switching transistor.

[0012] In example embodiments, the first oxide semiconductor pattern, the second oxide semiconductor pattern, and the third oxide semiconductor pattern may be located on the same layer.

[0013] In example embodiments, the first oxide semiconductor pattern and the third oxide semiconductor pattern may include the same material.

[0014] In example embodiments, the first oxide semiconductor pattern may include at least one of tin oxide (SnO), indium tin oxide (ITO), zinc tin oxide (ZTO), indium zinc tin oxide (IZTO), aluminum tin zinc oxide (TAZO), indium gallium tin oxide (IGTO), and indium tin gallium zinc oxide (ITGZO).

[0015] In example embodiments, the second oxide semiconductor pattern may include at least one of zinc oxide (ZnO), gallium oxide (GaO), titanium oxide (TiO), indium oxide (InO), indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZrO), indium gallium zinc oxide (IGZO), and indium gallium hafnium oxide (IGHO).

[0016] According to some example embodiments, a method of manufacturing an OLED display device is provided as follows.

[0017] A substrate is provided, the substrate having a display area including a plurality of sub-pixel areas and a peripheral area adjacent to the display area. A first preliminary oxide semiconductor layer is formed on the substrate. After patterning the first preliminary oxide semiconductor layer using a first etchant, a first oxide semiconductor pattern including Sn is formed in the peripheral area on the substrate. A second preliminary oxide semiconductor layer is formed on the substrate and the first oxide semiconductor pattern. After patterning the second preliminary oxide semiconductor layer using a second etchant, a second oxide semiconductor pattern is formed in each of the sub-pixel areas. A sub-pixel structure is formed on the second oxide semiconductor pattern.

[0018] In example embodiments, the second oxide semiconductor pattern may not include Sn.

[0019] In example embodiments, when the second preliminary oxide semiconductor layer is formed on the first oxide semiconductor pattern, the second preliminary oxide semiconductor layer may be in direct contact with the first oxide semiconductor pattern.

[0020] In example embodiments, when the second preliminary oxide semiconductor layer is patterned using the second etchant, the second etchant may be in direct contact with the first oxide semiconductor pattern.

[0021] In example embodiments, the first etchant may be different from the second etchant, and the first oxide semiconductor pattern may not be etched by the second etchant.

[0022] In example embodiments, the first etchant may include a compound including fluorine (F).

[0023] In example embodiments, the second etchant may include phosphoric acid, acetic acid, and nitric acid.

[0024] In example embodiments, the method may further include forming a third oxide semiconductor pattern including Sn in each of the sub-pixel regions.

[0025] In example embodiments, the first oxide semiconductor pattern, the second oxide semiconductor pattern, and the third oxide semiconductor pattern may be located on the same layer.

[0026] In example embodiments, the first oxide semiconductor pattern and the third oxide semiconductor pattern may be simultaneously formed using the same material.

[0027] Since the OLED display device according to the example embodiment includes a first oxide transistor having a relatively high electron mobility, the gate driver can include a relatively small number of transistors. Therefore, the unused space of the OLED display device can be reduced. In addition, since the gate driver includes a relatively small number of transistors, the manufacturing cost of the OLED display device can be reduced. In addition, since the second oxide transistor includes a second oxide semiconductor pattern that does not include Sn, the second oxide transistor can have a relatively large driving range.

[0028] In the method of manufacturing the OLED display device according to example embodiments, since oxide transistors having different characteristics from each other are manufactured in the same layer by using first and second etchants without adding a mask, the manufacturing cost of the OLED display device may be relatively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Example embodiments may be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a plan view illustrating an organic light emitting diode (OLED) display device according to an example embodiment;

[0031] Figure 2 is used to describe electrical connections to Figure 1 A block diagram of external devices of an OLED display device;

[0032] Figure 3 is a circuit diagram showing a sub-pixel circuit and an OLED provided on the sub-pixel circuit, wherein the sub-pixel circuit and the OLED are provided on Figure 1 In the sub-pixel area;

[0033] Figure 4 It is along Figure 1 A sectional view taken along line II';

[0034] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 and Figure 11 is a cross-sectional view illustrating a method of manufacturing an OLED display device according to an example embodiment; and

[0035] Figure 12 is a plan view illustrating an OLED display device according to example embodiments. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a plan view showing an organic light emitting diode (OLED) display device according to an example embodiment, and Figure 2 is used to describe electrical connections to Figure 1 Block diagram of the external devices of an OLED display device.

[0038] Reference Figure 1 and Figure 2 , an organic light emitting diode (OLED) display device 100 may have a display area 10 and a peripheral area 20 surrounding the display area 10. Here, the display area 10 may include a plurality of sub-pixel areas 30. The sub-pixel areas 30 may be arranged in a matrix throughout the display area 10. For example, the sub-pixel areas 30 may be repeatedly arranged along a first direction D1 and a second direction D2. Here, the first direction D1 may be parallel to the upper surface of the OLED display device 100, and the second direction D2 may be perpendicular to the first direction D1. The gate driver 300 may be provided at one side of the peripheral area 20 (e.g., the left side of the display area 10), and the plurality of pad electrodes 470 may be provided at the other side of the peripheral area 20 (e.g., the bottom side of the display area 10). Alternatively, the gate driver 300 may be provided at the right side or top side of the display area 10. In some example embodiments, the OLED display device 100 may further include a data driver, a timing controller, a light emitting driver, etc., and they may be provided in the peripheral area 20.

[0039] Sub-pixel circuits (e.g., Figure 3 A sub-pixel circuit (SUB-PIXEL CIRCUIT) may be provided in each sub-pixel region 30 in the display region 10, and an OLED may be provided on the sub-pixel circuit. An image may be displayed through the sub-pixel circuit and the OLED.

[0040] The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit may be disposed in the sub-pixel region 30. For example, the first sub-pixel circuit may be coupled to (or connected to) a first OLED capable of emitting red light, and the second sub-pixel circuit may be coupled to a second OLED capable of emitting green light. The third sub-pixel circuit may be coupled to a third OLED capable of emitting blue light.

[0041] In an example embodiment, the first OLED may be arranged to overlap with the first sub-pixel circuit, and the second OLED may be arranged to overlap with the second sub-pixel circuit. The third OLED may be arranged to overlap with the third sub-pixel circuit. Alternatively, the first OLED may be arranged to overlap with a portion of the first sub-pixel circuit and a portion of a sub-pixel circuit different from the first sub-pixel circuit, and the second OLED may be arranged to overlap with a portion of the second sub-pixel circuit and a portion of a sub-pixel circuit different from the second sub-pixel circuit. The third OLED may be arranged to overlap with a portion of the third sub-pixel circuit and a portion of a sub-pixel circuit different from the third sub-pixel circuit.

[0042] For example, the first, second, and third OLEDs may be arranged using an RGB stripe method in which quadrilaterals of the same size are sequentially arranged, an s stripe method including a blue OLED having a relatively large area, a WRGB method also including a white OLED, or a pen-tile method repeatedly arranged in an RG-GB pattern.

[0043] Furthermore, at least one driving transistor, at least one switching transistor, and at least one capacitor may be provided in each sub-pixel region 30. In example embodiments, one driving transistor (eg, Figure 3 a first transistor TR1), five switching transistors (eg, Figure 3 2nd transistor TR2 to 7th transistor TR7) and a capacitor (eg, Figure 3 A storage capacitor CST) may be provided in each of the sub-pixel regions 30. In example embodiments, the channel of the driving transistor may be substantially composed of an oxide semiconductor, and the channel of the switching transistor may be substantially composed of an oxide semiconductor including tin (Sn). Alternatively, the channel of the switching transistor may be substantially composed of an oxide semiconductor that does not include Sn.

[0044] In example embodiments, each of the sub-pixel regions 30 has a quadrangular planar shape, but the present inventive concept is not limited thereto. For example, each of the sub-pixel regions 30 may have a triangular planar shape, a rhombus planar shape, a polygonal planar shape, a circular planar shape, a racetrack planar shape, or an elliptical planar shape.

[0045] The external device 101 may be electrically connected to the OLED display device 100 through a flexible printed circuit board ("FPCB"). For example, one side of the FPCB may be in direct contact with the pad electrode 470, and the other side of the FPCB may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light emitting signal, a gate initialization signal, an initialization voltage or power, etc. to the OLED display device 100. In addition, a driver integrated circuit may be installed (e.g., placed) in the FPCB. In some example embodiments, the driver integrated circuit may be installed in the OLED display device 100 and positioned adjacent to the pad electrode 470. Alternatively, when the OLED display device 100 includes a curved area, the pad electrode 470 and the external device 101 may be electrically connected through a printed circuit board ("PCB").

[0046] The gate driver 300 may receive a gate signal and a gate initialization signal from the external device 101 and may provide the gate signal and the gate initialization signal to the sub-pixel circuit. In example embodiments, the gate driver 300 may include a plurality of transistors (eg, Figure 4 The first oxide transistor 650 of the OLED display 100 is provided, and the channel of each transistor can be substantially composed of an oxide semiconductor including Sn. When the gate driver 300 includes transistors, and the transistors include an oxide semiconductor including Sn, the gate driver 300 can include transistors with relatively high electron mobility. In this case, the gate driver 300 can include a relatively small number of transistors, and the OLED display device 100 can include a peripheral region 20 with a relatively reduced area. That is, the useless space of the OLED display device 100 can be reduced.

[0047] Figure 3 is a circuit diagram showing a sub-pixel circuit and an OLED provided on the sub-pixel circuit, wherein the sub-pixel circuit and the OLED are provided on Figure 1 in the sub-pixel area.

[0048] Reference Figure 3 , SUB-PIXEL CIRCUIT ("SPC") and OLED (eg, corresponding to Figure 4The sub-pixel structure 200 may be provided in each of the sub-pixel regions 30 in the OLED display device 100, and the OLED may be provided on the sub-pixel circuit SPC. One sub-pixel circuit SPC may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, a seventh transistor TR7, a storage capacitor CST, a high power supply ELVDD wiring, a low power supply ELVSS wiring, an initialization voltage VINT wiring, a data signal DATA wiring, a gate signal GW wiring, a gate initialization signal GI wiring, a light emitting signal EM wiring, and a diode initialization signal GB wiring, etc.

[0049] The OLED may emit light based on a driving current ID. The OLED may include a first terminal and a second terminal. In an example embodiment, the second terminal of the OLED receives a low power supply ELVSS. For example, the first terminal of the OLED is an anode terminal, and the second terminal of the OLED is a cathode terminal. Alternatively, the first terminal of the OLED may be a cathode terminal, and the second terminal of the OLED may be an anode terminal. In an example embodiment, the anode terminal of the OLED may correspond to Figure 4 The lower electrode 290 of the OLED may correspond to the cathode terminal of the OLED. Figure 4 The upper electrode 340 is provided.

[0050] The first transistor TR1 (eg, Figure 4 The second oxide transistor 250 may include a gate terminal, a first terminal, and a second terminal. In an example embodiment, the first terminal of the first transistor TR1 is a source terminal, and the second terminal of the first transistor TR1 is a drain terminal. Alternatively, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal. For example, the channel of the first transistor TR1 (e.g., Figure 4 The second oxide semiconductor pattern 130) may be substantially composed of an oxide semiconductor that does not include Sn.

[0051] The driving current ID may be generated by the first transistor TR1. In an exemplary embodiment, the first transistor TR1 operates in a saturation region. In this case, the first transistor TR1 may generate the driving current ID based on a voltage difference between a gate terminal and a source terminal, and grayscale gradation may be achieved based on the amount of driving current ID generated by the first transistor TR1. Alternatively, the first transistor TR1 may operate in a linear region. In this case, grayscale gradation may be achieved based on the amount of time that the first transistor TR1 supplies the driving current ID to the OLED within a frame.

[0052] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. A gate signal GW may be applied to the gate terminal of the second transistor TR2. The first terminal of the second transistor TR2 may receive a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. For example, Figure 1 The gate driver 300 generates a gate signal GW and can apply the gate signal GW to the gate terminal of the second transistor TR2 through the gate signal GW wiring. In an example embodiment, the first terminal of the second transistor TR2 is a source terminal, and the second terminal of the second transistor TR2 is a drain terminal. In addition, the channel of the second transistor TR2 can be substantially composed of an oxide semiconductor including Sn. Alternatively, the first terminal of the second transistor TR2 can be a drain terminal, and the second terminal of the second transistor TR2 can be a source terminal.

[0053] When the gate signal GW is activated, the second transistor TR2 may provide the data signal DATA to the first terminal of the first transistor TR1. In this case, the second transistor TR2 operates in a linear region.

[0054] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may receive a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, Figure 1 The gate driver 300 generates a gate signal GW, and the gate signal GW can be applied to the gate terminal of the third transistor TR3 via the gate signal GW wiring. In an example embodiment, the first terminal of the third transistor TR3 is a source terminal, and the second terminal of the third transistor TR3 is a drain terminal. In addition, the channel of the third transistor TR3 can be substantially composed of an oxide semiconductor containing Sn. Alternatively, the first terminal of the third transistor TR3 can be a drain terminal, and the second terminal of the third transistor TR3 can be a source terminal.

[0055] When the gate signal GW is activated, the third transistor TR3 can connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1. In this case, the third transistor TR3 can operate in the linear region. That is, when the gate signal GW is activated, the third transistor TR3 can form a diode connection with the first transistor TR1. A voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1, corresponding to the threshold voltage of the first transistor TR1, can be generated due to the diode connection of the first transistor TR1. As a result, when the gate signal GW is activated, the sum of the data signal DATA provided to the first terminal of the first transistor TR1 and the voltage difference (i.e., the threshold voltage) can be applied to the gate terminal of the first transistor TR1. Therefore, the data signal DATA can be compensated up to the threshold voltage of the first transistor TR1. The compensated data signal DATA can be applied to the gate terminal of the first transistor TR1. Since the influence of the threshold voltage of the first transistor TR1 is reduced, the uniformity of the drive current ID can be improved.

[0056] An input terminal of the initialization voltage VINT wiring providing the initialization voltage VINT is connected to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7 , and an output terminal of the initialization voltage VINT wiring is connected to the second terminal of the fourth transistor TR4 and the first terminal of the storage capacitor CST.

[0057] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may receive a gate initialization signal GI. For example, the gate initialization signal GI may be received from Figure 1 The gate driver 300 is generated, and the gate initialization signal GI can be applied to the gate terminal of the fourth transistor TR4 through the gate initialization signal GI wiring. The initialization voltage VINT can be applied to the first terminal of the fourth transistor TR4. The second terminal of the fourth transistor TR4 can be connected to the gate terminal of the first transistor TR1. In an example embodiment, the first terminal of the fourth transistor TR4 is a source terminal, and the second terminal of the fourth transistor TR4 is a drain terminal. In addition, the channel of the fourth transistor TR4 can be substantially composed of an oxide semiconductor including Sn. Alternatively, the first terminal of the fourth transistor TR4 can be a drain terminal, and the second terminal of the fourth transistor TR4 can be a source terminal.

[0058] When the gate initialization signal GI is activated, the fourth transistor TR4 can apply the initialization voltage VINT to the gate terminal of the first transistor TR1. In this case, the fourth transistor TR4 can operate in the linear region. Therefore, when the gate initialization signal GI is activated, the fourth transistor TR4 can initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT. In an example embodiment, the voltage level of the initialization voltage VINT is sufficiently lower than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame. The initialization voltage VINT can be applied to the gate terminal of the first transistor TR1, which is a P-channel metal oxide semiconductor ("PMOS") type transistor. In some example embodiments, the voltage level of the initialization voltage VINT is sufficiently higher than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame. The initialization voltage VINT can be applied to the gate terminal of the first transistor TR1, which is an N-channel metal oxide semiconductor ("NMOS") type transistor.

[0059] In an exemplary embodiment, the gate initialization signal GI is the same as the gate signal GW that is one horizontal period ahead. For example, the gate initialization signal GI (where n is an integer of 2 or greater) applied to the sub-pixel circuit located in the (n)th row among the plurality of sub-pixel circuits SPC included in the OLED display device 100 may be substantially the same as the gate signal GW applied to the sub-pixel circuit located in the (n-1)th row among the plurality of sub-pixel circuits SPC. That is, the activated gate initialization signal GI may be applied to the sub-pixel circuit located in the (n-1)th row among the plurality of sub-pixel circuits SPC by applying the activated gate signal GW to the sub-pixel circuit located in the (n)th row among the plurality of sub-pixel circuits SPC. As a result, when the data signal DATA is applied to the sub-pixel circuit located in the (n-1)th row among the plurality of sub-pixel circuits SPC, the gate terminal of the first transistor TR1 included in the sub-pixel circuit located in the (n)th row among the plurality of sub-pixel circuits SPC may be initialized to the initialization voltage VINT.

[0060] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. A light emitting signal EM may be applied to the gate terminal of the fifth transistor TR5. A high power supply ELVDD may be applied to the first terminal of the fifth transistor TR5. The second terminal of the fifth transistor TR5 may be connected to the first terminal of the first transistor TR1. In example embodiments, the first terminal of the fifth transistor TR5 is a source terminal, and the second terminal of the fifth transistor TR5 is a drain terminal. In addition, the channel of the fifth transistor TR5 may be substantially composed of an oxide semiconductor including Sn. In some example embodiments, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0061] When the emission signal EM is activated, the fifth transistor TR5 can apply the high power supply ELVDD to the first terminal of the first transistor TR1. On the other hand, when the emission signal EM is not activated, the fifth transistor TR5 does not apply the high power supply ELVDD. In this case, the fifth transistor TR5 can operate in the linear region. When the emission signal EM is activated, the fifth transistor TR5 can apply the high power supply ELVDD to the first terminal of the first transistor TR1, causing the first transistor TR1 to generate the drive current ID. Furthermore, when the emission signal EM is not activated, the fifth transistor TR5 does not apply the high power supply ELVDD, causing the data signal DATA applied to the first terminal of the first transistor TR1 to be applied to the gate terminal of the first transistor TR1.

[0062] The sixth transistor TR6 (eg, Figure 4 The third oxide transistor 255 may include a gate terminal, a first terminal, and a second terminal. The light emitting signal EM may be applied to the gate terminal of the sixth transistor TR6. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the OLED. In an example embodiment, the first terminal of the sixth transistor TR6 is a source terminal, and the second terminal of the sixth transistor TR6 is a drain terminal. In addition, the channel of the sixth transistor TR6 (for example, Figure 4 The third oxide semiconductor pattern 135) may be substantially composed of an oxide semiconductor including Sn. In some example embodiments, the first terminal of the sixth transistor TR6 may be a drain terminal, and the second terminal of the sixth transistor TR6 may be a source terminal.

[0063] When the emission signal EM is activated, the sixth transistor TR6 can provide the drive current ID generated by the first transistor TR1 to the OLED. In this case, the sixth transistor TR6 can operate in a linear region. That is, when the emission signal EM is activated, the sixth transistor TR6 can provide the drive current ID generated by the first transistor TR1 to the OLED, causing the OLED to emit light. In addition, when the emission signal EM is not activated, the sixth transistor TR6 can electrically disconnect the first transistor TR1 from the OLED, so that the compensated data signal DATA applied to the second terminal of the first transistor TR1 is applied to the gate terminal of the first transistor TR1.

[0064] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. A diode initialization signal GB may be applied to the gate terminal of the seventh transistor TR7. An initialization voltage VINT may be applied to the first terminal of the seventh transistor TR7. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the OLED. In an example embodiment, the first terminal of the seventh transistor TR7 is a source terminal, and the second terminal of the seventh transistor TR7 is a drain terminal. In addition, the channel of the seventh transistor TR7 may be substantially composed of an oxide semiconductor including Sn. In some example embodiments, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0065] When the diode initialization signal GB is activated, the seventh transistor TR7 can apply the initialization voltage VINT to the first terminal of the OLED. In this case, the seventh transistor TR7 can operate in the linear region. That is, when the diode initialization signal GB is activated, the seventh transistor TR7 can initialize the first terminal of the OLED to the initialization voltage VINT.

[0066] Alternatively, the gate initialization signal GI and the diode initialization signal GB are substantially the same signal. The initialization operation of the gate terminal of the first transistor TR1 does not affect the initialization operation of the first terminal of the OLED. That is, the initialization operation of the gate terminal of the first transistor TR1 and the initialization operation of the first terminal of the OLED can be independent of each other. Therefore, the gate initialization signal GI is used as the diode initialization signal GB, thereby improving manufacturing efficiency.

[0067] The storage capacitor CST may include a first terminal and a second terminal and may be connected between the high power supply ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power supply ELVDD wiring. When the gate signal GW is not activated, the storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1. When the gate signal GW is not activated, the light emitting signal EM may be activated (for example, an interval in which the gate signal GW is not activated may include an interval in which the light emitting signal EM is activated). When the light emitting signal EM is activated, the drive current ID generated by the first transistor TR1 may be provided to the OLED. Therefore, the drive current ID generated by the first transistor TR1 may be provided to the OLED based on the voltage level maintained by the storage capacitor CST.

[0068] Figure 4 It is along Figure 1 A cross-sectional view taken along line II'.

[0069] Reference Figure 4 The OLED display device 100 may include a substrate 110, a buffer layer 115, a first oxide transistor 650, a second oxide transistor 250, a third oxide transistor 255, a gate insulating layer 150, an insulating interlayer 190, a planarization layer 270, a sub-pixel structure 200, a pixel defining layer 310, a sealing member 390, and an encapsulation substrate 450. The first oxide transistor 650 may include a first oxide semiconductor pattern 530, a first gate electrode 570, a first source electrode 610, and a first drain electrode 630, and the second oxide transistor 250 may include a second oxide semiconductor pattern 130, a second gate electrode 170, a second source electrode 210, and a second drain electrode 230. In addition, the third oxide transistor 255 may include a third oxide semiconductor pattern 135, a third gate electrode 175, a third source electrode 215, and a third drain electrode 235. In addition, the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340. Since the OLED display device 100 has the display area 10 and the peripheral area 20 , the substrate 110 may be divided into the display area 10 and the peripheral area 20 .

[0070] The substrate 110 may include a transparent insulating material or an opaque insulating material. The substrate 110 may include at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and combinations thereof.

[0071] Alternatively, the substrate 110 may include a flexible transparent resin substrate (e.g., a polyimide substrate). In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, and a second polyimide layer, etc. For example, the substrate 110 may have a structure in which a first polyimide layer, a barrier film layer, and a second polyimide layer are sequentially stacked on a rigid glass substrate. In other words, since the polyimide substrate is relatively thin and flexible, the polyimide substrate can be formed on a rigid glass substrate to help support the formation of the upper structure. In the method for manufacturing the OLED display device 100, after an insulating layer (e.g., a buffer layer 115) is provided on the second polyimide layer of the polyimide substrate, an upper structure (e.g., a first oxide transistor 650, a second oxide transistor 250, a third oxide transistor 255, and a sub-pixel structure 200, etc.) may be formed on the insulating layer. After the upper structure is formed on the insulating layer, the rigid glass substrate on which the polyimide substrate is formed may be removed. That is, since the polyimide substrate is relatively thin and flexible, it is difficult to form the upper structure directly on the polyimide substrate. Therefore, the upper structure is formed on the polyimide substrate and the rigid glass substrate, and then after removing the rigid glass substrate, the polyimide substrate can be used as the substrate 110.

[0072] The buffer layer 115 may be provided on the entire substrate 110. The buffer layer 115 may prevent metal atoms and / or impurities from the substrate 110 from diffusing into the first oxide transistor 650, the second oxide transistor 250, the third oxide transistor 255, and the sub-pixel structure 200. In addition, when the surface of the substrate 110 is relatively irregular, the buffer layer 115 may improve the surface flatness of the substrate 110. According to example embodiments, at least two buffer layers 115 may be provided on the substrate 110, or no buffer layer 115 may be provided. For example, the buffer layer 115 may include an organic material or an inorganic material.

[0073] In the peripheral region 20, a first oxide semiconductor pattern 530 may be provided on the buffer layer 115. The first oxide semiconductor pattern 530 may include an oxide semiconductor including tin (Sn). In other words, the first oxide semiconductor pattern 530 may include an oxide semiconductor layer including a two-component compound (AB x ), ternary compound (AB x C y ) and four-component compounds (AB x C y D z), etc. These compounds contain Sn and at least one of indium (In), zinc (Zn), gallium (Ga), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). For example, the first oxide semiconductor pattern 530 may include at least one of tin oxide (SnO), indium tin oxide (ITO), zinc tin oxide (ZTO), indium zinc tin oxide (IZTO), aluminum tin zinc oxide (TAZO), indium gallium tin oxide (IGTO), and indium tin gallium zinc oxide (ITGZO). In example embodiments, the first oxide semiconductor pattern 530 may consist essentially of ITGZO.

[0074] In the display region 10 (or the sub-pixel region 30), the second oxide semiconductor pattern 130 may be provided on the buffer layer 115. The second oxide semiconductor pattern 130 may include an oxide semiconductor that does not include Sn. In other words, the second oxide semiconductor pattern 130 may include an oxide semiconductor layer including AB x , AB x Cy and AB x C y D z At least one of the compounds of In, Zn, Ga, Ti, Al, Hf, Zr, and Mg, etc. These compounds contain at least one of In, Zn, Ga, Ti, Al, Hf, Zr, and Mg, etc. For example, the second oxide semiconductor pattern 130 may include at least one of zinc oxide (ZnO), gallium oxide (GaO), titanium oxide (TiO), indium oxide (InO), indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZrO), indium gallium zinc oxide (IGZO), and indium gallium hafnium oxide (IGHO). In example embodiments, the second oxide semiconductor pattern 130 may be substantially composed of IGZO.

[0075] In the display area 10, the third oxide semiconductor pattern 135 may be disposed on the buffer layer 115. The third oxide semiconductor pattern 135 may be spaced apart from the second oxide semiconductor pattern 130 in the second direction D2. The third oxide semiconductor pattern 135 may include an oxide semiconductor including Sn. In other words, the third oxide semiconductor pattern 135 may include an oxide semiconductor layer including AB x , AB x C y and AB x C y D zThese compounds include Sn and at least one of In, Zn, Ga, Ti, Al, Hf, Zr, and Mg. For example, the third oxide semiconductor pattern 135 may include at least one of SnO, ITO, ZTO, IZTO, TAZO, IGTO, and ITGZO. In example embodiments, the third oxide semiconductor pattern 135 may consist essentially of ITGZO.

[0076] For example, in the method of manufacturing the OLED display device 100, the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 may include the same material and may be formed at the same time. At the same time, after the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 are formed, the second oxide semiconductor pattern 130 may be formed. Although the second oxide semiconductor pattern 130 is formed later than the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135, the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135 may be disposed on the buffer layer 115. That is, the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135 may be located on the same layer.

[0077] The gate insulating layer 150 may be disposed on the buffer layer 115, the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135. In the peripheral region 20, the gate insulating layer 150 may cover the first oxide semiconductor pattern 530 on the buffer layer 115 and may extend in the second direction D2 on the buffer layer 115. Furthermore, in the display region 10, the gate insulating layer 150 may cover the second oxide semiconductor pattern 130 and the third oxide semiconductor pattern 135 on the buffer layer 115 and may extend in the second direction D2 on the buffer layer 115. That is, the gate insulating layer 150 may be disposed on the entire buffer layer 115. For example, the gate insulating layer 150 may fully cover the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135 on the buffer layer 115 and may have a substantially flat upper surface without stepped portions around the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135. Alternatively, the gate insulating layer 150 may cover the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135 on the buffer layer 115, and may be provided to have a substantially uniform thickness along the contours of the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135. The gate insulating layer 150 may include a silicon compound or a metal oxide, etc. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), silicon carbide nitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum nitride (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ) or titanium oxide (TiO x )wait.

[0078] In the peripheral region 20, the first gate electrode 570 may be disposed on the gate insulating layer 150. The first gate electrode 570 may be disposed on a portion of the gate insulating layer 150 under which the first oxide semiconductor pattern 530 is disposed. The first gate electrode 570 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. For example, the first gate electrode 570 may include gold (Au), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy of aluminum, aluminum nitride (AlN), or the like. x ), silver alloy, tungsten nitride (WN x ), copper alloys, molybdenum alloys, titanium nitride (TiN x ), chromium nitride (CrN x ), tantalum nitride (TaN x ), strontium ruthenium oxide (SRO), zinc oxide (ZnO x ), indium tin oxide (ITO), tin oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ) or indium zinc oxide (IZO), etc. These materials may be used alone or in appropriate combination thereof. Alternatively, the first gate electrode 570 may have a multilayer structure including a plurality of layers.

[0079] In the display area 10, the second gate electrode 170 may be provided on the gate insulating layer 150. The second gate electrode 170 may be provided on a portion of the gate insulating layer 150 under which the second oxide semiconductor pattern 130 is provided. The second gate electrode 170 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the second gate electrode 170 may have a multilayer structure including a plurality of layers.

[0080] In the display area 10, the third gate electrode 175 may be disposed on the gate insulating layer 150, and the third gate electrode 175 may be spaced apart from the second gate electrode 170 in the second direction D2. The third gate electrode 175 may be disposed on a portion of the gate insulating layer 150 under which the third oxide semiconductor pattern 135 is disposed. The third gate electrode 175 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the third gate electrode 175 may have a multilayer structure including a plurality of layers.

[0081] For example, in the method of manufacturing the OLED display device 100, the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 can be simultaneously formed on the gate insulating layer 150 using the same material. In other words, the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 can be located on the same layer.

[0082] The insulating interlayer 190 may be provided on the gate insulating layer 150, the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175. In the peripheral region 20, the insulating interlayer 190 may cover the first gate electrode 570 on the gate insulating layer 150 and may extend in the second direction D2 on the gate insulating layer 150. Furthermore, in the display region 10, the insulating interlayer 190 may cover the second gate electrode 170 and the third gate electrode 175 on the gate insulating layer 150 and may extend in the second direction D2 on the gate insulating layer 150. That is, the insulating interlayer 190 may be provided on the entire gate insulating layer 150. For example, the insulating interlayer 190 may fully cover the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 on the gate insulating layer 150 and may have a substantially flat upper surface without stepped portions around the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175. Alternatively, the insulating interlayer 190 may cover the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 on the gate insulating layer 150, and may be provided to have a substantially uniform thickness along the contours of the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175. The insulating interlayer 190 may include a silicon compound, a metal oxide, or the like.

[0083] In the peripheral region 20, a first source electrode 610 and a first drain electrode 630 may be disposed on the insulating interlayer 190. The first source electrode 610 may contact the source region of the first oxide semiconductor pattern 530 via a first contact hole formed by removing a first portion of the gate insulating layer 150 and the insulating interlayer 190, and the first drain electrode 630 may contact the drain region of the first oxide semiconductor pattern 530 via a second contact hole formed by removing a second portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the first source electrode 610 and the first drain electrode 630 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the first source electrode 610 and the first drain electrode 630 may have a multilayer structure including multiple layers. Thus, a first oxide transistor 650 including the first oxide semiconductor pattern 530, the first gate electrode 570, the first source electrode 610, and the first drain electrode 630 may be provided. Here, the first oxide transistor 650 can be used as a transistor of the gate driver 300, and the transistor of the gate driver 300 includes the first oxide semiconductor pattern 530 containing Sn. The transistor can have relatively high electron mobility. In addition, the first oxide transistor 650 can be used as a transistor with a top gate structure. In some example embodiments, the first oxide transistor 650 can overlap with the sealing member 390.

[0084] In example embodiments, the gate driver 300 of the OLED display device 100 includes one transistor (eg, the first oxide transistor 650), but is not limited thereto. For example, the gate driver 300 may have a configuration including at least two transistors and at least one capacitor.

[0085] In addition, the first oxide transistor 650 of the gate driver 300 has a top gate structure, but is not limited thereto. For example, the first oxide transistor 650 may have a bottom gate structure or a double gate structure.

[0086] In addition, the configuration of the first oxide transistor 650 includes a first oxide semiconductor pattern 530, a first gate electrode 570, a first source electrode 610, and a first drain electrode 630, but is not limited thereto. For example, the first oxide transistor 650 may have a configuration including a first oxide semiconductor pattern 530, a gate insulating layer 150, a first gate electrode 570, an insulating interlayer 190, a first source electrode 610, and a first drain electrode 630.

[0087] In the display area 10, the second source electrode 210 and the second drain electrode 230 may be disposed on the insulating interlayer 190. The second source electrode 210 may contact the source region of the second oxide semiconductor pattern 130 via a third contact hole formed by removing the third portion of the gate insulating layer 150 and the insulating interlayer 190, and the second drain electrode 230 may contact the drain region of the second oxide semiconductor pattern 130 via a fourth contact hole formed by removing the fourth portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the second source electrode 210 and the second drain electrode 230 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the second source electrode 210 and the second drain electrode 230 may have a multilayer structure including multiple layers. Thus, a second oxide transistor 250 including the second oxide semiconductor pattern 130, the second gate electrode 170, the second source electrode 210, and the second drain electrode 230 may be provided. Here, the second oxide transistor 250 can be used as a driving transistor of the sub-pixel circuit SPC, and the driving transistor includes the second oxide semiconductor pattern 130 that does not contain Sn. The transistor can have a relatively large driving range. In addition, the second oxide transistor 250 can be used as a transistor with a top gate structure.

[0088] In example embodiments, the second oxide transistor 250 has a top gate structure, but is not limited thereto. For example, the second oxide transistor 250 may have a bottom gate structure or a double gate structure.

[0089] In addition, the configuration of the second oxide transistor 250 includes a second oxide semiconductor pattern 130, a second gate electrode 170, a second source electrode 210, and a second drain electrode 230, but is not limited thereto. For example, the second oxide transistor 250 may have a configuration including a second oxide semiconductor pattern 130, a gate insulating layer 150, a second gate electrode 170, an insulating interlayer 190, a second source electrode 210, and a second drain electrode 230.

[0090] In the display area 10, a third source electrode 215 and a third drain electrode 235 may be disposed on the insulating interlayer 190. The third source electrode 215 may contact the source region of the third oxide semiconductor pattern 135 via a fifth contact hole formed by removing a fifth portion of the gate insulating layer 150 and the insulating interlayer 190, and the third drain electrode 235 may contact the drain region of the third oxide semiconductor pattern 135 via a sixth contact hole formed by removing a sixth portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the third source electrode 215 and the third drain electrode 235 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the third source electrode 215 and the third drain electrode 235 may have a multilayer structure including multiple layers. Thus, a third oxide transistor 255 including the third oxide semiconductor pattern 135, the third gate electrode 175, the third source electrode 215, and the third drain electrode 235 may be provided. Here, the third oxide transistor 255 can be used as a switching transistor of the sub-pixel circuit SPC, and the switching transistor includes the third oxide semiconductor pattern 135 containing Sn. The transistor can have relatively high electron mobility. In addition, the third oxide transistor 255 can be used as a transistor with a top gate structure.

[0091] In example embodiments, the OLED display device 100 has a configuration including two transistors (eg, the second oxide transistor 250 and the third oxide transistor 255), but is not limited thereto. For example, the OLED display device 100 may have a configuration including at least three transistors and at least one capacitor.

[0092] In addition, the third oxide transistor 255 has a top-gate structure, but is not limited thereto. For example, the third oxide transistor 255 may have a bottom-gate structure or a double-gate structure.

[0093] In addition, the configuration of the third oxide transistor 255 includes a third oxide semiconductor pattern 135, a third gate electrode 175, a third source electrode 215, and a third drain electrode 235, but is not limited thereto. For example, the third oxide transistor 255 may have a configuration including a third oxide semiconductor pattern 135, a gate insulating layer 150, a third gate electrode 175, an insulating interlayer 190, a third source electrode 215, and a third drain electrode 235.

[0094] The planarization layer 270 may be provided on the insulating interlayer 190, the first source electrode 610 and the first drain electrode 630, the second source electrode 210 and the second drain electrode 230, and the third source electrode 215 and the third drain electrode 235. For example, the planarization layer 270 may be provided with a high thickness to sufficiently cover the first source electrode 610 and the first drain electrode 630, the second source electrode 210 and the second drain electrode 230, and the third source electrode 215 and the third drain electrode 235 on the insulating interlayer 190. In this case, the planarization layer 270 may have a substantially flat upper surface, and a planarization process may also be performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. A portion of the upper surface of the third drain electrode 235 may be exposed via a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In example embodiments, the planarization layer 270 may include an organic material such as polyimide, epoxy-based resin, acrylic-based resin, polyester, photoresist, polyacrylic-based resin, polyimide-based resin, polyamido resin, siloxane-based resin, or the like.

[0095] In the display area 10, the lower electrode 290 may be provided on the planarization layer 270. The lower electrode 290 may be in direct contact with the third drain electrode 235 via a contact hole of the planarization layer 270 and may be electrically connected to the third oxide transistor 255. The lower electrode 290 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0096] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290 and the planarization layer 270. The pixel defining layer 310 may cover both side portions of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or an inorganic material. In example embodiments, the pixel defining layer 310 may include an organic material.

[0097] The light-emitting layer 330 may be provided on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of the light-emitting materials capable of generating light of different colors (e.g., red light, blue light, and green light, etc.) according to the first, second, and third OLEDs. Alternatively, the light-emitting layer 330 may generate white light by stacking a plurality of light-emitting materials capable of generating light of different colors such as red light, green light, and blue light. In this case, a color filter may be provided on the light-emitting layer 330 (e.g., to overlap with the light-emitting layer 330). The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin or a color photoresist, etc.

[0098] The upper electrode 340 may be disposed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be completely disposed on the light emitting layer 330 and the pixel defining layer 310. In some example embodiments, the upper electrode 340 may be disposed in the peripheral region 20. The upper electrode 340 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These materials may be used alone or in appropriate combinations thereof. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Therefore, a sub-pixel structure 200 including a lower electrode 290, a light emitting layer 330, and an upper electrode 340 may be provided.

[0099] In the outermost portion of the peripheral region 20, the sealing member 390 may be disposed on the substrate 110. In other words, in the outermost portion of the peripheral region 20, the sealing member 390 may be disposed between the substrate 110 and the encapsulation substrate 450. The upper surface of the sealing member 390 may be in direct contact with the lower surface of the encapsulation substrate 450, and the lower surface of the sealing member 390 may be in direct contact with the upper surface of the insulating interlayer 190. Alternatively, the buffer layer 115, the gate insulating layer 150, and the insulating interlayer 190 on which the sealing member 390 is disposed may not be provided, and the lower surface of the sealing member 390 may be in direct contact with the upper surface of the substrate 110. The sealing member 390 may include glass frit, etc. Furthermore, the sealing member 390 may further include a photocurable material. For example, the sealing member 390 may include a compound such as an organic material and a photocurable material. Furthermore, when at least one of ultraviolet rays, a laser beam, and visible light is irradiated into the compound, the compound may be cured, thereby obtaining the sealing member 390. The photocurable material included in the sealing member 390 may include epoxy acrylate-based resin, polyester acrylate-based resin, polyurethane acrylate-based resin, polybutadiene acrylate-based resin, silicone acrylate-based resin, alkyl acrylate-based resin, or the like.

[0100] For example, a laser can be irradiated into a compound such as an organic material and a photocurable material. According to the irradiation of the laser light, the state of the compound (e.g., the sealing member 390) can be changed from a solid state to a liquid state. In addition, after a predetermined time, the liquid compound can be cured into a solid state. According to the change in the state of the compound, the compound can seal the substrate 110 and the encapsulation substrate 450.

[0101] In example embodiments, the sealing member 390 has a trapezoidal shape in which the width of the upper surface is smaller than the width of the lower surface, but is not limited thereto. For example, the sealing member 390 may have a trapezoidal shape in which the width of the upper surface is larger than the width of the lower surface, a quadrangular shape, a square shape, or the like.

[0102] The encapsulation substrate 450 may be disposed on the sealing member 390 and the upper electrode 340. The encapsulation substrate 450 and the substrate 110 may comprise substantially the same material. For example, the encapsulation substrate 450 may comprise at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, and an alkali-free glass substrate. In some example embodiments, the encapsulation substrate 450 may comprise a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate 450 may comprise a flexible transparent resin substrate. In this case, to increase the flexibility of the OLED display device 100, the encapsulation substrate 450 may have a stacked structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacked structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, the flexible first inorganic layer may be disposed along the contour of the upper electrode 340, and the flexible organic layer may be disposed on the first inorganic layer. The flexible second inorganic layer may be disposed on the organic layer. In other words, the stacked structure may correspond to a thin film encapsulation structure that is in direct contact with the upper electrode 340.

[0103] Since the OLED display device 100 according to example embodiments includes the first oxide transistor 650 having relatively high electron mobility, the gate driver 300 can include a relatively small number of transistors. Therefore, the unused space of the OLED display device 100 can be reduced. In addition, since the gate driver 300 includes a relatively small number of transistors, the manufacturing cost of the OLED display device 100 can be reduced. In addition, since the second oxide transistor 250 includes the second oxide semiconductor pattern 130 that does not include Sn, the second oxide transistor 250 can have a relatively large driving range.

[0104] Figures 5 to 11 is a cross-sectional view illustrating a method of manufacturing an OLED display device according to example embodiments.

[0105] Reference Figure 5 A substrate 110 including a transparent insulating material or an opaque insulating material may be provided. The substrate 110 may be formed using at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and combinations thereof.

[0106] A buffer layer 115 may be formed on the entire substrate 110. The buffer layer 115 may prevent the diffusion of metal atoms and / or impurities from the substrate 110. In addition, when the surface of the substrate 110 is relatively irregular, the buffer layer 115 may improve the surface flatness of the substrate 110. Depending on the type of substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be formed. For example, the buffer layer 115 may include an organic material or an inorganic material. Alternatively, the substrate 110 may be formed using a flexible transparent resin substrate (e.g., a polyimide substrate). In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, and a second polyimide layer, etc. For example, the substrate 110 may have a structure in which a first polyimide layer, a barrier film layer, and a second polyimide layer are sequentially stacked on a rigid glass substrate.

[0107] A first preliminary oxide semiconductor layer 531 may be formed on the buffer layer 115. In the display region 10 and the peripheral region 20, the first preliminary oxide semiconductor layer 531 may be formed on the entire buffer layer 115. After the first preliminary oxide semiconductor layer 531 is formed on the entire buffer layer 115, the first preliminary oxide semiconductor layer 531 may be selectively etched. For example, the first preliminary oxide semiconductor layer 531 may be etched by a first wet etching process. The first etchant used in the first wet etching process may be a compound including fluorine (F). For example, the first etchant may include sodium fluoride (NaF), sodium bifluoride (NaHF2), ammonium fluoride (NH4F), ammonium bifluoride (NH4HF2), ammonium fluoroborate (NH4BF4), potassium fluoride (KF), potassium bifluoride (KHF2), aluminum fluoride (AlF3), fluoroboric acid (HBF4), lithium fluoride (LiF), potassium fluoroborate (KBF4), or calcium fluoride (CaF2), etc.

[0108] Reference Figure 6 After patterning the first preliminary oxide semiconductor layer 531 by a first wet etching process, a first oxide semiconductor pattern 530 in the peripheral region 20 and a third oxide semiconductor pattern 135 in the display region 10 may be formed on the buffer layer 115. Each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 may be formed using an oxide semiconductor including Sn. In other words, each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 may include an oxide semiconductor layer including AB x , AB x C y and AB x C y D zAt least one of the compounds described above. These compounds contain Sn and at least one of In, Zn, Ga, Ti, Al, Hf, Zr, and Mg. For example, each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 may include at least one of SnO, ITO, ZTO, IZTO, TAZO, IGTO, and ITGZO. In example embodiments, each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 may consist essentially of ITGZO.

[0109] Reference Figure 7 , a second preliminary oxide semiconductor layer 131 may be formed on the buffer layer 115, the first oxide semiconductor pattern 530, and the third oxide semiconductor pattern 135. In the display area 10 and the peripheral area 20, the second preliminary oxide semiconductor layer 131 may be completely formed on the buffer layer 115, the first oxide semiconductor pattern 530, and the third oxide semiconductor pattern 135. Here, when the second preliminary oxide semiconductor layer 131 is formed on the buffer layer 115, the first oxide semiconductor pattern 530, and the third oxide semiconductor pattern 135, the lower surface of the second preliminary oxide semiconductor layer 131 may be in direct contact with the upper surface of the first oxide semiconductor pattern 530 and the upper surface of the third oxide semiconductor pattern 135. After the second preliminary oxide semiconductor layer 131 is completely formed on the buffer layer 115, the first oxide semiconductor pattern 530, and the third oxide semiconductor pattern 135, the second preliminary oxide semiconductor layer 131 may be partially etched. For example, the second preliminary oxide semiconductor layer 131 may be etched by a second wet etching process. In an example embodiment, a second etchant may be used in the second wet etching process, and the second etchant may be different from the first etchant. For example, the second etchant used in the second wet etching process may include an etchant in which the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 are not etched when the second preliminary oxide semiconductor layer 131 is etched. The second etchant may be a mixed solution containing phosphoric acid, acetic acid, nitric acid, etc. In an example embodiment, the second etchant may be substantially composed of phosphoric acid, acetic acid, and nitric acid. In addition, the second etchant may be in direct contact with the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135. Since each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 contains Sn, each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 may not react with the second etchant. In other words, each of the first oxide semiconductor pattern 530 and the third oxide semiconductor pattern 135 will not be etched by the second etchant.

[0110] Reference Figure 8After patterning the second preliminary oxide semiconductor layer 131 by the second wet etching process, a second oxide semiconductor pattern 130 may be formed on the buffer layer 115 in the display area 10. The second oxide semiconductor pattern 130 may be spaced apart from the third oxide semiconductor pattern 135. The second oxide semiconductor pattern 130 may be formed using an oxide semiconductor that does not contain Sn. In other words, the second oxide semiconductor pattern 130 may include an oxide semiconductor layer including AB x , AB x C y and AB x C y D z At least one of the compounds described above. These compounds include at least one of In, Zn, Ga, Ti, Al, Hf, Zr, and Mg. For example, the second oxide semiconductor pattern 130 may include at least one of ZnO, GaO, TiO, InO, IGO, IZO, GZO, ZMO, ZnZrO, IGZO, and IGHO. In example embodiments, the second oxide semiconductor pattern 130 may consist essentially of IGZO.

[0111] In example embodiments, although the first oxide semiconductor pattern 530, the third oxide semiconductor pattern 135, and the second oxide semiconductor pattern 130 are formed in different process steps, the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135 can be located on the same layer (e.g., the buffer layer 115).

[0112] Reference Figure 9, a gate insulating layer 150 may be formed on the buffer layer 115 and the first, second, and third oxide semiconductor patterns 530, 130, and 135. In the peripheral region 20, the gate insulating layer 150 may cover the first oxide semiconductor pattern 530 on the buffer layer 115 and may extend in the second direction D2 on the buffer layer 115. Furthermore, in the display region 10, the gate insulating layer 150 may cover the second and third oxide semiconductor patterns 130, 135 on the buffer layer 115 and may extend in the second direction D2 on the buffer layer 115. That is, the gate insulating layer 150 may be formed on the entire buffer layer 115. For example, the gate insulating layer 150 may fully cover the first, second, and third oxide semiconductor patterns 530, 130, and 135 on the buffer layer 115 and may have a substantially flat upper surface without stepped portions around the first, second, and third oxide semiconductor patterns 530, 130, and 135. Alternatively, the gate insulating layer 150 may cover the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135 on the buffer layer 115, and may be formed to have a substantially uniform thickness along the contours of the first oxide semiconductor pattern 530, the second oxide semiconductor pattern 130, and the third oxide semiconductor pattern 135. The gate insulating layer 150 may be formed using a silicon compound or a metal oxide, etc. For example, the gate insulating layer 150 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x or TiO x wait.

[0113] In the peripheral region 20, a first gate electrode 570 may be formed on the gate insulating layer 150. The first gate electrode 570 may be formed on a portion of the gate insulating layer 150 under which the first oxide semiconductor pattern 530 is disposed. The first gate electrode 570 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. For example, the first gate electrode 570 may include Au, Ag, Al, W, Cu, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, Mo, Sc, Nd, Ir, an alloy of aluminum, AlN, or the like.x , silver alloy, WN x , copper alloy, molybdenum alloy, TiN x 、CrN x 、TaN x 、SRO、ZnO x 、ITO、SnO x 、InO x 、GaO x Or IZO, etc. These materials may be used alone or in appropriate combination thereof. Alternatively, the first gate electrode 570 may have a multilayer structure including a plurality of layers.

[0114] In the display area 10, the second gate electrode 170 may be formed on the gate insulating layer 150. The second gate electrode 170 may be formed on a portion of the gate insulating layer 150 under which the second oxide semiconductor pattern 130 is provided. The second gate electrode 170 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the second gate electrode 170 may have a multilayer structure including a plurality of layers.

[0115] In the display area 10, the third gate electrode 175 may be formed on the gate insulating layer 150 and may be spaced apart from the second gate electrode 170 in the second direction D2. The third gate electrode 175 may be formed on a portion of the gate insulating layer 150 under which the third oxide semiconductor pattern 135 is provided. The third gate electrode 175 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the third gate electrode 175 may have a multilayer structure including a plurality of layers.

[0116] For example, after forming the first preliminary electrode layer on the entire gate insulating layer 150, the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 can be simultaneously formed by partially etching the first preliminary electrode layer. In other words, the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 can be formed using the same material and can be located on the same layer (e.g., the gate insulating layer 150).

[0117] An insulating interlayer 190 may be formed on the gate insulating layer 150, the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175. In the peripheral region 20, the insulating interlayer 190 may cover the first gate electrode 570 on the gate insulating layer 150 and may extend in the second direction D2 on the gate insulating layer 150. Furthermore, in the display region 10, the insulating interlayer 190 may cover the second gate electrode 170 and the third gate electrode 175 on the gate insulating layer 150 and may extend in the second direction D2 on the gate insulating layer 150. That is, the insulating interlayer 190 may be formed over the entire gate insulating layer 150. For example, the insulating interlayer 190 may fully cover the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 on the gate insulating layer 150 and may have a substantially flat upper surface without stepped portions around the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175. Alternatively, the insulating interlayer 190 may cover the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175 on the gate insulating layer 150, and may be formed to have a substantially uniform thickness along the contours of the first gate electrode 570, the second gate electrode 170, and the third gate electrode 175. The insulating interlayer 190 may be formed using a silicon compound, a metal oxide, or the like.

[0118] In the peripheral region 20, a first source electrode 610 and a first drain electrode 630 may be formed on the insulating interlayer 190. The first source electrode 610 may contact the source region of the first oxide semiconductor pattern 530 via a first contact hole formed by removing a first portion of the gate insulating layer 150 and the insulating interlayer 190, and the first drain electrode 630 may contact the drain region of the first oxide semiconductor pattern 530 via a second contact hole formed by removing a second portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the first source electrode 610 and the first drain electrode 630 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the first source electrode 610 and the first drain electrode 630 may have a multilayer structure including multiple layers. Thus, a first oxide transistor 650 including the first oxide semiconductor pattern 530, the first gate electrode 570, the first source electrode 610, and the first drain electrode 630 may be formed.

[0119] In the display area 10, a second source electrode 210 and a second drain electrode 230 may be formed on the insulating interlayer 190. The second source electrode 210 may contact the source region of the second oxide semiconductor pattern 130 via a third contact hole formed by removing a third portion of the gate insulating layer 150 and the insulating interlayer 190, and the second drain electrode 230 may contact the drain region of the second oxide semiconductor pattern 130 via a fourth contact hole formed by removing a fourth portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the second source electrode 210 and the second drain electrode 230 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the second source electrode 210 and the second drain electrode 230 may have a multilayer structure including multiple layers. Thus, a second oxide transistor 250 including the second oxide semiconductor pattern 130, the second gate electrode 170, the second source electrode 210, and the second drain electrode 230 may be formed.

[0120] In the display area 10, a third source electrode 215 and a third drain electrode 235 may be formed on the insulating interlayer 190. The third source electrode 215 may contact the source region of the third oxide semiconductor pattern 135 via a fifth contact hole formed by removing the fifth portion of the gate insulating layer 150 and the insulating interlayer 190, and the third drain electrode 235 may contact the drain region of the third oxide semiconductor pattern 135 via a sixth contact hole formed by removing the sixth portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the third source electrode 215 and the third drain electrode 235 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the third source electrode 215 and the third drain electrode 235 may have a multilayer structure including multiple layers. Thus, a third oxide transistor 255 including the third oxide semiconductor pattern 135, the third gate electrode 175, the third source electrode 215, and the third drain electrode 235 may be formed.

[0121] For example, after forming the second preliminary electrode layer on the entire insulating interlayer 190, the first source electrode 610 and the first drain electrode 630, the second source electrode 210 and the second drain electrode 230, and the third source electrode 215 and the third drain electrode 235 can be simultaneously formed by partially etching the second preliminary electrode layer. In other words, the first source electrode 610 and the first drain electrode 630, the second source electrode 210 and the second drain electrode 230, and the third source electrode 215 and the third drain electrode 235 can be formed using the same material and can be located on the same layer (e.g., the insulating interlayer 190).

[0122] Reference Figure 10 , a planarization layer 270 may be formed on the insulating interlayer 190, the first source electrode 610 and the first drain electrode 630, the second source electrode 210 and the second drain electrode 230, and the third source electrode 215 and the third drain electrode 235. For example, the planarization layer 270 may be formed with a high thickness to sufficiently cover the first source electrode 610 and the first drain electrode 630, the second source electrode 210 and the second drain electrode 230, and the third source electrode 215 and the third drain electrode 235 on the insulating interlayer 190. In this case, the planarization layer 270 may have a substantially flat upper surface, and a planarization process may also be performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. A portion of the upper surface of the third drain electrode 235 may be exposed through a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In example embodiments, the planarization layer 270 may be formed using an organic material such as polyimide, epoxy-based resin, acrylic-based resin, polyester, photoresist, polyacrylic-based resin, polyimide-based resin, polyamido resin, or siloxane-based resin.

[0123] In the display area 10, a lower electrode 290 may be formed on the planarization layer 270. The lower electrode 290 may be in direct contact with the third drain electrode 235 via a contact hole in the planarization layer 270. The lower electrode 290 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0124] A pixel defining layer 310 may be formed on a portion of the lower electrode 290 and the planarization layer 270. The pixel defining layer 310 may cover both side portions of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or an inorganic material. In example embodiments, the pixel defining layer 310 may be formed using an organic material.

[0125] A light-emitting layer 330 may be formed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of the light-emitting materials capable of generating light of different colors (e.g., red light, blue light, and green light, etc.) according to the first, second, and third OLEDs. Alternatively, the light-emitting layer 330 may generate white light by stacking a plurality of light-emitting materials capable of generating light of different colors such as red light, green light, and blue light. In this case, a color filter may be formed on the light-emitting layer 330. The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin or a color photoresist, etc.

[0126] The upper electrode 340 may be formed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be formed entirely on the light emitting layer 330 and the pixel defining layer 310. In some example embodiments, the upper electrode 340 may be formed in the peripheral region 20. The upper electrode 340 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These materials may be used alone or in appropriate combinations thereof. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Thus, a sub-pixel structure 200 including the lower electrode 290, the light emitting layer 330, and the upper electrode 340 may be formed.

[0127] Reference Figure 11 In the outermost portion of the peripheral region 20, a sealing member 390 may be formed on the substrate 110. The lower surface of the sealing member 390 may be in direct contact with the insulating interlayer 190. Alternatively, the buffer layer 115, the gate insulating layer 150, and the insulating interlayer 190 on which the sealing member 390 is provided may not be formed, and the lower surface of the sealing member 390 may be in direct contact with the upper surface of the substrate 110. The sealing member 390 may be formed using glass frit, etc. Furthermore, the sealing member 390 may further include a photocurable material. For example, the sealing member 390 may include a compound such as an organic material and a photocurable material. Furthermore, after irradiating the compound with at least one of ultraviolet rays, a laser beam, and visible light, the compound may be cured, thereby obtaining the sealing member 390. The photocurable material included in the sealing member 390 may include an epoxy acrylate-based resin, a polyester acrylate-based resin, a polyurethane acrylate-based resin, a polybutadiene acrylate-based resin, a silicone acrylate-based resin, or an alkyl acrylate-based resin.

[0128] An encapsulation substrate 450 may be formed on the sealing member 390 and the upper electrode 340. The encapsulation substrate 450 and the substrate 110 may comprise substantially the same material. For example, the encapsulation substrate 450 may be formed using at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, and an alkali-free glass substrate. In some example embodiments, the encapsulation substrate 450 may comprise a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate 450 may comprise a flexible transparent resin substrate. In this case, to increase the flexibility of the OLED display device, the encapsulation substrate 450 may have a stacked structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacked structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, the flexible first inorganic layer may be formed along the contour of the upper electrode 340, and the flexible organic layer may be formed on the first inorganic layer. The flexible second inorganic layer may be formed on the organic layer. In other words, the stacked structure may correspond to a thin film encapsulation structure that is in direct contact with the upper electrode 340.

[0129] After forming the package substrate 450, a laser may be irradiated on the portion of the upper surface of the package substrate 450 that overlaps with the sealing member 390. According to the irradiation of the laser light, the state of the compound of the sealing member 390 may change from a solid state to a liquid state. In addition, after a predetermined time, the liquid compound may solidify into a solid state. According to the change in the state of the compound, the compound may seal the substrate 110 and the package substrate 450. Thus, it is possible to manufacture Figure 4 The OLED display device 100 shown in FIG.

[0130] In the method of manufacturing an OLED display device according to example embodiments, since oxide transistors having different characteristics from each other are manufactured in the same layer by using first and second etchants without adding a mask, the manufacturing cost of the OLED display device may be relatively reduced.

[0131] Figure 12 1 is a plan view showing an OLED display device according to an example embodiment. In addition to the first bottom metal pattern 510 and the second bottom metal pattern 540, Figure 12 The OLED display device 500 shown in FIG. 4 may have the same Figures 1 to 4 The configuration of the OLED display device 100 described is substantially the same or similar configuration. Figure 12 In the middle, you can avoid duplication and reference Figures 1 to 4 Detailed description of elements that are described that are substantially the same or similar.

[0132] Reference Figure 12The OLED display device 500 may include a substrate 110, a first bottom metal pattern 510, a second bottom metal pattern 540, a buffer layer 115, a first oxide transistor 650, a second oxide transistor 250, a third oxide transistor 255, a gate insulating layer 150, an insulating interlayer 190, a planarization layer 270, a sub-pixel structure 200, a pixel defining layer 310, a sealing member 390, and an encapsulation substrate 450. The first oxide transistor 650 may include a first oxide semiconductor pattern 530, a first gate electrode 570, a first source electrode 610, and a first drain electrode 630, and the second oxide transistor 250 may include a second oxide semiconductor pattern 130, a second gate electrode 170, a second source electrode 210, and a second drain electrode 230. In addition, the third oxide transistor 255 may include a third oxide semiconductor pattern 135, a third gate electrode 175, a third source electrode 215, and a third drain electrode 235. In addition, the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340. Since the OLED display device 500 has the display area 10 and the peripheral area 20 , the substrate 110 may be divided into the display area 10 and the peripheral area 20 .

[0133] In the peripheral region 20, the first bottom metal pattern 510 may be provided between the substrate 110 and the buffer layer 115. The first bottom metal pattern 510 may be located below the first oxide transistor 650. In example embodiments, the first bottom metal pattern 510 may be electrically connected to the first gate electrode 570. In this case, the first oxide transistor 650 may function as a transistor having a dual-gate structure. Therefore, the first oxide transistor 650 may function as a transistor driven by the gate driver 300 using a high current.

[0134] In the display area 10, the second bottom metal pattern 540 may be provided between the substrate 110 and the buffer layer 115. The second bottom metal pattern 540 may be located below the second oxide transistor 250. In example embodiments, the second bottom metal pattern 540 may be electrically connected to the second source electrode 210. In this case, the output saturation characteristic of the second oxide transistor 250 may be improved, and the driving range of the second oxide transistor 250 may be ensured.

[0135] In some example embodiments, the OLED display device 500 may further include a third bottom metal pattern disposed under the third oxide transistor 255. In some example embodiments, the OLED display device 500 may further include an insulating layer disposed under the first and second bottom metal patterns 510 and 540.

[0136] The present invention can be applied to various display devices including organic light-emitting diode displays, for example, vehicle displays, ship displays, aircraft displays, portable communication devices, displays for displaying or transmitting information, and medical displays.

[0137] The foregoing is an illustration of example embodiments and is not to be construed as limiting the same. Although a number of example embodiments have been described, it will be readily apparent to those skilled in the art that many modifications may be made to the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and is not to be construed as being limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the present inventive concept.

Claims

1. A method for manufacturing an organic light emitting diode display device, wherein: The organic light emitting diode display device comprises: a substrate having a display area including a plurality of sub-pixel areas, and a peripheral area located next to the display area; a first oxide transistor in the peripheral region on the substrate, the first oxide transistor including a first oxide semiconductor pattern including tin; a second oxide transistor, wherein the second oxide transistor is located in each sub-pixel region on the substrate, the second oxide transistor includes a second oxide semiconductor pattern, and the first oxide transistor and the second oxide transistor are located in the same layer; a third oxide transistor, the third oxide transistor being disposed in each sub-pixel region on the substrate, the third oxide transistor comprising a third oxide semiconductor pattern, the third oxide semiconductor pattern comprising tin, and the first oxide semiconductor pattern, the second oxide semiconductor pattern, and the third oxide semiconductor pattern being located in the same layer; and A sub-pixel structure, the sub-pixel structure being on the second oxide transistor, the sub-pixel structure comprising: lower electrode; a light-emitting layer disposed on the lower electrode; and an upper electrode disposed on the light-emitting layer, wherein the second oxide transistor corresponds to a driving transistor, and the third oxide transistor corresponds to a switching transistor, wherein the second oxide semiconductor pattern does not include tin, wherein each of the second oxide transistor and the third oxide transistor overlaps with the lower electrode of the sub-pixel structure, The method comprises: providing the substrate; forming a first preliminary oxide semiconductor layer on the substrate; After patterning the first preliminary oxide semiconductor layer using a first etchant, forming the first oxide semiconductor pattern in the peripheral region, and simultaneously forming the third oxide semiconductor pattern in each of the sub-pixel regions; forming a second preliminary oxide semiconductor layer on the substrate and the first and third oxide semiconductor patterns; forming a second oxide semiconductor pattern in each of the sub-pixel regions after patterning the second preliminary oxide semiconductor layer using a second etchant different from the first etchant, wherein the first oxide semiconductor pattern and the third oxide semiconductor pattern are not etched by the second etchant; and The sub-pixel structure is formed on the second oxide semiconductor pattern.

2. The method according to claim 1, wherein The first oxide transistor further includes: a first gate electrode disposed on the first oxide semiconductor pattern; and A first source electrode and a first drain electrode are provided on the first gate electrode.

3. The method according to claim 1, wherein The organic light emitting diode display device further includes: a gate driver generating a gate signal, the gate driver being disposed in the peripheral region on the substrate, the gate driver including a transistor, The transistor included in the gate driver corresponds to the first oxide transistor.

4. The method according to claim 1, wherein The first oxide semiconductor pattern and the third oxide semiconductor pattern include the same material.

5. The method according to claim 1, wherein The first oxide semiconductor pattern includes at least one of tin oxide, indium tin oxide, zinc tin oxide, indium zinc tin oxide, tin aluminum zinc oxide, indium gallium tin oxide, and indium tin gallium zinc oxide.

6. The method according to claim 1, wherein The second oxide semiconductor pattern includes at least one of zinc oxide, gallium oxide, titanium oxide, indium oxide, indium gallium oxide, indium zinc oxide, gallium zinc oxide, zinc magnesium oxide, zinc zirconium oxide, indium gallium zinc oxide, and indium gallium hafnium oxide.

Images