Image sensor having a grating structure therein providing enhanced diffraction of incident light

Abstract

The image sensor may include a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart photoelectric conversion regions at adjacent positions therein. A grating structure is disposed on the light receiving surface. The grating structure extends relative to each of the plurality of spaced-apart photoelectric conversion regions. An optically transparent layer is disposed on the grating structure. The grating structure includes a plurality of spaced-apart grating patterns, which may have the same height and the same width. In addition, the grating patterns may be spaced a uniform distance from each other. The grating structure is configured to selectively generate ±1st order or higher order diffracted light to the photoelectric conversion region in response to light incident thereon.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0104648, filed on September 3, 2018, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to image sensors, and in particular to image sensors that sense incident light including relatively long wavelength light with improved sensitivity. Background Art

[0004] An image sensor is an electronic device that converts an optical image into an electrical signal within the device. With the recent development of the computer and communication industries, there is an increased demand for high-performance image sensors in various applications such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, miniature cameras for medical applications, and / or robots. In addition, image sensors for realizing three-dimensional images and / or color images are being developed recently. Summary of the invention

[0005] Some embodiments of the present invention provide an image sensor having improved sensitivity to incident light including relatively long wavelength light. For example, in some of these embodiments, an image sensor is provided, which includes a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart photoelectric conversion regions at adjacent positions therein. A grating structure is also provided near the light receiving surface, which extends relative to each of the plurality of spaced-apart photoelectric conversion regions. The grating structure may include a plurality of spaced-apart grating patterns having the same height and the same width. An optically transparent layer is disposed on the grating structure.

[0006] According to another embodiment of the present invention, a plurality of spaced apart grating patterns are spaced apart from each other by a uniform distance. And, in some cases, the spacing between adjacent grating patterns may be equal to twice the width of the grating pattern. Advantageously, in another embodiment of the present invention, the grating structure is configured to generate ±1 or higher order diffracted light to the photoelectric conversion region in response to light incident thereon, while relatively suppressing zero order diffracted light. In a further embodiment, the grating structure comprises a semiconductor material. The grating structure may also include a wider range of materials having a lower refractive index relative to the semiconductor substrate.

[0007] According to a further embodiment of the present invention, each of the plurality of spaced-apart photoelectric conversion regions is separated from an adjacent photoelectric conversion region by a corresponding pixel separation structure. In some embodiments, these pixel separation structures may extend completely through the semiconductor substrate.

[0008] According to another embodiment of the present invention, an image sensor may include: a semiconductor substrate having a first surface and a second surface facing each other and including a plurality of pixel regions; photoelectric conversion regions respectively disposed on the pixel regions of the semiconductor substrate; a grating pattern disposed on the first surface of the semiconductor substrate and spaced apart from each other by a uniform distance; and an optically transparent layer disposed to cover the grating pattern. The grating pattern may have substantially the same width and substantially the same height to achieve desired light diffraction characteristics.

[0009] Another embodiment of the image sensor may include: a semiconductor substrate of a first conductivity type; a photoelectric conversion region disposed in the semiconductor substrate and doped to have a second conductivity type; and a grating structure disposed on the semiconductor substrate. The grating structure may include a grating pattern configured to provide diffracted light generated by diffraction of incident light to the photoelectric conversion region and preferentially suppress zero-order diffracted light. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0011] Figure 1 is a schematic diagram illustrating an image sensor system according to some embodiments of the inventive concept.

[0012] Figure 2 is a block diagram illustrating an image sensor according to some embodiments of the inventive concept.

[0013] Figure 3 is a circuit diagram illustrating an active pixel sensor array of an image sensor according to some embodiments of the inventive concept.

[0014] Figure 4 is a schematic plan view illustrating an image sensor according to some embodiments of the inventive concept.

[0015] Figure 5 and Figure 6 They are along Figure 4 1 and 1 and illustrate a cross-sectional view of an image sensor according to some embodiments of the inventive concept.

[0016] Figure 7 is a diagram illustrating a grating structure provided in an image sensor according to some embodiments of the inventive concept.

[0017] Figure 8 is a schematic plan view of an image sensor according to some embodiments of the inventive concept.

[0018] Fig. 9is a schematic plan view of an image sensor according to some embodiments of the inventive concept.

[0019] Fig.10 Shown along Fig. 9 A pair of cross-sectional views of an image sensor according to some embodiments of the inventive concept are taken along lines AA′ and BB′ of FIG.

[0020] Fig.11A , Fig. 11B and Fig. 11C is a schematic plan view illustrating an image sensor according to some embodiments of the inventive concept.

[0021] Fig. 12A and Fig. 12B is a schematic plan view illustrating an image sensor according to some embodiments of the inventive concept.

[0022] Fig.13 It is along Fig. 12A , and illustrates a cross-sectional view of an image sensor according to some embodiments of the inventive concept.

[0023] Fig.14 and Fig.15 is a cross-sectional view illustrating an image sensor according to some embodiments of the inventive concept.

[0024] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values ​​or properties covered by the example embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0025] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0026] Figure 1 is a schematic diagram illustrating an image sensor system according to some embodiments of the inventive concept. Figure 1, an image sensor system according to some embodiments of the inventive concept may be configured to irradiate light to an object 0, sense light reflected from the object 0, and calculate an optical depth or distance D to the object 0. The image sensor system may include: a light source 1 that transmits light to the object 0; an image sensor 2 that senses light reflected from the object 0; and a timing controller 3 that is configured to provide a synchronization signal to the light source 1 and the image sensor 2.

[0027] The light source 1 may emit a pulse optical signal to the object 0. In some embodiments, the light source 1 may be configured to emit infrared light, microwaves, or visible light. A light emitting diode (LED), a laser diode (LD), or an organic light emitting diode (OLED) may be used for the light source 1.

[0028] The image sensor 2 may be formed to sense light reflected from the object 0 and output information about the optical depth to the object 0. Similar to an infrared camera, the optical depth information may be used to realize a three-dimensional picture. In addition, the image sensor 2 may include depth pixels and visible light pixels, and in this case, a three-dimensional color image may be realized.

[0029] The timing controller 3 may control the operations of the light source 1 and the image sensor 2. For example, the timing controller 3 may be configured to synchronize the light emission operation of the light source 1 with the light reception operation of the image sensor 2.

[0030] Figure 2 is a block diagram illustrating an image sensor according to some embodiments of the inventive concept. Figure 2 , the image sensor may include an active pixel sensor array (APS) 10, a row decoder 20, a row driver 30, a column decoder 40, a controller 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output (I / O) buffer 80.

[0031] The active pixel sensor array 10 may include a plurality of unit pixels arranged two-dimensionally and may be used to convert an optical signal into an electrical signal. The active pixel sensor array 10 may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) transmitted from the row driver 30. The converted electrical signal may be provided to the correlated double sampler 60.

[0032] The row driver 30 may be configured to generate a driving signal for driving the unit pixel based on the information decoded by the row decoder 20, and then transmit the driving signal to the active pixel sensor array 10. When the unit pixels are arranged in a matrix form (i.e., in rows and columns), the driving signal may be provided to each row. The controller 50 may provide a timing signal and a control signal to the row decoder 20 and the column decoder 40.

[0033] The correlated double sampler 60 may be configured to receive an electrical signal generated in the active pixel sensor array 10 and then perform an operation of holding and sampling the received electrical signal. For example, the correlated double sampler 60 may perform a double sampling operation on a specific noise level and a signal level of the electrical signal and then output a difference level corresponding to the difference between the noise level and the signal level.

[0034] The analog-to-digital converter 70 may be configured to convert an analog signal including information on a difference level output from the correlated double sampler 60 into a digital signal and then output the digital signal.

[0035] The I / O buffer 80 may be configured to latch digital signals and then sequentially output the latched digital signals to an image signal processing unit (not shown) based on information decoded by the column decoder 40 .

[0036] Figure 3 is a circuit diagram showing an active pixel sensor array of an image sensor according to some embodiments of the inventive concept. Figure 3 , the active pixel sensor array 10 may include a plurality of unit pixels P arranged two-dimensionally in rows and columns. In each unit pixel P, an electrical signal may be generated by incident light, and the operation of each unit pixel P may be controlled by a driving signal transmitted through a charge transfer line TG, a reset line RG, and a pixel selection line SG connected to the unit pixel P.

[0037] Each unit pixel P may include a transfer transistor TX and logic transistors RX, SX, and DX. Here, the logic transistors may include a reset transistor RX, a selection transistor SX, and a source follower transistor or an amplification transistor AX.

[0038] The transfer transistor TX may include a transfer gate electrode TG, a photoelectric conversion device PD, and a charge storage node or a floating diffusion region FD. The photoelectric conversion device PD may be configured to generate photocharges in proportion to the amount of external incident light and store the photocharges. In some embodiments, the photoelectric conversion device PD may be provided in the form of a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or any combination thereof.

[0039] The transfer transistor TX may transfer the charge accumulated in the photoelectric conversion device PD to the charge storage node FD. The transfer transistor TX may be controlled by a charge transfer signal provided through the charge transfer line TG. The charge storage node FD may be configured to accumulate and store photocharges generated in the photoelectric conversion device PD, and the potential of the gate electrode of the source follower transistor AX may be changed according to the amount of photocharges stored in the charge storage node FD.

[0040] The reset transistor RX may be configured to periodically release the photocharge stored in the charge storage node FD. For example, the gate electrode of the reset transistor RX may be connected to a reset line RG, and a reset signal is provided to the reset line RG. The drain electrode of the reset transistor RX may be connected to the charge storage node FD, and the source electrode of the reset transistor RX may be connected to a power supply voltage V DD If the reset transistor RX is turned on by the reset signal, the power supply voltage V connected to the source electrode of the reset transistor RX can be DD In other words, if the reset transistor RX is turned on, the photo charges stored in the charge storage node FD may be released, and the charge storage node FD may be reset.

[0041] The source follower transistor AX may be configured to amplify a change in the potential of the charge storage node FD and output the amplified signal or pixel signal to the output line V through the selection transistor SX. OUT The source follower transistor AX may be a source follower buffer amplifier configured to generate a source-drain current in proportion to the amount of photocharge input through its gate electrode. The gate electrode of the source follower transistor AX may be connected to the charge storage node FD, and the drain electrode of the source follower transistor AX may be connected to the power supply voltage V DD , and the source electrode of the source follower transistor AX can be connected to the drain electrode of the selection transistor SX.

[0042] The selection transistor SX can be used to select each row of the unit pixel PX for a read operation. The selection gate electrode of the selection transistor SX can be connected to the selection line SG, and the selection signal is provided to the selection line SG. If the selection transistor SX is turned on by the selection signal, the pixel signal output through the source electrode of the source follower transistor AX can be output to the output line V OuT .

[0043] although Figure 3 An example is shown in which each unit pixel P is configured to have four transistors, but the unit pixel P may be configured to have a three or five transistor structure or a grating structure similar to a four transistor structure.

[0044] Figure 4 is a schematic plan view illustrating an image sensor according to some embodiments of the inventive concept. Figure 5 and Figure 6 They are respectively along Figure 4 The image sensor is taken along line AA′ to illustrate a cross-sectional view of an image sensor according to some embodiments of the inventive concept. Figure 7 is a diagram illustrating a grating structure provided in an image sensor according to some embodiments of the inventive concept.

[0045] refer to Figure 4 and Figure 5 , an image sensor according to some embodiments of the inventive concept may include a photoelectric conversion layer, a readout circuit layer 200, and an optically transparent layer 300. When viewed in a vertical cross-section, the photoelectric conversion layer may be disposed between the readout circuit layer 200 and the optically transparent layer 300.

[0046] The photoelectric conversion layer may include a semiconductor substrate 100 , a pixel separation structure 103 defining a pixel region PR, and a photoelectric conversion region 110 disposed in the pixel region PR.

[0047] In detail, the semiconductor substrate 100 may have two opposing surfaces (e.g., a first surface or front surface 100a and a second surface or back surface 100b). In some embodiments, a substrate in which an epitaxial layer of a first conductivity type (e.g., p-type) is formed on a bulk silicon substrate of a first conductivity type may be provided for the semiconductor substrate 100, and during a process of manufacturing an image sensor, the bulk silicon substrate may be removed. For example, a substrate having only a p-type epitaxial layer may be used as the semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 may be a bulk semiconductor substrate in which a well region of the first conductivity type is provided.

[0048] The semiconductor substrate 100 may include a plurality of pixel regions PR defined by the pixel separation structure 103. The pixel regions PR may be arranged in two different directions (eg, a first direction D1 and a second direction D2) or in a matrix shape.

[0049] When viewed in a plan view, the pixel separation structure 103 may be disposed to surround each pixel region PR. For example, the pixel separation structure 103 may include first portions extending parallel to each other in a first direction D1 and second portions extending parallel to each other in a second direction D2 to intersect the first portions.

[0050] The pixel separation structure 103 may be formed of or include an insulating material having a refractive index lower than that of the semiconductor substrate 100 (e.g., silicon), and may include one or more insulating layers. For example, the pixel separation structure 103 may be formed of or include silicon oxide, silicon nitride, undoped polysilicon, air, or any combination thereof. In some embodiments, the formation of the pixel separation structure 103 may include patterning the first surface 100a and / or the second surface 100b to form a deep trench in the semiconductor substrate 100, and then filling the deep trench with an insulating material.

[0051] The pixel separation structure 103 may be provided to penetrate the semiconductor substrate 100. For example, the vertical thickness of the pixel separation structure 103 may be substantially equal to the vertical thickness of the semiconductor substrate 100. In some embodiments, the vertical thickness of the pixel separation structure 103 may be less than the vertical thickness of the semiconductor substrate 100. In other words, the second surface 100b of the semiconductor substrate 100 may be spaced apart from the pixel separation structure 103. In some embodiments, the pixel separation structure 103 may be an impurity region formed by doping the semiconductor substrate 100 of the first conductivity type with impurities of the second conductivity type.

[0052] The photoelectric conversion regions 110 may be respectively disposed in the pixel regions PR of the semiconductor substrate 100. The photoelectric conversion regions 110 may be arranged two-dimensionally in the first direction D1 and the second direction D2. In some embodiments, the photoelectric conversion regions 110 may be formed by injecting impurities into the semiconductor substrate 100, and may be formed to have a second conductivity type different from the first conductivity type of the semiconductor substrate 100. In this case, the semiconductor substrate 100 of the first conductivity type and the photoelectric conversion region 110 of the second conductivity type may form a PN junction serving as a photodiode. External incident light may be converted into an electrical signal in the photoelectric conversion region 110.

[0053] The readout circuit layer 200 may be disposed on the first surface 100a of the semiconductor substrate 100. The readout circuit layer 200 may include a readout circuit (eg, a MOS transistor) electrically connected to the photoelectric conversion region 110.

[0054] For example, in each pixel region PR, a transfer gate electrode TG may be disposed on the first surface 100a of the semiconductor substrate 100, and further, a reference electrode TG may be disposed on the first surface 100a of the semiconductor substrate 100. Figure 3 Here, the readout circuit layer 200 may include the previously referenced Figure 3 The reset transistor RX, the select transistor SX and the source follower transistor AX are described.

[0055] As an example, when viewed in a plan view, the transfer gate electrode TG may be located in a central region of each pixel region PR. A portion of the transfer gate electrode TG may be placed in the semiconductor substrate 100, and a gate insulating layer may be interposed between the transfer gate electrode TG and the semiconductor substrate 100. The floating diffusion region FD may be provided in a portion of the semiconductor substrate 100 located on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by implanting impurities into the semiconductor substrate 100, and may have a conductivity type different from that of the semiconductor substrate 100. For example, the floating diffusion region FD may be an n-type impurity region.

[0056] The interlayer insulating layer 210 may be stacked on the first surface 100a of the semiconductor substrate 100 to cover the MOS transistor and the transfer gate electrode TG of the readout circuit. The interlayer insulating layer 210 may be formed of, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride or may include at least one of these. A connection line 215 may be provided on each interlayer insulating layer 210 and may be electrically connected to the readout circuit through a contact plug.

[0057] In some embodiments, in each pixel region PR, a grating structure 105 may be provided on the second surface 100b of the semiconductor substrate 100. The grating structure 105 may include a plurality of grating patterns 105a and a plurality of recessed regions 105b that are alternately arranged. The grating patterns 105a may be provided to have a uniform width (e.g., a first width a) and may be spaced apart from each other by a uniform distance (e.g., a first distance b). In other words, the width of each recessed region 105b may correspond to the first distance b. The recessed region 105b may have a bottom surface that is substantially parallel to the second surface 100b of the semiconductor substrate 100. In other words, the grating pattern 105a may have a uniform height h. Referring to FIG. Figure 7 The structure of the grating structure 105 is described in more detail.

[0058] In some embodiments, the incident light L of a long wavelength may be diffracted in the semiconductor substrate 100 by the grating structure 105 to form diffracted light DL having an order of ±1 or higher and incident in an oblique direction. Due to the change in the refractive index, there may be a phase difference of 180° between the light passing through the grating pattern 105a and the recessed area 105b, and thus, the zero-order diffracted light may be minimized and only ±1-order or higher-order diffracted light may be generated. In addition, as Figure 4 As shown, the diffracted light DL may be generated in a direction (ie, the first direction D1 ) perpendicular to the extending direction (ie, the second direction D2 ) of the grating pattern 105 a .

[0059] As an example, the grating patterns 105a may be linear patterns that are parallel to each other and extend in the second direction D2. In other words, the grating patterns 105a may be disposed to intersect each photoelectric conversion region 110 when viewed in a plan view.

[0060] like Figure 5 As shown, the grating structure 105 may be formed by forming an etching mask pattern on the second surface 100b of the semiconductor substrate 100 and anisotropically etching the second surface 100b of the semiconductor substrate 100 using the etching mask pattern. In other words, the grating pattern 105a of the grating structure 105 may be a part of the semiconductor substrate 100, which means that the grating pattern 105a and the semiconductor substrate 100 may be formed of the same semiconductor material.

[0061] like Figure 6 As shown, the grating structure 105 may include a plurality of dielectric patterns 115a, which are spaced apart from each other on the second surface 100b of the semiconductor substrate 100. For example, the grating structure 105 may include the dielectric pattern 115a and a recessed region 115b, and the recessed region 115b is defined by the side surface of the dielectric pattern 115a and the second surface 100b of the semiconductor substrate 100. As an example, the formation of the dielectric pattern 115a may include depositing a dielectric layer and patterning the dielectric layer on the second surface 100b of the semiconductor substrate 100. Here, the dielectric pattern 115a may be formed of or include a dielectric material having a refractive index different from that of the semiconductor substrate 100. As an example, the dielectric pattern 115a may be formed of an insulating material (e.g., silicon oxide) having a refractive index lower than that of the semiconductor substrate 100 (e.g., silicon).

[0062] The optical transparent layer 300 may be disposed on the second surface 100b of the semiconductor substrate 100 provided with the grating structure 105. The optical transparent layer 300 may include a first planarization insulating layer 311, a filter layer 313, a second planarization insulating layer 315, and a microlens 317.

[0063] The first planarization insulating layer 311 may cover the second surface 100b of the semiconductor substrate 100 on which the grating structure 105 is disposed. In other words, the first planarization insulating layer 311 may be disposed to fill the recessed regions 105b and 115b of the grating structure 105. The first planarization insulating layer 311 may be formed of or include an insulating material having a refractive index different from that of the semiconductor substrate 100. For example, the first planarization insulating layer 311 may be formed of an insulating material having a refractive index lower than that of silicon. For example, the first planarization insulating layer 311 may have a refractive index of about 1.4 to about 4.0.

[0064] The filter layer 313 may be configured to pass a portion of external incident light (e.g., light of a specific wavelength range). For example, the filter layer 313 may be configured to allow infrared light of the external incident light to propagate toward the photoelectric conversion region 110. In this case, the photoelectric conversion region 110 may be configured to sense the infrared light and generate an electrical signal.

[0065] The second planarization insulating layer 315 may be made of, for example, Al 2 O 3 , CeF 3 , HfO 2 、ITO、MgO、Ta 2 0 5 、TiO 2 、ZrO 2 , Si, Ge, ZnSe, ZnS and PbF 2Alternatively, the second planarization insulating layer 315 may be formed of at least one of an organic material having a high refractive index (e.g., siloxane resin, benzocyclobutene (BCB), polyimide, acrylic, polyparaxylene C, poly(methyl methacrylate) (PMMA), polyethylene terephthalate (PET), etc.) or include at least one of such organic materials having a high refractive index. In some embodiments, the second planarization insulating layer 315 may be formed of, for example, strontium titanate (SrTiO 3 ), polycarbonate, glass, bromine, sapphire, cubic zirconia, potassium niobate (KNbO 3 ), moissanite (SiC), gallium (III) phosphide (GaP), gallium (III) arsenide (GaAs), etc., or may include at least one of these.

[0066] The microlenses 317 may be disposed on the second planarization insulating layer 315 to face the photoelectric conversion regions 110, respectively. The microlenses 317 may be arranged two-dimensionally in two different directions (e.g., a first direction D1 and a second direction D2). The microlenses 317 may have an upwardly convex shape with a specific radius of curvature. The microlenses 317 may be configured to change the propagation path of light incident into the image sensor and to converge the incident light. The microlenses 317 may be formed of or include an optically transparent resin.

[0067] In some embodiments, long wavelength light of about 750 nm or longer may be incident into the photoelectric conversion region 110, and in this case, the long wavelength light may have a penetration depth greater than the thickness of the semiconductor substrate 100. In some embodiments, the long wavelength incident light L may be diffracted by the grating structure 105 to form diffracted light DL incident into the photoelectric conversion region 110.

[0068] refer to Figure 7 , the grating structure 105 according to some embodiments of the inventive concept may be configured to have a period Λ corresponding to the sum of a width a of the grating pattern 105a and a distance b of the grating pattern 105a (i.e., A=a+b). The grating structure 105 may have a filling factor (FF), which is defined as a ratio of a width a of the grating pattern 105a to a period Λ of the grating structure 105. In other words, the filling factor (FF) of the grating structure 105 may be given by the following formula 1.

[0069] [Formula 1]

[0070] FF=a / (a+b)

[0071] In some embodiments, the grating structure 105 may be designed to have a fill factor of 50%. In other words, the width a of the grating pattern 105a may be substantially equal to the distance b of the grating pattern 105a. As an example, the period A of the grating structure 105 may be in the range of about 0.6 μm to about 0.9 μm.

[0072] The diffracted light DL passing through the grating structure 105 may have a phase difference (ΔΦ) given by Formula 2 below.

[0073] [Formula 2]

[0074] ΔΦ=(n1-n2)h2π / λ

[0075] Wherein, λ is the wavelength of incident light, n1-n2 is the difference between the refractive indices, and h is the height of the grating pattern. In addition, n1 is the refractive index of the grating pattern, and n2 is the refractive index of the material (eg, the first planarization insulating layer 311) disposed between the grating patterns.

[0076] In some embodiments, the height h of the grating structure 105 may be determined to achieve a phase difference (ΔΦ) of 180°. As an example, the height h of the grating structure 105 may be in a range of about 0.2 μm to about 0.4 μm.

[0077] In some embodiments, the angle θ of the diffracted light DL may be given by Formula 3 below.

[0078] [Formula 3]

[0079] sinθ=mλ / nΛ

[0080] Where λ is the wavelength of the incident light, m ​​is the order of the grating, n is the refractive index of the grating pattern, and Λ is the period of the grating structure.

[0081] In some embodiments, the grating structure 105 may be formed to have a filling factor of 50% and a phase difference of 180°, and in this case, the grating structure 105 may generate ±1 or higher order diffraction light DL without zero order diffraction light. In some embodiments, the grating structure 105 may be configured to suppress zero order and even order diffraction light and provide odd order diffraction light DL to the photoelectric conversion region 110. In other words, as Figure 5 and Figure 6 As shown, the diffracted light DL may be provided to the semiconductor substrate 100 at an angle inclined to the surface of the semiconductor substrate 100. Therefore, the length of the propagation path of the incident light propagating toward the photoelectric conversion region 110 may be increased, and this may make it possible to improve the optical absorption efficiency (e.g., quantum efficiency) in the photoelectric conversion region 110.

[0082] As an example, when incident light L of about 940 nm wavelength is incident into the grating structure 105, the period Λ of the grating structure 105 may be about 0.6 μm, the width a of the grating pattern 105a may be about 0.3 μm, and the height h of the grating pattern 105a may be about 0.25 μm.

[0083] For the sake of brevity of description, elements similar to those in the previously described embodiment may be identified by the same reference numerals, and a repeated description thereof will not be repeated.

[0084] Figure 8 is a schematic plan view of an image sensor according to some embodiments of the inventive concept. Figure 5 and Figure 8 , the grating structure 105 may be disposed on the second surface 100b of the semiconductor substrate 100, and the grating structure 105 may include a plurality of grating patterns 105a and a plurality of recessed regions 105b between the grating patterns 105a, each of the grating patterns 105a having a first width a. Here, when viewed in a plan view, the grating patterns 105a and the recessed regions 105b may extend in an inclined direction inclined at an angle to both the first direction D1 and the second direction D2. Figure 8 In the illustrated embodiment, the grating structure 105 may generate diffracted light DL in a direction perpendicular to the extending direction of the grating pattern 105 a .

[0085] Fig. 9 is a schematic plan view of an image sensor according to some embodiments of the inventive concept. Fig.10 It is along Fig. 9 The image sensor is cut along the line AA' and the line BB' to illustrate a cross-sectional view of an image sensor according to some embodiments of the inventive concept. Fig. 9 and Fig.10 , the grating structure 105 may be disposed in each pixel region PR, and the grating structure 105 may include a grating pattern 105a and a recessed region 105b. Here, the grating pattern 105a may include a plurality of circular patterns disposed concentrically. Each circular pattern may have a first width a and may be spaced apart from each other by the same distance b.

[0086] according to Fig. 9 and Fig.10 In the embodiment shown in , the period, fill factor, and height of the grating structure 105 may be the same in all directions. Since the diffracted light DL generated in the grating structure 105 is generated in a direction perpendicular to the extension direction of the grating pattern 105a, the diffracted light DL may be generated in all directions. Therefore, the quantum efficiency of the photoelectric conversion region 110 may be uniform in all directions.

[0087] Fig.11A , Fig. 11B and Fig. 11C is a schematic plan view showing an image sensor according to some embodiments of the inventive concept. Fig.11A and Fig. 11B , the grating structure 105 may be disposed in each pixel region PR, and the grating structure 105 may include a grating pattern 105a and a recessed region 105b. The grating patterns 105a may have a first width a in both the first direction D1 and the second direction D2, and may be spaced apart from each other by the same distance b in both the first direction D1 and the second direction D2. In some embodiments, each grating pattern 105a may have a rectangular shape, a circular shape, or a polygonal shape when viewed in a plan view. Fig.11A , the grating patterns 105a may be arranged along the first direction D1 and the second direction D2 or in a matrix shape. Fig. 11B , the grating patterns 105a may be arranged in a chessboard shape. Fig. 11C , the grating patterns 105a may be arranged to be spaced apart from each other by the same distance b in a diagonal direction inclined to both the first direction D1 and the second direction D2. Fig.11A , Fig. 11B and Fig. 11C As shown, the grating structure 105 may have substantially the same period, fill factor, and height in the first direction D1 and the second direction D2.

[0088] Fig. 12A and Fig. 12B is a schematic plan view illustrating an image sensor according to some embodiments of the inventive concept. Fig.13 It is along Fig. 12A The cross-sectional view of the image sensor according to some embodiments of the inventive concept is shown by taking the line CC' of FIG. Fig. 12A and Fig.13 , a pixel separation structure 103a may be provided to define a plurality of pixel regions PR, each pixel region PR including a light receiving region R1 and a light blocking region R2 defined by an isolation structure 103b. The isolation structure 103b may cross each pixel region PR in the first direction D1 or the second direction D2.

[0089] When viewed in a vertical cross-section, the pixel separation structure 103a and the isolation structure 103b may vertically extend from the first surface 100a to the second surface 100b of the semiconductor substrate 100. The vertical thickness of the isolation structure 103b may be substantially equal to the vertical thickness of the pixel separation structure 103a.

[0090] In the light receiving region R1 of each pixel region PR, the grating structure 105 may be disposed on the second surface 100b of the semiconductor substrate 100. The grating structure 105 may include a plurality of grating patterns 105a and a plurality of recessed regions 105b between the grating patterns 105a, each grating pattern 105a having a first width a. The grating patterns 105a may be line patterns that are parallel to each other and extend in the second direction D2, as previously described with reference to Figure 4 and Figure 8 In certain embodiments, Fig. 12B As shown, the grating structure 105 may include a plurality of grating patterns 105a arranged along the first direction D1 and the second direction D2. In addition, the grating structure 105 may be arranged in a checkerboard shape or in a diagonal direction or in an oblique direction, as previously described with reference to Fig. 11B and Fig. 11C described.

[0091] In some embodiments, the grating structure 105 may be designed to provide ±1st-order or higher-order diffracted light DL without zero-order diffracted light to the photoelectric conversion region 110. Therefore, when viewed in a plan view, the diffracted light DL generated by the grating structure 105 may propagate in a direction perpendicular to the extension direction of the grating pattern 105a (e.g., in the first direction D1). In other words, incident light may be prevented or suppressed from being incident on the light blocking region R2 of each pixel region PR.

[0092] In addition, in the light blocking region R2, a light blocking pattern 320 may be disposed on the second surface 100b of the semiconductor substrate 100. The light blocking pattern 320 may be configured to reflect incident light and prevent the incident light from being incident into the second surface 100b of the semiconductor substrate 100. In other words, due to the light blocking pattern 320, the incident light may be prevented from being incident into the light blocking region R2 of each pixel region PR. The light blocking pattern 320 may be formed of or may include at least one of metal materials (e.g., tungsten or aluminum). In the case where the grating pattern 105a is formed by patterning the semiconductor substrate 100, a buffer insulating layer 312 may be disposed between the light blocking pattern 320 and the semiconductor substrate 100. Alternatively, in reference to Figure 6 In the case where the grating structure is formed using a dielectric layer, a light blocking pattern 320 may be disposed in the dielectric layer.

[0093] In the light blocking region R2 of each pixel region PR, the signal processing circuit TR may be disposed on the first surface 100a of the semiconductor substrate 100. The signal processing circuit TR may include at least one MOS transistor, and they may be configured to perform operations of holding and sampling electrical signals generated from the light receiving region R1. In addition, the readout circuit layer 200 may include a capacitor CAP for holding or storing electrical signals generated from the light receiving region R1. The capacitor CAP may include a top electrode and a bottom electrode and a dielectric layer therebetween. In this case, the image sensor may be configured so that a global shutter operation is possible.

[0094] Fig.14 and Fig.15 is a cross-sectional view showing an image sensor according to some embodiments of the inventive concept. Fig.14 , the first grating structure 107 may be disposed on the first surface 100a of the semiconductor substrate 100. Figures 4 to 7 As described above, the first grating structure 107 may include a plurality of first grating patterns 107 a and a plurality of first recessed regions 107 b arranged alternately. The first recessed regions 107 b may be filled with a material having a refractive index lower than that of the semiconductor substrate 100 .

[0095] The reflective layer 205 may be disposed on the first surface 100a of the semiconductor substrate 100, and the anti-reflective layer 310 may be disposed on the second surface 100b of the semiconductor substrate 100. The reflective layer 205 may cover the first grating structure 107 and may include at least one of a metal material, such as tungsten (W) or aluminum (Al). The anti-reflective layer 310 may be formed of or may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0096] As described above, the first grating structure 107 may be designed to cause diffraction of the incident light L of a long wavelength and suppress zero-order diffracted light. For example, the width a of the first grating pattern 107a may be substantially the same as the distance b between the first grating patterns 107a. The first grating pattern 107a may have a substantially uniform height h. As described above, the first grating structure 107 may include a line pattern extending in a specific direction (e.g., in the x-direction, the y-direction, or the diagonal direction), or may include a concentric circular pattern. In addition, the first grating structures 107 may be spaced apart from each other to form an array-shaped arrangement, as previously described with reference to Fig.11A , Fig. 11B and Fig. 11C described.

[0097] In some embodiments, long-wavelength incident light L of about 750 nm or longer may be incident into the semiconductor substrate 100 through the optically transparent layer 300, and in this case, the penetration depth of the long-wavelength incident light L may be greater than the thickness of the semiconductor substrate 100. The long-wavelength incident light L may be reflected by the reflective layer 205 disposed on the first surface 100 a of the semiconductor substrate 100, and in this case, the reflected light may be diffracted by the first grating structure 107 to form diffracted light DL that enters the photoelectric conversion region 110 again.

[0098] refer to Fig.15 , the first grating structure 107 may be disposed on the first surface 100 a of the semiconductor substrate 100 , and the second grating structure 105 may be disposed on the second surface 100 b of the semiconductor substrate 100 .

[0099] The first grating structure 107 may include a plurality of first grating patterns 107 a and a plurality of first recessed regions 107 b that are alternately arranged. The first recessed regions 107 b may be filled with a material having a refractive index lower than that of the semiconductor substrate 100 .

[0100] The second grating structure 105 may include a plurality of second grating patterns 105 a and a plurality of second recessed regions 105 b arranged alternately. The second recessed regions 105 b may be filled with a first planarization insulating layer 311 having a lower refractive index than that of the semiconductor substrate 100 .

[0101] The first grating structure 107 and the second grating structure 105 may be designed to cause diffraction of the incident light L of a long wavelength and suppress zero-order diffracted light. The first grating pattern 107a and the second grating pattern 105a may have substantially the same period.

[0102] As described above, the first grating structure 107 and the second grating structure 105 may include a line pattern extending in a specific direction (e.g., in the x-direction, the y-direction, or the diagonal direction), or may include concentric circular patterns. In addition, the first grating pattern 107a and the second grating pattern 105a may be line patterns extending in the same direction. In some embodiments, the first grating pattern 107a may be arranged to cross the second grating pattern 105a. In some embodiments, the first grating structure 107 and the second grating structure 105 may be spaced apart from each other to form an array-shaped arrangement, such as with reference to Fig.11A , Fig. 11B and Fig. 11C described.

[0103] According to some embodiments of the inventive concept, the second grating structure 105 may be configured to diffract incident light incident through the optically transparent layer 300 and provide first diffracted light DL1 generated by the diffraction to the photoelectric conversion region 110. The first grating structure 107 may be configured to diffract light reflected by the reflective layer and provide second diffracted light DL2 generated by the diffraction to the photoelectric conversion region 110.

[0104] As described above, since the first and second diffracted lights DL1 and DL2 diffracted by the first and second grating structures 107 and 105 of the semiconductor substrate 100 are provided to the photoelectric conversion region 110 , the quantum efficiency of the photoelectric conversion region 110 may be improved.

[0105] According to some embodiments of the present inventive concept, the image sensor may include a grating structure that causes diffraction of incident light, and in this case, the diffracted light generated by the grating structure may be incident on the photoelectric conversion region in a direction inclined to the surface of the semiconductor substrate. Therefore, the length of the propagation path of the incident light can be increased and the optical absorption efficiency (e.g., quantum efficiency) in the photoelectric conversion region can be improved.

[0106] In some embodiments, the grating structure may be configured to allow light to be isotropically incident into the photoelectric conversion region, and in this case, crosstalk between pixel regions adjacent to each other may be suppressed.

[0107] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: a semiconductor substrate having a first semiconductor surface and a second semiconductor surface opposite to the first semiconductor surface; a photoelectric conversion region in the semiconductor substrate; a transfer gate electrode on the first semiconductor surface of the semiconductor substrate; A grating structure, which is on the second semiconductor surface of the semiconductor substrate, the grating structure includes a plurality of grating patterns and a plurality of recessed areas arranged alternately, and the grating patterns have the same height and the same width; and an optically transparent layer on the grating structure; The multiple recessed regions of the grating structure are recessed from the second semiconductor surface of the semiconductor substrate.

2. The image sensor according to claim 1, wherein: The plurality of grating patterns are spaced apart from each other by a uniform distance.

3. The image sensor according to claim 2, wherein: The spacing between adjacent grating patterns is equal to twice the width of the grating patterns.

4. The image sensor according to claim 1, wherein: The spacing between adjacent grating patterns is equal to twice the width of the grating patterns.

5. The image sensor according to claim 1, wherein: The grating structure is configured to generate ±1st-order or higher-order diffracted light to the photoelectric conversion region while suppressing zeroth-order diffracted light in response to light incident thereon.

6. The image sensor according to claim 1, wherein: The grating structure includes a semiconductor material.

7. The image sensor according to claim 1, wherein: The grating structure includes a material having a lower refractive index relative to the semiconductor substrate.

8. The image sensor according to claim 1, wherein: The photoelectric conversion region is separated from adjacent photoelectric conversion regions by corresponding pixel separation structures.

9. The image sensor according to claim 8, wherein: The pixel separation structure extends completely through the semiconductor substrate.

10. The image sensor according to claim 2, wherein: The plurality of grating patterns are arranged as a plurality of concentric rings.

11. An image sensor, comprising: a semiconductor substrate having a first surface and a second surface facing each other; A pixel separation structure, wherein in the semiconductor substrate, the pixel separation structure defines a plurality of pixel regions; an isolation structure, in the semiconductor substrate, the isolation structure defining a light receiving region and a light blocking region in each of the plurality of pixel regions; Photoelectric conversion regions, which are respectively arranged in the light receiving regions of the pixel regions; grating patterns disposed in the light receiving region on the first surface of the semiconductor substrate and spaced apart from each other by a uniform distance, the grating patterns having the same width and the same height; a blocking pattern in a light blocking region on the first surface of the semiconductor substrate; a transistor in a light blocking region on the second surface of the semiconductor substrate; an interlayer insulating layer stacked on the second surface of the semiconductor substrate; and a capacitor on the interlayer insulating layer in each of the plurality of pixel regions, the capacitor at least temporarily storing the charge generated from each of the photoelectric conversion regions, The grating pattern and the blocking pattern are located on the same horizontal plane relative to the second surface of the semiconductor substrate.

12. The image sensor according to claim 11, wherein: The width of the grating pattern is substantially equal to the distance between the grating patterns.

13. The image sensor according to claim 11, wherein: The grating pattern is configured to provide ±1st-order or higher-order diffracted light generated by diffraction of incident light to the photoelectric conversion region and to suppress zeroth-order diffracted light. 14 . The image sensor according to claim 11 , further comprising an optically transparent layer disposed to fill a region between the grating patterns and comprising an insulating layer having a refractive index different from that of the semiconductor substrate.

15. The image sensor according to claim 11, wherein: The grating pattern includes line patterns which are parallel to each other and extend in a specific direction.

16. The image sensor according to claim 15, wherein: The grating pattern diffracts incident light in a direction perpendicular to the specific direction.

17. The image sensor according to claim 15, wherein: When measured in the specific direction, the length of the grating pattern is shorter than the length of the photoelectric conversion region.

18. The image sensor according to claim 11, wherein: The semiconductor substrate includes barrier regions spaced apart from each other in a first direction, and The grating pattern includes a line pattern extending between the barrier regions in the first direction.

19. The image sensor according to claim 18, further comprising: A logic transistor is disposed on the second surface of the semiconductor substrate and in the blocking region.

20. The image sensor according to claim 11, wherein: The grating pattern includes a concentric circular pattern.

21. The image sensor according to claim 11, wherein: The pixel areas are two-dimensionally arranged in a first direction and a second direction, the first direction and the second direction are perpendicular to each other, and The grating pattern includes a line pattern extending in a direction oblique to the first direction and the second direction.

22. The image sensor according to claim 11, wherein: The pixel areas are two-dimensionally arranged in a first direction and a second direction, the first direction and the second direction are perpendicular to each other, and In each of the pixel areas, the grating patterns are spaced apart from each other by the same distance in the first direction and the second direction.

23. The image sensor according to claim 11, further comprising: A readout circuit layer is provided on the second surface of the semiconductor substrate and is electrically connected to the photoelectric conversion region.

24. An image sensor comprising: A semiconductor substrate of a first conductivity type having a first semiconductor surface and a second semiconductor surface opposite to the first semiconductor surface; A pixel separation structure, in the semiconductor substrate, wherein the pixel separation structure defines a pixel area; an isolation structure, in the semiconductor substrate, the isolation structure defining a light receiving region and a light blocking region in the pixel region; a photoelectric conversion region disposed in the light receiving region in the semiconductor substrate and doped to have a second conductivity type; a transfer gate electrode in a light receiving region on the first semiconductor surface of the semiconductor substrate; a transistor in a light blocking region on the first semiconductor surface of the semiconductor substrate; a grating structure on the second semiconductor surface of the semiconductor substrate, wherein the grating structure comprises a plurality of grating patterns and a plurality of recessed areas arranged alternately; and a blocking pattern in a light blocking region on the second semiconductor surface of the semiconductor substrate; The grating structure and the blocking pattern are located on the same horizontal plane relative to the first semiconductor surface of the semiconductor substrate.

25. The image sensor according to claim 24, wherein: The recessed regions are defined on the surface of the semiconductor substrate, and each of the recessed regions is disposed between the grating patterns, and The grating patterns have the same width and the same height.

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