Semiconductor structure and manufacturing method

Abstract

This disclosure relates to semiconductor structures and methods for manufacturing the same. The method for manufacturing a semiconductor structure includes forming an epitaxial source / drain component over a semiconductor layer, wherein the epitaxial source / drain component comprises silicon and germanium; forming a trench to expose a portion of the epitaxial source / drain component; annealing the exposed portion of the epitaxial source / drain component; wherein the annealing forms a first region having a first germanium concentration above the top surface of the epitaxial source / drain component and a second region having a second germanium concentration less than the first germanium concentration disposed below the first region; oxidizing the first region; removing the oxidized first region; and forming a source / drain contact in a trench above the second region.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to semiconductor structures and methods of manufacturing thereof. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuits than the previous one. Throughout the history of IC development, functional density (the number of interconnected devices per wafer area) has increased, while geometric dimensions (the smallest components or lines produced during manufacturing) have shrunk. This miniaturization process generally benefits production efficiency and reduces associated costs. However, it also increases the complexity of processing and manufacturing ICs.

[0003] For example, as component sizes continue to shrink, fabricating source / drain (S / D) contacts becomes more challenging. In particular, reducing the contact resistance between the source / drain components and the source / drain contacts subsequently formed on top of them remains a primary goal in semiconductor device fabrication. While current methods for forming source / drain contacts are generally appropriate, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] In some embodiments, a method of manufacturing a semiconductor structure is provided, the method comprising forming an epitaxial source / drain component over a semiconductor layer, wherein the epitaxial source / drain component comprises silicon and germanium; forming a trench to expose a portion of the epitaxial source / drain component; annealing the exposed portion of the epitaxial source / drain component, wherein the annealing forms a first region having a first germanium concentration above the top surface of the epitaxial source / drain component and a second region having a second germanium concentration less than the first germanium concentration disposed below the first region; oxidizing the first region; removing the oxidized first region; and forming a source / drain contact in a trench over the second region.

[0005] In some other embodiments, a method of manufacturing a semiconductor structure is provided, the method comprising forming an epitaxial source / drain component over a plurality of semiconductor fins, wherein the epitaxial source / drain component comprises silicon and germanium; forming a notch in the epitaxial source / drain component, wherein the step of forming the notch comprises: removing a portion of the epitaxial source / drain component to form a trench; annealing the top of the epitaxial source / drain component exposed by the trench; oxidizing the top of the epitaxial source / drain component after annealing; forming a silicide layer over the epitaxial source / drain component, wherein the step of forming the silicide layer removes the oxidized top of the epitaxial source / drain component to form the notch; and forming a source / drain contact over the silicide layer.

[0006] In other embodiments, a semiconductor structure is provided, the semiconductor device structure including a plurality of semiconductor fins disposed above a substrate; an epitaxial source / drain component disposed above the semiconductor fins, wherein the top surface of the epitaxial source / drain component includes two surfaces inclined downward toward each other at an angle; a silicide layer disposed above the epitaxial source / drain component; and a source / drain contact disposed above the silicide layer. Attached Figure Description

[0007] The embodiments of this disclosure can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to industry standard practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0008] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to various aspects of embodiments of the present disclosure.

[0009] Figure 2 This is a perspective view of a semiconductor device according to various aspects of embodiments of the present disclosure.

[0010] Figure 3 , 4 5, 6, 9, 10, 11, 12, 13, 14, 15, 16 and 17 are aspects of embodiments based on this disclosure. Figure 1 During the intermediate steps of an embodiment of the method, along Figure 2 A schematic cross-sectional view of the semiconductor device with line AA'.

[0011] Figure 7 Annealing energy and various aspects of embodiments according to this disclosure Figure 2 A schematic diagram showing the relationship between the contact resistances of the device.

[0012] Figure 8This is a schematic diagram illustrating the relationship between depth and germanium concentration measured from the surface of the semiconductor device 200 according to various aspects of embodiments of the present disclosure.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 100 methods

[0015] Operations 102, 104, 106, 108, 110, 112, 114

[0016] 200 Semiconductor Devices

[0017] 202 base

[0018] 204 fins

[0019] 206a, 206b spacer walls

[0020] 208 Isolation Structure

[0021] 210 High Dielectric Constant Metal Gate Structure

[0022] 212 Gate spacer wall

[0023] 214 Source / Drain Components

[0024] 214a and 214b epitaxial semiconductor material layers

[0025] 218 interlayer dielectric layer

[0026] 220 Etching Stop Layer

[0027] 222 Trench

[0028] 230 Surface Area

[0029] 232 Oxidation Zone

[0030] 234 Concave contour

[0031] 240 spacer layers

[0032] 250 silicide layers

[0033] 260 Conductive materials

[0034] 262 Source / Drain Contact

[0035] 270 dashed line

[0036] 272 Contact area

[0037] 310 Injection Process

[0038] 320 and 330 annealing processes

[0039] 340 Etching Process

[0040] 350 Pre-cleaning process

[0041] Distance between a and d

[0042] b and c surfaces Detailed Implementation

[0043] It is important to understand that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, the following disclosure describes a first component formed on or above a second component, indicating that it includes embodiments where the formed first component and the second component are in direct contact, as well as embodiments where additional components may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. Furthermore, different examples in the disclosure may use repeated reference numerals and / or wording. These repeated reference numerals or wording are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0044] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the accompanying drawings, spatially related terms such as "upper," "lower," "horizontal," "vertical," "above," "above," "below," "under," "top," "bottom," and similar terms (e.g., "horizontally," "vertically," "downward," "upward") are used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. Furthermore, when numbers or ranges of numbers are described using terms such as "approximately," "about," and similar terms, these terms are intended to cover numbers within a reasonable range, such as within + / - 10% of the described number, or other values ​​that would be understood by someone skilled in the art. For example, the term "approximately 5 nm" covers a size range of 4.5 nm to 5.5 nm.

[0045] This disclosure generally relates to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs or three-dimensional fin-like FETs (FinFETs). A primary objective of this disclosure is to provide a method for forming source / drain contacts above p-type epitaxial source / drain components in a field-effect transistor.

[0046] In field-effect transistor (FET) fabrication, source / drain (S / D) contacts are typically formed to connect device-level source / drain components (e.g., p-type epitaxial source / drain components) with interconnect components (e.g., vias). When forming source / drain contacts above source / drain components, it is often desirable to increase the contact area between the source / drain contact and the source / drain component by forming a recessed profile at the portion of the source / drain component that contacts the source / drain contact. Generally, the recessed profile can be formed by controlling the epitaxial layer growth and / or etching the epitaxial layer after its formation. While these methods are generally appropriate, they are not entirely satisfactory in all respects and may, for example, lead to non-uniform component dimensions and even damage to the source / drain component. For these and other reasons, in order to fabricate FETs with enhanced properties, it is desirable to improve the methods for increasing the contact area between the source / drain component (especially p-type epitaxial source / drain components) and the source / drain contact.

[0047] Figure 1 This disclosure illustrates a method 100 for manufacturing a semiconductor device 200 (sometimes simply referred to as a device) according to various aspects of embodiments of the present disclosure. Method 10 is merely exemplary and is not intended to limit the embodiments of the present disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, or after method 100, and in additional embodiments of this method, some of the described operations may be replaced, eliminated, or moved. Method 100 is described below in conjunction with... Figure 2-14 Joint description, Figure 2-14 A portion of the semiconductor device 200 is shown during an intermediate step of method 100. Figure 3-14 To pass along Figure 2 The diagram shows a cross-sectional view of the device 200 with the dashed line AA' of the source / drain region of the fin 204. For simplification purposes, Figure 3-14Only one source / drain component 214 is shown. Device 200 may be an intermediate device during the fabrication of an integrated circuit or a portion thereof, and may include static random-access memory (SRAM) and / or other logic circuitry, passive components (e.g., resistors, capacitors, and inductors), and active components (e.g., p-type FETs (PFETs), n-type FETs (NFETs), fin field-effect transistors, metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells). Embodiments of this disclosure are not limited to any particular number of devices or device regions, or any particular device configuration. For example, while semiconductor device 200 is shown as a three-dimensional fin field-effect transistor device, embodiments of this disclosure may also provide embodiments for fabricating planar field-effect transistor devices.

[0048] In operation 102, please refer to Figure 1-3 Method 100 provides a device semiconductor 200, the semiconductor device 200 including a substrate 202 having a semiconductor layer (hereinafter referred to as fin 204) disposed thereon, wherein two fins 204 are merged by source / drain components 214. The semiconductor device 200 also includes a high-k metal gate (HKMG) structure 210 disposed above the channel region of the fins 204, a gate spacer 212 formed on the sidewalls of the high-k metal gate structure 210, an isolation structure 208 disposed above the substrate 202 for separating various components of the semiconductor device 200, and an interlayer dielectric (ILD) layer 218 disposed above the isolation structure 208 and the source / drain components 214.

[0049] Substrate 202 may comprise elemental (single-element) semiconductors (e.g., silicon, germanium, and / or other suitable materials), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, and / or other suitable materials), and alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials). Substrate 202 may be a single layer of material with a uniform composition. Alternatively, substrate 202 may comprise multiple material layers with similar or different compositions suitable for manufacturing integrated circuit devices. In one example, substrate 202 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, substrate 202 may comprise conductive layers, semiconductor layers, dielectric layers, other layers, or combinations thereof.

[0050] In some embodiments where the substrate 202 includes a field-effect transistor, various doped regions (e.g., source / drain regions) are disposed in or on the substrate 202. The doped regions may be doped with n-type dopants (e.g., phosphorus or arsenic) and / or p-type dopants (e.g., boron or BF2) depending on design requirements. The doped regions may be formed directly on the substrate 202, in a p-type well structure, an n-type well structure, a double-well structure, or a bump structure. The doped regions can be formed by implanting dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0051] Please refer to Figure 2-3 The fin 204 can be manufactured using a suitable process including photolithography. The photolithography process may include forming a photoresist layer (resistor) over a substrate 202, exposing the resist as a pattern, performing a post-exposure baking process, and developing the resist to form a mask element (not shown) containing the resist. The mask element is then used to etch notches in the substrate 202 to leave the fin 204 on the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0052] Many other embodiments of the method for forming the fin may be suitable. For example, the fin 204 can be patterned using a dual-patterning or multi-patterning process. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrel can then be used to pattern the fin.

[0053] The isolation structure 208 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric material, and / or other suitable materials. The isolation structure 208 may comprise shallow trench isolation (STI) components. In one embodiment, the isolation structure 208 may be formed by etching trenches in the substrate 202 during the formation of fins 204. The trenches may then be filled with the aforementioned isolation material by a deposition process followed by a chemical mechanical planarization (CMP) process. Other isolation structures (e.g., field oxides, local oxidation of silicon (LOCOS), and / or other suitable structures) may also be used as the isolation structure 208. Alternatively, the isolation structure 208 may comprise a multilayer structure, such as having one or more thermally oxidized pad layers. The isolation structure 208 can be deposited by any suitable method, such as chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), spin-on-glass (SOG), other suitable methods, or a combination thereof.

[0054] Please refer to Figure 2-3Semiconductor device 200 includes source / drain components 214 disposed above fins 204. In many embodiments, each source / drain component 214 merges two fins 204 together. The source / drain components 214 can be formed by any suitable technique, such as an etching process followed by one or more epitaxial processes. In one example, one or more etching processes are performed to remove a portion of the fin 204 to form a notch (not shown) therein. A cleaning process can be performed using a hydrofluoric acid (HF) solution or other suitable solution to clean the notch. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial components in the notch. Each source / drain component 214 can be adapted to form a p-type fin field-effect transistor device (e.g., p-type epitaxial material) or an n-type fin field-effect transistor device (e.g., n-type epitaxial material). The p-type epitaxial material may comprise one or more epitaxial layers of silicon-germanium (epitaxysiGe), wherein the silicon-germanium is doped with p-type dopants, such as boron, germanium, indium, and / or other p-type dopants. The n-type epitaxial material may comprise one or more epitaxial layers of silicon or silicon-carbon (epitaxy Si or epitaxial SiC), wherein the silicon or silicon-carbon is doped with n-type dopants, such as arsenic, phosphorus, and / or other n-type dopants. In this embodiment, at least one of the source / drain components 214 comprises a p-type epitaxial semiconductor material, such as boron-doped epitaxial SiGe. Although not shown, the semiconductor device 200 may include additional p-type and / or n-type field-effect transistors. Of course, this configuration is for illustrative purposes only and is not a limitation.

[0055] Please refer to Figure 3The source / drain component 214 may include multiple epitaxial semiconductor material layers, such as epitaxial semiconductor material layer 214a and epitaxial semiconductor material layer 214b. In many embodiments, epitaxial semiconductor material layer 214a is disposed above fin 204 and thus merges two fins 204 together, while epitaxial semiconductor material layer 214b is disposed above epitaxial semiconductor material layer 214a and encapsulates epitaxial semiconductor material layer 214a. In this embodiment, epitaxial semiconductor material layers 214a and 214b both contain epitaxial SiGe but contain different amounts of Ge. In the illustrated embodiment, epitaxial semiconductor material layer 214a contains less Ge than epitaxial semiconductor material layer 214b. For example, epitaxial semiconductor material layer 214b may contain at least twice as much Ge as epitaxial semiconductor material layer 214a. Although not shown, the source / drain component 214 may include additional epitaxial semiconductor material layers. Furthermore, the source / drain component 214 may include a dielectric layer (hereinafter referred to as an etch-stop layer (CESL) 220) disposed over and surrounding the epitaxial semiconductor material layer 214b. The etch-stop layer 220 may include silicon nitride, silicon oxynitride, silicon nitride containing oxygen or carbon, other suitable materials, or combinations thereof, and may be formed by chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof.

[0056] The semiconductor device 200 also includes a high-dielectric-constant metal gate structure 210 disposed above the channel region of the fin 204, such that the high-dielectric-constant metal gate structure 210 is located between the source / drain components 214. The high-dielectric-constant metal gate structure 210 includes a high-dielectric-constant (e.g., dielectric constant greater than that of silicon oxide, which has a dielectric constant of approximately 3.9) dielectric layer (not shown) disposed above the fin 204 and a metal gate electrode (not shown) disposed above the high-dielectric-constant dielectric layer. The metal gate electrode may further include at least one work function metal layer and a bulk conductive layer disposed above the work function metal layer. The work function metal layer may be a p-type or n-type work function metal layer. The work function metal layer of the example includes TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The high-dielectric-constant metal gate structure 210 may include work function metal layers of the same type (e.g., all n-type or all p-type) or different types. The bulk conductive layer may include cobalt (Co), copper (Cu), tungsten (W), aluminum (Al), ruthenium (Ru), other suitable materials, or combinations thereof. The high-dielectric-constant metal gate structure 210 may also include a number of other layers (not shown), such as an interface layer, hard mask layer, capping layer, barrier layer, other suitable layers, or combinations thereof disposed between the fin 204 and the high-dielectric-constant dielectric layer. The high-k dielectric metal gate structure 210 can be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, other suitable methods, or combinations thereof. A polishing process (e.g., chemical mechanical polishing (CMP)) can be performed to remove excess material from the top surface of the high-k dielectric metal gate structure 210 to planarize the top surface of the semiconductor device 200.

[0057] A gate spacer 212 is disposed on the sidewall of a high-dielectric-constant metal gate structure 210 of a semiconductor device 200. The gate spacer 212 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate spacer 212 may be a single-layer structure or a multi-layer structure. The gate spacer 212 is formed on the sidewall of the high-dielectric-constant metal gate structure 210 by blanket deposition of spacer material over the semiconductor device 200, followed by an anisotropic etching process to remove excess spacer material.

[0058] In many embodiments, the high-k dielectric metal gate structure 210 is formed after the fabrication of other components of the semiconductor device 200 (e.g., source / drain components 214). This process is generally referred to as a gate replacement process, which includes forming a dummy gate structure (not shown) as a placeholder for the high-k dielectric metal gate structure 210, forming the source / drain components 214, forming an interlayer dielectric layer 218 and an etch stop layer 220 over the dummy gate structure and the source / drain components 214, planarizing the interlayer dielectric layer 218 by, for example, chemical mechanical polishing to expose the top surface of the dummy gate structure, removing the dummy gate structure in the interlayer dielectric layer 218 to form a trench exposing the channel region of the fin 204, and forming the high-k dielectric metal gate structure 210 in the trench to complete the gate replacement process. In some embodiments, the interlayer dielectric layer 218 comprises a dielectric material, such as a low dielectric constant dielectric material, tetraethylorthosilicate (TEOS), undoped silicate glass or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof). In the illustrated embodiment, the interlayer dielectric layer 218 comprises an oxygen-containing dielectric material. The interlayer dielectric layer 218 may comprise a multilayer structure having multiple dielectric materials and may be formed by a deposition process, such as chemical vapor deposition, flowable chemical vapor deposition, spin-coating glass, other suitable methods, or combinations thereof.

[0059] Please refer to Figure 4In operation 102, method 100 forms a trench 222 in an interlayer dielectric layer 218 above the source / drain components 214. Specifically, method 100 forms the trench 222 by performing a series of patterning and etching processes. In an exemplary embodiment, the series of patterning and etching processes includes forming a mask element (not shown) containing a resist (e.g., photoresist) configured to be patterned over the interlayer dielectric layer 218 by a lithography process to expose the interlayer dielectric layer 218 to be etched and the etch stop layer 220, and subsequently etching the interlayer dielectric layer 218 and the etch stop layer 220 by dry etching, wet etching, reactive ion etching (RIE), other suitable etching processes, or combinations thereof, to expose the source / drain components 214 in the trench 222. In some embodiments, the etching process is a dry etching process using one or more etchants, such as fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, oxygen-containing gases (e.g., O2), nitrogen-containing gases (e.g., N2), helium, argon, other suitable gases, or combinations thereof. After the etching process, the mask element is removed by any suitable method, such as plasma ashing or resist stripping.

[0060] In operation 104, please refer to Figure 5 Method 100 selectively implants a dopant into the source / drain component 214 in implantation process 310. In this embodiment, since the source / drain component 214 is a p-type epitaxial source / drain component, the dopant implanted in operation 104 is a p-type dopant, such as boron. Method 100 may implant the dopant in two steps in operation 104. First, Method 100 may bombard the portion of the source / drain component 214 exposed through trench 222 with Ge atoms to amorphize the surface region of the epitaxial semiconductor material layer 214b. Second, Method 100 implants the dopant (e.g., boron) into the amorphized surface region using a process similar to that described above for forming the source / drain component 214. It is noteworthy that once the dopant in the surface region of the epitaxial semiconductor material layer 214b is activated, it can help improve the conductivity between the source / drain component 214 and the subsequently formed source / drain junction, as well as reduce the resistance. The dopants injected in operation 104 can be activated by subsequent annealing processes, as will be discussed in detail below.

[0061] In operation 106, please refer to Figure 6Method 100 performs an annealing process 320 on the source / drain component 214. The annealing process 320 can be performed by any suitable method, such as melting laser annealing (MLA), rapid thermal annealing (RTA), peak annealing (e.g., dynamic spike annealing (DSA)), other suitable methods, or combinations thereof. In this embodiment, the annealing process 320 is performed by melting laser annealing. Melting laser annealing, as its name suggests, applies sufficient thermal energy (e.g., a laser source) to the target layer (e.g., the epitaxial semiconductor material layer 214b of the source / drain component 214) to cause the target layer to rapidly undergo a phase transition from solid to liquid. In other words, melting laser annealing is configured to rapidly heat at least a portion of the epitaxial semiconductor material layer 214b above its melting point. Due to the rapid nature of melting laser annealing, the annealing depth and annealing time are significantly less than other annealing methods that include rapid thermal annealing and dynamic spike annealing. In one example, the annealing depth of melt laser annealing can be approximately 10 times that of rapid thermal annealing. -5 To about 10 -4 The annealing time of melt laser annealing is approximately 10 times that of rapid thermal annealing. -7 In another example, the annealing depth of melt laser annealing can be approximately 10 times that of dynamic peak annealing. -4 To about 10 -3 The annealing time for molten laser annealing is approximately 10 times that of dynamic peak annealing, and the annealing time for molten laser annealing is approximately 10 times that of dynamic peak annealing. -5 To about 10 -3 Because melt laser annealing has a shallow annealing depth, it can be configured to selectively anneal only the surface portion of the substrate (e.g., a depth less than about 5 nm from the top of the substrate), thereby reducing thermal damage to other parts of the semiconductor device 200 (e.g., the high-dielectric-constant metal gate structure 210) during the annealing process 320.

[0062] In many embodiments, melt laser annealing achieves the desired annealing depth by adjusting the annealing energy and / or time. In this disclosure, the desired annealing depth of melt laser annealing can be from about 10 nm to 100 nm, and the annealing time can be less than 0.2 μs (e.g., about 160 ns). On the one hand, if the annealing time is too long, excess thermal energy can damage the high-dielectric-constant metal gate structure (e.g., unintentionally altering the critical energy of the high-dielectric-constant metal gate structure). On the other hand, if the annealing time is too short, the desired annealing result may not be achieved. In some examples, the energy of melt laser annealing can be about 0.48 J / cm². 2 To approximately 0.5 J / cm 2It is worth noting that if the energy exceeds this range, the epitaxial structure of the source / drain component 214 may be damaged, for example, melted. On the other hand, if the energy is below this range, the desired annealing result may not be achieved.

[0063] As described above, melt laser annealing is configured to rapidly heat the epitaxial semiconductor material layer 214b to at least its melting point. Specifically, melt laser annealing can be configured to heat the portion of the epitaxial semiconductor material layer 214b exposed through the trench 222 of the source / drain component 214 to above the melting point of SiGe contained in the source / drain component 214, which is approximately 1072°C. In an exemplary embodiment, melt laser annealing can heat the exposed portion of the epitaxial semiconductor material layer 214b to approximately 1200°C. In some embodiments, the epitaxial semiconductor material layer 214b with a higher Ge concentration has a lower melting point than the epitaxial semiconductor material layer 214a with a lower Ge concentration. Therefore, the annealing process 320 selectively melts the epitaxial semiconductor material layer 214b, while melt laser annealing does not melt or substantially does not melt the epitaxial semiconductor material layer 214a. In many embodiments, rapid melt activation of the exposed portions of the epitaxial semiconductor material layer 214b or increased solubility of p-type dopants (e.g., boron) in SiGe leads to improved dopant activation and device performance. It is worth noting that other annealing methods (e.g., rapid thermal annealing and dynamic peak annealing) cannot heat the substrate to this temperature range. Please refer to... Figure 7 For example, increasing the energy (i.e., the temperature at which the laser is applied) in melt laser annealing leads to a decrease in contact resistance, thus increasing device efficiency. Furthermore, since melt laser annealing can be operated at higher temperatures than dynamic peak annealing, the contact resistance can be significantly reduced (e.g., comparing the contact resistance achieved by melt laser annealing at energy level "A" with a reference value achieved by dynamic peak annealing at a similar energy level). Figure 7 As shown.

[0064] Please refer to Figure 9After molten laser annealing in annealing process 320, the molten SiGe is re-solidified (or recrystallized) when the temperature of SiGe drops below its melting point. Ge atoms in the epitaxial semiconductor layer 214b rearrange themselves such that the concentration of Ge atoms in the surface region 230 of the epitaxial semiconductor layer 214b is greater than the concentration of Ge atoms in the region below the surface region 230. In other words, when SiGe recrystallizes, Ge atoms accumulate in the surface region 230. In this disclosure, the surface region 230 is generally an inverted triangle with a depth at the center line BB' greater than the depth on either side of the center line BB'. Of course, this disclosure is not limited to this configuration. For example, the surface region 230 may have curved edges and / or corners instead of the straight edges shown herein. In another example, the contour of the surface region 230 may follow the contour of the top of the epitaxial semiconductor layer 214a. In one exemplary embodiment, the maximum depth of the surface region 230 (i.e., measured along the center line BB') may be approximately 5 nm. It is noteworthy that, since Ge atom stacking occurs primarily in epitaxial semiconductor layer 214b rather than in epitaxial semiconductor layer 214a, the profile of surface region 230 is defined by its proximity to epitaxial semiconductor layer 214a. For example, since a portion of epitaxial semiconductor layer 214b surrounds epitaxial semiconductor layer 214a, surface region 230 extends outward along a portion of the centerline BB'. In this disclosure, the Ge concentration in surface region 230 can be at least about 65% Ge (compared to no more than about 55% Ge concentration in surface region 230 after applying dynamic peak annealing (reference value processing),) and the Ge concentration gradually decreases in the region below surface region 230. An example Ge concentration profile in epitaxial semiconductor layer 214b is shown below. Figure 8 As shown, the Ge concentration is maximized at the top few nanometers (e.g., less than 5 nm) of the surface of the epitaxial semiconductor layer 214b. As will be described in detail below, this difference in Ge concentration can promote the formation of recessed profiles in the epitaxial semiconductor layer 214b, thereby increasing the contact area between the source / drain components 214 and the subsequently formed source / drain contacts. In many embodiments, the size of the surface region 230 is controlled by the energy of the molten laser annealing applied during the annealing process 320. In particular, as the energy of the molten laser annealing increases, the size of the surface region 230 can increase.

[0065] Although not required, after annealing process 320, method 100 may perform an additional annealing process 330 in operation 106. Please refer to... Figure 10Annealing process 330 performs an annealing method configured to operate at a temperature lower than that of melt laser annealing. In some embodiments, annealing process 330 is performed by dynamic peak annealing, which can activate p-type dopants in the region below surface region 230. In many embodiments, because annealing process 330 is performed at a temperature lower than that of melt laser annealing, annealing process 330 does not affect the Ge concentration in surface region 230. In other words, dynamic peak annealing does not provide sufficient energy for Ge atoms to rearrange themselves to change the concentration distribution of Ge atoms in epitaxial semiconductor material layer 214b.

[0066] In operation 108, method 100 oxidizes the SiGe in surface region 230 to form oxide region 232. Specifically, please refer to... Figure 11 In method 100, a spacer layer 240 is first deposited over the semiconductor device 200. The spacer layer 240 may comprise any suitable dielectric material, such as silicon nitride, and can be deposited by any suitable method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable methods, or combinations thereof. Although not illustrated in... Figure 11 In the cross-sectional schematic, spacer layer 240 provides electrical isolation between the subsequently formed source / drain contacts and the adjacent high-dielectric-constant metal gate structure 210. Next, please refer to... Figure 12 A portion of the spacer layer 240 is removed by etching process 340, leaving a portion of the spacer layer 240 remaining on the sidewall surface of the trench 222 between the source / drain component 214 and the high-dielectric-constant metal gate structure 210 (not shown). Figure 12(See the cross-sectional schematic diagram). The etching process 340 may include multiple steps. For example, the etching process 340 includes first performing an anisotropic dry etching process to remove a portion of the spacer layer 240, followed by a plasma ashing process (e.g., a dry etching process) to remove etching byproducts, and finally a wet etching process to remove any remaining polymer residues. In this disclosure, the wet etching process can be performed using an oxidizing etchant, such as ozone-deionized water (DIO3), which is ozone dissolved in deionized water (therefore DIO3 is considered an aqueous solution of the oxidizing etchant). In many embodiments, the oxidizing etchant DIO3 is configured to remove any remaining organic (or polymeric) etching residues from the semiconductor device 200 and oxidize SiGe in the surface region 230 to form germanium oxide and silicon oxide, thereby transforming the surface region 230 into an oxide region 232. It is noteworthy that the etchant DIO3 can be used to selectively oxidize regions with a Ge concentration greater than about 65% (e.g., surface region 230), while the etchant DIO3 does not oxidize or only minimally oxidizes the portion of the source / drain components 214 disposed below the surface region 230 (including a portion of the epitaxial semiconductor material layers 214a and 214b). Of course, other etchants can also be applied to oxidize SiGe in the surface region 230. Since germanium oxide is soluble in water (or an aqueous solution), the etchant DIO3 can also remove a portion of the germanium oxide formed during the etching process 340. Therefore, at least a portion of the surface region 230 with a high Ge content is removed or substantially removed by the oxidation process during the etching of the spacer layer 240.

[0067] In operation 110, please refer to Figure 13 and 14 In method 100, a silicide layer 250 is formed over the source / drain components 214 (i.e., the epitaxial semiconductor material layer 214b) in trench 222. Please refer to... Figure 11 Method 100 first performs a pre-cleaning process 350 on the semiconductor device 200 to prepare for the formation of a silicide layer 250. The pre-cleaning process 350 may be a dry etching process, a wet etching process, a reactive ion etching process, other suitable processes, or a combination thereof. In this embodiment, the pre-cleaning process 350 is an anisotropic dry etching process configured to remove any oxide layer on exposed portions of the epitaxial semiconductor material layer 214b. In one example, the pre-cleaning process 350 may be performed using a fluorine-containing gas, an argon-containing gas, other suitable gases, or a combination thereof. In many embodiments, the pre-cleaning process 350 selectively removes the remaining portion of the oxide region 232 (which contains silicon oxide and / or the remaining germanium oxide) to form a recessed profile 234 without etching or only minimally etching other components of the semiconductor device 200 (e.g., the interlayer dielectric layer 218, the etch stop layer 220, and the region beneath the oxide region 232).

[0068] As described above, since the epitaxial semiconductor material layer 214b has a lower melting point than the epitaxial semiconductor material layer 214a, the melt laser annealing applied in operation 106 preferentially melts the region of the epitaxial semiconductor material layer 214b, resulting in Figure 13 The downward concave profile 234 is shown. In some examples, the concave profile 234 can be defined by four parameters (distance a, surface b, surface c, distance d). In some examples, distance a is the distance across... Figure 13 The distance between the top surfaces of the source / drain component 214 shown is given by surfaces b and c, which are inclined towards each other, and distance d, which is the distance from the highest point to the lowest point of the recessed profile 234. In other words, surfaces b and c are configured to form an angle between them such that a portion of the recessed profile 234 slopes downward toward the fin 204. Although generally an inverted isosceles triangle is shown in the figure, in this disclosure, the recessed profile 234 is not limited to any particular geometry, and distances a, b, c, and d are not limited to any particular values ​​as long as the recessed profile 234 does not expose the underlying epitaxial semiconductor material layer 214a. In some examples, the lengths of surfaces b and c may not be equal. In some examples, surfaces b and c may be curved rather than... Figure 13 The straight surface is shown. In other examples, the ratio of distance d to distance a can be approximately 8 / 13 to approximately 2 / 3. However, it is important to note that due to the application of melt laser annealing, the concentration of Ge atoms in surface region 230 can be distributed such that the largest amount of Ge is located at the lowest part of the recessed profile 234 (i.e., where surfaces b and c intersect), forming an approximately inverted triangle as shown in the figure. Other annealing methods (e.g., dynamic peak annealing) would produce an approximately inverted trapezoidal profile, where surfaces b and c do not intersect directly but are connected by another surface.

[0069] Please refer to Figure 14Method 100 is performed in operation 110 until a silicide layer 250 is formed in the recessed contour 234. In many embodiments, the silicide layer 250 comprises a metal silicide, such as nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof. The silicide layer 250 can be formed by a deposition method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or combinations thereof. For example, a metal layer (e.g., nickel) can be deposited over the source / drain component 214 (e.g., epitaxial semiconductor material layer 214b). The semiconductor device 200 is then annealed, causing the metal layer to react with the semiconductor material of the source / drain component 214. Afterward, the unreacted metal layer is removed, leaving the silicide layer 250 over the source / drain component 214. Alternatively, the silicide layer 250 may be formed directly over the epitaxial semiconductor material layer 214b by any suitable deposition method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable methods, or combinations thereof.

[0070] In operation 112, please refer to Figure 15 and 16 In method 100, a source / drain contact 262 is formed over the source / drain component 214. In many embodiments, the source / drain contact 262 electrically connects the source / drain component 214 to additional components (e.g., interconnect components (e.g., vias)) formed after the semiconductor device 200 is formed. Please refer to... Figure 15 In method 100, in operation 112, a conductive material 260 is deposited in trench 222. The conductive material 260 may comprise any suitable material, such as tungsten, cobalt, ruthenium, copper, aluminum, titanium, nickel, platinum, palladium, other suitable conductive materials, or combinations thereof, and may be formed by any suitable method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, electroplating, other suitable processes, or combinations thereof. Then, please refer to... Figure 16 Method 100 removes excess conductive material 260 formed on the top surface of the interlayer dielectric layer 218 in a planarization process (e.g., chemical mechanical polishing) to form the source / drain contact 262. Note that the shape of the recessed profile 234 slopes downward toward the fin 204, compared to an example where the contact surface between the source / drain contact and the source / drain components is a generally flat profile. Figure 16 As shown by the dashed line 270, the contact area between the source / drain contact 262 and the source / drain component 214 is increased. The increased contact area 272 is determined by the parameters of the melt laser annealing during the annealing process 320 described above. In some examples, the contact area can be increased by about 11% and the maximum depth can be increased by about 50% compared to examples that do not use the manufacturing steps discussed herein (see [reference]). Figure 13 Distance a).

[0071] In some embodiments, please refer to Figure 17 The semiconductor device 200 may also include other elements. For example, spacer walls 206a and 206b may be provided extending along the sidewalls of the fin 204 to facilitate the fabrication of epitaxial semiconductor material layers 214a and / or 214b during the epitaxial growth process. Spacer wall 206a is disposed on the outer sidewall of the fin 204, while spacer wall 206b is disposed on the inner sidewall of the fin 204. In some embodiments, the heights of spacer walls 206a and 206b are different relative to the height of the fin 204. In some embodiments, as shown, spacer wall 206b may be physically connected. Furthermore, as described above, the recessed profile 234 may be described by distance a, surface b, surface c, and distance d, wherein the lengths of surfaces b and c are different, and one or both of surfaces b and c may be curved edges rather than straight edges. Similar to operations 110 and 112 described above, method 100 then forms a silicide layer 250 over the recessed contour 234, deposits a conductive material over the silicide layer 250, and performs a chemical mechanical polishing process to form source / drain contacts 262.

[0072] In operation 114, method 100 may perform additional manufacturing steps on the semiconductor device 200. For example, additional vertical interconnect components (e.g., contacts and / or vias) and / or horizontal interconnect components (e.g., wires) and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) may be formed over the semiconductor device 200. Various conductive materials may be used for the interconnect components, including copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), gold (Au), manganese (Mn), zirconium (Zr), ruthenium (Ru), alloys thereof, metal silicides, and / or other suitable materials. Metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, and / or other suitable metal silicides.

[0073] This disclosure provides a method for forming source / drain contacts in a field-effect transistor. Embodiments of this disclosure include forming a contact trench over a germanium-containing source / drain component, performing a melt laser annealing (MLA) process on the source / drain component exposed by the contact trench to form a germanium-rich region, oxidizing the source / drain component and removing the germanium-rich region from the source / drain component, forming a silicide layer over the remaining portion of the source / drain component, and forming a source / drain contact over the silicide layer. In some embodiments, the method provided herein includes implanting a dopant into the source / drain component prior to performing the melt laser annealing process. In some embodiments, the melt laser annealing process is configured as part of selectively annealing the source / drain component to form a germanium-rich region at the surface of the source / drain component. In some embodiments, oxidizing and removing the germanium-rich region includes applying various cleaning and etching agents to the germanium-rich region. In some embodiments, removing the germanium-rich region results in the formation of a recessed profile (e.g., a non-linear profile) on the top of the source / drain component.

[0074] While not restrictive, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and methods of forming the same. For example, a recessed profile formed at the top of the source / drain components increases the contact area between the source / drain components and subsequently formed source / drain contacts, thereby reducing the contact resistance of the formed device. Compared to growing the source / drain components into specific profiles to match the formation of source / drain contacts and / or directly etching the source / drain components to obtain the recessed profile, embodiments of this disclosure ensure that the dimensions of the source / drain components remain relatively consistent and that over-etching of the source / drain components does not adversely damage their structure and performance.

[0075] In one aspect, this disclosure provides a method comprising forming an epitaxial source / drain component over a semiconductor layer, wherein the epitaxial source / drain component comprises silicon and germanium; forming a trench to expose a portion of the epitaxial source / drain component; and annealing the exposed portion of the epitaxial source / drain component such that the annealing forms a first region having a first germanium concentration above the top surface of the epitaxial source / drain component and a second region having a second germanium concentration less than the first germanium concentration disposed below the first region. Subsequently, the first region is oxidized, the oxidized first region is removed, and a source / drain contact is formed in the trench above the second region.

[0076] In some other embodiments, the step of annealing the exposed portions of the epitaxial source / drain components includes performing a melt laser annealing process.

[0077] In some other embodiments, the step of oxidizing the first region includes: depositing a dielectric layer in a trench; removing a portion of the dielectric layer to form a spacer wall; and performing a wet cleaning process on the spacer wall, wherein the wet cleaning process oxidizes the first region to form silicon oxide and germanium oxide.

[0078] In some other embodiments, a wet cleaning process is used to remove germanium oxide.

[0079] In some other embodiments, the wet cleaning process includes treating the epitaxial source / drain components with an oxide etchant.

[0080] In some other embodiments, the step of removing the oxidized first region includes performing an anisotropic dry etching process.

[0081] In some other embodiments, the step of performing the anisotropic dry etching process includes applying an etchant comprising a fluorine-containing gas, an argon-containing gas, or a combination thereof.

[0082] In some other embodiments, the method further includes forming a silicide layer in the trench after removing the first oxidized region and before forming the source / drain contacts.

[0083] On the other hand, this disclosure provides a method comprising forming an epitaxial source / drain component over a semiconductor fin, the epitaxial source / drain component comprising silicon and germanium, and subsequently forming a notch in the epitaxial source / drain component. Specifically, the step of forming the notch includes removing a portion of the epitaxial source / drain component to form a trench, annealing the top of the epitaxial source / drain component exposed in the trench, oxidizing the top of the epitaxial source / drain component after annealing, and forming a silicide layer over the epitaxial source / drain component. This method also includes forming a source / drain contact over the silicide layer.

[0084] In some other embodiments, the step of forming the epitaxial source / drain components combines multiple semiconductor fins together.

[0085] In some other embodiments, the step of forming the epitaxial source / drain components includes forming a first epitaxial layer over a plurality of semiconductor fins and forming a second epitaxial layer over the first epitaxial layer, wherein the second epitaxial layer contains a greater amount of germanium than the first epitaxial layer.

[0086] In some other embodiments, the annealing process includes heating the top of the second epitaxial layer above its melting point.

[0087] In some other embodiments, the annealing process is performed using a melt laser annealing process.

[0088] In some other embodiments, the step of oxidizing the top of the epitaxial source / drain component includes selectively oxidizing the top of the epitaxial source / drain component relative to the bottom disposed below the top.

[0089] In some other embodiments, the step of forming the silicide layer includes a pre-cleaning process for the epitaxial source / drain components, wherein the pre-cleaning process selectively removes the top of the epitaxial source / drain components relative to the bottom disposed below the top.

[0090] In some other embodiments, the step of oxidizing the top of the epitaxial source / drain component includes applying ozone to the top of the epitaxial source / drain component.

[0091] In another aspect, this disclosure provides a semiconductor structure including semiconductor fins disposed above a substrate and epitaxial source / drain components disposed above the semiconductor fins, wherein the top surface of the epitaxial source / drain components includes two surfaces inclined downward toward each other at an angle. The semiconductor structure also includes a silicide layer disposed above the epitaxial source / drain components and a source / drain contact disposed above the silicide layer.

[0092] In some other embodiments, the epitaxial source / drain components combine multiple semiconductor fins together.

[0093] In some other embodiments, the epitaxial source / drain component includes a first epitaxial layer disposed above a plurality of semiconductor fins and a second epitaxial layer surrounding the first epitaxial layer, wherein the second epitaxial layer contains a greater amount of germanium than the first epitaxial layer.

[0094] In some other embodiments, a portion of the source / drain contact penetrates into the second epitaxial layer.

[0095] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to the embodiments of this disclosure without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: An epitaxial source / drain component is formed above a semiconductor layer, wherein the epitaxial source / drain component comprises silicon and germanium; A trench is formed to expose a portion of the epitaxial source / drain component; An anneal is performed on the exposed portion of the epitaxial source / drain component, wherein the annealing forms a first region having a first germanium concentration above the top surface of the epitaxial source / drain component and a second region having a second germanium concentration less than the first germanium concentration disposed below the first region. The first region is oxidized; Remove the oxidized first region; and A source / drain contact is formed in the trench above the second region.

2. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the step of annealing the exposed portion of the epitaxial source / drain component comprises performing a melt laser annealing process.

3. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the step of oxidizing the first region comprises: A dielectric layer is deposited in the trench; Remove a portion of the dielectric layer to form a spacer wall; and A wet cleaning process is performed on the spacer wall, wherein the wet cleaning process oxidizes the first region to form silicon oxide and germanium oxide.

4. The method for manufacturing a semiconductor structure as claimed in claim 3, wherein the wet cleaning process removes germanium oxide.

5. The method for manufacturing a semiconductor structure as claimed in claim 3, wherein the step of performing the wet cleaning process includes treating the epitaxial source / drain components with an etchant monoxide.

6. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the step of removing the oxidized first region comprises performing an anisotropic dry etching process.

7. The method for manufacturing a semiconductor structure as claimed in claim 6, wherein the step of performing the anisotropic dry etching process includes applying an etchant comprising a fluorine-containing gas, an argon-containing gas, or a combination thereof.

8. The method of manufacturing a semiconductor structure as claimed in claim 1, further comprising forming a silicide layer in the trench after removing the oxidized first region and before forming the source / drain junction.

9. A method for manufacturing a semiconductor structure, comprising: An epitaxial source / drain component is formed above multiple semiconductor fins, wherein the epitaxial source / drain component comprises silicon and germanium; A notch is formed in the epitaxial source / drain component, wherein the step of forming the notch includes: Remove a portion of the epitaxial source / drain component to form a trench; An annealing process is performed on the top of the epitaxial source / drain component exposed by the trench; After the annealing process, the top of the epitaxial source / drain component is oxidized; and A silicide layer is formed over the epitaxial source / drain component, wherein the step of forming the silicide layer includes removing the oxidized top of the epitaxial source / drain component to form the notch; and A source / drain contact is formed above the silicide layer.

10. The method of manufacturing a semiconductor structure as claimed in claim 9, wherein the step of forming the epitaxial source / drain component combines the plurality of semiconductor fins together.

11. The method of manufacturing a semiconductor structure as claimed in claim 9, wherein the step of forming the epitaxial source / drain component includes forming a first epitaxial layer over the plurality of semiconductor fins and forming a second epitaxial layer over the first epitaxial layer, wherein the second epitaxial layer contains a greater amount of germanium than the first epitaxial layer.

12. The method of manufacturing a semiconductor structure as claimed in claim 11, wherein the step of performing the annealing process includes heating a top of the second epitaxial layer to above the melting point of the second epitaxial layer.

13. The method for manufacturing a semiconductor structure as claimed in claim 9, wherein the annealing process is performed by a melt laser annealing process.

14. The method of manufacturing a semiconductor structure as claimed in claim 13, wherein the step of oxidizing the top of the epitaxial source / drain component comprises selectively oxidizing the top of the epitaxial source / drain component relative to a bottom disposed below the top.

15. The method of manufacturing a semiconductor structure as claimed in claim 13, wherein the step of forming the silicide layer includes performing a pre-cleaning process on the epitaxial source / drain component, and wherein the pre-cleaning process selectively removes the top of the epitaxial source / drain component relative to a bottom disposed below the top.

16. The method of manufacturing a semiconductor structure as claimed in claim 9, wherein the step of oxidizing the top of the epitaxial source / drain component comprises applying ozone to the top of the epitaxial source / drain component.

17. A method for manufacturing a semiconductor structure, comprising: An epitaxial source / drain component is provided above a plurality of semiconductor fins, wherein the epitaxial source / drain component integrates the plurality of semiconductor fins, and wherein the epitaxial source / drain component comprises silicon germanium; A silicide layer is formed above the epitaxial source / drain component, wherein the step of forming the silicide layer includes: A trench is formed in the epitaxial source / drain component; A first region of the epitaxial source / drain component exposed to the trench is subjected to a melt laser annealing; Oxidize the first region of the epitaxial source / drain component; and A silicide layer is formed over a second region of the epitaxial source / drain component disposed below the first region, wherein the step of forming the silicide layer removes the oxidized first region; and A source / drain contact is formed above the silicide layer.

18. The method of manufacturing a semiconductor structure as claimed in claim 17, wherein the melt laser annealing melts the first region of the epitaxial source / drain component.

19. The method of manufacturing a semiconductor structure as claimed in claim 17, wherein the step of oxidizing the first region of the epitaxial source / drain component comprises applying an oxidizing agent solution.

20. The method of manufacturing a semiconductor structure as claimed in claim 17, wherein the step of removing the oxidized first region comprises oxidizing the first region with an etchant comprising a fluorine-containing gas, an argon-containing gas, or a combination thereof.

21. A semiconductor structure, comprising: Multiple semiconductor fins are disposed above a substrate; An epitaxial source / drain component is disposed above the plurality of semiconductor fins, wherein the top surface of the epitaxial source / drain component includes two surfaces inclined downward toward each other at an angle, wherein the epitaxial source / drain component includes a first epitaxial layer disposed above the plurality of semiconductor fins and a second epitaxial layer surrounding the outermost sidewall of the first epitaxial layer, wherein the first epitaxial layer extends from the top surface of one of the plurality of semiconductor fins across to the top surface of the other of the plurality of semiconductor fins, and the second epitaxial layer defines the top surface of the epitaxial source / drain component; A silicide layer is disposed above the epitaxial source / drain component; as well as A source / drain contact is disposed above the silicide layer; as well as An etch stop layer extends along the sidewall surface of the second epitaxial layer of the epitaxial source / drain component and directly contacts the sidewall surface of the second epitaxial layer of the epitaxial source / drain component.

22. The semiconductor structure of claim 21, wherein the epitaxial source / drain component integrates the plurality of semiconductor fins together.

23. The semiconductor structure of claim 21, wherein the second epitaxial layer contains a greater amount of germanium than the first epitaxial layer.

24. The semiconductor structure of claim 23, wherein a portion of the source / drain contact penetrates into the second epitaxial layer.

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