Semiconductor device structure and method for forming the same

Abstract

Some embodiments of the present disclosure provide a method for forming a structure of a semiconductor device. The method includes forming a passivation layer above a semiconductor substrate. The method also includes forming a magnetic element above the passivation layer. The method also includes forming an isolation layer above the magnetic element and the passivation layer, wherein the isolation layer includes a polymer material. Furthermore, the method includes forming a wire above the isolation layer, and the wire extends across the magnetic element.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a structure of a semiconductor device, and more particularly to a method for forming a structure of a semiconductor device having a magnetic element. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design of integrated circuits (ICs) have created generations of ICs, each with smaller and more complex circuits than the previous generation.

[0003] In the course of integrated circuit evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometry size has been reduced. Such size reduction process generally brings benefits in terms of improving production efficiency and reducing related costs.

[0004] However, such size reduction also increases the complexity of processing and manufacturing of integrated circuits. As the size of components continues to decrease, the manufacturing process continues to become more complex to execute. Therefore, how to form reliable semiconductor devices while continuing to reduce size is a challenge. Summary of the invention

[0005] Some embodiments of the present invention provide a method for forming a structure of a semiconductor device. The method includes forming a passivation layer above a semiconductor substrate, and forming a magnetic element above the passivation layer. The method also includes forming an isolation layer above the magnetic element and the passivation layer, wherein the isolation layer includes a polymer material. The method also includes forming a wire above the isolation layer, wherein the wire extends across the magnetic element.

[0006] Some embodiments of the present invention provide another method for forming a structure of a semiconductor device. The method includes forming a first polymer layer above a semiconductor substrate. The method also includes forming a magnetic element above the first polymer layer. The method also includes forming a second polymer layer above the first polymer layer to cover the magnetic element. The method also includes forming a wire above the second polymer layer, wherein the wire extends across the magnetic element.

[0007] Some embodiments of the present invention provide a structure of a semiconductor device. The structure of the semiconductor device includes a semiconductor substrate and a magnetic element located above the semiconductor substrate. The structure of the semiconductor device also includes a passivation layer located between the semiconductor substrate and the magnetic element. The structure of the semiconductor device also includes an isolation layer located above the magnetic element and the passivation layer, wherein the isolation layer includes a polymer material. The structure of the semiconductor device also includes a wire located above the isolation layer and extending across the magnetic element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the content of the embodiments of the present invention. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0009] Figures 1A to 1J is a cross-sectional view illustrating various stages of a process for forming a semiconductor device structure according to some embodiments of the present invention.

[0010] Figure 2 is a schematic cross-sectional view of the structure of a semiconductor device according to some embodiments of the present invention.

[0011] Figure 3 is a top view layout diagram of a semiconductor device structure according to some embodiments of the present invention.

[0012] Figure 4 is a top view layout diagram of an intermediate stage in a process of forming a structure of a semiconductor device according to some embodiments of the present invention.

[0013] Figure 5 is a schematic cross-sectional view of the structure of a semiconductor device according to some embodiments of the present invention.

[0014] Figure 6 is a top view of an isolation layer of a semiconductor device structure according to some embodiments of the present invention.

[0015] Description of reference numerals:

[0016] 100~Semiconductor substrate;

[0017] 102~Internal connection structure;

[0018] 104~Protective layer;

[0019] 106~etching stop layer;

[0020] 108a-108e~magnetic layer / sublayer;

[0021] 109~Magnetic components;

[0022] 109T ~ top surface of magnetic element;

[0023] 109S ~ side wall surface of magnetic element;

[0024] 110~patterned mask layer;

[0025] 112~Hollow structure;

[0026] 114~Cover element;

[0027] 500A~Part 1;

[0028] 500B ~ Part II;

[0029] 502 ~ concave part;

[0030] 802~conductive layer;

[0031] 804~conductive pad;

[0032] 806~Isolation layer;

[0033] 806'~cured isolation layer;

[0034] 808~seed layer;

[0035] 810~Patterned mask layer;

[0036] 812 ~ Opening;

[0037] 814~conductor;

[0038] 902~color wheel;

[0039] R 1 ~ Central area;

[0040] R 2 ~Surrounding areas;

[0041] R 3 ~ area;

[0042] II, 1J-1J, 2-2~ line;

[0043] H 1 ~First thickness;

[0044] H 2 ~Second thickness;

[0045] L 1 ~First imaginary line;

[0046] L 2 ~ The second imaginary line;

[0047] W 1 ~width;

[0048] W 2 ~width. DETAILED DESCRIPTION

[0049] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed above or located on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present invention may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplicity and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0050] In addition, spatially relative terms may be used herein, such as "under", "beneath", "below", "above", "above" and other similar terms may be used herein to describe the relationship between an element or component as shown in the figure and other elements or components. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device can be rotated to other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein can also be interpreted based on the rotated orientation.

[0051] Some embodiments of the present disclosure are presented below. The stages described in these embodiments may be preceded, during and / or followed by other steps. Some steps in the method may be replaced or omitted in different embodiments. Other components may be added to the structure of the semiconductor device. Although the steps discussed in some embodiments are performed in a certain order, these steps may also be performed in another logical order.

[0052] Figures 1A to 1J 1 is a cross-sectional view of multiple stages of a process for forming a structure of a semiconductor device according to some embodiments of the present invention. Figure 1A As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may include a semiconductor wafer having a plurality of device elements formed therein. For example, the semiconductor substrate 100 is a silicon wafer having a plurality of transistors formed therein.

[0053] In some embodiments, an interconnection structure 102 is formed above the semiconductor substrate 100. The interconnection structure 102 may include multiple dielectric layers and multiple conductive components. These conductive components form electrical connections between device components and other components that are subsequently formed. For example, the interconnection structure 102 includes a conductive layer 802 and a conductive pad 804, such as Figure 1A In some embodiments, the uppermost dielectric layer in the interconnect structure 102 is made of or includes a passivation layer. In some embodiments, the passivation layer is made of or includes a polymer material. For example, the polymer material is polyimide or one or more other suitable polymers.

[0054] like Figure 1A As shown, according to some embodiments, a protective layer 104 is deposited above the interconnect structure 102. In a subsequent etching process, the protective layer can be used to protect the interconnect structure 102 (including the passivation layer of the interconnect structure 102) to improve the quality of the magnetic element. In some embodiments, the protective layer 104 is in direct contact with the interconnect structure 102. In some other embodiments, one or more other material layers are formed between the protective layer 104 and the interconnect structure 102.

[0055] In some embodiments, the protective layer 104 is a single layer. In some other embodiments, the protective layer 104 includes multiple sub-layers. These sub-layers can be made of the same material. Alternatively, some of the sub-layers are made of different materials.

[0056] The protective layer 104 may be made of or include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, one or more suitable materials, or a combination of the foregoing materials. The protective layer 104 may be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a spin coating process, one or more other applicable processes, or a combination of the foregoing processes.

[0057] The protective layer 104 may have a thickness of about 0.1 μm to about 3 μm. In some examples, if the thickness of the protective layer 104 is thinner than about 0.1 μm, the protective layer 104 may be too thin to protect the underlying interconnect structure 102. In some other examples, if the thickness of the protective layer 104 is thicker than about 3 μm, the stress of the protective layer 104 may be too high. High stress may cause the protective layer 104 to crack or peel / delaminate, which may negatively affect the quality and reliability of the semiconductor device structure.

[0058] However, many changes and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the protective layer 104 has a different thickness range. In some other embodiments, the protective layer 104 is not formed.

[0059] like Figure 1A As shown, according to some embodiments, an etch stop layer 106 is deposited on the top of the protection layer 104. The etch stop layer 106 can protect the protection layer 104 and the interconnect structure 102 below to prevent the protection layer 104 and the interconnect structure 102 from being damaged in the subsequent etching process of forming the magnetic element. In some embodiments, the etch stop layer 106 is a single layer. In some other embodiments, the etch stop layer 106 includes multiple sub-layers. These sub-layers can be made of the same material. Alternatively, some of the sub-layers are made of different materials.

[0060] In some embodiments, the etching stop layer 106 and the protection layer 104 are made of different materials. The material of the etching stop layer 106 may use or include tantalum oxide, zirconium oxide, tantalum nitride, one or more other suitable materials, or a combination of the foregoing materials. In some embodiments, the etching stop layer 106 may be deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, one or more other applicable processes, or a combination of the foregoing processes. In some other embodiments, a metal layer is deposited above the interconnect structure 102. Thereafter, an oxidation process and / or a nitridation process is performed to convert the metal layer into the etching stop layer 106.

[0061] like Figure 1AAs shown, according to some embodiments, two or more magnetic layers (e.g., magnetic layers 108a-108e) are sequentially deposited above the etch stop layer 106. These magnetic layers 108a-108e will be patterned later to form one or more magnetic elements. In some embodiments, the magnetic layers 108a-108e are made of the same material. In some other embodiments, some of the magnetic layers 108a-108e are made of different materials. In some embodiments, the magnetic layers 108a-108e have the same thickness respectively. In some other embodiments, some of the magnetic layers 108a-108e have different thicknesses.

[0062] In some embodiments, the magnetic layers 108a-108e include cobalt, zirconium, tantalum, iron, nickel, one or more other elements, or a combination of the foregoing elements. The magnetic layers 108a-108e may use or include the following materials: an alloy containing cobalt, zirconium, and tantalum (CZT), an alloy containing cobalt and zirconium, an alloy containing iron and nickel, one or more other suitable materials, or a combination of the foregoing materials. The magnetic layers 108a-108e may be deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination of the foregoing processes.

[0063] like Figure 1B As shown, according to some embodiments, a patterned mask layer 110 is formed above the magnetic layer 108e. The patterned mask layer 110 can assist in the subsequent patterning process of the magnetic layers 108a-108e. In some embodiments, the patterned mask layer 110 is a patterned photoresist layer. A lithography process can be performed to form the patterned mask layer 110 having a desired pattern. For example, the top view of the patterned mask layer 110 can have a square, a rectangle, or other suitable shapes.

[0064] Thereafter, according to some embodiments, the magnetic layers 108a-108e are partially removed, such as Figure 1BAs shown. The remaining portions of the magnetic layers 108a-108e together form a magnetic element 109. In some embodiments, the patterned mask layer 110 is used as an etching mask, and an etching process is used to partially remove the magnetic layers 108a-108e. In some embodiments, the etching process is a wet etching process. The etchant used in the wet etching process may include nitric acid, hydrochloric acid, hydrofluoric acid, one or more other suitable etchants, or a combination of the foregoing etchants. For example, a mixture containing nitric acid, hydrochloric acid and hydrofluoric acid can be used as an etchant for the wet etching process. The etching stop layer 106 and the protective layer 104 can protect the interconnect structure 102 to prevent the interconnect structure 102 from being damaged during the wet etching process for patterning the magnetic layers 108a-108e.

[0065] In some examples, due to the characteristics of the magnetic layers 108a-108e and the wet etching process, hollow structures 112 may be formed on the sidewall surface of the magnetic element 109, such as Figure 1B The hollow structure 112 may contain voids inside, which may have a negative impact on the quality and reliability of the formed magnetic element 109 .

[0066] like Figure 1C As shown, according to some embodiments, the patterned mask layer 110 is removed, and then a new mask element 114 is formed to partially cover the top surface of the magnetic element 109. The material and formation method of the mask element 114 can be the same or similar to the material and formation method of the patterned mask layer 110. In some embodiments, the magnetic element 109 includes a stack of multiple magnetic layers 108a-108e. In some embodiments, the topmost magnetic layer (i.e., magnetic layer 108e) is wider than the mask element 114.

[0067] In some embodiments, the mask element 114 covers the central region R of the uppermost magnetic layer 108e. 1 ,like Figure 1C The top magnetic layer 108e has a peripheral region R not covered by the mask element 114. 2 The peripheral region R of the uppermost magnetic layer 108e 2 The central region R of the uppermost magnetic layer 108e is surrounded by 1 .

[0068] Afterwards, if Figure 1CAs shown, according to some embodiments, an etching process is performed to partially remove the magnetic element 109. In some embodiments, the etching process is a dry etching process, and the dry etching process can remove the hollow structure 112 (including the void) formed on the sidewall surface of the magnetic element 109. The etchant used in the dry etching process may include CF 4 , other suitable etchants, or a combination thereof. In some embodiments, due to the protection of the protective layer 104, the dry etching process can be performed for a longer period of time to ensure that the hollow structure 112 is completely removed. Since the hollow structure 112 is removed, the quality and reliability of the magnetic element 109 can be improved.

[0069] In some embodiments, the etching process used to remove the hollow structure 112 also partially removes the etching stop layer 106 and the protection layer 104. In addition, in some other embodiments, another etching process is used to remove the protection layer 104 and the etching stop layer 106. Therefore, according to some embodiments, a portion of the interconnect structure 102 is exposed, such as Figure 1C For example, the passivation layer of the interconnect structure 102 is exposed. In some embodiments, one or more conductive pads (e.g., conductive pad 804) formed in or above the interconnect structure 102 are exposed. Other conductive components such as redistribution layers may be formed later to connect the exposed conductive pads.

[0070] Afterwards, if Figure 1D As shown, according to some embodiments, the mask element 114 is removed to expose the top surface 109T of the magnetic element 109. Figure 1D As shown, the sidewall surface 109S of the magnetic element 109 has stair-like profiles. According to some embodiments, the magnetic element 109 includes a plurality of sub-layers 108a-108e, and each sub-layer is larger or wider than the sub-layer above it, such as Figure 1D shown.

[0071] Figure 4 is a top view layout diagram of an intermediate stage of a process for forming a structure of a semiconductor device according to some embodiments of the present invention. In some embodiments, Figure 4 Yes Figure 1D A top view of a portion of the structure shown in FIG. Figure 1D The portion of the structure shown (excluding the conductive pad 804) is based on Figure 4 Draw the line II in.

[0072] In some embodiments, the magnetic element 109 has multiple sub-layers, such as magnetic layers 108a-108e. In some embodiments, each sub-layer is larger than the sub-layer above it, such as Figure 1D and Figure 4 For example, magnetic layer 108a is larger than magnetic layer 108b. Similarly, magnetic layer 108d is larger than magnetic layer 108e.

[0073] like Figure 1E As shown, according to some embodiments, an isolation layer 806 is formed above the interconnect structure 102, the conductive pad 804, and the magnetic element 109. In some embodiments, the isolation layer 806 covers the entire top surface of the magnetic element 109. In some embodiments, the isolation layer 806 is in direct contact with the interconnect structure 102. For example, the isolation layer 806 is in direct contact with the passivation layer of the interconnect structure 102. In some embodiments, the isolation layer 806 is in direct contact with the conductive pad 804 and the magnetic element 109.

[0074] The isolation layer 806 may be made of or include a polymer material. Therefore, the isolation layer 806 may have a lower stress than other material layers made of silicon nitride. The polymer material may include polyimide, one or more other suitable polymers, or a combination of the foregoing. The isolation layer 806 may be deposited using a spin coating process, a spray coating process, a lamination process, one or more other applicable processes, or a combination of the foregoing processes. In some embodiments, the isolation layer 806 is formed directly on the magnetic element 109 using a spin coating process.

[0075] In some embodiments, the isolation layer 806 includes a first polymer material, and the passivation layer of the interconnect structure 102 includes a second polymer material. In some embodiments, since both the isolation layer 806 and the passivation layer of the interconnect structure 102 are made of polymer materials, there is high adhesion between the isolation layer 806 and the passivation layer of the interconnect structure 102. In some embodiments, the isolation layer 806 and the passivation layer of the interconnect structure 102 both include or are made of the same polymer material, such as polyimide, which can further enhance the adhesion between the isolation layer 806 and the passivation layer of the interconnect structure 102. The isolation layer 806 can serve as a stress buffer layer. This can prevent the isolation layer 806 from cracking at a corner near the magnetic element 109.

[0076] In some other examples of isolation layers made of silicon nitride or silicon oxynitride without polymer materials, delamination or cracks may occur between the isolation layer and the passivation layer of the interconnect structure 102. For example, delamination may occur between the isolation layer 806 and the interconnect structure 102 and near the magnetic element 109. In addition, conductive pads formed in or above the interconnect structure 102 may be damaged due to the high stress of the isolation layer. For example, the isolation layer may shrink and cause delamination between the isolation layer and the passivation layer (e.g., polyimide) of the interconnect structure 102. The isolation layer may also crack.

[0077] In some embodiments, the adhesion between the isolation layer 806 and the magnetic element 109 can also be improved due to the material properties of the isolation layer 806. Good adhesion helps ensure that there is no or substantially no delamination between the isolation layer 806 and the magnetic element 109. The isolation layer 806 has low stress and can also serve as a stress buffer. Therefore, the isolation layer 806 also helps to avoid delamination between the magnetic layers 108a-108e. Therefore, the performance and reliability of the structure of the semiconductor device can be improved.

[0078] like Figure 1F As shown, according to some embodiments, the isolation layer 806 is patterned to form an opening, which exposes the conductive pad 804 originally located under the isolation layer 806. The patterning of the isolation layer 806 can be performed by a lithography process, an energy beam drilling process, one or more other applicable processes, or a combination of the foregoing processes. The energy beam drilling process may include partially drilling the isolation layer 806 using an ion beam, an electron beam, a plasma beam, one or more other suitable energy beams, or a combination of the foregoing. In some embodiments, after the isolation layer 806 is patterned, the remaining isolation layer 806 still covers the entire top surface of the magnetic element 109, such as Figure 1F shown.

[0079] like Figure 1G As shown, according to some embodiments, the isolation layer 806 is cured to form a cured isolation layer 806'. A thermal operation can be used to cure the isolation layer 806 to form a cured isolation layer 806'. The thermal operation can be performed at a temperature ranging from about 250°C to about 350°C for 1 hour or more. For example, the isolation layer 806 is cured at a temperature of about 310°C for about 4 hours.

[0080] In some embodiments, the isolation layer 806 is cured using a light irradiation process to form a cured isolation layer 806'. The light irradiation process for irradiating the isolation layer 806 may involve the use of ultraviolet light, laser light, one or more other suitable light sources, or a combination thereof, thereby forming a cured isolation layer 806'. In some other embodiments, both a thermal curing process and a light irradiation process may be used to cure the isolation layer 806.

[0081] However, many changes and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the isolation layer 806 is not cured.

[0082] In some embodiments, due to the material properties of the isolation layer 806, the cured isolation layer 806' also has an inclined side surface. The inclined profile of the cured isolation layer 806' can be beneficial to subsequent formation processes. Therefore, the reliability and performance of the semiconductor device structure can be improved.

[0083] like Figure 1G As shown, according to some embodiments, the thickness of the cured isolation layer 806' gradually increases along the direction from the upper portion of the cured isolation layer 806' to the lower portion of the cured isolation layer 806'. Figure 1G As shown, the cured isolation layer 806' has a first thickness H 1 and the second thickness H 2 The first thickness H 1 The second thickness H is measured from the inclined side surface of the cured isolation layer 806' to the upper edge corner of the magnetic element 109. 2 The first thickness H is measured from the inclined side surface of the cured isolation layer 806' to the lower edge corner. 1 Greater than the second thickness H 2 .

[0084] like Figure 1G As shown, the first imaginary line L 1 The inclined side surface of the cured isolation layer 806' and the second imaginary line L 2 The first imaginary line L passes through the topmost edge corner of the magnetic element 109. 1 and the second imaginary line L 2 Together they define an angle θ. In some embodiments, the angle θ is in a range of about 5 degrees to about 25 degrees. In some other embodiments, the angle θ is in a range of about 10 degrees to about 20 degrees.

[0085] like Figure 1H As shown, according to some embodiments, a seed layer 808 is deposited on the cured isolation layer 806 ′ and the conductive pad 804 . The seed layer 808 can be used to assist in subsequent plating, such as an electroplating process. The seed layer 808 covers the entire top surface of the magnetic element 109 .

[0086] The seed layer 808 may be made of copper, aluminum, titanium, gold, cobalt, platinum, nickel, one or more other suitable materials, or a combination of the foregoing materials, or may contain these materials. The seed layer 808 may be deposited by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a stacking process, one or more other applicable processes, or a combination of the foregoing processes.

[0087] like Figure 1H As shown, according to some embodiments, a patterned mask layer 810 is then formed on the seed layer 808. The patterned mask layer 810 has an opening 812, and the opening 812 exposes a portion of the seed layer 808 directly above the conductive pad 804. The patterned mask layer 810 includes one or more openings (including the opening 812), and the portion of the seed layer 808 exposed by the one or more openings will subsequently form one or more conductive lines. The patterned mask layer 810 can be a patterned photoresist layer. The formation process of the patterned mask layer 810 may involve a lithography process.

[0088] like Fig. 1I As shown, according to some embodiments, a conductive line 814 is formed on the exposed portion of the seed layer 808. The conductive line 814 may be made of copper, gold, cobalt, one or more other suitable materials, or a combination of the foregoing materials, or the conductive line 814 may include the foregoing materials. The conductive line 814 may be formed by an electroplating process, a chemical plating process, one or more other applicable processes, or a combination of the foregoing processes.

[0089] like Figure 1J As shown, according to some embodiments, the patterned mask layer 810 is removed. Then, the exposed portion of the seed layer 808 not covered by the conductive line (eg, conductive line 814) is removed, as shown in FIG. Figure 1J The exposed portion of the seed layer 808 may be removed by an etching process.

[0090] In some embodiments, during the etching process to remove the exposed portion of the seed layer 808, the magnetic element 109 can be protected from damage by the solidified isolation layer 806'. The surface of the magnetic element 109 can be kept in good condition. This ensures the quality and reliability of the magnetic element 109.

[0091] Figure 3 is a top view layout diagram of a semiconductor device structure according to some embodiments of the present invention. In some embodiments, Figure 3 yes Figure 1J In some embodiments, Figure 1J The structure shown in the cross section is based on Figure 3 The line 1J-1J in FIG.

[0092] Figure 2 is a cross-sectional schematic diagram of a structure of a semiconductor device according to some embodiments of the present invention. In some embodiments, Figure 3 yes Figure 2 In some embodiments, Figure 2 The structure shown in the cross section is based on Figure 3 Draw the line 2-2 in the figure.

[0093] like Figure 2 As shown, according to some embodiments, the wire 814 extends across the top of the magnetic element 109. Figure 3 As shown, according to some embodiments, a plurality of conductive lines 814 are formed above the cured isolation layer 806'. In some embodiments, each conductive line 814 extends across the magnetic element 109 (the magnetic element 109 is below the cured isolation layer 806' and is drawn in dashed lines). The cured isolation layer 806' physically isolates and / or electrically isolates the magnetic element 109 from the conductive lines 814.

[0094] In some embodiments, the wires 814 are electrically connected to each other. In some embodiments, each wire 814 is electrically connected to other wires located above and below the magnetic element 109. The wires (including the wires 814) surround the magnetic element 109 together. The wires and the magnetic element 109 can be used together as an inductor.

[0095] In some of the above-described embodiments, the formation of the conductive line 814 involves an electroplating process. Many changes and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, a metal layer is deposited using a physical vapor deposition process, a chemical vapor deposition process, one or more other applicable processes, or a combination of the foregoing processes. Thereafter, the metal layer is patterned using a lithography process and an etching process to form the conductive line 814.

[0096] Thereafter, multiple material layers and multiple device elements may be formed in the Figure 1J , Figure 2 as well as Figure 3 Afterwards, a sawing process may be performed to cut the structure into a plurality of semiconductor dies or die packages separated from each other.

[0097] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 5 is a cross-sectional schematic diagram of a structure of a semiconductor device according to some embodiments of the present invention. In some embodiments, Figure 5 yes Figure 1C 1 is an enlarged cross-sectional view of a portion of the structure shown in FIG. In some embodiments, after an etching process is performed to remove the hollow structure 112, the top surface of a portion of the topmost magnetic layer 108e is recessed. Figure 5 As shown, the magnetic layer 108e has a first portion 500A covered by the mask element 114 and a second portion 500B not covered by the mask element 114. After the etching process, the second portion 500B is recessed to a height level lower than the first portion 500A. In some embodiments, a recess 502 is formed. The recess 502 surrounds the first portion 500A. In some embodiments, the recess 502 is located at Figure 4 The surrounding area R 2 Therefore, the recess 502 surrounds the central region R 1 .

[0098] In some embodiments, the recess 502 has a width measured from the sidewall of the recess 502 to the edge of the magnetic layer 108e. This width may be in the range of about 5 μm to about 10 μm. In some examples, if the width is less than about 5 μm, it may have a negative impact on the etching process of removing the hollow structure 112. Once the coverage of the mask element 114 shifts during the formation of the mask element 114, some of the hollow structure 112 may be covered by the mask element 114. Therefore, the hollow structure 112 may not be completely removed, resulting in degradation of the performance of the structure of the semiconductor device. In some other examples, if the width is greater than about 10 μm, not only the hollow structure 112 but also more portions of the magnetic element 109 may be removed, which may also result in degradation of the performance of the structure of the semiconductor device.

[0099] Figure 6 is a top view of an isolation layer of a semiconductor device structure according to some embodiments of the present invention. In some embodiments, Figure 6 Yes Figure 1J , Figure 2 as well as Figure 3 806' is a top view of the entire or a portion of the structure shown. In some embodiments, due to the characteristics of the isolation layer 806', when the cured isolation layer 806' is viewed from above, when the cured isolation layer 806' is observed under the irradiation of visible light, the cured isolation layer 806' includes one or more color rings. The color ring 902 may include orange, green, yellow, red, other colors, or a combination of the aforementioned colors.

[0100] In some embodiments, the cured isolation layer 806' has a thickness measured between the top surface of the cured isolation layer 806' and the top surface of the magnetic element 109. The thickness may be in the range of about 1.5 μm to about 2.5 μm. In some embodiments, the thickness of the cured isolation layer 806' is not uniform. The non-uniform thickness of the cured isolation layer 806' may cause the appearance of the color ring 902.

[0101] In some examples, if the thickness of the cured isolation layer 806' is less than about 1.5 μm, some parts of the magnetic element 109 may not be well covered and may be exposed. Therefore, the magnetic element 109 may directly contact with the subsequently formed wires, causing the structure of the semiconductor device to fail in function. In some other examples, if the thickness of the cured isolation layer 806' is greater than about 2.5 μm, the distance between the magnetic element 109 and the subsequently formed wires may be too large, causing the structure of the semiconductor device to perform poorly.

[0102] In some embodiments, some color rings 902 are continuous rings. In some embodiments, some color rings 902 are discontinuous rings. In some embodiments, the portion of isolation layer 806' directly above magnetic element 109 may have 4 to 6 color rings. In some embodiments, some color rings 902 have a different width than other color rings 902. In some embodiments, a thinner width W 1 One of the color rings 902 is surrounded by a thicker width W 2 Another color wheel 902, such as Figure 6 In some embodiments, the inner color ring 902 has a lighter color than the outer color ring 902. In some other embodiments, the color rings 902 are substantially equal in width to each other. One color ring 902 surrounds one or more other color rings 902. In some embodiments, the innermost color ring 902 surrounds an elliptical region R 3 ,like Figure 6 shown.

[0103] In one aspect, some embodiments of the present invention provide a method for forming a structure of a semiconductor device. The method includes forming a passivation layer above a semiconductor substrate, and forming a magnetic element above the passivation layer. The method also includes forming an isolation layer above the magnetic element and the passivation layer, wherein the isolation layer includes a polymer material. The method also includes forming a wire above the isolation layer, wherein the wire extends across the magnetic element.

[0104] In some embodiments, the method of forming a semiconductor device structure further includes patterning the isolation layer to expose a pad structure under the isolation layer.

[0105] According to some embodiments, in a method of forming a structure of a semiconductor device, after the isolation layer is patterned to expose the pad structure, the isolation layer covers the entire top surface of the magnetic element.

[0106] According to some embodiments, the method for forming a structure of a semiconductor device further includes curing the isolation layer after patterning the isolation layer and before forming the conductive line.

[0107] According to some embodiments, in a method of forming a structure of a semiconductor device, an isolation layer is formed by a spin coating process.

[0108] According to some embodiments, in a method of forming a structure of a semiconductor device, an isolation layer is directly formed on a magnetic element and a passivation layer to cover the magnetic element.

[0109] According to some embodiments, in a method of forming a structure of a semiconductor device, the passivation layer includes a second polymer material.

[0110] According to some embodiments, in a method of forming a structure of a semiconductor device, both the isolation layer and the passivation layer include polyimide.

[0111] According to some embodiments, in a method of forming a structure of a semiconductor device, the formation of a magnetic element includes: forming a plurality of magnetic layers above a passivation layer; forming a patterned mask layer above these magnetic layers; and wet etching these magnetic layers to partially remove these magnetic layers, wherein remaining portions of these magnetic layers form magnetic elements.

[0112] According to some embodiments, in a method of forming a structure of a semiconductor device, a mask element is formed to partially cover a top surface of the magnetic element; and the magnetic element is partially removed using a wet etching process to remove voids from the sidewalls of the magnetic element.

[0113] In one aspect, some embodiments of the present invention provide another method for forming a structure of a semiconductor device. The method includes forming a first polymer layer on a semiconductor substrate, and forming a magnetic element on the first polymer layer. The method also includes forming a second polymer layer on the first polymer layer to cover the magnetic element. The method also includes forming a wire on the second polymer layer, wherein the wire extends across the magnetic element.

[0114] According to some embodiments, in a method for forming a structure of a semiconductor device, the first polymer layer and the second polymer layer each include polyimide.

[0115] According to some embodiments, the method for forming a semiconductor device structure further includes partially removing the second polymer layer to expose a pad structure located under the second polymer layer.

[0116] According to some embodiments, in the method for forming a structure of a semiconductor device, after partially removing the second polymer layer and before forming the conductive line, the method further includes curing the second polymer layer.

[0117] According to some embodiments, in a method of forming a semiconductor device structure, a second polymer layer is directly formed on a magnetic element by a spin coating process.

[0118] In one aspect, some embodiments of the present invention provide a structure of a semiconductor device. The structure of the semiconductor device includes a semiconductor substrate and a magnetic element located above the semiconductor substrate. The structure of the semiconductor device also includes a passivation layer located between the semiconductor substrate and the magnetic element. The structure of the semiconductor device also includes an isolation layer located above the magnetic element and the passivation layer, wherein the isolation layer includes a polymer material. The structure of the semiconductor device also includes a wire located above the isolation layer and extending across the magnetic element.

[0119] In some embodiments, when the isolation layer is viewed from above the structure of the semiconductor device and is observed under illumination of visible light, the isolation layer includes at least one color ring.

[0120] In some embodiments, the passivation layer and the isolation layer in the structure of the semiconductor device respectively include polyimide.

[0121] In some embodiments, a magnetic element in a structure of a semiconductor device includes a plurality of sub-layers, and each sub-layer is larger than another sub-layer located above it.

[0122] In some embodiments, the isolation layer in the structure of the semiconductor device directly contacts the magnetic element.

[0123] The above summarizes the components of several embodiments so that the technical personnel in the technical field to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. The technical personnel in the technical field to which the present invention belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments introduced herein. The technical personnel in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as defined by the appended claims.

Claims

1. A method for forming a structure of a semiconductor device, comprising: forming a passivation layer on a semiconductor substrate; forming a magnetic element on the passivation layer, wherein the magnetic element comprises a plurality of sub-layers, and each sub-layer of the plurality of sub-layers is larger than another sub-layer located thereon; forming an isolation layer above the magnetic element and the passivation layer, wherein the isolation layer comprises a polymer material; and A conductive line is formed above the isolation layer, wherein the conductive line extends across the magnetic element. 2 . The method for forming a semiconductor device structure as claimed in claim 1 , further comprising patterning the isolation layer to expose a pad structure located under the isolation layer. 3 . The method for forming a semiconductor device structure as claimed in claim 2 , wherein after the isolation layer is patterned to expose the pad structure, the isolation layer covers the entire top surface of the magnetic element. 4 . The method for forming a structure of a semiconductor device according to claim 2 , further comprising curing the isolation layer after patterning the isolation layer and before forming the conductive line.

5. The method for forming a semiconductor device structure as claimed in claim 1, wherein the isolation layer is formed by a spin coating process. 6 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the isolation layer is directly formed on the magnetic element and the passivation layer to cover the magnetic element. 7 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the passivation layer comprises a second polymer material. 8 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein both the isolation layer and the passivation layer comprise polyimide.

9. The method for forming a semiconductor device structure as claimed in claim 1, wherein forming the magnetic element comprises: forming a plurality of magnetic layers on the passivation layer; forming a patterned mask layer on the plurality of magnetic layers; as well as The plurality of magnetic layers are wet etched to partially remove the plurality of magnetic layers, wherein remaining portions of the plurality of magnetic layers form the plurality of sub-layers of the magnetic element.

10. The method for forming a semiconductor device structure according to claim 9, further comprising: forming a mask element to partially cover a top surface of the magnetic element; as well as The magnetic element is partially removed by a wet etching process to remove the hole from the sidewall of the magnetic element. 11 . The method for forming a structure of a semiconductor device according to claim 9 , wherein a lower magnetic layer of the plurality of magnetic layers is wider than an upper magnetic layer of the plurality of magnetic layers.

12. A method for forming a structure of a semiconductor device, comprising: forming a first polymer layer on a semiconductor substrate; Forming a magnetic element on the first polymer layer, wherein the magnetic element comprises a plurality of sub-layers, and each sub-layer of the plurality of sub-layers is larger than another sub-layer located thereon; forming a second polymer layer on the first polymer layer to cover the magnetic element; and A conductive line is formed above the second polymer layer, wherein the conductive line extends across the magnetic element. 13 . The method for forming a semiconductor device structure as claimed in claim 12 , wherein the first polymer layer and the second polymer layer respectively comprise polyimide. 14 . The method for forming a semiconductor device structure as claimed in claim 12 , further comprising partially removing the second polymer layer to expose a pad structure under the second polymer layer. 15 . The method for forming a semiconductor device structure according to claim 14 , further comprising curing the second polymer layer after partially removing the second polymer layer and before forming the conductive line. 16 . The method for forming a semiconductor device structure as claimed in claim 12 , wherein the second polymer layer is directly formed on the magnetic element by a spin coating process.

17. A structure of a semiconductor device, comprising: a semiconductor substrate; a magnetic element located above the semiconductor substrate, wherein the magnetic element comprises a plurality of sub-layers, and each sub-layer of the plurality of sub-layers is larger than another sub-layer located above the sub-layer; a passivation layer located between the semiconductor substrate and the magnetic element; an isolation layer, located above the magnetic element and the passivation layer, wherein the isolation layer comprises a polymer material; and A conductive line is located above the isolation layer and extends across the magnetic element. 18 . The structure of the semiconductor device as claimed in claim 17 , wherein when the isolation layer is viewed from above and the isolation layer is observed under illumination of visible light, the isolation layer comprises at least one color ring. 19 . The semiconductor device structure as claimed in claim 17 , wherein the passivation layer and the isolation layer respectively comprise polyimide. 20 . The semiconductor device structure as claimed in claim 17 , wherein the isolation layer directly contacts the magnetic element.

21. A method of forming a structure of a semiconductor device, comprising: Forming a magnetic element above a passivation layer above a semiconductor substrate, wherein the magnetic element comprises a plurality of sub-layers, and each sub-layer of the plurality of sub-layers is larger than another sub-layer located above the sub-layer; forming an isolation layer above the magnetic element and the semiconductor substrate, wherein the isolation layer comprises a polymer material; and A conductive line is formed on the isolation layer, wherein the conductive line extends beyond the edge of the magnetic element. 22 . The method for forming a semiconductor device structure as claimed in claim 21 , further comprising partially removing the isolation layer before forming the conductive line. 23 . The method for forming a structure of a semiconductor device according to claim 22 , further comprising curing the isolation layer after partially removing the isolation layer and before forming the conductive line. 24 . The method for forming a semiconductor device structure as claimed in claim 21 , wherein the isolation layer is directly formed on the magnetic element.

25. The method for forming a semiconductor device structure as claimed in claim 21, wherein forming the magnetic element comprises: forming a plurality of magnetic layers above the semiconductor substrate; forming a patterned mask layer on the plurality of magnetic layers; as well as The plurality of magnetic layers are wet etched to partially remove the plurality of magnetic layers, wherein remaining portions of the plurality of magnetic layers form the plurality of sub-layers of the magnetic element.

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