Method for manufacturing semiconductor device structure

Abstract

A semiconductor device structure and manufacturing method. The method includes forming an adhesive layer on a semiconductor substrate and forming a magnetic element on the adhesive layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the upper surface of the magnetic element and partially covers multiple side wall surfaces of the magnetic element. The method also includes partially removing the adhesive layer so that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. In addition, the method includes forming a wire on the isolation element.

Description

Technical Field

[0001] This invention relates to a semiconductor technology, and more particularly to a semiconductor device structure and its manufacturing method. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to multiple generations of ICs. Each generation features smaller and more complex circuits than the previous one.

[0003] In the evolution of ICs, functional density (i.e., the number of interconnects per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using the process) decreases. This scale-down process usually brings many benefits by increasing production efficiency and reducing associated costs.

[0004] However, these advancements have increased the complexity of process and IC manufacturing. As feature size continues to shrink, processes become increasingly difficult to execute. Therefore, fabricating reliable and ever-smaller semiconductor devices has become a challenge. Summary of the Invention

[0005] A method for manufacturing a semiconductor device structure includes: forming an adhesive layer on a semiconductor substrate and forming a magnetic element on the adhesive layer. The method further includes forming an isolation element extending across the magnetic element. The isolation element partially covers the upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. Additionally, the method includes forming a conductive line on the isolation element.

[0006] A method for manufacturing a semiconductor device structure includes forming a metal layer on a semiconductor substrate. The method also includes forming a magnetic element on the metal layer. The method further includes directly forming an isolation element on the magnetic element and the metal layer. Additionally, the method includes forming a conductive wire on the isolation element.

[0007] A semiconductor device structure includes a semiconductor substrate and a magnetic element disposed on the semiconductor substrate. The semiconductor device structure also includes an adhesive element disposed between the magnetic element and the semiconductor substrate. The semiconductor device structure further includes an isolation element extending across the magnetic element, wherein the isolation element partially covers the upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element. An edge of the adhesive element is laterally disposed between an edge of the magnetic element and an edge of the isolation element. Additionally, the semiconductor device structure includes a conductive wire disposed on the isolation element. Attached Figure Description

[0008] Figures 1A to 1M A cross-sectional schematic diagram of a semiconductor device structure manufacturing method at different manufacturing stages according to some embodiments is shown.

[0009] Figures 2A to 2E A cross-sectional schematic diagram of a semiconductor device structure manufacturing method at different manufacturing stages according to some embodiments is shown.

[0010] Figures 3A to 3D A schematic planar layout of a semiconductor device structure manufacturing method at different manufacturing stages according to some embodiments is shown.

[0011] Figure 4 A schematic cross-sectional view of a semiconductor device structure is shown according to some embodiments.

[0012] Figure 5 A schematic cross-sectional view of a semiconductor device structure is shown according to some embodiments.

[0013] Figure 6 A schematic planar layout diagram of a semiconductor device structure is shown according to some embodiments.

[0014] Figure 7 A schematic plan view of a semiconductor device structure manufacturing method at an intermediate manufacturing stage according to some embodiments is shown.

[0015] Explanation of reference numerals in the attached figures:

[0016] Mask elements 12, 114, and 117

[0017] 100 Semiconductor substrate

[0018] 100E, 501, E1, E2, E3, E4 Edge

[0019] 102 Internal Connection Structure

[0020] 103 Adhesive layer

[0021] 103' Adhesive element

[0022] 103T end

[0023] 104 Protective Layer

[0024] 106 Etching Stop Layer

[0025] Magnetic layers 108a, 108b, 108c, 108d, 108e

[0026] 109 Magnetic Components

[0027] 109S sidewall surface

[0028] 109T upper surface

[0029] 110 Mask layer

[0030] 112 Hollow Structure

[0031] 116 Isolation Layer

[0032] 116' Isolation element

[0033] 118A and 118B wires

[0034] 120 dielectric layer

[0035] 500A Part 1

[0036] 500B Part 2

[0037] 502 recess

[0038] d3 width

[0039] Distances of d1, d2, D1, D2, D3

[0040] R, R2 outer area

[0041] R1 Central Area

[0042] S-shaped hole DETAILED DESCRIPTION

[0043] The following disclosure provides numerous different embodiments or examples for implementing various feature components of the present invention. The following disclosure describes specific examples of the various components and their arrangements to simplify the present disclosure. Of course, these are merely illustrative examples and are not intended to limit the invention. For example, if the following disclosure describes forming a first feature component on or above a second feature component, it indicates that it includes embodiments where the formed first feature component and the second feature component are in direct contact, and also includes embodiments where additional feature components may be formed between the first feature component and the second feature component, so that the first feature component and the second feature component may not be in direct contact. Furthermore, reference numerals and / or text are repeated in the various examples of this disclosure. Repetition is for simplification and clarity, and not to specify the relationships between the various embodiments and / or configurations discussed.

[0044] Furthermore, spatial terms such as "below," "under," "down," "above," and "upper" are used herein to readily express the relationship between elements or features in the accompanying drawings and other elements or features. These spatial terms cover not only the orientations shown in the drawings but also different orientations of the device during use or operation. The device may have different orientations (rotation 90 degrees or other orientations), and the spatial symbols used herein also have corresponding interpretations.

[0045] The following describes some embodiments. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the stages may be replaced or excluded. Additional features may be added to the semiconductor device structure. For different embodiments, some of the features described below may be replaced or excluded. Although some of the embodiments discussed operate in a particular order, these operations may be performed in another logical order.

[0046] Figures 1A to 1M This diagram illustrates a cross-sectional view of a semiconductor device structure manufacturing method at different manufacturing stages according to some embodiments. Figure 1A As shown, a semiconductor substrate 100 is received or provided. The semiconductor substrate 100 may include a semiconductor wafer in which a plurality of device elements are formed. For example, the semiconductor substrate 100 is a silicon wafer in which transistors are formed.

[0047] In some embodiments, an interconnect structure 102 is formed over a semiconductor substrate 100. The interconnect structure 102 may include multiple dielectric layers and multiple conductive features. These conductive features form electrical connections between device elements and other elements to be subsequently formed. In some embodiments, the topmost dielectric layer of the interconnect structure 102 is made of or includes a polymeric material. For example, the polymeric material is polyimide or other suitable materials.

[0048] like Figure 1A As shown, according to some embodiments, an adhesive layer 103 is deposited on the interconnect structure 102. The adhesive layer 103 can be used to improve the adhesion between the interconnect structure 102 and subsequently formed elements. In some embodiments, the adhesive layer 103 further extends onto a sidewall of the interconnect structure 102. The adhesive layer 103 further extends onto a sidewall of the semiconductor substrate 100.

[0049] In some embodiments, the adhesive layer 103 is made of or comprises a metallic material. The metallic material may include titanium, aluminum, copper, one or more other suitable materials, or combinations thereof. For example, the metallic material may include substantially pure metallic materials (e.g., titanium) or alloys (e.g., a combination of copper and aluminum). The thickness of the adhesive layer 103 may be approximately [missing information - likely a value]. to within the range.

[0050] The adhesive layer 103 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, electroless electroplating, one or more other suitable processes, or combinations thereof.

[0051] Subsequently, according to some embodiments, a mask element 12 is formed on the adhesive layer 103, such as... Figure 1A As shown. In some embodiments, the mask element 12 covers an interior of the adhesive layer 103. The adhesive layer 103 has an exterior surrounding the interior, exposing the exterior of the adhesive layer 103 located above a peripheral region of the semiconductor substrate 100. The mask element 12 may be a patterned photoresist layer. The mask element 12 may be formed using a photolithography process.

[0052] like Figure 1B As shown, according to some embodiments, the exposed portion of the adhesive layer 103 is removed. In some embodiments, the exposed portion (outer portion) of the adhesive layer 103 is removed by an etching process using a mask element 12 as an etching mask.

[0053] Subsequently, according to some embodiments, the mask elements are removed, such as... Figure 1C As shown. After removing the exterior of the adhesive layer 103, the peripheral region R of the internal connection structure 102 is exposed. The remaining portion of the adhesive layer 103 is formed into an end 103T. The end 103T is laterally spaced from the edge 100E of the semiconductor substrate 100 by a distance D1.

[0054] Figure 7 A schematic plan view of a semiconductor device structure manufacturing method at an intermediate manufacturing stage according to some embodiments is shown. In some embodiments, Figure 7 It shows Figure 1C A planar schematic diagram of the structure shown. Figure 7 It also shows Figure 1C A plan view of other parts not shown. In some embodiments, the semiconductor substrate 100 is a semiconductor wafer. The peripheral region R of the internal interconnect structure 102 laterally surrounds the adhesive layer 103. In some embodiments, the distance D1 is in the range of approximately 1000 μm to 2000 μm. In some other embodiments, the distance D1 is in the range of approximately 1500 μm to 1800 μm.

[0055] In some embodiments, removing the exterior of the adhesive layer 103 prevents the etchant used during subsequent processes for forming magnetic elements from extending into the adhesive layer 103 beneath the magnetic elements. This prevents peeling problems between material layers from occurring near the peripheral region of the semiconductor substrate 100. Peeling problems may still occur in some cases where the distance D1 is less than about 1000 μm. In some other cases where the distance D1 is greater than about 2000 μm, the outer region R occupies too much space. This reduces the number of device elements that can be formed.

[0056] like Figure 1D As shown, according to some embodiments, a protective layer 104 is deposited on the adhesive layer 103 and the interconnect structure 102. The protective layer 104 can be used during subsequent etching processes to protect the interconnect structure 102 to improve the quality of the magnetic element. In some embodiments, the protective layer 104 is in direct contact with the adhesive layer 103 and the interconnect structure 102. In some other embodiments, one or more other material layers are formed between the protective layer 104 and the adhesive layer 103 or between the protective layer 104 and the interconnect structure 102.

[0057] In some embodiments, the protective layer 104 is a single layer. In some other embodiments, the protective layer 104 includes multiple sublayers. The sublayers may be made of the same material. Alternatively, some sublayers may be made of different materials.

[0058] The protective layer 104 may be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, one or more other suitable materials, or combinations thereof. The protective layer 104 may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating, one or more other applicable processes, or combinations thereof.

[0059] The protective layer 104 may have a thickness ranging from approximately 0.1 μm to 3 μm. In some cases, if the protective layer 104 is thinner than approximately 0.1 μm, it will be too thin to protect the underlying interconnect structure 102. In other cases, if the protective layer 104 is thicker than approximately 3 μm, the stress on the protective layer 104 will be too high. The protective layer 104 may crack or delaminate due to high stress, which will negatively affect the quality and reliability of the semiconductor device structure.

[0060] However, many variations and / or modifications can be made to the embodiments described herein. In some other embodiments, the protective layer 104 is not formed.

[0061] like Figure 1DAs shown, according to some embodiments, an etch stop layer 106 is deposited on the protective layer 104. The etch stop layer 106 protects the protective layer 104, the adhesive layer 103, and the underlying interconnect structure 102 from damage during subsequent etching processes for forming magnetic elements. In some embodiments, the etch stop layer 106 is a single layer. In some other embodiments, the etch stop layer 106 includes multiple sublayers. The sublayers may be made of the same material. Alternatively, some sublayers may be made of different materials.

[0062] In some embodiments, the etch stop layer 106 and the protective layer 104 are made of different materials. The etch stop layer 106 may be made of tantalum oxide, zirconium oxide, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the etch stop layer 106 is deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof. In some other embodiments, a metal layer is deposited over the internal interconnect structure 102. Subsequently, an oxidation process and / or a nitriding process is used to transform the metal layer into the protective layer 104.

[0063] like Figure 1D As shown, according to some embodiments, two or more magnetic layers (such as magnetic layers 108a-108e) are sequentially deposited on the etch stop layer 106. These magnetic layers 108a-108e are later patterned to form one or more magnetic elements. In some embodiments, the magnetic layers 108a-108e are made of the same material. In some other embodiments, some magnetic layers 108a-108e are made of different materials. In some embodiments, each magnetic layer 108a-108e has the same thickness. In some other embodiments, some magnetic layers 108a-108e have different thicknesses.

[0064] In some embodiments, the magnetic layers 108a-108e comprise cobalt, zirconium, tantalum, iron, nickel, one or more other elements, or combinations thereof. The magnetic layers 108a-108e may be made of an alloy comprising cobalt, zirconium, and tantalum (CZT), an alloy comprising cobalt and zirconium, an alloy comprising iron and nickel, one or more other suitable materials, or combinations thereof. The magnetic layers 108a-108e may be deposited using PVD, CVD, ALD, electroplating, electroless electroplating, one or more other suitable processes, or combinations thereof.

[0065] like Figure 1EAs shown, according to some embodiments, a patterned mask layer 110 is formed on the magnetic layer 108e. The patterned mask layer 110 is used to assist subsequent patterning processes of the magnetic layers 108a-108e. In some embodiments, the patterned mask layer 110 is a patterned photoresist layer. A lithography process can be used to form the patterned mask layer 110 with the desired pattern. For example, a planar schematic diagram of the patterned mask layer 110 may have a square shape, a rectangular shape, or other suitable shape.

[0066] Subsequently, according to some embodiments, the magnetic layers 108a-108e are locally removed, such as... Figure 1E As shown. In this way, the remaining portions of magnetic layers 108a-108e together form magnetic element 109. In some embodiments, a patterned mask layer 110 is used as an etching mask, and an etching process is used to locally remove magnetic layers 108a-108e. In some embodiments, the etching process is a wet etching process. The etchant used in a wet etching process may include nitric acid, hydrochloric acid, hydrofluoric acid, one or more other suitable etchants, or combinations thereof. For example, a mixture of nitric acid, hydrochloric acid, and hydrofluoric acid is used as the etchant in a wet etching process. The etch stop layer 106 and the protective layer 104 can protect the internal connection structure 102 and the adhesive layer 103 from damage during the wet etching process used for patterning magnetic layers 108a-108e.

[0067] In some cases, due to the characteristics of the magnetic layers 108a-108e and the wet etching process, multiple hollow structures 112 can be formed on multiple sidewall surfaces of the magnetic element 109, such as... Figure 1E As shown. The hollow structure 112 may contain voids, which may adversely affect the quality and reliability of the formed magnetic element 109.

[0068] like Figure 1F As shown, according to some embodiments, mask element 110 is removed, and then a new mask element 114 is formed to partially cover the top surface of magnetic element 109. The material and formation method of mask element 114 may be the same as or similar to the material and formation method of patterned mask layer 110. In some embodiments, magnetic element 109 includes a stack of multiple magnetic layers 108a-108e. In some embodiments, the topmost magnetic layer (i.e., magnetic layer 108e) is wider than mask element 114.

[0069] In some embodiments, the mask element 114 covers the central region R1 of the topmost magnetic layer 108e, such as... Figure 1F As shown. The topmost magnetic layer 108e has a peripheral region R2 that is not covered by the mask element 114. The peripheral region R2 of the topmost magnetic layer 108e surrounds the central region R1 of the topmost magnetic layer 108e.

[0070] Subsequently, according to some embodiments, an etching process is performed to locally remove the magnetic element 109, such as... Figure 1F As shown. In some embodiments, the etching process is a dry etching process, which removes the hollow structure 112 (including voids) at the sidewall surface of the magnetic element 109. The etchant used in the dry etching process may include CF4 or other suitable etchants. In some embodiments, the dry etching process is performed for a longer period of time because it is protected by the protective layer 104 to ensure complete removal of the hollow structure 112. Because the hollow structure 112 is removed, the quality and reliability of the magnetic element 109 can be improved.

[0071] In some embodiments, the etching process for removing the hollow structure 112 also partially removes the etch stop layer 106 and the protective layer 104. Alternatively, another etching process is used to remove the protective layer 104 or the etch stop layer 106. In this way, according to some embodiments, a portion of the inner connection structure 102 and a portion of the adhesive layer 103 are exposed, such as... Figure 1F As shown, one or more conductive pads formed in the internal connection structure 102 may be exposed. Other conductive features, such as those in the redistribution layer, may later be formed to connect the exposed conductive pads.

[0072] Subsequently, according to some embodiments, the mask element 114 is removed to expose the upper surface 109T of the magnetic element 109, such as... Figure 1G As shown. Figure 1G As shown, the sidewall surface 109S of the magnetic element 109 has a stepped profile.

[0073] Figures 3A to 3D A schematic planar layout of a semiconductor device structure manufacturing method at different manufacturing stages according to some embodiments is shown. In some embodiments, Figure 3A for Figure 1G The diagram shows a top view of the structure. In some embodiments, Figure 1G The structure shown is along Figure 3A Middle II line.

[0074] In some embodiments, the magnetic element 109 has multiple sublayers, such as magnetic layers 108a-108e. In some embodiments, each sublayer is larger than the other sublayer above it, such as... Figure 1G and Figure 3A As shown. For example, magnetic layer 108a is larger than magnetic layer 108b. Similarly, magnetic layer 108d is larger than magnetic layer 108e.

[0075] like Figure 1HAs shown, according to some embodiments, an isolation layer 116 is deposited on the internal connection structure 102, the adhesive layer 103, and the magnetic element 109. The isolation layer 116 may be made of silicon nitride, silicon oxide, silicon oxynitride, one or more other suitable dielectric materials, or combinations thereof. The isolation layer 116 may be deposited using CVD, ALD, PVD, one or more other suitable processes, or combinations thereof.

[0076] In some embodiments, the adhesion between the material of the isolation layer 116 and the adhesive layer 103 is greater than the adhesion between the material of the isolation layer 116 and the inner connection structure 102. In some embodiments, the isolation layer 116 is in direct contact with the adhesive layer 103.

[0077] In some other cases where the adhesive layer 103 is not formed, delamination may occur between the isolation layer 116 and the internal connection structure 102, and at locations near the magnetic element 109. Alternatively, a conductive pad formed within the internal connection structure 102 may be damaged due to the high stress on the isolation layer 116. For example, the isolation layer 116 may shrink, causing delamination between the isolation layer 116 and the polyimide layer of the internal connection structure 102. The isolation layer 116 may also be damaged.

[0078] Subsequently, according to some embodiments, a mask element 117 is formed on the isolation layer 116, such as... Figure 1H As shown. Mask element 117 is used to assist in the subsequent patterning process of isolation layer 116. The material and forming method of mask element 117 may be the same as or similar to the material and forming method of mask element 114.

[0079] Figures 2A to 2E A cross-sectional schematic diagram of a semiconductor device structure manufacturing method at different manufacturing stages according to some embodiments is shown. Figure 2A It can be shown along Figure 1H Another cross-sectional view of the structure shown in section 2A. In some embodiments, mask element 117 extends beyond magnetic element 109, as... Figure 2A As shown.

[0080] like Figure 1I As shown, according to some embodiments, the isolation layer 116 is partially removed. The mask element 117 can serve as an etching mask, and an etching process is used to remove the isolation layer 116 not covered by the mask element 117. In this way, the remaining portion of the isolation layer 116 forms the isolation element 116', as... Figure 1I As shown. After locally removing the isolation layer 116, the adhesive layer 103 is locally exposed, as shown. Figure 1I As shown.

[0081] like Figure 1J and Figure 2BAs shown, mask element 117 is removed according to some embodiments. In some embodiments, Figure 3B for Figure 1J and Figure 2B The diagram shows a plan layout of the structure. In some embodiments, Figure 1J The structure shown is along Figure 3B Line II in some embodiments. Figure 2B The structure shown is along Figure 3B The JJ line in the middle.

[0082] In some embodiments, each isolation element 116' extends across the magnetic element 109. In some embodiments, each isolation element 116' partially covers the upper surface 109T of the magnetic element 109. The upper surface 109T is not covered by the isolation element 116', as... Figure 1J and Figure 3B As shown. In some embodiments, each isolation element 116' partially covers the sidewall surface 109S of the magnetic element 109. A portion of the sidewall surface 109S is not covered by the isolation element 116'.

[0083] like Figure 1K and Figure 2C As shown, according to some embodiments, the adhesive layer 103 is partially removed. In some embodiments, Figure 3C for Figure 1K and Figure 2C The figure shows a plan layout of the structure. In some embodiments, Figure 1K The structure shown is along Figure 3C Line II in some embodiments. Figure 2C The structure shown is along Figure 3C The JJ line in the middle.

[0084] An etching process can be used to locally remove the adhesive layer 103. Removing the exposed portion of the adhesive layer 103 exposes a portion of the internal connection structure 102 originally covered by the adhesive layer 103, such as... Figure 1K , Figure 2B and Figure 3C As shown. In some embodiments, the adhesive layer 103 near the exposed portion is also removed. The remaining portion of the adhesive layer 103 forms an adhesive element 103'. In some embodiments, because the adhesive layer 103 is partially removed, electrical contact between the resulting adhesive element 103' and the subsequently formed wire is prevented. Therefore, a short circuit between the adhesive element 103' and the subsequently formed wire can be avoided.

[0085] In some embodiments, after the isolation layer 116 (or isolation element 116') is formed, the adhesive layer 103 is partially removed to form the adhesive element 103'. The adhesive layer 103 intersects with the isolation layer 116 and the internal connection structure 102. This prevents the high-stress isolation layer 116 (or isolation element 116') from directly contacting the polymer layer (e.g., a polyimide layer). Therefore, it prevents the internal connection structure 102 from being damaged due to the high stress of the isolation layer 116 (or isolation element 116').

[0086] In some other cases, the adhesive layer 103 is partially removed to form the adhesive element before the isolation layer 116 (or isolation element 116') is formed. A portion of the isolation layer 116 (or isolation element 116') with high stress may come into direct contact with the internal connection structure 102. This could damage the internal connection structure 102. For example, cracks or voids may form in the polymer layer (e.g., the polyimide layer) and / or the conductive pads of the internal connection structure 102.

[0087] In some embodiments, the adhesive element 103' directly contacts the insulating element 116' and the inner connection structure 102. The adhesive element 103' improves the adhesion between the insulating element 116' and the inner connection structure 102. In some embodiments, in other cases where the adhesive element 103' is not formed, delamination may occur between the insulating element 116' and the inner connection structure 102. Due to the high stress of the insulating element 116', cracks may form within the polymer (e.g., polyimide) layer of the inner connection structure 102.

[0088] In some embodiments, the edge E2 of the adhesive element 103' is laterally disposed between the edge E3 of the magnetic element 109 and the edge E1 of the insulating element 116', such as Figure 2C As shown. In some embodiments, the edge E4 of the adhesive element 103' is located below the magnetic element 109, as... Figure 1K As shown.

[0089] like Figure 2C As shown, the edge E2 of the adhesive element 103' is laterally separated from the edge E1 of the insulating element 116' by a distance D2. The edge E2 of the adhesive element 103' is laterally separated from the edge E3 of the magnetic element 109 by a distance D3. The distance D2 can be approximately... to Within a certain range. In some embodiments, distance D3 is less than distance D1. In these cases, distance D3 can be approximately... to Within a certain range. In some other embodiments, distance D3 is greater than distance D1. In these cases, distance D3 can be approximately... to within the range.

[0090] In some cases, if the distance D2 is less than approximately Then the adhesive element 103' will make electrical contact with the subsequently formed wire. This will cause a short circuit between the adhesive element 103' and the wire. In some other cases, if the distance D2 is greater than approximately... This may prevent the isolation element 116' from being adequately supported. As a result, the isolation element 116' may be damaged.

[0091] like Figure 1L , Figure 2D and Figure 3D As shown, according to some embodiments, wires 118A and 118B are formed above the insulating element 116'. The insulating element 116' physically separates the magnetic element 109 from the wires 118A and 118B. In some embodiments, wire 118A extends along the extending direction of the insulating element 116' below it. Similarly, wire 118B also extends along the extending direction of the insulating element 116' below it.

[0092] In some embodiments, wires 118A and 118B are electrically connected to each other. In some embodiments, wires 118A and 118B are electrically connected to other wires formed above and below the magnetic element 109. These wires together surround the magnetic element 109. These wires and the magnetic element 109 can together serve as an inductor.

[0093] Conductors 118A and 118B may be made of copper, aluminum, gold, cobalt, platinum, one or more other suitable materials, or combinations thereof. In some embodiments, conductors 118A and 118B are formed using an electroplating process. A seed layer is first deposited, and then a mask element is formed on the seed layer. In some embodiments, the seed layer is separated from the adhesive element 103' by vias S.

[0094] The openings in the mask element define the location and contour of the conductors. Then, one or more conductive materials are electroplated onto the exposed portion of the seed layer. The mask element is then removed, and the seed layer initially covered by the mask element is removed using an etching process. This forms conductors 118A and 118B. Figure 2D As shown, the wire 118A is separated from the adhesive element 103' through the hole S. In some embodiments, the insulating element 116', the adhesive element 103', and the wire 118A together surround the hole S.

[0095] Many variations and / or modifications can be made to the embodiments described herein. In some other embodiments, a metal layer is deposited using a PVD process, a CVD process, one or more other suitable processes, or a combination thereof. Subsequently, the metal layer is patterned into conductors 118A and 118B using lithography and etching processes.

[0096] In some embodiments, each isolation element 116' is wider than the wires 118A or 118B formed thereon, such as Figure 1L and Figure 3D As shown. Therefore, even if an overlay shift occurs during the formation of conductors 118A and 118B, the isolation element 116', which is wider than conductors 118A or 118B, can still separate the magnetic element 109 from conductors 118A and 118B. Therefore, the magnetic element 109 can still provide the required function.

[0097] In some embodiments, the aspect ratio of wire 118A or 118B to insulating element 116' is in the range of about 0.5 to 0.9. In some cases, if the aspect ratio is less than about 0.5, the resistance of wire 118A or 118B will be high. The performance of magnetic element 109 will be negatively affected. In some other cases, if the aspect ratio is greater than about 0.9, the risk of electrical short circuit between wire 118A or 118B and magnetic element 109 is high. Once wire 118A or 118B comes into contact with magnetic element 109, magnetic element 109 cannot provide the required function.

[0098] like Figure 3D As shown, the first edge of conductor 118A is laterally separated from the first edge of isolation element 116' by a distance d1. The second edge of conductor 118A is laterally separated from the second edge of isolation element 116' located below conductor 118A by a distance d2. In some embodiments, distance d1 is the same as distance d2. In some other embodiments, distance d1 and distance d2 are different from each other. Distance d1 or d2 may be in the range of approximately 2 μm to 4 μm.

[0099] In some embodiments, the conductor 118A (or 118B) and the insulating element 116' further extend onto the inner connection structure 102 and are not covered by the magnetic element 109, such as... Figure 3D As shown. Due to the adhesive element 103', the inner connection structure 102 is protected from damage caused by high stress from the isolation element 116'. As... Figure 3D As shown, one end of the wire 118A (or 118B) is laterally separated from the edge of the magnetic element 109 by a distance L. In some embodiments, the distance L is in the range of about 4 μm to about 6 μm.

[0100] In some cases, if the distance L is less than about 4 μm, the performance and quality of the magnetic element 109 may be negatively affected. For example, if a shift occurs during the formation of the conductor 118A (or 118B), the sidewall surface of the insulating element 109 may not be covered by the conductor 118A (or 118B). That is, the conductor 118A (or 118B) does not extend beyond the magnetic element 109, which may lead to a decrease in the efficiency of the magnetic element 109. In other cases, if the distance L is greater than about 6 μm, the stress between the conductor 118A (or 118B) and the subsequently formed dielectric layer will increase. Therefore, there is a risk that the conductor 118A (or 118B) may be damaged or destroyed.

[0101] like Figure 1M and Figure 2E As shown, according to some embodiments, a dielectric layer 120 is formed on the conductors 118A and 118B, the isolation element 116', and the magnetic element 109. In some embodiments, the dielectric layer 120 is deposited directly on the conductors 118A and 118B, the isolation element 116', and the magnetic element 109. In some embodiments, the dielectric layer 120 directly contacts the isolation element 116', the conductors 118A and 118B, and the magnetic element 109.

[0102] In some embodiments, the dielectric layer 120 is made of or comprises a polymeric material. The polymeric material may include PBO, epoxy resin, polyimide, one or more other suitable materials, or combinations thereof. The dielectric layer 120 may be formed using spin coating, spray coating, injection molding, molding, one or more other suitable processes, or combinations thereof.

[0103] In some embodiments, the formation of the dielectric layer 120 involves thermal processing steps. For example, a polymer-containing material is cured at a high temperature to form the dielectric layer 120. Therefore, high thermal stress may be generated during the formation of the dielectric layer 120. Figure 3D As shown, according to some embodiments, the exposed portion of the isolation element 116' is minimized. The contact area between the isolation element 116' and the dielectric layer 120 is small. This reduces the thermal stress applied to the isolation element 116'.

[0104] The adhesive element 103' also helps to secure the insulating element 116' and the internal connection structure 102. Therefore, it prevents the insulating element 116' and its wires 118A (or 118B) from being damaged or destroyed due to thermal stress from the dielectric layer 120. Figure 1M The quality and reliability of the semiconductor device structure shown can be significantly improved.

[0105] Subsequently, multiple material layers and device components can be formed on the dielectric layer 120. Then, a dicing process can be performed to divide the above structure into multiple separate semiconductor chips or chip packages.

[0106] Many variations and / or modifications may be made to the embodiments described herein. Figure 4 A schematic cross-sectional view of a semiconductor device structure is shown according to some embodiments. In some embodiments, the isolation element 116' extends compliantly along the sidewall surface of the magnetic element 109. In these cases, both the magnetic element 109 and the isolation element 116' have a stepped profile, such as... Figure 4 As shown.

[0107] Figure 5 A schematic cross-sectional view of a semiconductor device structure according to some embodiments is shown. In some embodiments, Figure 5 Show Figure 1F The diagram shows a partially enlarged cross-sectional view of the structure. In some embodiments, after an etching process to remove the hollow structure 112, a portion of the upper surface of the topmost magnetic layer 108e is recessed. (See diagram below.) Figure 5 As shown, the magnetic layer 108e has a first portion 500A covered by the mask element 114 and a second portion 500B not covered by the mask element 114. After an etching process, the second portion 500B is recessed to a lower height level than the first portion 500A. In some embodiments, a recess 502 is formed. The recess 502 surrounds the first portion 500A.

[0108] Figure 6 A schematic planar layout of a semiconductor device structure is shown according to some embodiments. In some embodiments, the recess 502 is formed by an etching process for removing the hollow structure 112. Figure 6 As shown, the recess 502 has an edge 501 that defines the first portion 500A. As... Figure 6 As shown, the recess 502 has a width d3. In some embodiments, the width d3 is in the range of approximately 5 μm to 10 μm.

[0109] In some cases, if the width d3 is less than about 5 μm, the etching process used to remove the hollow structure 112 may be negatively affected. If a stacking misalignment occurs during the formation of the mask element 114, some of the hollow structure 112 may be covered by the mask element 114. As a result, the hollow structure 112 may not be completely removed, leading to a decrease in the performance of the semiconductor device structure.

[0110] The above embodiments form an adhesive layer between the magnetic element and the interconnect structure. A patterned isolation element and its conductive lines extend across and partially cover the magnetic element. A dielectric layer is then formed on the magnetic element, the patterned isolation element, and the conductive lines. Because the contact area between the patterned isolation element and the dielectric layer is limited, the stress between the dielectric layer and the patterned isolation element is reduced. The adhesive layer prevents direct contact between the interconnect structure and the patterned isolation element, and prevents damage due to the high stress on the patterned isolation element. Damage to components within the interconnect structure (e.g., polymer layers and / or conductive pads) is prevented. The quality and reliability of the semiconductor device structure can be significantly improved.

[0111] According to some embodiments, a method for manufacturing a semiconductor device structure is provided. The method includes forming an adhesive layer on a semiconductor substrate and forming a magnetic element on the adhesive layer. The method further includes forming an isolation element extending across the magnetic element. The isolation element partially covers the upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. Additionally, the method includes forming a conductive line on the isolation element.

[0112] In some embodiments, the adhesive layer comprises titanium, aluminum, copper, or a combination thereof. In some embodiments, the adhesive layer comprises an outer portion and an inner portion surrounded by the outer portion, and the method further comprises removing the outer portion of the adhesive layer before forming the magnetic element. In some embodiments of the method, the semiconductor substrate is a semiconductor wafer, the adhesive layer has an end portion after the outer portion is removed, and the end portion of the adhesive layer is laterally spaced from the edge of the semiconductor substrate by a distance. In some embodiments of the method, the distance is in the range of about 1000 μm to about 2000 μm. In some embodiments, forming the magnetic element comprises forming a plurality of magnetic layers on the adhesive layer; forming a patterned mask layer on the magnetic layers; and etching the magnetic layers to partially remove the magnetic layers, wherein the remaining portion of the magnetic layers forms the magnetic element. In some embodiments of the method, the method further comprises forming a protective layer and an etch stop layer on the semiconductor substrate before forming the magnetic layers and after forming the adhesive layer. In some embodiments of the method, the etch stop layer and the protective layer are made of different materials. In some embodiments, the method further comprises forming a dielectric layer on the conductor, the isolation element, and the magnetic element. In some embodiments of the above method, the dielectric layer is formed directly on the magnetic element.

[0113] According to some embodiments, a method for manufacturing a semiconductor device structure is provided. The method includes: forming a metal layer on a semiconductor substrate. The method also includes forming a magnetic element on the metal layer. The method further includes directly forming an isolation element on the magnetic element and the metal layer. Additionally, the method includes forming a conductive line on the isolation element.

[0114] In some embodiments, the method further includes partially removing the metal layer such that one edge of the metal layer is located below the insulating element. In some embodiments, the method further includes partially removing the metal layer such that one edge of the metal layer is laterally disposed between one edge of the magnetic element and one edge of the insulating element. In some embodiments, the method further includes removing the exterior of the metal layer before forming the magnetic element. In some embodiments, the metal layer is made of titanium, aluminum, copper, or a combination thereof.

[0115] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element located on the semiconductor substrate. The semiconductor device structure also includes an adhesive element located between the magnetic element and the semiconductor substrate. The semiconductor device structure further includes an isolation element extending across the magnetic element, wherein the isolation element partially covers the upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element. An edge of the adhesive element is laterally disposed between an edge of the magnetic element and an edge of the isolation element. Additionally, the semiconductor device structure includes a conductive wire located on the isolation element.

[0116] In some embodiments, the adhesive element comprises titanium, aluminum, copper, or a combination thereof. In some embodiments, the semiconductor device structure further includes a protective layer and an etch stop layer located between the magnetic element and the adhesive element, wherein the etch stop layer and the protective layer are made of different materials. In some embodiments, the magnetic element comprises a plurality of sublayers, each sublayer being larger than the next sublayer thereon. In some embodiments, the insulating element, the adhesive layer, and the conductive wires together surround a hole.

[0117] The foregoing summary outlines the features of several embodiments of the present invention, enabling those skilled in the art to more readily understand the nature of this disclosure. Anyone skilled in the art will understand that this disclosure can be readily used as a basis for modifications or designs to other processes or structures to achieve the same objectives and / or obtain the same advantages as the embodiments described herein. It will also be understood by anyone skilled in the art that equivalent structures described above do not depart from the concept and scope of this disclosure, and that variations, substitutions, and modifications can be made without departing from the concept and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device structure, comprising: forming an adhesive layer on a semiconductor substrate; forming a magnetic element on the adhesive layer; forming an isolation element extending across the magnetic element, wherein the isolation element partially covers the upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element; Partially removing the adhesive layer so that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element; and A conductive line is formed on the isolation element. 2 . The method for manufacturing a semiconductor device structure as claimed in claim 1 , wherein the adhesion layer comprises titanium, aluminum, copper or a combination thereof.

3. The method for manufacturing a semiconductor device structure according to claim 1, wherein the adhesive layer comprises an outer portion and an inner portion surrounded by the outer portion, and the method further comprises: This outer portion of the adhesive layer is removed prior to forming the magnetic element. 4 . The method for manufacturing a semiconductor device structure as claimed in claim 3 , wherein the semiconductor substrate is a semiconductor wafer, the adhesive layer has an end portion after the outer portion is removed, and the end portion of the adhesive layer is laterally spaced a distance from an edge of the semiconductor substrate. 5 . The method for fabricating a semiconductor device structure as claimed in claim 4 , wherein the distance is approximately in the range of 1000 μm to approximately 2000 μm.

6. The method for manufacturing a semiconductor device structure as claimed in claim 1, wherein forming the magnetic element comprises: forming a plurality of magnetic layers on the adhesive layer; forming a patterned mask layer on the magnetic layer; as well as The magnetic layer is wet-etched to partially remove the magnetic layer, wherein the remaining portion of the magnetic layer forms the magnetic element. 7 . The method for manufacturing a semiconductor device structure as claimed in claim 6 , further comprising forming a protection layer and an etch stop layer on the semiconductor substrate before forming the magnetic layer and after forming the adhesion layer. 8 . The method for manufacturing a semiconductor device structure as claimed in claim 7 , wherein the etching stop layer and the protection layer are made of different materials. 9 . The method for manufacturing a semiconductor device structure as claimed in claim 1 , further comprising forming a dielectric layer on the conductive line, the isolation element and the magnetic element. 10 . The method for manufacturing a semiconductor device structure as claimed in claim 9 , wherein the dielectric layer is directly formed on the magnetic element.

11. A method for manufacturing a semiconductor device structure, comprising: forming a metal layer on a semiconductor substrate; forming a magnetic element on the metal layer; directly forming an isolation element on the magnetic element and the metal layer; Partially removing the metal layer so that an edge of the metal layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element; and A conductive line is formed on the isolation element. 12 . The method for manufacturing a semiconductor device structure as claimed in claim 11 , further comprising partially removing the metal layer so that an edge of the metal layer is located below the isolation element. 13 . The method for manufacturing a semiconductor device structure as claimed in claim 11 , further comprising removing an outer portion of the metal layer before forming the magnetic element. 14 . The method for manufacturing a semiconductor device structure as claimed in claim 11 , wherein the metal layer is made of titanium, aluminum, copper or a combination thereof. 15 . The method for manufacturing a semiconductor device structure as claimed in claim 11 , further comprising forming a dielectric layer on the conductive line, the isolation element, and the magnetic element, wherein the dielectric layer is directly formed on the magnetic element.

16. A semiconductor device structure, comprising: a semiconductor substrate; a magnetic element, located on the semiconductor substrate; an adhesive element located between the magnetic element and the semiconductor substrate; an isolation element extending across the magnetic element, wherein the isolation element partially covers an upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element, and an edge of the adhesive element is laterally disposed between an edge of the magnetic element and an edge of the isolation element; and A conductor is located on the isolation element. 17 . The semiconductor device structure of claim 16 , wherein the adhesive element comprises titanium, aluminum, copper or a combination thereof. 18 . The semiconductor device structure as claimed in claim 16 , further comprising a protection layer and an etch stop layer located between the magnetic element and the adhesive element, wherein the etch stop layer and the protection layer are made of different materials.

19. The semiconductor device structure of claim 16, wherein the magnetic element comprises a plurality of sub-layers, and each sub-layer is larger than another sub-layer located thereon. 20 . The semiconductor device structure as claimed in claim 16 , wherein the isolation element, the adhesive element and the conductive line together surround a hole.

21. A semiconductor device structure, comprising: a semiconductor substrate; a magnetic element disposed on the semiconductor substrate, wherein the magnetic element has a first edge; an adhesive element located between the magnetic element and the semiconductor substrate, wherein the adhesive element has a second edge; an isolation element extending across the magnetic element, wherein the isolation element partially covers an upper surface of the magnetic element and partially covers a plurality of sidewall surfaces of the magnetic element, an edge of the adhesive element is laterally disposed between an edge of the magnetic element and an edge of the isolation element, the adhesive element has a third edge, and the second edge is closer to the third edge than the first edge; and A conductor is located on the isolation element. 22 . The semiconductor device structure of claim 21 , wherein the second edge is laterally located between the first edge and the third edge.

23. The semiconductor device structure of claim 21, wherein the adhesive element extends beyond an interface between the magnetic element and the isolation element.

24. The semiconductor device structure of claim 21, wherein the adhesive element is in direct contact with the isolation element.

25. The semiconductor device structure of claim 21, wherein the adhesive element comprises titanium, aluminum, copper or a combination thereof. 26 . The semiconductor device structure as claimed in claim 21 , further comprising a protection layer and an etch stop layer located between the magnetic element and the adhesive element.

27. The semiconductor device structure of claim 21, wherein the magnetic element comprises a plurality of sub-layers, and each sub-layer is larger than another sub-layer located thereon. 28 . The semiconductor device structure of claim 27 , wherein an uppermost sub-layer among the plurality of sub-layers has a first portion and a second portion, the second portion surrounds the second portion, and the first portion is thicker than the second portion.

29. The semiconductor device structure as claimed in claim 21, wherein the isolation element, the adhesive element and the conductive line together surround a hole.

30. The semiconductor device structure of claim 21, wherein the isolation element is wider than the conductive line.

31. A semiconductor device structure comprising: a semiconductor substrate; a magnetic stack located on the semiconductor substrate; an isolation element extending along an upper surface and a plurality of sidewall surfaces of the magnetic stack, wherein the isolation element partially covers the magnetic stack and extends beyond an edge of the magnetic stack; as well as A conductor is located on the isolation element. 32 . The semiconductor device structure of claim 31 , further comprising an adhesive layer disposed between the magnetic stack and the semiconductor substrate.

33. The semiconductor device structure as claimed in claim 32, wherein the adhesive layer separates the conductive line through a hole.

34. The semiconductor device structure of claim 32, wherein the adhesion layer comprises titanium, aluminum, copper or a combination thereof.

35. The semiconductor device structure of claim 32, wherein the isolation element covers an entire upper surface of the adhesive layer.

36. A semiconductor device structure comprising: a semiconductor substrate; a magnetic stack located on the semiconductor substrate; a spacer element extending across the magnetic stack, wherein the magnetic stack is wider than the spacer element; as well as A conductor is located on the isolation element.

37. The semiconductor device structure as claimed in claim 36, wherein the conductive line partially covers the isolation element. 38 . The semiconductor device structure of claim 36 , further comprising an adhesive layer disposed between the magnetic stack and the semiconductor substrate. 39 . The semiconductor device structure of claim 38 , wherein an edge of the adhesive layer is laterally located between an edge of the magnetic stack and an edge of the isolation element. 40 . The semiconductor device structure of claim 39 , wherein the edge of the adhesive layer is closer to the edge of the isolation element than the edge of the magnetic stack.

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