Switching elements, variable resistance memory devices, and methods for manufacturing switching elements

Abstract

A switching element, a variable resistance memory device, and a method of manufacturing the switching element are provided. The switching element includes: a lower blocking electrode on a substrate, a switching pattern on the lower blocking electrode, and an upper blocking electrode on the switching pattern. The lower blocking electrode includes: a first lower blocking electrode layer and a second lower blocking electrode layer inserted between the first lower blocking electrode layer and the switching pattern, the density of the second lower blocking electrode layer being different from the density of the first lower blocking electrode layer.

Description

[0001] Priority Statement

[0002] This application claims priority to Korean Patent Application No. 10-2018-0105378, filed with the Korean Intellectual Property Office on September 4, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to a variable resistance memory device, a switching element of the variable resistance memory device, and a method of manufacturing the switching element. Background Technology

[0004] Semiconductor memory devices are generally classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted. Volatile memory devices include Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices. Conversely, non-volatile memory devices retain their stored data even when their power supply is interrupted. Non-volatile memory devices include Programmable ROM (PROM), Erasable ROM (EPROM), Electrically EEPROM (EEPROM), and Flash Memory devices.

[0005] In addition, next-generation semiconductor memory devices (e.g., ferroelectric random access memory (FRAM) devices, magnetic random access memory (MRAM) devices, and phase-change random access memory (PRAM) devices) have been developed to provide high-performance and low-power semiconductor memory devices. The materials of these next-generation semiconductor memory devices have a resistance value that varies depending on the current or voltage applied to them, and maintains its resistance value even when the current or voltage is interrupted. Summary of the Invention

[0006] According to one aspect of the present invention, a switching element is provided, comprising: a lower blocking electrode on a substrate, a switching pattern on the lower blocking electrode, and an upper blocking electrode on the switching pattern. The lower blocking electrode comprises: a first lower blocking electrode layer and a second lower blocking electrode layer inserted between the first lower blocking electrode layer and the switching pattern. The density of the second lower blocking electrode layer is different from the density of the first lower blocking electrode layer.

[0007] According to one aspect of the present invention, a variable resistive memory device is also provided, comprising: a first conductor extending longitudinally in a first direction; a second conductor extending longitudinally in a second direction intersecting the first direction when viewed in plan view; a variable resistive structure inserted between the first and second conductors; and a switching element inserted between the variable resistive structure and the second conductor. The switching element includes: a lower blocking electrode, a switching pattern on the lower blocking electrode, and an upper blocking electrode on the switching pattern. The lower blocking electrode includes: a first lower blocking electrode layer and a second lower blocking electrode layer inserted between the first lower blocking electrode layer and the switching pattern. The density of the second lower blocking electrode layer is different from the density of the first lower blocking electrode layer.

[0008] According to one aspect of the present invention, a variable resistive memory device is also provided, comprising: a first wire, a second wire, and a memory cell inserted between and electrically connected to the first and second wires. The memory cell includes: a variable resistor and a switch inserted between the variable resistor and the second wire, the resistivity of the variable resistor depending on temperature. The switch includes: a switch pattern selectively conductively connecting the variable resistor to the second wire, a first lower layer of blocking material inserted between the variable resistor and the switch pattern, and a second lower layer of blocking material inserted between the first lower layer of blocking material and the switch pattern. The density of the blocking material in the second lower layer is different from the density of the blocking material in the first lower layer.

[0009] According to another aspect of the present invention, a method for manufacturing a switching element is provided, comprising: forming a lower barrier layer on a substrate; forming a switching layer on the lower barrier layer; forming an upper barrier layer on the switching layer; and removing a portion of the lower barrier layer, the switching layer, and the upper barrier layer to form a switching element. The formation of the lower barrier layer may include: forming a first lower barrier layer and forming a second lower barrier layer on the first lower barrier layer, wherein the density of the second lower barrier layer is different from the density of the first lower barrier layer. Attached Figure Description

[0010] The inventive concept will become more apparent from the accompanying drawings and detailed description.

[0011] Figure 1 This is a perspective view of an example of a variable resistance memory device conceived according to the present invention.

[0012] Figure 2 yes Figure 1 A circuit diagram of the stacked memory cells of a variable resistance memory device.

[0013] Figure 3 This is a plan view of an example of a variable resistance memory device conceived according to the present invention.

[0014] Figure 4 It is along Figure 3 The image shows a cross-sectional view of an example of a variable resistance memory device according to the present invention, taken by lines I-I' and II-II'.

[0015] Figure 5 It is along Figure 3 A cross-sectional view of another example of a variable resistance memory device according to the present invention, taken by lines I-I' and II-II'.

[0016] Figure 6 It is manufactured according to the concept of the present invention. Figure 3 A flowchart illustrating an example of a method for constructing a variable resistance memory device.

[0017] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 In the context of Figure 3 A cross-sectional view of the variable resistance memory device taken in the directions corresponding to lines I-I' and II-II' during its manufacturing process.

[0018] Figure 16 Therefore Figure 6 The flowchart shows an example of the method used to form the operation of a switching element.

[0019] Figure 17 Is Figure 13 A schematic diagram of a thin-film deposition apparatus used to form the lower and upper barrier layers in the stages of the method shown.

[0020] Figure 18 This is a cross-sectional view of a traditional switching element. Detailed Implementation

[0021] Reference Figure 1 The variable resistance memory device 100 according to the present invention may include a plurality of memory cell arrays (MCAs) sequentially stacked on a substrate W. Each memory cell array (MCA) may include a two-dimensional array of variable resistance memory cells. The variable resistance memory device 100 may also include wires (not shown) disposed between the memory cell arrays for writing data to, reading data from, and / or erasing data from the variable resistance memory cells. Figure 1 The diagram shows a stack of five memory cell arrays (MCAs). However, the invention is not limited thereto.

[0022] Figure 2 yes Figure 1 A circuit diagram of one of the memory cell arrays. Figure 2 The first memory cell array MCA1 is shown as an example. The first memory cell array MCA1 may include memory cells MC disposed at the intersection of the first conductor CL1 and the second conductor CL2 (when viewed in a plan view). Although Figure 2 Not shown, but a second memory cell array may be disposed on the first memory cell array MCA1. Similar to the first memory cell array MCA1, the second memory cell array may include memory cells disposed at the intersection of a third and a fourth conductor. For example, the third conductor is a separate conductor perpendicularly spaced from the second conductor CL2. Alternatively, the second memory cell array may share the second conductor CL2 with the first memory cell array MCA1. In this case, the third conductor corresponds to the second conductor CL2. The memory cells MC of the first memory cell array MCA1 may be arranged two-dimensionally on the substrate W to form rows and columns.

[0023] Figure 3 yes Figure 2 The circuit diagram shows the first wire CL1, the second wire CL2, and the memory cell MC in plan view. Figure 4 It is along Figure 3 Cross-sectional views taken from lines I-I' and II-II'. Figure 2 , Figure 3 and Figure 4 Examples of variable resistance memory devices conceived according to the present invention can be shown together.

[0024] Reference Figure 3 and Figure 4 A first conductive line CL1 may extend on the substrate W in a first direction D1, and a second conductive line CL2 may extend on the substrate W in a second direction D2. The substrate W may contain a single-crystal semiconductor material. For example, the substrate W may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium (SiGe) substrate. The first conductive line CL1 may be a word line, and the second conductive line CL2 may be a bit line. Alternatively, the first conductive line CL1 may be a bit line, and the second conductive line CL2 may be a word line. The first conductive line CL1 and the second conductive line CL2 contain a conductive material such as copper or aluminum. The first conductive line CL1 and the second conductive line CL2 may also contain a conductive metal nitride, such as TiN or WN. The first conductive line CL1 may be disposed in a lower insulating layer 105. The second conductive line CL2 may be disposed in an upper insulating layer 119. The lower insulating layer 105 and the upper insulating layer 119 may each be a silicon oxide layer or a silicon oxynitride layer.

[0025] Memory cells MC are inserted between a first conductor CL1 and a second conductor CL2. In an example of the inventive concept, each memory cell MC includes a variable resistor and a switch, hereinafter referred to as a variable resistor structure CR and a switching element SW, respectively. The variable resistor structure CR can be connected to the first conductor CL1. The variable resistor structure CR has a variable resistance value to store logic data. The switching element SW can be connected to the second conductor CL2. When a threshold voltage (V) higher than that of the switching element SW is applied across the switching element... th When the voltage is specified, the switching element SW can connect the second wire CL2 to the variable resistor structure CR; that is, the switching element SW selectively conducts the variable resistor structure CR to the second wire CL2. The memory cell MC may also include an intermediate electrode ME between the variable resistor structure CR and the switching element SW. The variable resistor structure CR may be disposed between the switching element SW and the substrate W. Alternatively, the switching element SW may be disposed between the variable resistor structure CR and the substrate W. Hereinafter, for ease of explanation and convenience, an example of the variable resistor structure CR being disposed between the first wire CL1 and the switching element SW will be described, but the inventive concept is not limited thereto.

[0026] The variable resistor structure CR can be disposed in the recesses RS formed in the first to third interlayer insulating layers 111, 113, and 115 on the first conductor CL1. The first to third interlayer insulating layers 111, 113, and 115 can be silicon nitride or silicon oxynitride layers, respectively. When viewed in a plan view, multiple recesses RS can be disposed at the intersection of the first conductor CL1 and the second conductor CL2, and can be arranged in two dimensions. Alternatively, the variable resistor structure CR can have a linear shape extending in a first direction D1 or a second direction D2.

[0027] The variable resistance structure CR can be formed of at least one material capable of storing logic data. When the variable resistance memory device 100 is a phase change memory device, the variable resistance structure CR contains a material having a phase transition temperature in which its state changes between a crystalline phase and an amorphous phase.

[0028] For example, the phase transition temperature between the crystalline and amorphous phases of the variable resistance structure CR can be in the range of about 250 degrees Celsius to about 350 degrees Celsius. The variable resistance structure CR can be formed from a compound containing at least one of Te and Se (i.e., chalcogenide elements) and at least one material selected from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. For example, the variable resistance structure CR can contain layers (patterns) of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, or InSbTe. In some examples, the variable resistance structure CR can have a superlattice structure in which layers containing Ge and layers not containing Ge are repeatedly and alternately stacked. For example, the variable resistance structure CR can have a structure in which GeTe layers and SbTe layers are repeatedly and alternately stacked.

[0029] In some examples, the variable resistance structure CR comprises at least one material selected from the perovskite compound group and the conductive metal oxide group. For example, the variable resistance structure CR may comprise layers (patterns) of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr,Ca)MnO3 (PCMO), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, or barium strontium zirconium oxide. When the variable resistance structure CR comprises a transition metal oxide, the dielectric constant of the variable resistance structure CR is greater than that of silicon oxide. In some examples, the variable resistance structure CR has a two-layer structure of a conductive metal oxide layer and a tunnel insulating layer. In some other examples, the variable resistance structure CR has a three-layer structure of a first conductive metal oxide layer, a tunnel insulating layer, and a second conductive metal oxide layer. The tunnel insulating layer may comprise aluminum oxide, hafnium oxide, or silicon oxide.

[0030] A heating electrode HE may be disposed between a first conductor CL1 and a variable resistance structure CR. The heating electrode HE may connect corresponding variable resistance structures CR adjacent to each other in a first direction D1 to the first conductor CL1. For example, the heating electrode HE may include a horizontal portion BP connected to the first conductor CL1 and a pair of vertical portions SP extending from the end of the horizontal portion BP to the variable resistance structure CR. Alternatively, multiple heating electrodes HE may be disposed at the intersection of the first conductor CL1 and the second conductor CL2, and may be arranged in a two-dimensional manner. The heating electrode HE is used to heat the variable resistance structure CR to change the state of the variable resistance structure CR. The heating electrode HE may be formed of a material with a resistivity greater than that of the first conductor CL1. For example, the heating electrode HE may include at least one material layer (pattern) selected from the group consisting of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.

[0031] Spacer pattern 120 may be disposed between heating electrode HE and second interlayer insulating layer 113. Spacer pattern 120 may extend along the horizontal portion BP and vertical portion SP of heating electrode HE. Spacer pattern 120 may be formed of silicon oxide and / or silicon oxynitride.

[0032] The lower portion of the recessed RS may be occupied by a variable resistor structure CR, and the upper portion of the recessed RS may be occupied by an intermediate electrode ME. The intermediate electrode ME electrically connects the variable resistor structure CR and the switching element SW, and prevents the variable resistor structure CR from directly contacting the switching element SW. The intermediate electrode ME may include at least one material layer (pattern) selected from the group consisting of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN. The top surfaces of the first to third interlayer insulating layers 111, 113, and 115 may be substantially coplanar with the top surface of the intermediate electrode ME. Alternatively, the intermediate electrode ME may be disposed on the first to third interlayer insulating layers 111, 113, and 115.

[0033] A switching element SW may be disposed on an intermediate electrode ME. In some examples, the switching element SW includes a bidirectional threshold switch (OTS) element with bidirectional characteristics. The switching element SW may include an element based on a threshold switching phenomenon having a nonlinear IV curve (e.g., an S-shaped IV curve). In some examples, the switching element SW includes a switching pattern 130, a lower blocking electrode 140, an upper blocking electrode 150, and an upper electrode 160.

[0034] A switch pattern 130 may be disposed on the lower blocking electrode 140. The switch pattern 130 may have a phase transition temperature between a crystalline and amorphous phase, said phase transition temperature being higher than the phase transition temperature of the variable resistor structure CR. For example, the phase transition temperature of the switch pattern 130 may be in the range of about 350 degrees Celsius to about 450 degrees Celsius. Therefore, when operating an example of the variable resistor memory device 100 according to the present invention, the state of the variable resistor structure CR may be reversibly changed between a crystalline and amorphous phase by an operating voltage (e.g., a programming voltage), but even when an operating voltage is applied to it, the amorphous state of the switch pattern 130 may be substantially maintained without a phase transition. In this specification, the term "substantially amorphous" means completely amorphous, but also refers to the case where grain boundaries or crystalline portions are locally present in a portion of the described material. The switch pattern 130 may be formed from a compound comprising at least one of Te and Se (i.e., at least one chalcogenide element) and at least one material selected from the group consisting of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. In addition to compounds, the switch pattern 130 may also include a thermally stabilizing element. The thermally stabilizing element may include at least one of C, N, and O. For example, the switch pattern 130 may include layers (patterns) of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsSeGeC, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, AsTeGeSiSeNS, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, or GeAsBiSe.

[0035] A lower blocking electrode 140 may be disposed between the intermediate electrode ME and the switching pattern 130. The lower blocking electrode 140 prevents or minimizes heat transfer between the intermediate electrode ME and the switching pattern 130. The lower blocking electrode 140 is a multilayer structure of electrode layers, which are distinguished by differences in the corresponding densities of the electrode layers, and may also have different resistivities and / or surface roughness. In some examples, the lower blocking electrode 140 includes a first blocking material layer and a second blocking material layer, hereinafter referred to as the first lower blocking electrode 142 (or the first lower blocking electrode layer) and the second lower blocking electrode 144 (or the second lower blocking electrode layer), respectively.

[0036] A first lower blocking electrode 142 may be disposed between the intermediate electrode ME and the switch pattern 130. The first lower blocking electrode 142 can reduce the stress between the intermediate electrode ME and the switch pattern 130 and can increase the adhesive strength between them. In some examples, the first lower blocking electrode 142 is wider than the intermediate electrode ME in a first direction D1 or a second direction D2. The intermediate electrode ME may have a first width WD1, and the first lower blocking electrode 142 may have a second width WD2 greater than the first width WD1. Therefore, the first lower blocking electrode 142 may also be disposed between the switch pattern 130 and a portion of the first to third interlayer insulating layers 111, 113, and 115. The first lower blocking electrode 142 can reduce the stress between the switch pattern 130 and a portion of the first to third interlayer insulating layers 111, 113, and 115 and can increase the adhesive strength between them. For example,

[0037] The first lower blocking electrode 142 has (or includes) a density of less than about 2.0 g / cm³. 3 (For example, the density is approximately 1.73 g / cm³) 3 The low-density carbon film. The first lower blocking electrode 142 may have a resistivity of about 46.5 mΩ·cm and a surface roughness of about 1.0 nm.

[0038] A second lower blocking electrode 144 may be disposed between the first lower blocking electrode 142 and the switch pattern 130. The density of the second lower blocking electrode 144 may be higher than that of the first lower blocking electrode 142. For example, the second lower blocking electrode 144 may have a density greater than about 2.0 g / cm³. 3 (For example, a density of approximately 2.34 g / cm³) 3 High-density carbon film.

[0039] The second lower blocking electrode 144 prevents or minimizes the diffusion of elements contained in the switch pattern 130. Additionally, the second lower blocking electrode 144 prevents or minimizes mixing between the first lower blocking electrode 142 and the switch pattern 130. The resistivity of the second lower blocking electrode 144 may be less than that of the first lower blocking electrode 142. The surface roughness of the second lower blocking electrode 144 may be less than that of the first lower blocking electrode 142. For example, the second lower blocking electrode 144 may have a resistivity of approximately 24.8 mΩ·cm and a surface roughness of approximately 0.4 nm.

[0040] An upper blocking electrode 150 may be disposed on the switch pattern 130. The upper blocking electrode 150 prevents or minimizes heat transfer between the switch pattern 130 and the second conductor CL2. The upper blocking electrode 150 may be a multilayer structure comprising electrode layers that are distinguished from each other by differences in their respective densities and also by differences in their resistivity and / or surface roughness. In some examples, the upper blocking electrode 150 includes a first upper blocking electrode 152 (or a first upper blocking electrode layer) and a second upper blocking electrode 154 (or a second upper upper blocking electrode layer).

[0041] A first upper blocking electrode 152 may be disposed between the switch pattern 130 and the second upper blocking electrode 154. The first upper blocking electrode 152 may have a density of approximately 2.34 g / cm³. 3 The density of the first upper barrier electrode 152 is such that it can be a high-density carbon film. The first upper barrier electrode 152 prevents or minimizes the diffusion of elements contained in the switch pattern 130. The first upper barrier electrode 152 also prevents or minimizes the mixing of the switch pattern 130 and the second upper barrier electrode 154. For example, the first upper barrier electrode 152 may have a resistivity of approximately 24.8 mΩ·cm and a surface roughness of approximately 0.4 nm.

[0042] The second upper blocking electrode 154 may be disposed between the first upper blocking electrode 152 and the upper electrode 160. The density of the second upper blocking electrode 154 may be less than that of the first upper blocking electrode 152. For example, the second upper blocking electrode 154 may have a density of approximately 1.73 g / cm³. 3 Therefore, the second upper barrier electrode 154 can be a low-density carbon film. The second upper barrier electrode 154 can reduce the stress between the first upper barrier electrode 152 and the upper electrode 160, and can increase the adhesion strength between them. The second upper barrier electrode 154 can have a resistivity of about 46.5 mΩ·cm and a surface roughness of about 1.0 nm.

[0043] The upper electrode 160 may be disposed on the second upper blocking electrode 154. The upper electrode 160 may electrically connect the second wire CL2 to the switch pattern 130. The upper electrode 160 may contain at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, and TiO.

[0044] The fourth interlayer insulating layer 117 may fill the space between the upper electrodes 160. The fourth interlayer insulating layer 117 may be disposed between the upper insulating layer 119 and the first to third interlayer insulating layers 111, 113, and 115. The top surface of the fourth interlayer insulating layer 117 may be substantially coplanar with the top surface of the upper electrodes 160. The fourth interlayer insulating layer 117 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. The upper insulating layer 119 and the second conductor CL2 may be disposed on the fourth interlayer insulating layer 117.

[0045] Figure 5 It is along Figure 3 The cross-sectional views taken from lines I-I' and II-II', and with Figure 2 Another example of a variable resistance memory device according to the present invention is shown together. Hereinafter, for the sake of simplicity, components referred to by similar reference numerals as in the above examples will not be described in detail.

[0046] exist Figure 5 In the example shown, there is no upper electrode. The density of the second upper barrier electrode layer 154 may be higher than that of the first upper barrier electrode layer 152. The surface roughness of the second upper barrier electrode layer 154 may be less than that of the first upper barrier electrode layer 152. The first upper barrier electrode layer 152 may be a low-density carbon layer, and the second upper barrier electrode 154 may be a high-density carbon layer.

[0047] Figure 6 It is shown Figure 3 A flowchart of a method for manufacturing a variable resistance memory device 100.

[0048] Reference Figure 6 The method of manufacturing a variable resistance memory device 100 according to the present invention may include forming a first wire CL1 (S100), forming a heating electrode HE (S200), forming a variable resistance structure CR and an intermediate electrode ME (S300), forming a switching element SW (S400), and forming a second wire CL2 (S500).

[0049] Figures 7 to 15 Is Figure 3 A cross-sectional view taken along lines I-I' and II-II' to illustrate the manufacturing process. Figure 3 An example of a method for a variable resistance memory device.

[0050] Reference Figure 6 and Figure 7A first conductive line CL1 is formed on the substrate W (S100). In some examples, the first conductive line CL1 is formed by a deposition process, a photolithography process, and an etching process to form a metal layer. Subsequently, a lower insulating layer 105 is formed between the first conductive lines CL1. In some examples, the first conductive lines CL1 are formed by an damascene method. More specifically, a lower insulating layer 105 with a lower trench can be formed on the substrate W, and then the first conductive line CL1 can be formed in the lower trench by a deposition process to form a covering metal layer for filling the lower trench and a chemical mechanical polishing (CMP) process to planarize the metal layer.

[0051] Reference Figure 6 , Figure 8 and Figure 9 A heating electrode HE is formed on the first conductor CL1 (S200). In some examples, the formation of the heating electrode HE includes forming first to third interlayer insulating layers 111, 113 and 115.

[0052] Reference Figure 8 An example of forming a heating electrode HE on one of the first conductors CL1 will be described. It should also be noted that in the following description, for simplicity, sometimes only the formation of one element or feature may be described, but it will be clear from the accompanying drawings that the method may require forming multiple elements or features at once.

[0053] A first interlayer insulating layer 111 may be formed on the first conductor CL1 and the lower insulating layer 105. The first interlayer insulating layer 111 may be formed of silicon nitride or silicon oxynitride. An upper trench TC may be formed in the first interlayer insulating layer 111. The formation of the upper trench TC may include an anisotropic etching process. The upper trench TC may intersect with the first conductor CL1. Next, an electrode layer 121 and a spacer layer 126 may be sequentially formed on the first interlayer insulating layer 111 having the upper trench TC. The electrode layer 121 and the spacer layer 126 may be formed conformally along the surface defining the upper trench TC. The electrode layer 121 may include a layer of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO. The spacer layer 126 may contain at least one of silicon oxide and silicon oxynitride. A second interlayer insulating layer 113 may be formed on the spacer layer 126 to fill the remaining portion of the upper trench TC. The second interlayer insulating layer 113 may be formed of the same material as the first interlayer insulating layer 111.

[0054] Reference Figure 9The second interlayer insulating layer 113, spacer layer 126, and electrode layer 121 can be planarized until the first interlayer insulating layer 111 is exposed. Subsequently, portions of the first interlayer insulating layer 111, the second interlayer insulating layer 113, the spacer layer 126, and the electrode layer 121 that do not overlap with the first conductor CL1 can be etched to form an opening OP. As a result, a heating electrode HE can be formed from the electrode layer 121, and a spacer pattern 120 can be formed from the spacer layer 126.

[0055] Multiple heating electrodes HE can be formed, and the multiple heating electrodes HE can be spaced apart from each other in a first direction D1 and a second direction D2. Subsequently, a third interlayer insulating layer 115 can be formed to fill the opening OP. The third interlayer insulating layer 115 can be formed of the same material as the first interlayer insulating layer 111. The formation of the third interlayer insulating layer 115 may include a deposition process for forming a dielectric and a CMP process.

[0056] Reference Figure 6 and Figures 10 to 12 A variable resistance structure CR and an intermediate electrode ME (S300) can be formed on the heating electrode HE. In some examples, the variable resistance structure CR and the intermediate electrode ME can be formed by the Damascus method.

[0057] Reference Figure 10 A recess RS can be formed to expose the heating electrode HE. The formation of the recess RS may include a process of etching the upper portion of the spacer pattern 120 and a process of etching the upper portion of the heating electrode HE. The respective processes of etching the spacer pattern 120 and the heating electrode HE can be wet etching processes. Subsequently, an isotropic wet etching process can be performed to expand the space formed by etching the upper portion of the heating electrode HE and the upper portion of the spacer pattern 120. For example, an etchant containing phosphoric acid can be used to perform the isotropic wet etching process.

[0058] Reference Figure 11 A variable resistance structure CR is formed in the recessed RS. In some examples, a variable resistance layer is formed to fill the recessed RS, and then the top of the variable resistance layer is etched to form the variable resistance structure CR. The variable resistance layer can be a layer of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, or InSbTe. The variable resistance layer can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0059] Reference Figure 12An intermediate electrode ME is formed in the upper part of the recessed RS. The intermediate electrode ME may be formed from at least one material layer selected from the group consisting of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN. In some examples, an electrode layer is formed on the resulting structure having a variable resistance structure CR, and then the electrode layer is planarized to form the intermediate electrode ME. Alternatively, the process of forming the intermediate electrode ME may be omitted.

[0060] Reference Figure 6 , Figure 13 and Figure 14 A switching element SW (S400) is formed on the resulting structure (e.g., a structure with an intermediate electrode ME). The switching element SW can be formed by thin-layer deposition, photolithography, and etching processes.

[0061] Figure 16 It is shown that Figure 6 The flowchart illustrates an example of how the switching element SW is used to form the operation of the S400.

[0062] Reference Figure 16 An example of operation S400 for forming the switching element SW includes: forming a lower barrier layer 141 (S410), depositing a switching layer 132 (S420), forming an upper barrier layer 151 (S430), depositing an upper electrode layer 162 (S440), and etching a portion of the lower barrier layer 141, the switching layer 132, the upper barrier layer 151, and the upper electrode layer 162 (S450).

[0063] Figure 17 Showing the formation Figure 13 Thin-layer deposition apparatus 1000 for a lower barrier layer 141 and an upper barrier layer 151.

[0064] Reference Figure 17The thin-layer deposition apparatus 1000 is a sputtering apparatus. For example, the thin-layer deposition apparatus 1000 may include a chamber 1, a heater chuck 2, a target 3, a magnetron 4, a first power supply unit 6, a second power supply unit 7, and a gas supply unit 8. The gas supply unit 8 supplies process gas to the chamber 1. The process gas may include argon (Ar), nitrogen (N2), or krypton (Kr). The heater chuck 2 may be disposed in the lower part of the chamber 1, and the magnetron 4 may be disposed in the upper part of the chamber 1. The substrate W may be disposed on the heater chuck 2. The target 3 may be fixed to the bottom surface of the magnetron 4. The target 3 may include a carbon target, a compound target, or a metal target. The compound target may include a compound comprising at least one of Te and Se (i.e., one or more chalcogenide elements) and at least one material selected from the group consisting of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. The metal target may comprise titanium or titanium nitride. A first power supply unit 6 provides a first radio frequency (RF) power 5 (e.g., source power) to the magnetron 4. The first RF power 5 excites the process gas to induce plasma in the chamber 1. The first RF power 5 accelerates the plasma toward the target 3 to generate target particles. The target particles can be deposited as a thin layer on the substrate W. A second power supply unit 7 provides a second RF power 9 (e.g., bias power) to the heater chuck 2. The second RF power 9 accelerates the target particles and plasma toward the substrate W to increase the density of the thin layer.

[0065] Reference Figure 13 , Figure 16 and Figure 17 The thin-layer deposition apparatus 1000 can use a target 3 (which is a carbon target) to form a lower barrier layer 141 (S410). The lower barrier layer 141 can be formed by sputtering. In some examples, the lower barrier layer 141 is formed by forming a first lower barrier layer 143 (S412) and a second lower barrier layer 145 (S414).

[0066] For example, the first power supply unit 6 can supply first radio frequency power 5 to the magnetron 4 to form a first lower barrier layer 143 on the substrate W (S412). The heater chuck 2 can heat the substrate W to a high temperature of approximately 350 degrees Celsius. The gas supply unit 8 can supply argon gas as a process gas above the substrate W. The first lower barrier layer 143 may include low-density carbon.

[0067] Next, the first power supply unit 6 and the second power supply unit 7 supply first RF power 5 and second RF power 9 to the magnetron 4 and heater chuck 2, respectively, to form a second lower barrier layer 145 on the substrate W (S414). The heater chuck 2 can heat the substrate W to a low temperature of approximately 150 degrees Celsius. The gas supply unit 8 can provide nitrogen or krypton as a process gas above the substrate W. The second lower barrier layer 145 is formed on the first lower barrier layer 143. The second lower barrier layer 145 may include high-density carbon. In this example, the second lower barrier layer 145 includes high-density carbon doped with nitrogen (N).

[0068] Next, the switching layer 132 (S420) can be formed by sputtering. The switching layer 132 can be formed from a compound containing at least one of Te or Se (i.e., one or more chalcogenide elements) and at least one material selected from the group consisting of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. In addition to the compound, the switching layer 132 may also contain a thermally stabilizing element. The thermally stabilizing element may include at least one of C, N, or O. For example, the switch layer 132 can be a layer (pattern) of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsSeGeC, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, AsTeGeSiSeNS, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, or GeAsBiSe.

[0069] Subsequently, the thin-layer deposition apparatus 1000 may use a target 3 (which is a carbon target) to form an upper barrier layer 151 (S430). The upper barrier layer 151 may be formed by a sputtering method. In some examples, the upper barrier layer 151 is formed by forming a first upper barrier layer 153 (S432) and a second upper barrier layer 155 (S434).

[0070] Reference Figure 13 , Figure 16 and Figure 17The first power supply unit 6 and the second power supply unit 7 can supply first radio frequency power 5 and second radio frequency power 9 to the magnetron 4 and the heater chuck 2, respectively, to form a first upper barrier layer 153 on the substrate W (S432). The heater chuck 2 can heat the substrate W to a low temperature of approximately 150 degrees Celsius. The gas supply unit 8 can provide nitrogen or krypton as a process gas above the substrate W. The first upper barrier layer 153 may include high-density carbon. In this example, the first upper barrier layer 153 includes high-density carbon doped with nitrogen (N).

[0071] Next, the first power supply unit 6 supplies first radio frequency power 5 to the magnetron 4 to form a second upper barrier layer 155 on the substrate W (S434). The heater chuck 2 can heat the substrate W to a high temperature of approximately 350 degrees Celsius. The gas supply unit 8 can supply argon gas as a process gas above the substrate W. The second upper barrier layer 155 may include low-density carbon.

[0072] Next, the upper electrode layer 162 can be formed by sputtering (S440). The upper electrode layer 162 may contain at least one material selected from the group consisting of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN and TiO.

[0073] Reference Figure 14 and Figure 16 An etching apparatus (not shown) can etch a portion of the lower barrier layer 141, the switching layer 132, the upper barrier layer 151, and the upper electrode layer 162 to form a switching element SW (S450). For example, a portion of the lower barrier layer 141, the switching layer 132, the upper barrier layer 151, and the upper electrode layer 162 can be etched using a reactive ion etching (RIE) method. The switching element SW may include a lower barrier electrode 140, a switching pattern 130, an upper barrier electrode 150, and an upper electrode 160. The upper barrier electrode 150 may include a first upper barrier electrode 152 and a second upper barrier electrode 154, and the first upper barrier electrode 152 and the second upper barrier electrode 154 may be formed from a first upper barrier layer 153 and a second upper barrier layer 155, respectively. The lower barrier electrode 140 may include a first lower barrier electrode 142 and a second lower barrier electrode 144, and the first lower barrier electrode 142 and the second lower barrier electrode 144 may be formed from a first lower barrier layer 143 and a second lower barrier layer 145, respectively. The first lower barrier layer 143 can increase the adhesion strength of the switching element SW to the intermediate electrode ME and / or the first to third interlayer insulating layers 111, 113 and 115. In addition, the first lower barrier layer 143 can prevent or minimize tilting and / or detachment of the switching element SW during the etching process used to form the switching element SW.

[0074] Figure 18An example of a conventional switching element 190 formed using an etching process is shown.

[0075] Reference Figure 18 A typical switching element 190 includes a first blocking electrode 192 and a second blocking electrode 194.

[0076] A first barrier electrode 192 is inserted between the substrate W and the switch pattern 130. The first barrier electrode 192 comprises high-density carbon. The first barrier electrode 192 reduces or weakens the adhesion strength between the substrate W and the switch pattern 130 during the etching process, thus the conventional switch element 190 may tilt and / or detach. The conventional switch element 190 may even be detached from the substrate W.

[0077] A second blocking electrode 194 is inserted between the switch pattern 130 and the upper electrode 160. The second blocking electrode 194 comprises high-density carbon. The second blocking electrode 194 reduces the adhesion strength between the switch pattern 130 and the upper electrode 160 during the etching process, causing the upper electrode 160 to detach. The upper electrode 160 can be separated from the second blocking electrode 194.

[0078] Refer to Figure 14 Compared to the conventional switching elements described above, the upper blocking electrode 150 of the switching element conceived according to the present invention includes a first upper blocking electrode 152 and a second upper blocking electrode 154 formed from a first upper blocking layer 153 and a second upper blocking layer 155, respectively. The second upper blocking electrode 154 provides a high level of adhesion strength between the first upper blocking electrode 152 and the upper electrode 160 during the etching process of forming the first upper blocking layer 153 and the second upper blocking layer 155. Therefore, detachment of the upper electrode 160 can be minimized or prevented. The upper electrode 160 can be formed from the upper electrode layer 162 by an etching process.

[0079] Reference Figure 15 A fourth interlayer insulating layer 117 can be formed between the switching elements SW. The fourth interlayer insulating layer 117 can be formed by a dielectric deposition process and a CMP process performed on the deposited dielectric.

[0080] Refer to Figure 4 and Figure 6 A second conductor CL2 (S500) can be formed on a portion of the fourth interlayer insulating layer 117 and on the switching element SW. The second conductor CL2 can be formed by a deposition process, a photolithography process, and an etching process to form a metal layer.

[0081] Subsequently, an upper insulating layer 119 can be formed between the second conductors CL2. The upper insulating layer 119 can be formed by a dielectric deposition process and a CMP process performed on the deposited dielectric.

[0082] The switching element conceived according to the present invention can minimize or prevent the diffusion of constituent elements by using a blocking electrode. Furthermore, the method of manufacturing the switching element conceived according to the present invention can increase the adhesive strength of the blocking electrode to minimize or prevent tilting and / or detachment of the switching element.

[0083] Although the inventive concept has been described with reference to various examples, it will be apparent to those skilled in the art that various changes and modifications can be made to the examples without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above examples are not restrictive but exemplary. Consequently, the scope of the inventive concept will be determined by the most lenient interpretation of the following claims, and should not be limited or restricted by the foregoing description.

Claims

1. A variable resistance memory device, comprising: A first conductor, which extends longitudinally in a first direction; The second conductor, when viewed in a plan view of the first conductor and the second conductor, extends longitudinally in a second direction that intersects the first direction; A variable resistor structure is inserted between the first wire and the second wire; A heating electrode is inserted between the variable resistor structure and the first wire; as well as A switching element, which is inserted between the variable resistor structure and the second wire, The switching element includes: Lower blocking electrode; The switch pattern on the lower blocking electrode; and The upper blocking electrode on the switch pattern, and The lower blocking electrode includes: The first lower barrier electrode layer; and A second lower blocking electrode layer is inserted between the first lower blocking electrode layer and the switch pattern. Wherein, the first lower barrier electrode layer is a carbon film, and the second lower barrier electrode layer is a carbon film. The density of the first lower barrier electrode layer is less than or equal to 1.73 g / cm³. 3 Furthermore, the density of the second lower barrier electrode layer is greater than or equal to 2.34 g / cm³. 3 ,and The heating electrode is used to heat the variable resistor structure to change its state. The switching pattern has a phase transition temperature between a crystalline and an amorphous phase, and the phase transition temperature of the switching pattern is higher than that of the variable resistor structure. This allows the state of the variable resistor structure to be reversibly changed between a crystalline and an amorphous phase by an operating voltage. However, even when an operating voltage is applied to the switching pattern, the amorphous state of the switching pattern is maintained without a phase transition.

2. The variable resistance memory device according to claim 1, further comprising: An intermediate electrode is inserted between the first lower blocking electrode layer and the variable resistor structure.

3. The variable resistance memory device according to claim 2, wherein, The width of the first lower blocking electrode layer is greater than the width of the intermediate electrode.

4. The variable resistance memory device according to claim 1, wherein, The upper blocking electrode includes: First upper barrier electrode layer; and A second upper blocking electrode layer is inserted between the first upper blocking electrode layer and the second wire, and the density of the second upper blocking electrode layer is different from that of the first upper blocking electrode layer.

5. The variable resistance memory device according to claim 1, wherein, The switching element further includes an upper electrode inserted between the upper blocking electrode and the second wire.

6. A variable resistance memory device, comprising: First conductor; Second conductor; as well as A memory cell, inserted between and electrically connected to the first and second wires, includes a variable resistor, a heating electrode inserted between the variable resistor and the first wire, and a switch inserted between the variable resistor and the second wire. The resistivity of the variable resistor depends on temperature. The switch includes: A switch pattern that selectively connects the variable resistor to the second wire; A first lower layer of blocking material, inserted between the variable resistor and the switch pattern; and A second lower layer of blocking material is inserted between the first lower layer of blocking material and the switch pattern. Wherein, the first lower layer of the switch is a carbon film, and the second lower layer of the switch is a carbon film, and The density of the first lower layer of the blocking material in the switch is less than or equal to 1.73 g / cm³. 3 Furthermore, the density of the second lower layer of the blocking material in the switch is greater than or equal to 2.34 g / cm³. 3 ,and The heating electrode is used to heat the variable resistor to change the state of the variable resistor. The switching pattern has a phase transition temperature between a crystalline phase and an amorphous phase, and the phase transition temperature of the switching pattern is higher than the phase transition temperature of the variable resistor, so that the state of the variable resistor can be reversibly changed between a crystalline phase and an amorphous phase by an operating voltage. However, even if the operating voltage is applied to the switching pattern, the amorphous state of the switching pattern is maintained without phase transition.

7. The variable resistance memory device according to claim 6, wherein, The switch pattern is formed from compounds containing chalcogenide elements.

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