Semiconductor device including contacts and conductive lines intersecting with the sidewalls of the contacts.

Abstract

A semiconductor device is disclosed, comprising: a substrate; a first dielectric layer and a second dielectric layer sequentially stacked on the substrate; a contact extending through the first dielectric layer toward the substrate; and a conductive line disposed in the second dielectric layer and electrically connected to the contact. The conductive line extends in a first direction. The contact includes a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. The width of the conductive line in a second direction decreases with decreasing distance from the substrate. The second direction intersects the first direction. The sidewall of the upper segment of the contact contacts the conductive line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0108392, filed on September 11, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to interconnect structures in semiconductor devices. Background Technology

[0004] Semiconductor devices are widely used in the electronics industry due to their small size, versatility, and / or low manufacturing cost. A semiconductor device can include a memory device for storing data, a logic device for processing data, and a hybrid device for simultaneously operating various functions.

[0005] With the advancements in the electronics industry, semiconductor devices are increasingly being used for high integration. However, manufacturing semiconductor devices is becoming increasingly difficult due to the reduced process margin in exposure processes that define fine patterns. Furthermore, semiconductor devices are increasingly being used for high speeds. Various studies have been conducted to meet the demands for high integration and / or high speed in semiconductor devices. Summary of the Invention

[0006] Embodiments of the present invention can provide a semiconductor device including a contact and a conductive line intersecting with the sidewall of the contact. According to these embodiments, the semiconductor device may include a substrate and a first dielectric layer and a second dielectric layer sequentially stacked on the substrate. The contact may penetrate the first dielectric layer and extend toward the substrate, and the contact may include a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. The conductive line may extend in the second dielectric layer in a first direction and be electrically connected to the contact. The sidewall of the upper segment of the contact contacts the conductive line.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device may include a substrate and a first dielectric layer and a second dielectric layer sequentially stacked on the substrate. A contact may penetrate the first dielectric layer and extend toward the substrate. A conductive line may be disposed in the second dielectric layer and electrically connected to the contact, wherein the conductive line extends in a first direction, wherein the contact may include a lower segment in the first dielectric layer and an upper segment in the second dielectric layer, wherein the width of the upper segment of the contact in a second direction increases with decreasing distance from the substrate, the second direction intersecting the first direction, and wherein the width of the conductive line in the second direction decreases with decreasing distance from the substrate.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device may include a first dielectric layer and a second dielectric layer sequentially stacked on a substrate, and a contact extending through the first dielectric layer toward the substrate. A conductive line may be located in the second dielectric layer and electrically connected to the contact, wherein the conductive line extends in a first direction, and wherein the contact includes a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. The conductive line may include a recess located in the lowermost surface of the conductive line and recessed in a direction away from the substrate, and the upper segment of the contact contacts the recess. Attached Figure Description

[0009] Figure 1A A plan view of a semiconductor device illustrating some example embodiments of a concept according to the present invention is shown.

[0010] Figure 1B It shows along Figure 1A A cross-sectional view taken from line A-A'.

[0011] Figure 1C It shows along Figure 1A The cross-sectional view taken by line B-B'.

[0012] Figure 1D It shows along Figure 1A A cross-sectional view taken from line C-C'.

[0013] Figure 2A , Figure 3A and Figure 4A A plan view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention is shown.

[0014] Figure 2B , Figure 3B and Figure 4B They respectively show along Figure 2A , Figure 3A and Figure 4A A cross-sectional view taken from line A-A'.

[0015] Figure 4C It shows along Figure 4A The cross-sectional view taken by line B-B'.

[0016] Figure 4D It shows along Figure 4A A cross-sectional view taken from line C-C'.

[0017] Figure 5A A plan view of a semiconductor device illustrating some example embodiments of a concept according to the present invention is shown.

[0018] Figure 5B It shows along Figure 5A A cross-sectional view taken from line A-A'.

[0019] Figure 6 Cross-sectional views of semiconductor devices illustrating some example embodiments of the concept according to the present invention are shown. Detailed Implementation

[0020] Figure 1A A plan view of a semiconductor device illustrating some example embodiments of a concept according to the present invention is shown. Figure 1B It shows along Figure 1A A cross-sectional view taken from line A-A'. Figure 1C It shows along Figure 1A The cross-sectional view taken by line B-B'. Figure 1D It shows along Figure 1A A cross-sectional view taken from line C-C'.

[0021] Reference Figure 1A , Figure 1B , Figure 1C and Figure 1D A first dielectric layer 110 and a second dielectric layer 120 may be sequentially disposed on a substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Transistors and / or memory cells may be disposed thereon on the substrate 100. The first dielectric layer 110 may include a silicon oxide layer or a silicon oxynitride layer. The second dielectric layer 120 may include a material that is etch-selective relative to the first dielectric layer 110. For example, the second dielectric layer 120 may include tetraethyl orthosilicate (TEOS).

[0022] Conductive lines ML can be disposed on the first dielectric layer 110. Conductive lines ML can be disposed in the second dielectric layer 120. Each of the conductive lines ML can have a rod shape or a line shape extending in a first direction D1. The first direction D1 can be parallel to the top surface of the substrate 100. The conductive lines ML can be spaced apart from each other in a second direction D2. For example, the conductive lines ML can be arranged in the second direction D2. The second direction D2 can be parallel to the top surface of the substrate 100 and can intersect the first direction D1. The conductive lines ML can comprise copper or aluminum.

[0023] Each of the conductive lines ML may include a first sidewall MLS1 and a second sidewall MLS2. The first sidewall MLS1 may be opposite to the second sidewall MLS2. The first sidewall MLS1 and the second sidewall MLS2 may extend in a first direction D1. Each of the first sidewall MLS1 and the second sidewall MLS2 may have a slope relative to the top surface of the substrate 100. The conductive line ML may have a width in a second direction D2, which may decrease as the distance from the substrate 100 decreases. The conductive line ML may have a minimum width or a first width W1 in the second direction D2. The conductive line ML may have a first width W1 at its bottom. The conductive line ML may have a maximum width or a second width W2 in the second direction D2. The conductive line ML may have a second width W2 at its top. The second width W2 may be greater than the first width W1. The conductive line ML may include a recess RS recessed in a direction away from the substrate 100. The recess RS may be disposed at the lower part of the conductive line ML.

[0024] Substrate 100 may be provided with contacts CT for electrically connecting conductive lines ML to substrate 100. Conductive lines ML can be electrically connected to transistors and / or memory cells on substrate 100 via contacts CT. Contacts CT may penetrate the first dielectric layer 110 and extend in a third direction D3. Contacts CT may extend toward substrate 100. The third direction D3 may be perpendicular to the top surface of substrate 100. Contacts CT may include a conductive material. Contacts CT may include the same or different material as the conductive lines ML. For example, contacts CT may include a metal or doped silicon.

[0025] Each of the contact elements CT may include a lower segment CTL disposed in the first dielectric layer 110 and an upper segment CTU disposed on the lower segment CTL. The upper segment CTU may be disposed in the second dielectric layer 120. When viewed in a planar manner, the lower segment CTL may be surrounded by the first dielectric layer 110. When viewed in a planar manner, the upper segment CTU may be surrounded by the second dielectric layer 120. The upper segment CTU may contact the conductive line ML. The upper segment CTU may fill the recess RS of the conductive line ML. The upper segment CTU may have a width in the second direction D2, which may increase as the distance from the substrate 100 decreases. The lower segment CTL may have a width in the second direction D2, which may decrease as the distance from the substrate 100 decreases. The upper segment CTU may have a minimum width or a third width W3 in the second direction D2. The third width W3 may be less than the first width W1 of the conductive line ML. The upper segment CTU may have a maximum width or a fourth width W4 in the second direction D2. The fourth width W4 may be greater than the first width W1 of the conductive line ML. The fourth width W4 can be smaller than the second width W2 of the conductive line ML.

[0026] The upper section CTU of the contact CT can have a top surface CTUT and a third sidewall CTUS. When viewed from a plane, the top surface CTUT can have a circular shape. When viewed from a plane, the third sidewall CTUS can surround the top surface CTUT. The third sidewall CTUS can be inclined to have a ramp relative to the top surface of the substrate 100. The inclination of the third sidewall CTUS can be opposite to the inclination of the first sidewall MLS1 and the second sidewall MLS2.

[0027] The top surface CTUT can be covered by the conductive line ML. For example, the top surface CTUT can be in contact with the conductive line ML.

[0028] The third sidewall CTUS may include a first portion CTUS1 and a second portion CTUS2. The first portion CTUS1 may be a portion connected to the top surface CTUT of the contact CT. The second portion CTUS2 may be a portion connected to the lower segment CTL of the contact CT. The first portion CTUS1 of the third sidewall CTUS may be covered by a conductive line ML. For example, the first portion CTUS1 of the third sidewall CTUS may be in contact with the conductive line ML. The second portion CTUS2 of the third sidewall CTUS may not be covered by the conductive line ML. For example, the second portion CTUS2 of the third sidewall CTUS may not be in contact with the conductive line ML. The second portion CTUS2 of the third sidewall CTUS may be covered by a second dielectric layer 120. For example, the second portion CTUS2 of the third sidewall CTUS may be in contact with the second dielectric layer 120.

[0029] The third sidewall CTUS of the upper segment CTU of the contact CT can contact the first sidewall MLS1 and the second sidewall MLS2 of the conductive line ML. A first boundary BO1 can be defined as the boundary where the third sidewall CTUS contacts the first sidewall MLS1. A second boundary BO2 can be defined as the boundary where the third sidewall CTUS contacts the second sidewall MLS2. The first sidewall MLS1, the third sidewall CTUS, and the second dielectric layer 120 can contact each other at the first boundary BO1. The second sidewall MLS2, the third sidewall CTUS, and the second dielectric layer 120 can contact each other at the second boundary BO2. When in a plane (see...) Figure 1A When viewed from above, the first boundary BO1 and the second boundary BO2 can be curved. The first boundary BO1 and the second boundary BO2 can divide the third sidewall CTUS into a first part CTUS1 and a second part CTUS2. Therefore, Figure 1B The cross-section of the structure shown can define an hourglass shape at the boundary between the conductive line ML and the contact CT.

[0030] The barrier layer BL can be configured to conformally cover the sidewalls and bottom surface of the lower segment CTL of the contact CT. Each of the barrier layers BL can be interposed between the contact CT and the first dielectric layer 110. The barrier layer BL may include titanium nitride.

[0031] According to some exemplary embodiments of the present invention, because the conductive line ML and the contact CT are in contact with each other at the third sidewall CTUS of the upper CTU, a relatively large contact area can be provided between the conductive line ML and the contact CT. As a result, it may be possible to improve the characteristics of the interface resistance between the conductive line ML and the contact CT.

[0032] Figure 2A , Figure 3A and Figure 4A A plan view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept according to the present invention is shown. Figure 2B , Figure 3B and Figure 4B They respectively show along Figure 2A , Figure 3A and Figure 4A A cross-sectional view taken from line A-A'. Figure 4C It shows along Figure 4A The cross-sectional view taken by line B-B'. Figure 4D It shows along Figure 4A A cross-sectional view taken from line C-C'.

[0033] Reference Figure 2A and Figure 2B A first dielectric layer 110 and a third dielectric layer 130 may be sequentially formed on a substrate 100. The first dielectric layer 110 may include a silicon oxide layer or a silicon oxynitride layer. The third dielectric layer 130 may include a material that is etch-selective relative to the first dielectric layer 110. For example, the third dielectric layer 130 may include tetraethyl orthosilicate (TEOS).

[0034] A barrier layer BL and a contact CT can be formed in the first dielectric layer 110 and the third dielectric layer 130. The contact CT can extend in the third direction D3 and penetrate the first dielectric layer 110 and the third dielectric layer 130. Each of the contact CTs can include a lower segment CTL disposed in the first dielectric layer 110 and an upper segment CTU disposed on the lower segment CTL. The upper segment CTU can be disposed in the third dielectric layer 130. The barrier layer BL can conformally cover the bottom surface and sidewalls of the contact CT.

[0035] The formation of the barrier layer BL and the contact CT may include: patterning the first dielectric layer 110 and the third dielectric layer 130; conformally forming a barrier material layer on the entire surface of the substrate 100; forming a contact material layer on the barrier material layer; and performing a planarization process to partially remove the barrier material layer and the contact material layer. The planarization process may continue until the top surface of the third dielectric layer 130 is exposed. The planarization process may include a chemical mechanical polishing process. The barrier material layer may include titanium nitride. The contact material layer may include a conductive material. For example, the contact material layer may include a metal or doped silicon.

[0036] Reference Figure 3A and Figure 3B A first etching process can be performed to remove the third dielectric layer 130. For example, the first etching process can simultaneously remove the third dielectric layer 130, the barrier layer BL located within the third dielectric layer 130, and a portion of the upper segment CTU of the contact CT. In another example, a first etching process can be performed to remove the third dielectric layer 130, and then a second etching process can be performed to remove an exposed portion of the barrier layer BL and a portion of the exposed portion of the upper segment CTU of the contact CT. The partial removal of the upper segment CTU of the contact CT can define a top surface CTUT and a third sidewall CTUS at the upper segment CTU of the contact CT. The removal of the third dielectric layer 130 can expose the upper segment CTU of the contact CT.

[0037] Reference Figure 4A , Figure 4B , Figure 4C and Figure 4D A second dielectric layer 120 may be formed on the first dielectric layer 110. The second dielectric layer 120 may cover the upper section CTU of the contact CT. The second dielectric layer 120 may include a material that is etch-selective relative to the first dielectric layer 110. For example, the second dielectric layer 120 may include tetraethyl orthosilicate (TEOS).

[0038] The second dielectric layer 120 can be patterned to form trenches TR in the second dielectric layer 120. The trenches TR can extend in a first direction D1. The trenches TR can be spaced apart from each other in a second direction D2. For example, the trenches TR can be arranged in the second direction D2. The trenches TR can have a width in the second direction D2, which can decrease as the distance from the substrate 100 decreases. The trenches TR can have sidewalls, each of which has a slope relative to the top surface of the substrate 100.

[0039] The trench TR can expose the top surface CTUT of the upper section CTU of the contact CT. The third sidewall CTUS of the upper section CTU of the contact CT can have a first portion CTUS1 exposed to the trench TR.

[0040] Return to reference Figure 1A , Figure 1B , Figure 1C and Figure 1D Conductive lines ML can be formed to fill the trench TR. Conductive lines ML can cover the top surface CTUT of the upper section CTU of the contact CT. Conductive lines ML can cover the first part CTUS1 of the third sidewall CTUS of the upper section CTU of the contact CT.

[0041] Forming the conductive line ML may include forming a conductive material layer on the entire surface of the substrate 100 and performing a planarization process to partially remove the conductive material layer. The planarization process may continue until the top surface of the second dielectric layer 120 is exposed. The planarization process may include a chemical mechanical polishing process. The conductive material layer may include copper or aluminum.

[0042] Figure 5A A plan view of a semiconductor device illustrating some example embodiments of a concept according to the present invention is shown. Figure 5B It shows along Figure 5A A cross-sectional view taken from line A-A'. In the following embodiments, references to the above will be omitted. Figure 1A , Figure 1B , Figure 1C and Figure 1D The technical features discussed will be described in detail, and their differences will be discussed in detail.

[0043] Reference Figure 5A and Figure 5B The conductive line ML can completely cover the third sidewall CTUS of the upper section CTU of the contact CT. For example, the third sidewall CTUS may not be in contact with the second dielectric layer 120. The conductive line ML can separate the third sidewall CTUS and the second dielectric layer 120 from each other.

[0044] The conductive line ML can have a minimum width or a fifth width W5 in the second direction D2. The upper segment CTU of the contact CT can have a maximum width or a sixth width W6 in the second direction D2. The fifth width W5 and the sixth width W6 can be substantially the same.

[0045] Figure 6 Cross-sectional views of semiconductor devices illustrating some exemplary embodiments of the concept according to the present invention are shown. In the following embodiments, references to the above will be omitted. Figure 1A , Figure 1B , Figure 1C and Figure 1D The technical features discussed will be described in detail, and their differences will be discussed in detail.

[0046] Reference Figure 6The substrate 100 can be configured to include a first region RG1 and a second region RG2. The first region RG1 can be a memory cell region on which DRAM devices are disposed. The second region RG2 can be a peripheral circuit region or a core region.

[0047] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST can separate the first region RG1 and the second region RG2 from each other. The device isolation layer ST can define a first active portion ACT1 on the first region RG1 of the substrate 100, and can also define a second active portion ACT2 on the second region RG2 of the substrate 100. For example, the device isolation layer ST may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0048] A first gate line GL1 traversing a first active portion ACT1 may be disposed on a first region RG1 of substrate 100. The first gate line GL1 may extend in a first direction D1 and may be arranged along a second direction D2. The first gate line GL1 may be embedded in the first region RG1 of substrate 100. The first gate line GL1 may include a conductive material. For example, the conductive material may include one or more of the following: doped semiconductors (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0049] The first gate dielectric pattern GI1 can be interposed between the first active portion ACT1 and each first gate line GL1. For example, the first gate dielectric pattern GI1 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0050] The first cover pattern CP1 may be disposed on the top surface of each of the first gate lines GL1. For example, the first cover pattern CP1 may include a silicon nitride layer or a silicon oxynitride layer.

[0051] The first active portion ACT1 may contain a first impurity region SD1 and a pair of second impurity regions SD2. The pair of second impurity regions SD2 may be spaced apart from each other on both sides of the first impurity region SD1 in the second direction D2.

[0052] A first impurity region SD1 may be disposed in a first active portion ACT1 between a pair of adjacent first gate lines GL1. A second impurity region SD2 may be disposed in the first active portion ACT1 located on opposite sides of a pair of adjacent first gate lines GL1. The second impurity region SD2 may be spaced apart from each other on both sides of a pair of adjacent first gate lines GL1 in a second direction D2. The first impurity region SD1 may have a conductivity type substantially the same as that of the second impurity region SD2.

[0053] A first dielectric layer 110 covering the first active portion ACT1 may be disposed on a first region RG1 of substrate 100. The first dielectric layer 110 may include a silicon oxide layer or a silicon oxynitride layer.

[0054] Bit line BT can be disposed in the first dielectric layer 110. Bit line BT can extend in the first direction D1. Bit line BT can be electrically connected to the first impurity region SD1. For example, bit line BT can include one of a doped semiconductor, a conductive metal nitride, a metal, and a metal-semiconductor compound. Second cap pattern CP2 can be disposed on bit line BT. For example, second cap pattern CP2 can include a silicon nitride layer or a silicon oxynitride layer.

[0055] The first dielectric layer 110 may have a first contact CT1 and a landing pad LP disposed therein. The landing pad LP may be disposed on the corresponding first contact CT1. The first contact CT1 may be electrically connected to the corresponding second impurity region SD2. The first contact CT1 and the landing pad LP may include a conductive material such as metal or doped silicon.

[0056] A capacitor CAP can be disposed on the first dielectric layer 110. The capacitor CAP may include a first electrode LEL1, a second electrode LEL2, and a dielectric layer DIL located between the second electrode LEL2 and the first electrode LEL1. The first electrode LEL1 can be disposed on a corresponding landing pad LP. Each of the first electrodes LEL1 is electrically connected to the second impurity region SD2 via the landing pad LP and the first contact CT1.

[0057] Each of the first electrodes LEL1 may have a cylindrical (or cup-shaped) shape comprising a base plate segment and a sidewall segment extending vertically from the base plate segment. The base plate segment and the sidewall segment of each of the first electrodes LEL1 may have substantially the same thickness.

[0058] The first electrode LEL1 may include one of a doped semiconductor, a conductive metal nitride, a metal, and a metal-semiconductor compound. For example, the first electrode LEL1 may include a metal nitride layer, such as a titanium nitride (TiN) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tantalum nitride (TaN) layer, a tantalum silicon nitride (TaSiN) layer, a tantalum aluminum nitride (TaAlN) layer, and a tungsten nitride (WN) layer.

[0059] The dielectric layer DIL can be configured to have a uniform thickness on the surface of the first electrode LEL1. For example, the dielectric layer DIL may comprise a high-k dielectric material such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2.

[0060] The second electrode LEL2 can be disposed on the dielectric layer DIL. The second electrode LEL2 can cover the first electrode LEL1, wherein the dielectric layer DIL is located between the second electrode LEL2 and the first electrode LEL1. The second electrode LEL2 can fill the cylindrical (or cup-shaped) portion inside the first electrode LEL1. The second electrode LEL2 can include one of a doped semiconductor, a conductive metal nitride, a metal, and a metal-semiconductor compound. For example, the second electrode LEL2 can have a structure in which a metal nitride layer and a semiconductor layer are sequentially stacked.

[0061] The second dielectric layer 120 and the third dielectric layer 130 may be sequentially stacked on the capacitor CAP. The second dielectric layer 120 may include a silicon oxide layer or a silicon oxynitride layer. The third dielectric layer 130 may include a material that is etch-selective relative to the second dielectric layer 120. For example, the third dielectric layer 130 may include tetraethyl orthosilicate (TEOS).

[0062] The second contact CT2 can be configured to penetrate the second dielectric layer 120 and have an electrical connection with the second electrode LEL2. A first conductive line ML1 can be disposed in the third dielectric layer 130. The first conductive line ML1 can extend in a first direction D1. The first conductive line ML1 can be electrically connected to the capacitor CAP via the second contact CT2. The first conductive line ML1 can have a width in a second direction D2, which can decrease as the distance from the substrate 100 decreases.

[0063] The second contact CT2 may include a lower segment CT2L disposed in the second dielectric layer 120 and an upper segment CT2U disposed on the lower segment CT2L. The upper segment CT2U may be disposed in the third dielectric layer 130. The upper segment CT2U may have a width in the second direction D2, which may increase as the distance from the substrate 100 decreases. The upper segment CT2U may have a top surface covered by the first conductive line ML1. The upper segment CT2U may have sidewalls partially covered by the first conductive line ML1.

[0064] A second gate line GL2 traversing the second active portion ACT2 may be disposed thereon in a second region RG2 of substrate 100. The second gate line GL2 may extend in a first direction D1. The second gate line GL2 may include a conductive material. For example, the conductive material may include one or more of the following: doped semiconductors (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0065] The second gate dielectric pattern GI2 can be interposed between the second active portion ACT2 and the second gate line GL2. For example, the second gate dielectric pattern GI2 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0066] The gate spacer GS can be disposed on the opposite sidewalls of the second gate line GL2. The gate spacer GS can be spaced apart from each other on both sides of the second gate line GL2 in the second direction D2. The gate spacer GS may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0067] The third cover pattern CP3 can be disposed on the top surface of the second gate line GL2. For example, the third cover pattern CP3 may include a silicon nitride layer or a silicon oxynitride layer.

[0068] A pair of third impurity regions SD3 can be disposed in the second active portion ACT2. The pair of third impurity regions SD3 can be separated from each other on both sides of the second gate line GL2 in the second direction D2. The third impurity regions SD3 can have substantially the same conductivity type.

[0069] The first dielectric layer 110, the second dielectric layer 120, and the third dielectric layer 130 can be stacked sequentially on the second region RG2 of the substrate 100.

[0070] The third contact CT3 can be configured to penetrate the first dielectric layer 110 and the second dielectric layer 120 and have an electrical connection with the third impurity region SD3. A second conductive line ML2 can be disposed in the third dielectric layer 130. The second conductive line ML2 can extend in the first direction D1. The second conductive line ML2 can be electrically connected to the third impurity region SD3 via the third contact CT3. The second conductive line ML2 can have a width in the second direction D2, which can decrease as the distance from the substrate 100 decreases.

[0071] The third contact CT3 may include a lower segment CT3L disposed in the first dielectric layer 110 and the second dielectric layer 120, and an upper segment CT3U disposed on the lower segment CT3L. The upper segment CT3U may be disposed in the third dielectric layer 130. The upper segment CT3U may have a width in the second direction D2, which may increase as the distance from the substrate 100 decreases. The upper segment CT3U may have a top surface covered by the second conductive line ML2. The upper segment CT3U may have sidewalls partially covered by the second conductive line ML2.

[0072] According to the present invention, the sidewall of the upper section of the contact can contact the conductive wire, which can lead to an improvement in the interface resistance characteristics between the contact and the conductive wire.

[0073] Although the invention has been described with reference to some exemplary embodiments of the inventive concept shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made therein without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor device, comprising: Substrate; A first dielectric layer and a second dielectric layer are sequentially stacked on the substrate; A contact that penetrates the first dielectric layer and extends toward the substrate, the contact including a lower segment in the first dielectric layer and an upper segment in the second dielectric layer; as well as A conductive line extends in a first direction within the second dielectric layer and is electrically connected to the contact. The upper sidewall of the contact element is in contact with the conductive wire. Wherein, the width of the upper segment of the contact element in the second direction increases as the distance from the substrate decreases. The width of the conductive line in the second direction decreases as the distance from the substrate decreases. Wherein, the minimum width of the conductive line in the second direction is less than the maximum width of the upper segment of the contact in the second direction.

2. The semiconductor device according to claim 1, wherein, The upper sidewall of the contact includes a first portion that contacts the conductive line and a second portion that contacts the second dielectric layer.

3. The semiconductor device according to claim 1, wherein, The conductive line completely covers the sidewall of the upper section of the contact.

4. The semiconductor device according to claim 1, wherein, When viewed from a plane, the top surface of the upper section of the contact is surrounded by the sidewalls of the upper section of the contact.

5. The semiconductor device according to claim 1, wherein, The width of the lower segment of the contact in the second direction decreases as the distance from the substrate decreases.

6. The semiconductor device of claim 1, further comprising a barrier layer located between the first dielectric layer and the lower segment of the contact.

7. A semiconductor device, comprising: Substrate; A first dielectric layer and a second dielectric layer are sequentially stacked on the substrate; A contact element that penetrates the first dielectric layer and extends toward the substrate; as well as A conductive wire, disposed in the second dielectric layer and electrically connected to the contact, extends in a first direction. The contact element includes a lower segment located in the first dielectric layer and an upper segment located in the second dielectric layer. Wherein, the width of the upper segment of the contact in the second direction increases as the distance from the substrate decreases, the second direction intersects the first direction, and The width of the conductive line in the second direction decreases as the distance from the substrate decreases. Wherein, the minimum width of the conductive line in the second direction is less than the maximum width of the upper segment of the contact in the second direction.

8. The semiconductor device according to claim 7, wherein, The sidewall of the upper section of the contact element is in contact with the conductive wire.

9. The semiconductor device according to claim 8, wherein, The upper sidewall of the contact includes a first portion that contacts the conductive line and a second portion that contacts the second dielectric layer.

10. The semiconductor device according to claim 7, wherein, The minimum width of the conductive line in the second direction is greater than the minimum width of the upper segment of the contact in the second direction.

11. The semiconductor device according to claim 7, wherein, The maximum width of the conductive line in the second direction is greater than the maximum width of the upper segment of the contact in the second direction.

12. The semiconductor device according to claim 8, wherein, When viewed from a plane, the top surface of the upper section of the contact is surrounded by the sidewalls of the upper section of the contact.

13. A semiconductor device, comprising: Substrate; A first dielectric layer and a second dielectric layer are sequentially stacked on the substrate; A contact element that penetrates the first dielectric layer and extends toward the substrate; as well as A conductive line, located in the second dielectric layer and electrically connected to the contact, extends in a first direction. The contact element includes a lower segment located in the first dielectric layer and an upper segment located in the second dielectric layer. The conductive line includes a recessed portion located on the lowest surface of the conductive line and recessed in a direction away from the substrate. The upper section of the contact element contacts the recessed portion. Wherein, the width of the upper segment of the contact element in the second direction increases as the distance from the substrate decreases. The width of the conductive line in the second direction decreases as the distance from the substrate decreases. Wherein, the minimum width of the conductive line in the second direction is substantially equal to the maximum width of the upper segment of the contact in the second direction.

14. The semiconductor device according to claim 13, wherein, The conductive line completely covers the sidewall of the upper section of the contact.

15. The semiconductor device according to claim 14, wherein, The second direction intersects with the first direction.

16. The semiconductor device according to claim 13, wherein, The opposing sidewalls of the upper section of the contact are inclined inward relative to the substrate, and the opposing sidewalls of the conductive wire are inclined outward relative to the substrate, so as to define an hourglass-shaped cross section at the boundary where the opposing sidewalls of the upper section of the contact and the opposing sidewalls of the conductive wire intersect.

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