A multi-port low-capacitance voltage surge protection chip and manufacturing method thereof

Abstract

The present invention provides a multi-port low-capacitance voltage surge protection chip and a manufacturing method thereof. The chip has a multi-port protection function, good overall current discharge capacity and stability, fast protection response speed and wide application range: the chip comprises at least two protection units arranged side by side and opposite to each other, including: a substrate having a first conductivity type; a base region having a second conductivity type; a first highly doped diffusion region having the second conductivity type; an emitter region having the first conductivity type, a short circuit structure being formed between the emitter region and the base region; an annular region having the first conductivity type and being arranged around the base region; a highly doped secondary diffusion region having the second conductivity type, being located in the base region and on one side of the emitter region; a strip region having the first conductivity type, being located between the annular region and the emitter region and being connected to the annular region; a second highly doped diffusion region having the first conductivity type, the first highly doped diffusion region and the second highly doped diffusion region being complementary; and an electrode being arranged on the upper surface of the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a multi-port low-capacitance voltage surge protection chip and a manufacturing method thereof. Background Art

[0002] With the rapid development of electronic technology, there are often unexpected voltage transients and surge currents that cause the performance of the entire system to degrade, malfunction or even damage. Especially in communication systems, surges such as lightning strikes, power supply voltage fluctuations, and electromagnetic induction can have a great impact on or even damage communication equipment.

[0003] Semiconductor surge protection devices have the superior performance of precise conduction, infinite repetition and fast response, which are far beyond the reach of other instantaneous overvoltage protection devices. For example, the Chinese invention patent with publication number CN104900645A provides a voltage surge protection device and a manufacturing method thereof. However, with the development of the communication field, higher requirements are put forward for the overall discharge capacity and stability of semiconductor surge protection devices, requiring them to be able to achieve multi-port protection. In addition, the capacitance of the device is also required to be smaller and smaller, and the requirements for protection response speed and application range are also getting higher and higher. Summary of the invention

[0004] In view of the above problems, the present invention provides a multi-port low-capacitance voltage surge protection chip and a manufacturing method thereof, which has a multi-port protection function, good overall current discharge capacity and stability, fast protection response speed and a wide range of applications.

[0005] The technical solution is as follows: a multi-port low-capacitance voltage surge protection chip, characterized in that it includes at least two protection units arranged side by side and opposite to each other, and the protection units include:

[0006] a substrate having a first conductivity type;

[0007] A base region, having a second conductivity type, extending downward from the upper surface of the substrate into the substrate;

[0008] A first highly doped diffusion region, having a second conductivity type, extending upward from the lower surface of the substrate into the substrate;

[0009] An emitter region, having a first conductivity type, extending downward from the upper surface of the substrate into the base region, and forming a short-circuit structure between the emitter region and the base region;

[0010] an annular region, having a first conductivity type, disposed around the base region and extending downward from the upper surface of the substrate into the substrate;

[0011] a highly doped secondary diffusion region, having a second conductivity type, located in the base region and on one side of the emitter region;

[0012] a strip region, having a first conductivity type, located between the annular region and the emitter region, connected to the annular region, and extending downward from the upper surface of the substrate into the substrate;

[0013] A second highly doped diffusion region, having a first conductivity type, extending upward from the lower surface of the substrate into the substrate, wherein the first highly doped diffusion region is complementary to the second highly doped diffusion region;

[0014] An electrode, disposed on the upper surface of the substrate;

[0015] The first conductivity type is complementary to the second conductivity type.

[0016] Furthermore, the center lines of the strip region, the emitter region, and the first highly doped diffusion region in the longitudinal direction are located on the same longitudinal straight line.

[0017] Furthermore, the highly doped secondary diffusion region extends downward from the upper surface of the substrate through the base region into the substrate.

[0018] Furthermore, ohmic contact holes are arranged at the four corners of the protection unit and on the annular area of ​​the protection unit, and the ohmic contact hole between two protection units is arranged across the two protection units and is connected by metal.

[0019] Furthermore, the protection unit is integrated on the same substrate.

[0020] Further, the first conductivity type is N type, and the second conductivity type is P type; or the first conductivity type is P type, and the second conductivity type is N type.

[0021] Furthermore, the thickness of the substrate is 170nm-230nm.

[0022] A method for manufacturing the above-mentioned multi-port low-capacitance voltage surge protection chip is characterized by comprising:

[0023] A substrate of a first conductive type is provided, at least two protection units arranged side by side and in opposite directions are divided on the substrate, and the following steps are performed on each protection unit:

[0024] forming a base region of a second conductivity type on the substrate, wherein the base region of the second conductivity type extends downward from the upper surface of the substrate into the substrate;

[0025] forming a first highly doped diffusion region of the second conductivity type under the substrate, the first highly doped diffusion region of the second conductivity type extending upward from the lower surface of the substrate into the substrate;

[0026] A plurality of emitter regions of the first conductivity type are formed on the base region, wherein the emitter regions of the first conductivity type extend downward from the upper surface of the substrate into the base region;

[0027] A first conductive type annular region is formed around the base region, and the annular region extends downward from the upper surface of the substrate into the substrate;

[0028] forming a highly doped secondary diffusion region of the second conductivity type in the base region and located on one side of the emitter region;

[0029] Forming a strip region of the first conductivity type between the annular region and the emitter region, connecting the strip region with the annular region, wherein the strip region extends downward from the upper surface of the substrate into the substrate;

[0030] forming a second highly doped diffusion region of the first conductivity type under the substrate, the second highly doped diffusion region extending upward from the lower surface of the substrate into the substrate;

[0031] An electrode is formed on the upper surface of the substrate.

[0032] Furthermore, the emitting area, the annular area and the strip area are formed simultaneously or the emitting area, the annular area and the strip area are formed successively.

[0033] The multi-port low-capacitance voltage surge protection chip of the present invention has a protection unit corresponding to each port, which can realize full forward and reverse overvoltage protection for multiple channels. An electrode is drawn out from the surface of each protection unit, and every two protection units form a structure with forward and reverse protection functions in the transverse direction; and the protection units are arranged side by side and in reverse order to ensure the uniformity of current flow and better achieve high consistency of forward and reverse protection functions; the second conductivity type base region of any protection unit, the first conductivity type substrate and the second conductivity type base region of another protection unit, and the first conductivity type emitter region in the second conductivity type base region of another unit form a four-layer PNPN structure, which has a "clamping" characteristic, and can maintain the voltage of the triggered device at a low voltage level to ensure the safety of subsequent circuits;

[0034] The short-circuit ring channel formed by the first conductive type emitter region and the second conductive type base region together constitutes a cathode short-circuit structure, which plays a role in balancing the current to avoid local breakdown, thereby improving the overall current discharge capacity and stability of the device;

[0035] The highly doped secondary diffusion region of the second conductivity type formed in the base region of the second conductivity type of each protection unit has a junction depth after annealing greater than the base region of the second conductivity type and extends into the substrate, which can reduce the body capacitance after conduction, effectively improve the ability to discharge current, and play a role in independently adjusting the capacitance size, overcoming the contradiction between the breakdown voltage and the capacitance size adjustment. The smaller the capacitance value, the faster the response speed of the device in the circuit, meeting the current development requirements of the communication field for smaller and smaller capacitance of the device;

[0036] In addition, the strip area of ​​the first conductive type is connected to the ring structure of the first conductive type and is only formed between the ring structure of the first conductive type and the emitter area of ​​the first conductive type, so that in each unit, the longitudinal center lines of the strip area of ​​the first conductive type, the emitter area of ​​the first conductive type and the first highly doped diffusion area of ​​the second conductive type are located on the same longitudinal straight line. By adjusting the distance between the strip area and the emitter area of ​​the first conductive type, independent adjustment of the breakdown voltage can be achieved, thereby realizing the serialization of product voltage levels, adapting to more application requirements and having a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic top view of a multi-port low-capacitance voltage surge protection chip of the present invention;

[0038] Figure 2 It is a schematic diagram of a semi-finished product obtained in step S1 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0039] Figure 3 It is a schematic diagram of a semi-finished product obtained in step S2 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0040] Figure 4 It is a schematic diagram of a semi-finished product obtained in step S3 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0041] Figure 5 It is a schematic diagram of a semi-finished product obtained in step S4 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0042] Figure 6 It is a schematic diagram of a semi-finished product obtained in step S5 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0043] Figure 7 It is a schematic diagram of a semi-finished product obtained in step S6 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0044] Figure 8It is a schematic diagram of a semi-finished product obtained in step S7 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0045] Fig. 9 It is a schematic diagram of a semi-finished product obtained in step S8 in a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0046] Fig.10 It is a schematic diagram of a product obtained in step S9 of a method for manufacturing a three-port low-capacitance voltage surge protection chip of the present invention;

[0047] Fig.11 It is a schematic top view of the front structure of the protection unit of the present invention;

[0048] Fig.12 is a schematic top view of the back structure of the protection unit of the present invention;

[0049] Fig.13 A schematic top view of the front structure of a three-port low-capacitance voltage surge protection chip of the present invention;

[0050] Fig.14 The present invention is a flowchart of a method for manufacturing a three-port low-capacitance voltage surge protection chip. DETAILED DESCRIPTION

[0051] The following is a detailed description with reference to the accompanying drawings, which form a part of the present invention, and in the present invention, the drawings are represented by explanations of specific embodiments for implementing the present invention. It should be understood that other embodiments may be adopted and structural or logical changes may be made without departing from the scope of the present invention. For example, the features explained or described for one embodiment may be used in other embodiments or combined with other embodiments to generate another embodiment. It is intended that the present invention includes such modifications and variations. These examples are described with specific sentences, but they should not be construed as limiting the scope of the appended claims. The drawings are for illustrative purposes only and are not drawn to scale. Unless otherwise specified, corresponding elements are represented by the same reference numerals in different drawings for the purpose of clarity.

[0052] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "upper surface", "lower surface", "lateral", "longitudinal", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0053] The terms “having”, “containing”, “including”, “comprising” and the like are open ended and indicate the presence of described structures, elements or features but do not exclude additional elements or features.

[0054] In the figures, the corresponding doping concentration is indicated by indicating "+" or "++" after the doping type "n" or "p". For example, "n-" indicates a doping concentration that is lower than the doping concentration of an n-doping region, while an "n+ / n++" doping region has a doping concentration that is higher than the doping concentration of an n-doping region, and an "n++" doping region has a doping concentration that is higher than the doping concentration of an n+ doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different n-doping regions can have the same or different absolute doping concentrations.

[0055] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. Specific embodiment 1:

[0057] like Figure 1 As shown, Figure 1 This is a top view of a three-port low-capacitance voltage surge protection chip of the present invention, which includes three protection units 100 arranged side by side and opposite to each other. The three protection units 100 have the same structure. The three protection units 100 are arranged side by side and opposite to each other, which can make the current flow more uniform and achieve better bidirectional symmetrical protection function. Each protection unit leads to an electrode, namely T1, T2, and T3.

[0058] In this embodiment, the first conductivity type is N type, the second conductivity type is P type, and the first conductivity type is complementary to the second conductivity type.

[0059] For details, see Fig.10 , the protection unit includes:

[0060] Substrate 101, conductive type is N type;

[0061] The base region 102 is of P-type conductivity and extends downward from the upper surface of the substrate 101 into the substrate 101 ;

[0062] A first highly doped diffusion region 103 , of P-type conductivity, extending upward from the lower surface of the substrate 101 into the substrate 101 ;

[0063] The emitter region 104 is of N-type conductivity and extends downward from the upper surface of the substrate into the base region. In this embodiment, four short-circuit points are arranged horizontally and four vertically in the emitter region 104, for a total of 16 short-circuit points. The emitter region 104 and the base region 102 are connected to the same surface metal to form a short-circuit ring channel, which constitutes a short-circuit structure 105, thereby increasing the turning current of the thyristor, solving the problem that the protection device based on the thyristor principle is susceptible to high-temperature leakage, PN junction leakage or displacement current generated by a higher voltage rise rate due to too small a turning current, thereby increasing the safety performance of the protection device. In this embodiment, 16 short-circuit structures 205 are formed in the N-type emitter region;

[0064] The ring region 106 is of N-type conductivity, is disposed around the base region 102, and extends downward from the upper surface of the substrate 101 into the substrate 101. In this embodiment, any two protection units form a PNPN thyristor structure formed laterally. In order to prevent the current from flowing along the chip surface, causing the surface leakage to increase and the breakdown to occur in advance, the current flow path needs to be changed. The N-type ring structure can help redistribute the current to avoid the above situation.

[0065] The highly doped secondary diffusion region 107 is of P-type conductivity and is located in the base region 102 and on one side of the emitter region 104. In this embodiment, the highly doped secondary diffusion region 107 extends downward from the upper surface of the substrate 101 through the base region 102 into the substrate 101, which can achieve a good current flow. The influence of the highly doped secondary diffusion region 107 on the breakdown voltage does not need to be considered, and the contradiction between the breakdown voltage and the capacitance adjustment is overcome. The smaller the capacitance value, the faster the response speed of the device in the circuit.

[0066] The strip region 108 is of N-type conductivity, located between the annular region 106 and the emitter region 104, and connected to the annular region 106, extending downward from the upper surface of the substrate 101 into the substrate 101, and the center lines of the strip region 108, the emitter region 104, and the first highly doped diffusion region 103 in the longitudinal direction are located on the same longitudinal straight line, and the maximum length of the strip region 108 does not exceed the width of the entire protection unit, and the breakdown voltage can be adjusted from a few volts to several hundred volts by adjusting the spacing between the highly doped secondary diffusion region 107 and the emitter region 104; the breakdown voltage can be adjusted independently, and the voltage level of the product can be serialized to meet more application requirements and have a wide range of applications;

[0067] The second highly doped diffusion region 109 is of N-type conductivity and extends upward from the lower surface of the substrate 101 into the substrate 101. The first highly doped diffusion region 103 and the second highly doped diffusion region 109 are complementary to each other and function to adjust the body resistance of the entire protection unit, thereby improving the current carrying capacity.

[0068] A metal 110 is formed on the P-type base region 102 of each protection unit to form electrodes T1 , T2 , and T3 .

[0069] In the scheme, the term “extending into” means extending into but not penetrating. For example, the emitter region 104 extends from the upper surface of the substrate 200 into the base region 102 , which means that the emitter region 104 ends in the base region 102 and does not penetrate the base region 102 .

[0070] In this embodiment, eight square ohmic contact holes 111 are opened on the surface of the N-type annular region 206. Figure 1 As shown, the ohmic contact hole 111 between the two protection units 100 is set across the two protection units and is connected by a metal 112. The metal interconnection plays a role in balancing the surface charge to prevent surface breakdown and affect device safety.

[0071] Preferably, the protection unit adopts the power integration design technology on the same silicon substrate, and the multiple protection units are rationally arranged to lead out each protection port respectively, so that any two ports between port 1, port 2, and port 3 can work symmetrically in the protected circuit, and multiple protection units are integrated into the same substrate. Compared with multiple discrete units, the advantage of integration lies in the uniformity of process implementation, simplification of process steps, cost savings, and the ability to maximize process consistency and facilitate the adjustment of device performance.

[0072] Preferably, the longitudinal structure of the thyristor is arranged laterally, that is, the P-type base region 102 of a protection unit, the N-type substrate 101, the P-type base region 102 and the N-type emitter region 104 of another protection unit form a laterally distributed PNPN structure thyristor, and the P-type base region 102 and the N-type emitter region 104 form a short-circuit structure through the short-circuit structure 105. Compared with the longitudinal structure, the lateral thyristor is easier to adjust the base junction depth and doping concentration of the forward and reverse thyristors to achieve consistent process, and overcome the shortcomings of the longitudinal thyristor that the double-sided injection is required, the junction depth is difficult to control, and the bidirectional symmetry is difficult to ensure.

[0073] like Fig.11 As shown, a top view schematic diagram of the front structure of the protection unit is shown, such as Fig.12 As shown, a top view schematic diagram of the back structure of the protection unit is shown; Fig.13 , which shows a top view schematic diagram of the front structure of a three-port low-capacitance voltage surge protection chip in this embodiment;

[0074] This embodiment also provides a method for manufacturing the above-mentioned three-port low-capacitance voltage surge protection chip, including:

[0075] See Figure 2Step S1: Provide an N-type substrate 101. In this embodiment, the substrate 101 is made of a substrate material with a thickness of 200 microns. Three protection units 100 arranged side by side and in opposite directions are divided on the N-type substrate 101. The following steps are performed on each protection unit 100:

[0076] See Figure 3 Step S2: forming a P-type base region 102 on the substrate 101, wherein the P-type base region 102 extends downward from the upper surface of the substrate 101 into the substrate 101, and the base region 102 may be formed by a method well known to those skilled in the art, such as by implantation or diffusion;

[0077] See Figure 4 Step S3: forming a first P-type highly doped diffusion region 103 under the substrate 101, the P-type first highly doped diffusion region 103 extending upward from the lower surface of the substrate 101 into the substrate 101, the first highly doped diffusion region 103 can be formed by a method well known to those skilled in the art, such as by injection or diffusion, the doping concentration of the P-type first highly doped diffusion region 103 is higher than that of the P-type base region 102, and its function is to adjust the base width of the thyristor, on the one hand, to change the current amplification factor of the transistor and adjust the performance of the entire thyristor; on the other hand, it can reduce the parasitic capacitance in the vertical direction and improve the response speed of the thyristor;

[0078] See Figure 5 Step S4: forming an N-type emitter region 104 on the base region 102, the N-type emitter region 104 extending downward from the upper surface of the substrate 101 into the base region 102, and the emitter region 104 and the base region 102 are connected to the same surface metal, forming a short-circuit ring channel together, forming a short-circuit structure 105, thereby increasing the turning current of the thyristor, solving the problem that the protection device based on the thyristor principle is susceptible to high-temperature leakage, PN junction leakage or displacement current generated by a high voltage rise rate due to too small a turning current, thereby increasing the safety performance of the protection device. The emitter region 104 can be formed by a method well known to those skilled in the art, such as by injection or diffusion;

[0079] See Figure 6 , step S5: forming an N-type annular region 106 around the base region 102, the annular region 106 extending downward from the upper surface of the substrate 101 into the substrate 101. This embodiment adopts a PNPN thyristor structure formed laterally. In order to avoid the current flowing along the chip surface, causing the surface leakage to increase and the breakdown to occur in advance, it is necessary to change the current flow path. The N-type ring structure can help redistribute the current to avoid the above situation.

[0080] The N-type emitter region 104 and the N-type annular region 106 can be formed by implantation and annealing together, which simplifies the process and saves costs. They can also be manufactured one after another.

[0081] See Figure 7 , step S6: forming a P-type highly doped secondary diffusion region 107 in the base region 102 and on one side of the emitter region 104, the P-type highly doped secondary diffusion region 107 is formed by injection from the upper surface of the base region 202, the highly doped secondary diffusion region 107 extends from the upper surface of the substrate 101 downward through the base region 102 into the substrate 101, the depth of the highly doped secondary diffusion region 107 is greater than the base region 102, the process adopts P++ secondary injection, with the advanced semiconductor process technology, it can break the restrictive relationship between breakdown voltage and capacitance, overcome the contradiction between breakdown voltage and capacitance adjustment, can have a smaller capacitance value, the faster the response speed of the device in the circuit, the more easily the capacitance can be adjusted, and adapt to more applications with different capacitance requirements;

[0082] See Figure 8 , step S7: forming an N-type strip region 108 between the annular region 106 and the emitter region 104, connecting the strip region 108 to the annular region 106, and extending the strip region 108 downward from the upper surface of the substrate 101 into the substrate 101; the center lines of the strip region 108, the emitter region 104, and the first highly doped diffusion region 103 in the longitudinal direction are located on the same longitudinal straight line, and the maximum length of the strip region 108 does not exceed the width of the entire protection unit, and the breakdown voltage is adjusted from a few volts to several hundred volts by adjusting the spacing between the highly doped secondary diffusion region 107 and the emitter region 104; the breakdown voltage is adjusted independently, and the voltage level of the product is serialized, without the need to re-plate, saving time and economic costs, and can adapt to a wider range of application needs, and has good competitiveness in terms of economic benefits and social value;

[0083] The strip region 108 can be formed by injection and annealing together with the N-type emitter region 104 and the N-type ring region 106, which simplifies the process, saves costs, and avoids adding additional process steps due to structural changes. Of course, it can also be completed in the order of the N-type emitter region 104, the N-type ring region 106, and the strip region 108.

[0084] See Fig. 9 Step S8: forming an N-type second highly doped diffusion region 109 under the substrate 101, the second highly doped diffusion region 109 extending upward from the lower surface of the substrate 101 into the substrate 101, and the second highly doped diffusion region 109 can be formed by a method well known to those skilled in the art, such as by implantation or diffusion;

[0085] See Fig.10 , step S9: forming a metal 110 on the P-type base region 102 of each protection unit to form electrodes T1, T2, and T3.

[0086] After completing the above method or after additionally completing the above additional preferred steps, eight square ohmic contact holes 111 are opened on the surface of the N-type annular region 206, such as Figure 1 As shown, the ohmic contact hole 111 between the two protection units 100 is set across the two protection units and is connected by a metal 112. The metal interconnection plays a role in balancing the surface charge to prevent surface breakdown and affect device safety.

[0087] The three-port low-capacitance voltage surge protection chip obtained in the above embodiment can realize the bidirectional surge protection function of the voltage between ports, overcome the problem of unbalanced forward and reverse protection capabilities of semiconductor surge protection devices, and provide a three-port protection function. It uses independent voltage variable technology and independent capacitance variable technology to make it suitable for more application scenarios.

[0088] Example 2

[0089] The structure and manufacturing method of the port low-capacitance voltage surge protection chip formed in Embodiment 2 are similar to those in Embodiment 1, except that the conductivity type N in Embodiment 1 is changed to P, and P is changed to N. Therefore, no further description is given here.

[0090] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various means in the prior art can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

[0091] The present invention has been described above with reference to the embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A multi-port low-capacitance voltage surge protection chip, characterized in that: It comprises at least two protection units arranged side by side and opposite to each other, and the protection units comprise: a substrate having a first conductivity type; A base region, having a second conductivity type, extending downward from the upper surface of the substrate into the substrate; A first highly doped diffusion region, having a second conductivity type, extending upward from the lower surface of the substrate into the substrate; An emitter region, having a first conductivity type, extending downward from the upper surface of the substrate into the base region, and forming a short-circuit structure between the emitter region and the base region; an annular region, having a first conductivity type, disposed around the base region and extending downward from the upper surface of the substrate into the substrate; a highly doped secondary diffusion region, having a second conductivity type, located in the base region and on one side of the emitter region; a strip region, having a first conductivity type, located between the annular region and the emitter region, connected to the annular region, and extending downward from the upper surface of the substrate into the substrate; A second highly doped diffusion region, having a first conductivity type, extending upward from the lower surface of the substrate into the substrate, wherein the first highly doped diffusion region is complementary to the second highly doped diffusion region; An electrode, disposed on the upper surface of the substrate; wherein the first conductivity type is complementary to the second conductivity type; The highly doped secondary diffusion region extends downward from the upper surface of the substrate through the base region into the substrate; Ohmic contact holes are arranged on the four corners of the protection unit and on the annular area of ​​the protection unit, and the ohmic contact hole between the two protection units is arranged across the two protection units and is connected by metal.

2. A multi-port low-capacitance voltage surge protection chip according to claim 1, characterized in that: The center lines of the strip region, the emitter region, and the first highly doped diffusion region in the longitudinal direction are located on the same longitudinal straight line.

3. The multi-port low-capacitance voltage surge protection chip according to claim 1, characterized in that: The protection unit is integrated on the same substrate.

4. The multi-port low-capacitance voltage surge protection chip according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; or the first conductivity type is P type, and the second conductivity type is N type.

5. The multi-port low-capacitance voltage surge protection chip according to claim 1, characterized in that: The thickness of the substrate is 170nm-230nm.

6. A method for manufacturing a multi-port low-capacitance voltage surge protection chip as claimed in claim 1, characterized in that: include: A substrate of a first conductive type is provided, at least two protection units arranged side by side and in opposite directions are divided on the substrate, and the following steps are performed on each protection unit: forming a base region of a second conductivity type on the substrate, wherein the base region of the second conductivity type extends downward from the upper surface of the substrate into the substrate; forming a first highly doped diffusion region of the second conductivity type under the substrate, the first highly doped diffusion region of the second conductivity type extending upward from the lower surface of the substrate into the substrate; A plurality of emitter regions of the first conductivity type are formed on the base region, wherein the emitter regions of the first conductivity type extend downward from the upper surface of the substrate into the base region; A first conductive type annular region is formed around the base region, and the annular region extends downward from the upper surface of the substrate into the substrate; forming a highly doped secondary diffusion region of the second conductivity type in the base region and located on one side of the emitter region; Forming a strip region of the first conductivity type between the annular region and the emitter region, connecting the strip region with the annular region, wherein the strip region extends downward from the upper surface of the substrate into the substrate; forming a second highly doped diffusion region of the first conductivity type under the substrate, the second highly doped diffusion region extending upward from the lower surface of the substrate into the substrate; An electrode is formed on the upper surface of the substrate.

7. The method for manufacturing a multi-port low-capacitance voltage surge protection chip according to claim 6, characterized in that: The emitting area, the annular area and the strip area are formed simultaneously or the emitting area, the annular area and the strip area are formed successively.

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