Thin film transistor and method of manufacturing the same

Abstract

This application belongs to the field of semiconductor device technology and provides a thin-film transistor and its fabrication method. By using a first active layer and a second active layer with different Fermi levels to form an active layer, and providing a plurality of spaced protrusions on the upper surface of the first active layer, a corrugated heterojunction is formed between the second active layer and the first active layer. This not only reduces the leakage current of the amorphous IGZO thin-film transistor, but also improves the electromobility and on / off ratio of the amorphous IGZO thin-film transistor, solving the problem that existing IGZO thin-film transistors cannot meet new requirements due to their low electromobility and output current.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, and in particular relates to a thin-film transistor and its fabrication method. Background Technology

[0002] Thin-film transistors (TFTs) based on metal-semiconductor oxides (MSOs) have attracted widespread attention due to their advantages such as high field-effect mobility, high light transmittance, low leakage current, low deposition temperature, and low manufacturing cost. After years of research, amorphous IGZO TFTs have achieved excellent device performance, but their electromobility remains relatively low. The electromobility of IGZO TFTs deposited by physical methods is between 10⁻⁴⁰ cm⁻¹. 2 The electromobility of chemically deposited IGZO thin-film transistors is between 1 and 14 cm⁻¹. 2 / V s between.

[0003] However, as flat panel displays become larger, the demand for more transistors and lower power consumption increases. At the same time, emerging display technologies, such as 3D and virtual reality, also place higher demands on resolution and refresh rate. Existing IGZO thin-film transistors, due to their low electromobility and output current, cannot meet these new requirements. Summary of the Invention

[0004] The purpose of this application is to provide a thin-film transistor and its fabrication method, which aims to solve the problem that existing IGZO thin-film transistors cannot meet new requirements due to their low electromobility and output current.

[0005] To address the aforementioned technical problems, this application provides a thin-film transistor, comprising a substrate, a gate electrode layer, a dielectric layer, an active layer, a source electrode, and a drain electrode; the gate electrode layer is disposed on the substrate, the dielectric layer is disposed on the surface of the gate electrode layer, and the active layer is disposed on the surface of the dielectric layer; wherein, the active layer comprises a first active layer and a second active layer, the Fermi level of the first active layer is different from the Fermi level of the second active layer; the lower surface of the first active layer is in contact with the dielectric layer, the upper surface of the first active layer is in contact with the second active layer, a plurality of spaced-apart protrusions are provided on the upper surface of the first active layer, and the source electrode and the drain electrode are respectively disposed on opposite sides of the upper surface of the second active layer without contacting each other.

[0006] Optionally, the first active layer is indium tin zinc oxide, and the second active layer is indium gallium zinc oxide.

[0007] Optionally, a plurality of first active layer protrusions are periodically arranged on the upper surface of the first active layer, and the lower surface portion of the second active layer is embedded in the groove formed by adjacent first active layer protrusions.

[0008] Optionally, the first active layer protrusions are at least one of square, rectangular, triangular, and spherical shapes.

[0009] Optionally, a plurality of the first active layer protrusions are integrally formed with the first active layer, and the upper surface of the first active layer is serrated.

[0010] This application also provides a method for fabricating a thin-film transistor, comprising:

[0011] A dielectric layer is formed on the gate electrode layer;

[0012] A first active layer and a second active layer are sequentially formed on the surface of the dielectric layer; wherein the Fermi level of the first active layer is different from the Fermi level of the second active layer; the lower surface of the first active layer is in contact with the dielectric layer, the upper surface of the first active layer is in contact with the second active layer, and a plurality of spaced-apart protrusions of the first active layer are provided on the upper surface of the first active layer.

[0013] A source and a drain are formed on the second active layer. The source and the drain are not in contact with each other and are respectively located on opposite sides of the upper surface of the active layer.

[0014] Optionally, forming a dielectric layer on the gate electrode layer includes:

[0015] At least one of alumina, silicon dioxide, or silicon nitride / silicon dioxide stack is deposited on the front side of the ITO glass.

[0016] Optionally, the step of sequentially forming a first active layer and a second active layer on the surface of the dielectric layer includes:

[0017] A first photoresist is formed on the upper surface of the dielectric layer using a first photoresist, and multiple first ITZO thin films are formed on the upper surface of the dielectric layer under the masking of the first photoresist;

[0018] A second photoresist is formed on the upper surface of the dielectric layer using a second photoresist, and a second ITZO film is formed between adjacent first ITZO films under the mask of the second photoresist; wherein the thickness of the second ITZO film is different from the thickness of the first ITZO film, and the first ITZO film and the second ITZO film are spaced apart to form a first active layer.

[0019] A second active layer is formed on the first active layer.

[0020] Optionally, the thickness of the second ITZO film is greater than the thickness of the first ITZO film.

[0021] Optionally, forming a second active layer on the first active layer includes:

[0022] A second active layer is deposited on the first active layer using radio frequency magnetron sputtering; wherein the thickness of the second active layer is greater than the thickness of the first active layer.

[0023] This application provides a thin-film transistor and its fabrication method. By using a first active layer and a second active layer with different Fermi levels to form an active layer, and providing a plurality of spaced protrusions on the upper surface of the first active layer, a corrugated heterojunction is formed between the second active layer and the first active layer. This not only reduces the leakage current of the amorphous IGZO thin-film transistor, but also improves the on / off ratio of the amorphous IGZO thin-film transistor, solving the problem that existing IGZO thin-film transistors cannot meet new requirements due to their low electromobility and output current. Attached Figure Description

[0024] Figure 1 A schematic diagram of the structure of a thin-film transistor provided in one embodiment of this application;

[0025] Figure 2 A schematic diagram of the structure of a thin-film transistor provided for another embodiment of this application;

[0026] Figure 3 A schematic diagram of the structure of a thin-film transistor provided for another embodiment of this application;

[0027] Figure 4 A schematic diagram of a structure forming a dielectric layer on a gate electrode layer is provided for one embodiment of this application;

[0028] Figure 5 A schematic diagram of the structure of forming a first ITZO thin film 411 on a dielectric layer is provided for one embodiment of this application;

[0029] Figure 6 A schematic diagram of the structure of forming a second ITZO thin film 412 on a dielectric layer is provided for one embodiment of this application;

[0030] Figure 7 A schematic diagram of a structure in which a second active layer is formed on a first active layer, according to an embodiment of this application;

[0031] Figure 8 This is a schematic diagram of a structure in which a source and a drain are formed on an active layer, according to an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0034] To address the aforementioned technical problems, this application provides a thin-film transistor, see [link to relevant documentation]. Figure 1 As shown, the thin-film transistor in this embodiment includes a substrate 10, a gate electrode layer 20, a dielectric layer 30, an active layer 40, a source electrode 50, and a drain electrode 60. The gate electrode layer 20 is disposed on the substrate 10, the dielectric layer 30 is disposed on the surface of the gate electrode layer 20, and the active layer 40 is disposed on the surface of the dielectric layer 30. The active layer 40 includes a first active layer 41 and a second active layer 42. The Fermi level of the first active layer 41 is different from that of the second active layer 42. The lower surface of the first active layer 41 is in contact with the dielectric layer 30, and the upper surface of the first active layer 41 is in contact with the second active layer 42. A plurality of spaced-apart first active layer protrusions are provided on the upper surface of the first active layer 41. The source electrode 50 and the drain electrode 60 are respectively disposed on opposite sides of the upper surface of the active layer 40 without contacting each other.

[0035] In this embodiment, a heterojunction is formed by a first active layer 41 and a second active layer 42 with different Fermi levels. The contact surface between the first active layer 41 and the second active layer 42 forms a heterojunction interface. A plurality of first active layer protrusions are provided on the upper surface of the first active layer 41. Since the plurality of first active layer protrusions are arranged sequentially on the upper surface of the first active layer 41, the heterojunction interface has a corrugated structure (also known as a concave-convex structure). Specifically, the shape of the corrugated structure is determined by the shape of the first active layer protrusions. For example, the shape of the first active layer protrusions can be at least one of the following shapes: square, rectangle, triangle, sphere, etc. Specifically, multiple protrusions in the first active layer 41 form grooves on its surface, allowing the second active layer 42 to be embedded within these grooves. Since the first and second active layers use semiconductor materials with different Fermi levels, a potential well is formed at their interface. Free electrons accumulate in this potential well, forming a two-dimensional electron gas. When a positive bias is applied to the thin-film transistor (TFT), this two-dimensional electron gas is injected into the first active layer 41. In this embodiment, the first active layer 41 has a higher carrier concentration and electron mobility than the second active layer 42. The injection of the two-dimensional electron gas into the first active layer 41 can significantly improve the electromobility and output current of the TFT. Furthermore, when a negative bias is applied to the TFT, the protrusions on the surface of the first active layer 41 increase the resistance of the electron transport path, meaning that free electrons in both the second and first active layers 41 will be confined within the potential well, thereby reducing the leakage current of the TFT and improving its on / off ratio.

[0036] In one embodiment, the first active layer 41 is indium tin zinc oxide (ITZO), and the second active layer is indium gallium zinc oxide (IGZO). In this embodiment, the first active layer 41 can be an ITZO thin film, i.e., an ITZO active layer, and the second active layer 42 can be an IGZO thin film, i.e., an IGZO active layer. In this case, the thin-film transistor is an IGZO thin-film transistor. By placing an ITZO thin film with higher carrier concentration and electromobility between the dielectric layer 30 and the IGZO thin film, the electromobility and output current of the IGZO thin-film transistor can be greatly improved. Since the Fermi levels of the two thin-film semiconductor materials, ITZO and IGZO, are different, a potential well will be formed at their interface, and free electrons will accumulate in the potential well, forming a two-dimensional electron gas. When the thin-film transistor is on, the two-dimensional electron gas will be injected into the inserted ITZO thin film; in addition, the inserted ITZO thin film has a higher carrier concentration and electromobility, thereby greatly improving the electromobility and output current of the IGZO thin-film transistor. When the thin-film transistor is off, the bumps on the surface of the first active layer 41 increase the resistance of the electron transport path. Free electrons in the second active layer 42 and the first active layer 41 will be confined in the potential well, thereby reducing the leakage current of the thin-film transistor and improving the on / off ratio of the thin-film transistor.

[0037] In one embodiment, a plurality of first active layer protrusions are periodically arranged on the upper surface of the first active layer 41, and the second active layer 42 is embedded in a groove formed by adjacent first active layer protrusions.

[0038] In this embodiment, among the multiple first active layer protrusions on the upper surface of the first active layer 41 (i.e. the contact surface with the second active layer 42), a groove is formed between adjacent first active layer protrusions. At this time, the side of the second active layer 42 that contacts the first active layer 41 also forms a matching concave-convex structure. When a positive bias voltage is applied to the thin film transistor, two-dimensional electron gas is injected into the first active layer 41 through the protrusion structure of the second active layer 42.

[0039] In one embodiment, the first active layer protrusion is at least one of a square, rectangle, triangle, and sphere. In this embodiment, the first active layer protrusion can be configured in various shapes, for example, see [reference needed]. Figure 1 As shown, the first active layer protrusion is rectangular, see [reference]. Figure 2 As shown, the first active layer protrudes in a triangular shape. (See attached image) Figure 3 As shown, the first active layer protrusions can include various shapes such as circles, rectangles, and triangles.

[0040] In one embodiment, a plurality of first active layer protrusions are integrally formed with the first active layer 41, and the upper surface of the first active layer 41 is serrated. In this embodiment, see [link to documentation]. Figure 2 As shown, the first active layer protrusion is made of the same semiconductor material as the first active layer 41 and is integrally formed. At this time, the upper surface of the first active layer 41 is serrated.

[0041] In one embodiment, the dielectric layer 30 may be a dielectric material, which may include aluminum oxide, silicon dioxide, silicon dioxide / silicon nitride stack, etc.

[0042] In one embodiment, the dielectric layer 30 is aluminum oxide.

[0043] In one embodiment, the substrate 10 and the gate electrode layer 20 can be ITO glass, wherein the ITO glass is fabricated by depositing a layer of indium tin oxide (ITO) film on a sodium calcium-based or silicon boron-based substrate glass using a magnetron sputtering method, the conductive layer on the ITO glass serves as the gate electrode layer 20, and the insulating layer on the ITO glass serves as the substrate 10.

[0044] In one embodiment, the thickness of the first active layer 41 is less than the thickness of the second active layer 42.

[0045] In one embodiment, the thickness of the first active layer protrusion is greater than the thickness of the first active layer 41 between adjacent first active layer protrusions.

[0046] In one embodiment, the thickness of the second active layer 42 is eight times the thickness of the first active layer 41.

[0047] In one embodiment, the thickness of the first active layer 41 is 5 nm, and the thickness of the second active layer 42 is 40 nm.

[0048] In one embodiment, both the source 50 and the drain 60 are ITO thin films.

[0049] In one embodiment, the thickness of the source 50 and the drain 60 is 100-500 nm.

[0050] In one embodiment, the thickness of the source 50 and the drain 60 is 200 nm.

[0051] This application also provides a method for fabricating a thin-film transistor, including steps A, B, and C.

[0052] Step A: Form a dielectric layer on the gate electrode layer.

[0053] In this embodiment, see Figure 4 As shown, a dielectric layer 30 is formed on the gate electrode layer 20, which is disposed on the substrate 10. For example, a dielectric material is deposited on the conductive surface of ITO or FTO glass to form the dielectric layer 30.

[0054] In one embodiment, step A: forming a dielectric layer on the gate electrode layer includes: depositing at least one of aluminum oxide, silicon dioxide, or silicon nitride / silicon dioxide stack on the front side of the ITO glass.

[0055] In one embodiment, the dielectric layer 30 may be aluminum oxide, silicon dioxide, or a silicon dioxide / silicon nitride stack, etc.

[0056] Specifically, in one embodiment, the ITO glass and the gate photomask are ultrasonically cleaned sequentially using acetone, isopropanol, and water, wherein the area of ​​the ITO glass and the gate photomask can be 10cm × 10cm. After cleaning, the ITO glass and the gate photomask are dried with nitrogen gas and baked at a temperature of 60-70°C for 10-15 minutes. Prepare a developer solution with a developer-to-water ratio of 1:2. Take out the ITO glass and spin-coat photoresist onto the front side of the ITO glass at a speed of 2000-3000 rpm for 20-30 seconds. Bake the ITO glass with photoresist on a hot plate at 100-105℃ for 2-3 minutes, and then expose it using a photolithography machine. After exposure, develop it in the developer solution for 2-3 minutes, then rinse it with deionized water, dry it with nitrogen, and bake it at 100-110℃ for 10-20 minutes. Further, wet etch it in 37% hydrochloric acid for 5.5-10 minutes, rinse it with deionized water, and then sonicate it in acetone for 8-12 minutes for stripping. Then, deposit a 40-50 nm Al2O3 dielectric layer on the front side of the ITO glass using an ALD (atomic layer deposition) device.

[0057] Step B: A first active layer and a second active layer are sequentially formed on the surface of the dielectric layer; wherein the Fermi level of the first active layer is different from the Fermi level of the second active layer; the lower surface of the first active layer is in contact with the dielectric layer, the upper surface of the first active layer is in contact with the second active layer, and a plurality of first active layer protrusions are provided on the upper surface of the first active layer.

[0058] In this embodiment, see Figure 5As shown, a first active layer 41 and a second active layer 42 are sequentially formed on the dielectric layer 30. The contact surface between the first active layer 41 and the second active layer 42 forms a heterojunction interface. Multiple first active layer protrusions are provided on the upper surface of the first active layer 41. Because these protrusions are arranged sequentially on the upper surface of the first active layer 41, the heterojunction interface exhibits a corrugated structure (also called a concave-convex structure). Specifically, the shape of this corrugated structure is determined by the shape of the first active layer protrusions. For example, the shape of the first active layer protrusions can be at least one of a square, rectangle, triangle, or sphere. Specifically, grooves are formed on the surface of the first active layer 41 by the multiple first active layer protrusions, allowing the second active layer 42 to be embedded in the grooves. Since the semiconductor materials used in the first active layer 41 and the second active layer 42 have different Fermi levels, a potential well will form at their contact interface. At this time, free electrons accumulate in the potential well to form a two-dimensional electron gas. When a positive bias voltage is applied to the thin-film transistor, the two-dimensional electron gas is injected into the first active layer 41. In this embodiment, the first active layer 41 has a higher carrier concentration and electron mobility than the second active layer 42. The injection of two-dimensional electron gas into the first active layer 41 can greatly improve the electromobility and output current of the thin film transistor. Furthermore, when the thin film transistor is negatively biased, the protrusions on the surface of the first active layer 41 increase the resistance of the electron transport path. Free electrons in the second active layer 42 and the first active layer 41 will be confined in the potential well, thereby reducing the leakage current of the thin film transistor and improving the on / off ratio of the thin film transistor.

[0059] In one embodiment, the first active layer 41 is indium tin zinc oxide (ITZO), and the second active layer is indium gallium zinc oxide (IGZO).

[0060] In one embodiment, the first active layer 41 can be formed by sequentially forming active layer films of different thicknesses using two matching photomasks, thereby forming first active layer protrusions that are spaced apart from each other and whose spacing is adjustable, and the shape of the first active layer protrusions can be adjusted by adjusting the process.

[0061] In one embodiment, step B: sequentially forming a second active layer and a first active layer on the surface of the dielectric layer includes steps B1, B2, and B3.

[0062] Step B1: A first photoresist is formed on the upper surface of the dielectric layer using a first photoresist, and multiple first ITZO thin films are formed on the upper surface of the dielectric layer under the masking of the first photoresist.

[0063] In this embodiment, see Figure 5 As shown, a first photoresist 401 is formed on the upper surface of the dielectric layer 30 by a first photoresist, and a plurality of first ITZO thin films 411 are formed under the mask of the first photoresist 401.

[0064] In one embodiment, the thickness of the first ITZO film 411 is 5-10 nm.

[0065] Specifically, in one embodiment, the ITZO layer photomask (i.e., the first photomask in the above embodiment) is sequentially cleaned with acetone, isopropanol, and water. The ITZO layer photomask is used to define the protrusion positions of the ITZO active layer. It is then dried with nitrogen and baked at 50-60°C for 10-20 minutes. A developer solution is prepared with a developer-to-water ratio of 1:1. Next, photoresist is spin-coated onto the upper surface of the dielectric layer 30 at a speed of 3000-4000 rpm for 20-30 seconds. After spin-coating, the sample is baked in a hot plate at 100-105°C for 2-5 minutes, and then aligned and exposed using a photolithography machine. After exposure, the sample is baked at 100-110°C for 5-8 minutes, followed by a second exposure, with the exposure time being 5-10 times longer than the first exposure. Development is then performed in the developer solution for 30-40 seconds, followed immediately by rinsing with deionized water and drying with nitrogen. Next, an ITZO thin film was deposited on the front side of the photoresist using radio frequency magnetron sputtering. The deposition process conditions were argon flow rate of 40-50 sccm, sputtering power of 100W, and deposition time of 40s. The thickness of the first ITZO thin film 411 was 5-10nm.

[0066] Furthermore, in one embodiment, after removing the photoresist, by continuing to deposit ITZO material on the dielectric layer 30, a thinner ITZO film can be formed between the intervals of adjacent first ITZO films 411, thereby forming a first active layer 41 with an uneven upper surface.

[0067] Step B2: A second photoresist is formed on the upper surface of the dielectric layer using a second photoresist, and a plurality of second ITZO thin films are formed on the upper surface of the dielectric layer under the masking of the second photoresist; wherein the thickness of the second ITZO thin film is different from the thickness of the first ITZO thin film, and the first ITZO thin film and the second ITZO thin film are spaced apart to form a first active layer.

[0068] In this embodiment, see Figure 6 As shown, a second photoresist 402 is formed on the upper surface of the dielectric layer 30 using a second photoresist 402, and multiple second ITZO thin films 412 are formed under the mask of the second photoresist 402. The second ITZO thin films 412 have different thicknesses from the first ITZO thin film 411. Since the first photoresist 411 and the second ITZO thin film 412 are matched, the first ITZO thin film 411 and the second ITZO thin film 412 are spaced apart from each other to form a first active layer 41 with an uneven upper surface.

[0069] Specifically, in one embodiment, the sample from step B1 is ultrasonically exfoliated in acetone for 5-8 minutes, revealing that the interfaces of the first ITZO film 411 after development are spaced apart, with the spacing adjustable. Next, the IGZO layer photomask (i.e., the second photomask in the above embodiment) is sequentially cleaned with acetone, isopropanol, and water. The IGZO layer photomask is used to define the protrusion positions of the IGZO active layer. It is then dried with nitrogen and baked at 50-60°C for 10-20 minutes. A developing solution is prepared, with a developing-to-water ratio of 1:1. Next, photoresist is spin-coated a second time on the front side of the ITZO active layer at a spin speed of 3000-4000 rpm for 20-30 seconds. After spin-coating, the sample is baked on a hot plate at 100-105℃ for 2-5 minutes, followed by the first exposure using a photolithography machine. After exposure, the sample is baked at 100-110℃ for 8-10 minutes, followed by a second exposure, which is 5-10 times longer than the first exposure. The sample is then developed in a developer for 30-40 seconds, immediately rinsed with deionized water, and dried with nitrogen. An ITZO film is then deposited again on the front side of the first ITZO film 411 using RF magnetron sputtering to form a second ITZO film 412. The deposition conditions are: argon flow rate of 50 sccm, sputtering power of 100 W, and deposition time of 40 seconds. The thickness of the second ITZO film 412 is 10-40 nm.

[0070] Step B3: Form a second active layer on the first active layer.

[0071] In this embodiment, the interface of the developed ITZO active layer can be seen to have a corrugated structure with varying heights. For example, in one embodiment, the second ITZO film 412 has a thickness of 10 nm, and the first ITZO film 411 has a thickness of 5 nm. Next, IGZO films are deposited on the front side of the ITZO layer using radio frequency magnetron sputtering. The deposition conditions are: argon flow rate of 50 sccm, sputtering power of 100 W, deposition time of 300-400 s, and an IGZO film thickness of 20-50 nm. The sample is then ultrasonically peeled off in acetone for 5-10 seconds. Finally, the sample is annealed at 300°C in a nitrogen atmosphere for 1 hour to obtain the corrugated heterojunction channel layer.

[0072] In one embodiment, step B3: forming a second active layer on the first active layer includes: depositing a second active layer on the first active layer using radio frequency magnetron sputtering; wherein the thickness of the second active layer is greater than the thickness of the first active layer.

[0073] In this embodiment, the second active layer 42 can be formed directly on the first active layer 41 by radio frequency magnetron sputtering, see [link to documentation]. Figure 7As shown, the second active layer 42 is embedded in the groove between the adjacent protrusions of the first active layer. When a positive bias voltage is applied to the thin film transistor, two-dimensional electron gas is injected into the first active layer 41 through the protrusion structure of the second active layer 42.

[0074] In one embodiment, the thickness of the second active layer is 40 nm.

[0075] Step C: Form a source and a drain on the second active layer. The source and the drain are not in contact with each other and are located on opposite sides of the upper surface of the active layer.

[0076] In this embodiment, see Figure 8 As shown, the positions of the source 50 and drain 60 are defined using a source / drain photolithography pattern, and then the source and drain are formed on the active layer 40 by deposition.

[0077] In one embodiment, the source / drain photomask is sequentially cleaned with acetone, isopropanol, and water, dried with nitrogen, and baked at 50-60°C for 10-20 min. A developer solution is prepared with a developer-to-water ratio of 1:1. Photoresist is then spin-coated onto the IGZO active layer surface at a spin speed of 4000 rpm for 30 s, and baked on a hot plate at 100-105°C for 3-5 min. The image is then aligned and exposed using a photolithography machine. After exposure, the image is baked at 100-110°C for 5-8 min, followed by a second exposure, with the exposure time being 5-10 times longer than the first exposure. After the second exposure, the image is developed in the developer solution for 30-40 s, immediately rinsed with deionized water, and dried with nitrogen. An ITO thin film is deposited using radio frequency magnetron sputtering under the following conditions: argon flow rate of 40-50 sccm, sputtering power of 100 W, deposition time of 30 min, and an ITO film thickness of 200-500 nm. Finally, the sample was placed in acetone and sonicated for 5-8 minutes to peel off, and then baked at 100-110℃ for 10-20 minutes.

[0078] In one embodiment, the thickness of the second ITZO film is greater than the thickness of the first ITZO film.

[0079] This application provides a thin-film transistor and its fabrication method. By using a first active layer and a second active layer with different Fermi levels to form an active layer, and providing a plurality of spaced protrusions on the upper surface of the first active layer, a corrugated heterojunction is formed between the second active layer and the first active layer. This not only reduces the leakage current of the amorphous IGZO thin-film transistor, but also improves the on / off ratio of the amorphous IGZO thin-film transistor, solving the problem that existing IGZO thin-film transistors cannot meet new requirements due to their low electromobility and output current.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A thin-film transistor, characterized in that, The device includes a substrate, a gate electrode layer, a dielectric layer, an active layer, a source electrode, and a drain electrode. The gate electrode layer is disposed on the substrate, the dielectric layer is disposed on the surface of the gate electrode layer, and the active layer is disposed on the surface of the dielectric layer. The active layer includes a first active layer and a second active layer, wherein the Fermi level of the first active layer is different from that of the second active layer. The lower surface of the first active layer is in contact with the dielectric layer, and the upper surface of the first active layer is in contact with the second active layer. The upper surface of the first active layer has a plurality of spaced-apart protrusions. The source electrode and the drain electrode are disposed on opposite sides of the upper surface of the second active layer without contacting each other. The first active layer is formed by using a first photoresist to form a first photoresist on the upper surface of the dielectric layer, and forming a plurality of first ITZO thin films on the upper surface of the dielectric layer under the masking of the first photoresist. The second photoresist is formed on the upper surface of the dielectric layer using a second photoresist, and forming second ITZO thin films between adjacent first ITZO thin films under the masking of the second photoresist. The thickness of the second ITZO thin film is different from the thickness of the first ITZO thin film, and the first ITZO thin film and the second ITZO thin film are spaced apart from each other. The second active layer is formed on the first active layer.

2. The thin-film transistor as claimed in claim 1, characterized in that, The first active layer is indium tin zinc oxide, and the second active layer is indium gallium zinc oxide.

3. The thin-film transistor as claimed in claim 1, characterized in that, Multiple first active layer protrusions are periodically arranged on the upper surface of the first active layer, and the lower surface portion of the second active layer is embedded in the groove formed by adjacent first active layer protrusions.

4. The thin-film transistor as claimed in claim 1, characterized in that, The first active layer protrusions are at least one of square, rectangular, triangular and spherical shapes.

5. The thin-film transistor as claimed in claim 1, characterized in that, Multiple first active layer protrusions are integrally formed with the first active layer, and the upper surface of the first active layer is serrated.

6. A method for fabricating a thin-film transistor, characterized in that, include: A dielectric layer is formed on the gate electrode layer; A first active layer and a second active layer are sequentially formed on the surface of the dielectric layer; wherein the Fermi level of the first active layer is different from the Fermi level of the second active layer; the lower surface of the first active layer is in contact with the dielectric layer, the upper surface of the first active layer is in contact with the second active layer, and a plurality of spaced-apart protrusions of the first active layer are provided on the upper surface of the first active layer. A source and a drain are formed on the second active layer, wherein the source and the drain are not in contact with each other and are respectively disposed on opposite sides of the upper surface of the active layer; The step of sequentially forming a first active layer and a second active layer on the surface of the dielectric layer includes: A first photoresist is formed on the upper surface of the dielectric layer using a first photoresist, and multiple first ITZO thin films are formed on the upper surface of the dielectric layer under the masking of the first photoresist; A second photoresist is formed on the upper surface of the dielectric layer using a second photoresist, and a second ITZO film is formed between adjacent first ITZO films under the masking of the second photoresist; wherein the thickness of the second ITZO film is different from the thickness of the first ITZO film, and the first ITZO film and the second ITZO film are spaced apart to form a first active layer. A second active layer is formed on the first active layer.

7. The preparation method according to claim 6, characterized in that, The formation of a dielectric layer on the gate electrode layer includes: At least one of alumina, silicon dioxide, or silicon nitride / silicon dioxide stack is deposited on the front side of the ITO glass.

8. The preparation method according to claim 6, characterized in that, The thickness of the second ITZO film is greater than the thickness of the first ITZO film.

9. The preparation method according to claim 6, characterized in that, The formation of the second active layer on the first active layer includes: A second active layer is deposited on the first active layer using radio frequency magnetron sputtering; wherein the thickness of the second active layer is greater than the thickness of the first active layer.

Images