Method and apparatus for concatenated coding

Abstract

The application provides a concatenated coding method, which can improve decoding performance. The method comprises: performing group coding on an information bit sequence to obtain a plurality of first code words with code length B, B is greater than or equal to 0 and is an integer; performing n-stage polar coding on the plurality of first code words to obtain a second code word with length B x 2 n n is greater than or equal to 1 and is an integer; and outputting the second code word.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of coding, and in particular to a method and apparatus for concatenated coding. BACKGROUND

[0002] Polar codes are a kind of structured channel coding method which is theoretically strictly proved to be able to reach the channel capacity, and have been widely applied and made great progress in recent years. However, with the rapid evolution of wireless communication systems, some new features will appear in future communication systems (for example, 5G). For example, as one of the three most typical communication scenarios in 5G, ultra reliable low latency communication (URLLC) has very high requirements for the reliability and latency of data transmission. The most popular decoding method for polar codes is the successive cancellation list (SCL) decoding algorithm. The SCL decoding algorithm is a bit-by-bit decision and output during decoding, and the decoding delay is relatively large, which needs to be further optimized. SUMMARY

[0003] The present application provides a method and apparatus for concatenated coding, which can reduce the decoding delay of polar codes.

[0004] In a first aspect, a method for concatenated coding is provided, which includes: performing group coding on an information bit sequence to obtain a plurality of first code words with a code length of B, B≥1 and is an integer; performing n-stage polar coding on the plurality of first code words to obtain a second code word with a code length of B×2n, n≥1 and is an integer; and transmitting the second code word. n

[0005] In the technical solution of the present application, the outer code coding of the concatenated coding adopts group coding, and the inner code coding adopts polar coding. During coding, the outer code coding divides the information bit sequence into a plurality of groups for coding respectively, and the plurality of first code words obtained are taken as the input of the polar coding. Since each first code word includes a plurality of bits, the inner code coding actually performs polar coding in units of blocks (i.e., first code words) including a plurality of bits. Therefore, during decoding, it is no longer necessary to perform decision and decoding in units of bits as in the existing SCL decoding algorithm, but decoding is performed in units of blocks. Therefore, the decoding delay can be reduced.

[0006] In combination with the first aspect, in some implementations of the first aspect, performing group coding on the information bit sequence to obtain a plurality of first code words with a code length of B includes: obtaining a target code length N of the second code word and a code length B of the first code word, N=B×2n n ​, N is an integer; grouping the information bit sequence according to the target code length N of the second codeword and the code length B of the first codeword, to obtain a plurality of sub-sequences; determining a generator matrix required for encoding each sub-sequence according to the number of bits included in each sub-sequence of the plurality of sub-sequences; and encoding the plurality of sub-sequences using the generator matrix corresponding to each sub-sequence of the plurality of sub-sequences, to obtain a plurality of first codewords with the code length B.

[0007] With reference to the first aspect, in some implementations of the first aspect, the method further includes: according to the target code length N and the code length B of the first codeword, if it is determined that there is no positive integer R such that R = 2 n , selecting a positive integer L, and performing m-stage polar encoding on the plurality of first codewords with the code length B, to obtain a third codeword with the code length B x L, L = 2 m , L > R, m > n, m, L and R are positive integers; and performing rate matching on the third codeword with the code length B x L, to obtain the second codeword with the code length B x 2 n .

[0008] With reference to the first aspect, in some implementations of the first aspect, each sub-sequence of the information bit sequence can be encoded using any one of the following codes: repetition code, BCH code, simplex code, dual code of the simplex code, polar code, parity check code, and dual code of the repetition code of the simplex code.

[0009] The second aspect provides an encoding apparatus having the functions of implementing the method of the first aspect and any possible implementation thereof. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0010] In a possible design, when part or all of the functions are implemented by hardware, the encoding apparatus includes: an input interface circuit configured to obtain an information bit sequence to be encoded; a logic circuit configured to group and encode the information bit sequence, to obtain a plurality of first codewords with the code length B, B > 0 and is an integer; perform n-stage polar encoding on the plurality of first codewords, to obtain a second codeword with the length B x 2 n , n > 1 and is an integer; and an output interface circuit configured to output the second codeword.

[0011] In the technical solution of the present application, the outer code of the concatenated coding adopts group coding, and the inner code adopts polar coding. During coding, the outer code divides the information bit sequence into multiple groups for coding respectively, and the obtained multiple first codewords are taken as the input of the polar coding. Since each first codeword includes multiple bits, the inner code actually performs polar coding in units of blocks (i.e., first codewords) including multiple bits. Thus, during decoding, it is no longer necessary to make decisions and decoding in units of bits as in the existing SCL decoding algorithm, but decoding in units of blocks. Thus, the decoding delay can be reduced.

[0012] In a specific implementation, the encoding apparatus can be a chip or an integrated circuit.

[0013] In a possible design, when part or all of the functions are implemented by software, the encoding apparatus includes a memory for storing a computer program, and a processor for executing the computer program stored in the memory. When the computer program is executed, the encoding apparatus can implement the method of the concatenated coding according to the first aspect and any possible implementation of the first aspect.

[0014] Optionally, the memory can be a physically independent unit, or can be integrated with the processor.

[0015] In a possible design, when part or all of the functions are implemented by software, the encoding apparatus includes only the processor. The memory for storing the program is located outside the encoding apparatus, and the processor is connected with the memory through a circuit / wire, for reading and running the program stored in the memory, to implement the method of the concatenated coding according to the first aspect and any possible implementation of the first aspect.

[0016] In a third aspect, the present application provides a decoding method, which includes: obtaining a bit sequence to be decoded, the length of the bit sequence to be decoded being N, N being a positive integer; performing SCL decoding on the bit sequence to be decoded to obtain N / B sub-code blocks, performing hard decision on the bits in each of the N / B sub-code blocks to obtain a hard decision result of each sub-code block, and querying a symptom diagnosis table according to the hard decision result of each sub-code block to obtain multiple candidate codewords of each sub-code block; calculating the path metric values of the multiple candidate codewords of each sub-code block, and determining a decoding path of each sub-code block according to the path metric values of the multiple candidate codewords of each sub-code block; and sequentially outputting the multiple decoding paths corresponding to the multiple sub-code blocks as a decoding result.

[0017] In a fourth aspect, the present disclosure provides a decoding apparatus having the functions of implementing the method in the third aspect and any possible implementation of the third aspect. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0018] In a possible design, when part or all of the functions are implemented by hardware, the decoding apparatus includes: an input interface circuit, configured to acquire a bit sequence to be decoded; a logic circuit, configured to perform the decoding method in the third aspect to decode the bit sequence to be decoded to obtain a decoding result; and an output interface circuit, configured to output the decoding result.

[0019] Optionally, the decoding apparatus can be a chip or an integrated circuit.

[0020] In a possible design, when part or all of the functions are implemented by software, the decoding apparatus includes: a memory, configured to store a computer program; and a processor, configured to execute the computer program stored in the memory, and when the computer program is executed, the decoding apparatus can implement the decoding method in the third aspect.

[0021] Optionally, the memory can be a physically independent unit, or can be integrated with the processor.

[0022] In a possible design, when part or all of the functions are implemented by software, the decoding apparatus includes only the processor. The memory for storing the program is located outside the decoding apparatus, and the processor is connected with the memory through a circuit / wire, for reading and running the program stored in the memory to execute the decoding method in the third aspect.

[0023] In a specific implementation, the decoding apparatus can be a chip or an integrated circuit.

[0024] In a fifth aspect, the present disclosure provides a network device including a transceiver, a processor and a memory. The processor is configured to control the transceiver to transceive signals, and the memory is configured to store a computer program. The processor is configured to invoke and run the computer program stored in the memory, so that the network device executes the method in any possible implementation of the first aspect or the second aspect.

[0025] Specifically, when the network device is a sending end of information and / or data, the network device executes the concatenation encoding method in the first aspect and any possible implementation of the first aspect to perform concatenation encoding on information and / or data to be sent. When the network device is a receiving end of information and / or data, the network device executes the decoding method in the third aspect to decode a bit sequence to be decoded received from the sending end.

[0026] In a sixth aspect, the present application provides a terminal device, comprising a transceiver, a processor and a memory. The processor is configured to control the transceiver to transceive signals, and the memory is configured to store a computer program. The processor is configured to invoke and run the computer program stored in the memory, so that the terminal device executes the method in any possible implementation manner of the first aspect or the second aspect.

[0027] Specifically, when the terminal device is a sending end of information and / or data, the terminal device executes the concatenation encoding method in the first aspect and any possible implementation manner thereof to perform concatenation encoding on information and / or data to be sent. When the terminal device is a receiving end of information and / or data, the terminal device executes the decoding method in the third aspect to decode a bit sequence to be decoded received from the sending end.

[0028] In a seventh aspect, the present application provides a computer readable storage medium, which stores instructions, when the instructions are run on a computer, the computer executes the method in the first aspect or any possible implementation manner of the first aspect.

[0029] In an eighth aspect, the present application provides a computer program product, which comprises computer program codes, when the computer program codes are run on a computer, the computer executes the method in the first aspect and any possible implementation manner thereof.

[0030] In a ninth aspect, the present application provides a chip, which comprises a processor. The processor is configured to read and execute a computer program stored in a memory, so as to execute the method in the first aspect or any possible implementation manner of the first aspect. Optionally, the chip further comprises the memory, which is connected to the memory through a circuit or a wire. Further optionally, the chip further comprises a communication interface, which is connected to the processor. The communication interface is configured to receive a bit sequence to be encoded. The processor obtains the information bit sequence from the communication interface, and performs concatenation encoding on the information bit sequence by using the concatenation encoding method described in the first aspect. The communication interface outputs the encoded bit sequence. The communication interface can be an input / output interface.

[0031] In a tenth aspect, the present application provides a computer readable storage medium, which stores instructions, when the instructions are run on a computer, the computer executes the method in the third aspect or any possible implementation manner of the third aspect.

[0032] In an eleventh aspect, the present application provides a computer program product, which comprises computer program codes, when the computer program codes are run on a computer, the computer executes the method in the third aspect or any possible implementation manner of the third aspect.

[0033] In a twelfth aspect, the present application provides a chip comprising a processor. The processor is configured to read and execute a computer program stored in a memory to perform the method in the third aspect or any possible implementation manner of the third aspect.

[0034] Optionally, the chip further comprises a memory connected to the processor via a circuit or a wire. Further optionally, the chip further comprises a communication interface connected to the processor. The communication interface is configured to receive a bit sequence to be decoded. The processor obtains the bit sequence to be decoded from the communication interface, and decodes the bit sequence to be decoded by using the decoding method in the third aspect to obtain a decoding result. The communication interface outputs the decoding result. The communication interface can be an input / output interface.

[0035] In a thirteenth aspect, the present application provides a communication system comprising the network device in the fifth aspect and the terminal device in the sixth aspect.

[0036] In the technical solution of the present application, the outer code encoding of the concatenated encoding adopts block encoding, and the inner code encoding adopts polar encoding. During encoding, the information bit sequence is divided into multiple groups for encoding by the outer code encoding, and the obtained multiple first code words are used as the input of the polar encoding. Since each first code word comprises multiple bits, the inner code encoding is actually polar encoding in units of blocks (i.e., first code words) comprising multiple bits. Therefore, during decoding, it is no longer necessary to make decisions and decoding in units of bits as in the existing SCL decoding algorithm, but decoding in units of blocks. Therefore, the decoding delay can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is an architecture diagram of a wireless communication system 100 suitable for embodiments of the present application.

[0038] Figure 2 FIG. 2 is a basic flowchart of communication using wireless technology.

[0039] Figure 3 FIG. 3 is a schematic diagram of polar encoding.

[0040] Figure 4 FIG. 4 is a schematic diagram of input and output of an F2 polar network.

[0041] Figure 5 FIG. 5 is a schematic flowchart of the concatenated encoding 200 provided by the present application.

[0042] Figure 6 FIG. 6 is a schematic diagram of the polar process of a block code with B=3.

[0043] Figure 7is a performance comparison diagram of a concatenated code with N=256 and K=124 and a polar code.

[0044] Figure 8 is a performance comparison diagram of a concatenated code with N=1024 and K=512 and a polar code.

[0045] Figure 9 is a schematic block diagram of the communication apparatus 500 provided in the present application.

[0046] Figure 10 is a schematic structural diagram of the communication apparatus 600 provided in the present application.

[0047] Figure 11 is a schematic diagram of the internal structure of the processing apparatus 601.

[0048] Figure 12 is a schematic block diagram of the communication apparatus 700 provided in the present application.

[0049] Figure 13 is a schematic block diagram of the communication apparatus 800 provided in the present application.

[0050] Figure 14 is a schematic diagram of the internal structure of the processing apparatus 802.

[0051] Figure 15 is a schematic structural diagram of the network device 3000 provided in the present application.

[0052] Figure 16 is a schematic structural diagram of the terminal device 900 provided in the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0054] Referring to Figure 1 , Figure 1 is an architecture diagram of a wireless communication system 100 suitable for embodiments of the present application. As Figure 1 indicated. The wireless communication system 100 can include at least one network device, one or more terminal devices. The network device (such as 101 shown in Figure 1 ) can perform wireless communication with the one or more terminal devices (such as 102 and 103 shown in Figure 1 ).

[0055] The wireless communication system involved in the present application includes but is not limited to global system of mobile communication (GSM) system, code division multiple access (CDMA) system, wideband code division multiple access (WCDMA) system, general packet radio service (GPRS), long term evolution (LTE) system, frequency division duplex (FDD) system of LTE, time division duplex (TDD) system of LTE, universal mobile communication system (UMTS), worldwide interoperability for microwave access (WiMAX) communication system, three major application scenarios of next-generation 5G mobile communication system, namely, enhanced mobile broadband (eMBB), ultra reliable low latency communication (URLLC) and enhanced massive machine type communication (eMTC), or new communication system to be appeared in the future, etc.

[0056] The terminal device can be a user equipment (UE), a terminal, an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device. The terminal device can also be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device having wireless communication function, a computing device, or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a future 5G network, or a terminal device in a future evolved public land mobile network (PLMN), etc. The present application is not limited in this regard.

[0057] The network device can be a device for communicating with the terminal device. The network device can be a base station, a device integrated with a base station controller, or other devices with similar communication functions. The base station can be a base transceiver station (BTS) in a global system of mobile communication (GSM) system or a code division multiple access (CDMA) system, a base station (nodeB, NB) in a wideband code division multiple access (WCDMA) system, an evolved nodeB (eNB or eNodeB) in a long term evolution (LTE) system, a radio controller in a cloud radio access network (CRAN) scenario, or a relay station, an access point, a vehicle-mounted device, a wearable device, and a network device in a future 5G network, etc. The present application is not limited in this regard.

[0058] Figure 1In this system, network devices and terminal devices communicate using wireless technology. When a network device sends a signal, it acts as the transmitter; when it receives a signal, it acts as the receiver. The same applies to terminal devices: when a terminal device sends a signal, it acts as the transmitter; when it receives a signal, it acts as the receiver.

[0059] Figure 2 This is a basic flowchart of communication using wireless technology. The signal source at the transmitting end undergoes source coding, channel coding, rate matching, and modulation sequentially before being transmitted over the channel. The receiving end receives the signal and then performs demodulation, rate matching dematching, channel decoding, and source decoding sequentially to obtain the final signal.

[0060] Channel coding and decoding is one of the core technologies in the field of wireless communication, and its performance improvement directly enhances network coverage and user transmission rates. Currently, polar codes are a channel coding technique that can be theoretically proven to reach the Shannon limit and possesses practical linear complexity coding and decoding capabilities. Polar codes are linear block codes, and their coding matrix (also called the generator matrix) is F. N The encoding process can be represented by the following formula:

[0061]

[0062] in, It is a binary row vector (i.e., a sequence of information bits) with a length of N, where N = 2. n , where n is a positive integer. F N It is an N×N matrix. Defined as log2 N The Kronecker product of matrices F2, The addition and multiplication operations involved in the above formulas are all addition and multiplication operations on the binary Galois field.

[0063] The encoding generated by this method will exhibit polarization when decoded using a successive cancellation (SC) decoding method. That is, a portion of the bits in u will be decoded correctly with a high probability after passing through an equivalent high-reliability channel, while the remaining bits will be decoded correctly with a low probability after passing through an equivalent low-reliability channel. Therefore, the high-reliability channel can be used for information transmission, while the bits corresponding to the low-reliability channel can be set to zero (i.e., frozen) and not used for data transmission, or for transmitting data already known to both communicating parties.

[0064] See Figure 3 , Figure 3 This is a schematic diagram of polar code encoding. (Example) Figure 3 As shown, the symbol represents binary addition, whose input is left and bottom, and output is right. Figure 3 Each solid line in the figure represents 1 bit. We set {u1, u2, u3, u5} as frozen bits, and polar encode {u4, u6, u7, u8} which is 4 information bits, to obtain 8 encoded bits. After encoding, the 8 encoded bits are modulated and sent through a noisy channel.

[0065] From the encoding process of the polar code, it can be seen that, from the information bits, the polar network is polarized. The input and output relationship of the F2 polar network can be seen from FIG. 2. Figure 4

[0066] Referring to FIG. 2, Figure 4 Figure 4 is an input and output schematic diagram of the F2 polar network. The input and output relationship shown in FIG. 2 can be described by a formula, which can be represented as: Figure 4

[0067] [x0x1]=[μ0μ1]×F2 (2)

[0068] Where [x0x1] and [u0, u1] are binary vectors, and all operations are also performed in the binary field.

[0069] According to the above polar encoding principle, the decoding of the polar code adopts the SCL decoding algorithm. When the SCL decoding algorithm is used for decoding, the decoder is bit by bit to make a decision and output, and the decoding delay is large.

[0070] Therefore, the application provides a cascaded encoding method, which can reduce the decoding delay and improve the decoding performance of the polar code.

[0071] For ease of understanding, first, the cascaded encoding is simply introduced.

[0072] ​​​When channel coding techniques are applied in practice, many practical factors such as efficiency, performance and latency need to be considered. According to channel coding theory, as the code length N increases, the decoding error probability tends to zero exponentially. Therefore, in order to improve the effectiveness of error correction codes, long codes must be used. However, as the code length increases, the code rate decreases accordingly, and the complexity and computational load of the decoder also increase accordingly. Concatenated codes are proposed to solve this contradiction. The encoding process is divided into several stages to meet the requirements of channel error correction for encoding length, and to obtain close to or even the same error correction capability and high coding gain as long codes. Moreover, the increasing complexity of encoding and decoding is not very large. In other words, if a system includes multiple (at least two) encodings, the multiple encodings are considered to be concatenated encodings. Concatenated coding includes outer code encoding and inner code encoding. The input of the outer code encoding is the information bit sequence to be encoded, and the output of the outer code is used as the input of the inner code. The output of the inner code encoding is the code word after the completion of the concatenated encoding. It should be understood that the outer code and the inner code are a relative concept. For example, if a system includes three encodings, the first encoding relative to the second encoding is outer code encoding, and the second encoding relative to the first encoding is inner code encoding. After the first encoding is completed, the second encoding relative to the third encoding is outer code encoding, and the third encoding relative to the second encoding is inner code encoding. For example, if a system includes two encodings, the first encoding is outer code encoding, and the second encoding is inner code encoding. The output of the outer code encoding is used as the input of the inner code encoding.

[0073] In the technical solutions provided in the present application, the concatenated coding involves two encodings. Among them, the outer code of the concatenated coding adopts group coding, and the inner code coding adopts polar coding.

[0074] Referring to Figure 5 , Figure 5 is a schematic flowchart of the concatenated coding method 200 provided in the present application. The method 200 can be executed by a sending end.

[0075] 210. Group coding the information bit sequence to obtain a plurality of first code words with a code length B.

[0076] Wherein, B>1 and is an integer.

[0077] In step 210, the encoder obtains the information bit sequence to be encoded, and group codes the information bit sequence to obtain a plurality of first code words.

[0078] Here, the length B of the first code word is preset. It should be understood that step 210 is a group coding process. Group coding is to divide the information bit sequence to be encoded into a plurality of groups, and encode each group to obtain a plurality of first code words with a code length B. How to group the information bit sequence can refer to the prior art, which will not be described in detail in the present application.

[0079] The code length B of a block code is related to the complexity and latency of decoding. The code length B of a block code can be set by considering a trade-off between complexity and latency.

[0080] 220. Perform n-level polarization encoding on the multiple first codewords to obtain a codeword of length B×2. n The second character.

[0081] Where n ≥ 1 and is an integer.

[0082] In step 220, the transmitting end performs n-level polar coding on the multiple first codewords obtained from the group coding in step 210, resulting in a codeword of length B×2. n The second character.

[0083] If the length of the first codeword is B, and in step 220, the transmitting end performs n-level polarization encoding on the first codeword (or, in other words, performs n polarizations), then the length of the resulting concatenated code is B×2. n .

[0084] Since B ≥ 1 and is an integer, 2 n Since the length of the concatenated code is a power of 2, B×2 n The size can be arbitrary. In other words, according to the concatenation coding method provided in this application, concatenation codes of arbitrary length can be generated.

[0085] In the technical solution of this application, the outer code encoding of the concatenated encoding adopts block encoding, and the inner code encoding adopts polar encoding. Specifically, the outer code encoding divides the information bit sequence into multiple groups and encodes them separately, and the resulting multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually performed polar encoding on a block basis (i.e., first codeword) containing multiple bits. Therefore, during decoding, it is no longer necessary to make decisions and decode on a bit-by-bit basis as in the existing SCL decoding algorithm, but rather to decode on a block-by-block basis. This reduces decoding latency.

[0086] In step 210 above, the information bit sequence is grouped and encoded to obtain multiple first codewords of code length B, including:

[0087] Obtain the target code length N of the second codeword and the code length B of the first codeword, where N = B × 2. n N is an integer;

[0088] Based on the target code length N of the second codeword and the code length B of the first codeword, the information bit sequence is grouped to obtain multiple subsequences;

[0089] determining a generator matrix required for performing the block encoding on each of the sub-sequences according to the number of bits included in each of the sub-sequences;

[0090] performing block encoding on the plurality of sub-sequences using the generator matrix corresponding to each of the sub-sequences to obtain a plurality of first code words with a code length of B.

[0091] It should be understood that when encoding, a desired code length N after encoding (i.e., target code length) is usually required to be set. In the present application, the target code length N is the code length of the concatenated code (i.e., second code word) finally output by the encoder. Therefore, N = B x 2 n .

[0092] As introduced above, the code length of the block code is also pre-set when block encoding. The block code refers to the output of the block encoding, i.e., the first code word in the present application. That is, before performing the concatenated encoding, the pre-set target code length N and the code length B of the block code are obtained. According to the target code length and the code length B of the block code, the information bit sequence to be encoded is determined to be divided into several groups. Here, the process of grouping the information bit sequence involved in the block encoding can refer to the prior art, which will not be described in detail here.

[0093] After grouping the information bit sequence, a plurality of sub-sequences are obtained, each of which includes one or more bits, or some of the sub-sequences can not include bits. Next, a generator matrix required for performing the block encoding on each of the sub-sequences is determined according to the generator matrix corresponding to each of the sub-sequences.

[0094] Here, the plurality of sub-sequences obtained after grouping the information bit sequence can also be considered as a plurality of sub-blocks of the information bit sequence. That is, each sub-sequence is a sub-block of the information bit sequence, or is also called a sub-code block.

[0095] It should be understood that after the information bit sequence is divided into a plurality of sub-sequences, each sub-sequence will be encoded into a first code word with a length of B. The number of bits included in the plurality of sub-sequences is not the same, and therefore, the generator matrix required for encoding each sub-sequence needs to be determined according to the number of bits included in the sub-sequence. That is, each of the plurality of sub-sequences corresponds to a respective generator matrix. The plurality of sub-sequences are encoded using the plurality of generator matrices to obtain a plurality of first code words, each of which has a code length of B.

[0096] It can be known from the above description that N and B satisfy N = B x 2 nwhere n is the number of polarizations in step 220. If N and B are usually set according to the coding requirement, there can be a case that after the target code length N and the code length B of the first codeword are set, there is no positive integer R that satisfies R = 2 n . For example, the target code length N = 20, and the length B of the first codeword = 3. At this time, a positive integer L can be selected first, such that L = 2 m , m > n, and the plurality of first codewords with the code length B are polarized to obtain the third codeword with the code length B x 2 m . Next, rate matching is performed on the third codeword to finally obtain the second codeword with the code length B x 2 n . For example, N = 20, B = 3, and 2 m＝ 8 (i.e., m = 3) is selected. That is, after step 210, the information bit sequence is first grouped and coded to obtain a plurality of first codewords with the code length 3, and next, in step 220, the plurality of codewords with the code length 3 are polarized to obtain the codeword (denoted as the third codeword) with the length 3 x 2 3 . Finally, rate matching (for example, by puncturing 4 bits) is performed on the third codeword with the code length 24 to finally obtain the second codeword with the length 20.

[0097] According to the technical solution of the present application, in the case that the target code length N and the code length B of the grouped code (i.e., the first codeword) are set, if there is a positive integer R = 2 n that satisfies N = B x R, the codeword with the target code length can be directly obtained after the concatenated coding. Compared with the polar coding that can only generate the code length of an integer power of 2, rate matching is not required.

[0098] Further, if in the case that the target code length N and the code length B of the grouped code (i.e., the first codeword) are set, there is no positive integer R = 2 n that satisfies N = B x R, a codeword close to the target code length can be first generated according to the concatenated coding method of the present application, and then a small amount of rate matching is performed on the codeword, and the codeword with the target code length can also be obtained.

[0099] Optionally, when L is selected, L = 2 m is usually selected, and B x L > N and is closest to N. In this way, the number of bits that need to be rate matched subsequently can be reduced. For example, N = 20, B = 3, and L = 2 m 8 are selected, which satisfies that L is a power of 2 and B x L is closest to 20.

[0100] Of course, L can also be selected to satisfy only L = 2 m , but B x L is not necessarily closest to N. The present application is not limited in this regard.

[0101] 230. transmitting the second codeword.

[0102] After the encoder finishes the concatenated encoding, the second codeword is transmitted to the receiving end.

[0103] It should be understood that before the second codeword is transmitted, a small amount of rate matching, modulation, resource mapping, etc. as mentioned above can also be needed. These processes can be referred to the prior art, and will not be described here.

[0104] In the method 200, the step 210 and the step 230 can be performed by an encoder of the transmitting end. The step 230 can be performed by a transceiver of the transmitting end. Specifically, after the encoder finishes the step 210 and the step 220, the second codeword can be output to the transceiver for transmission by the transceiver. Alternatively, the encoder can also perform rate matching, modulation mapping, etc. on the second codeword and then transmit the second codeword after the rate matching and modulation mapping to the transceiver, and the transceiver transmits the second codeword to the receiving end.

[0105] Optionally, as an implementation manner, the encoder performing the step 210 and the step 220 of the method 200 can include an outer code encoder and an inner code encoder.

[0106] Specifically, the outer code encoder obtains the information bit sequence, and performs group encoding on the information bit sequence to obtain a plurality of first codewords with a code length of B, and completes the outer code encoding. After the outer code encoding is completed, the outer code encoder inputs the plurality of first codewords to the inner code encoder. The inner code encoder receives the plurality of first codewords from the outer code encoder, performs n-stage polar encoding on the plurality of first codewords to obtain a second codeword, and completes the inner code encoding. After the inner code encoding is completed, the inner code encoder outputs the second codeword.

[0107] Optionally, after the outer code encoder outputs the first bit sequence, before inputting the inner code encoder, the first bit sequence can be bit interleaved, and then the interleaved bit sequence is input to the inner code encoder for inner code encoding.

[0108] Further, in order to obtain better decoding performance, when performing the outer code encoding in the step 210, the following factors can be considered to select a group code as the outer code.

[0109] (1) Select a group code that can support parallel decoding.

[0110] (2) Avoid some intermediate code rates.

[0111] (3) Consider larger minimum distance and better distance spectrum.

[0112] (4) For various outer code rates, the optimal block code can be selected.

[0113] Considering these factors, some block codes with good distance spectrum characteristics and high decoding parallelism are selected as outer codes. Finally, multiple block codes are concatenated and polarized by a F N polar network. In this way, the decoding parallelism can be improved and the latency can be reduced. At the same time, since the code length of the outer code block code does not need to be an integer power of 2, the code length of the final concatenated code also has more choices, and the rate matching process can be omitted or only a small amount of rate matching is required.

[0114] Two examples of B = 3 and B = 16 are given below to illustrate the above-mentioned concatenated encoding process.

[0115] 1. The length of the first code word is B = 3.

[0116] Referring to Figure 6 , Figure 6 is a schematic diagram of the polarization process of the block code with B = 3. As Figure 6 shown, assuming the information bit sequence is [u0u1u2u3u4u5], and assuming the information bit sequence is divided into the following 4 sub-sequences: [u0], [u1u2], [u3u4u5]. Among them, indicates that the sub-sequence does not contain bits. The number of bits contained in each sub-sequence can also be referred to as the information length of the sub-sequence. According to the information length of each sub-sequence, its corresponding generator matrix can be represented as:

[0117] When the information length is 0, the generator matrix can be represented as

[0118] When the information length is 1, the generator matrix can be represented as G1 =

[111] ;

[0119] When the information length is 2, the generator matrix can be represented as

[0120] When the information length is 3, the generator matrix can be represented as

[0121] Here, the information length of 0 can be understood as no information input.

[0122] (1) Outer code encoding.

[0123] In this application, the outer code encoding adopts block encoding.

[0124] For the above information lengths of 0, 1, 2 and 3, the process of outer code encoding can be represented as:

[0125] [o0 o1 o2] = [0 0 0]

[0126] [o3 o4 o5] = [u0] x [1 1 1]

[0127]

[0128]

[0129] The information bit sequence [u0 u1 u2 u3 u4 u5] is subjected to outer code encoding, and finally four code words are output, which are [o0 o1 o2], [o3 o4 o5], [o6 o7 o8] and [o6 o7 o8], and the code length of each code word is 3. Each code word here is the first code word in the present application.

[0130] (2) Inner code encoding.

[0131] In the present application, the inner code encoding is polarization encoding.

[0132] Continuing to refer to Figure 5 , the polarization process of the outer code word can be expressed as:

[0133] [x0 x3 x6 x9] = [o0 o3 o6 o9] x F4

[0134] [x1 x4 x7 x 10 ] = [o1 o4 o7 o 10 ] x F4

[0135] [x2 x5 x8 x 11 ] = [o2 o5 o8 o 11 ] x F4

[0136] In fact, it can also be considered that the above four first code words are spliced to obtain o = [o0, o1,..., o 11 , and the spliced code word is subjected to polar encoding. After the inner code encoding using the polar code, the final output of the concatenated code is x = [x0, x1,..., x 11 . That is, the second code word in the present application.

[0137] According to the method for concatenated encoding provided in the present application, assuming that the total information length of the block code is K when the outer code encoding is performed, and the information length of the i-th sub-code block of the block code is K i , then the following is satisfied:

[0138]

[0139] If the above process of concatenated encoding can be written in a general formula, it can be expressed as:

[0140] When encoding the outer code, for i∈{1,2,...,N}, perform

[0141]

[0142] In formula (4), is the K i information bits of the i-th sub-code block of the block code before encoding, is the B code word bits after encoding of the i-th sub-code block. is the generator matrix of the i-th sub-code block, with size K i ×B.

[0143] When encoding the inner code, for j∈{1,2,...,B}

[0144]

[0145] In formula (5), is the N bits to be polar coded, which are composed of the j-th code word bits of each sub-code block, is the bit after polar coding.

[0146] The above detailed the process of the cascade coding of the outer code provided by the present application using a block code and the inner code using a polar code. Next, an example of a hybrid block code is given in combination with Table 1,

[0147] 2, the code length B of the first code word is 16.

[0148] For the sake of simplicity in description, first group the information bit sequence, and then the information length of the subsequence is denoted as K, K is an integer. It should be understood that K≤B.

[0149] Table 1

[0150]

[0151]

[0152] It should be understood that the first column of Table 1 represents the information length of the subsequence. The second column of Table 1 represents the code selected as the outer code when performing concatenation coding. The second column of Table 1 corresponds to the information length of the subsequence of the first column. For example, if a certain subsequence has an information length of 1 after grouping the information bit sequence, the repetition code is selected as the outer code to perform the outer code coding of step 210. For another example, if a certain subsequence has an information length of 6, the eBCH code is selected as the outer code to perform the outer code coding of step 210. Other information lengths are similar and will not be described one by one. The third column of Table 1 represents the generator matrix used when performing the outer code coding. The third column of Table 1 also corresponds to the second column and the first column one by one. For example, when the information length of the subsequence is 1, the repetition code is used to perform the outer code coding, and the generator matrix G1 is used when performing the outer code coding. For another example, when the information length of the subsequence is 3, the repetition code of the simplex code is used to perform the outer code coding, and the generator matrix G3 is used when performing the outer code coding.

[0153] It should be noted that G in the third column of Table 1 is the generator matrix, and the matrix S is listed for the purpose of simplifying the representation of the generator matrix G. The matrix H is the check matrix of some codes, and the generator matrix can be determined according to the check matrix H. According to the definition of the dual code, if code A is the dual code of code B, the generator matrix of code B is the same as the generator matrix of code A. For example, when the information length of the subsequence is 9, the dual code of the eBCH code is used to perform the outer code coding on the subsequence, and therefore, the check matrix H9 of the dual code of the eBCH code is equal to the generator matrix of the eBCH code.

[0154] The grouping codes involved in Table 1 are as follows:

[0155] (1) Repetition code.

[0156] The repetition code is to repeatedly transmit each bit to be transmitted, or to encode each source bit into multiple identical bits. For example, the binary repetition code (3, 1) encodes each 0 in a binary bit sequence into 000 and each 1 into 111. Therefore, when the information sequence length is 1, the generator matrix of the repetition code is a 16-bit all-1 matrix.

[0157] (2) Simplex code.

[0158] The simplex code has a large code distance for codes with a short information length of the subsequence. The required code length can be obtained by repeating it.

[0159] (3) eBCH code.

[0160] BCH code is taken from the initials of Bose, Ray-Chaudhuri and Hocquenghem, and is a coding method that is studied more in coding theory, especially error correction code. The extended BCH code (eBCH) is obtained by extending the BCH code, and has the characteristics of simple construction and large minimum distance in known codes.

[0161] (4) Dual code.

[0162] The linear block code generated by taking the uniform parity check matrix of the linear block code as the generator matrix is called the dual code of the original linear block code. Therefore, it can be understood that when the length of the information sequence is 9 or 10, the linear block code generated by taking the uniform parity check matrix of the eBCH code as the generator matrix is the dual code of the eBCH code.

[0163] (5) Parity check code.

[0164] The parity check code is a coding method that makes the number of "1"s in the codeword constant by adding redundant bits to the codeword. Among them, the single-bit parity check code refers to a code with only one parity check bit.

[0165] In the case of B = 16, after grouping the information bit sequence, a plurality of sub-sequences are obtained, and according to the information length of each sub-sequence, the corresponding outer code and generator matrix are selected from Table 2 to perform outer code encoding on the sub-sequence, to obtain a plurality of first codewords. Finally, the plurality of first codewords obtained by performing outer code encoding on all sub-sequences are subjected to inner code encoding to obtain a concatenated code.

[0166] It should be noted that the polar code itself can be regarded as a concatenated coding of the polar outer code and the polar inner code. If the grouping code with B = 16 shown in Table 2 is used to replace the polar outer code, better decoding performance and decoding delay can be obtained.

[0167] It should be understood that the outer code of the polar code is replaced by the grouping code, that is, the outer code encoding of the polar code uses the grouping code described in the present application. The first codeword output after grouping coding is subjected to polar inner code encoding.

[0168] If the grouping code is used as the outer code of the polar code, compared with the polar code, the code distance spectrum comparison can be seen in Table 2

[0169] Table 2

[0170]

[0171] In the case of B = 16, the value of K is 0-16. Among them, when K = 0, it can be considered that no information bits are input, and Table 2 is not listed. When K = 1, a repetition code is used, and the specific method is to repeat the information bits in the sub-block 16 times to obtain, and Table 2 is also not listed, and Table 1 can be referred to. When K = 16, it can be considered that the input sub-block that needs to be encoded by the outer code includes 16 bits, and the code word output after completing the outer code encoding also contains 16 bits, so no encoding is needed, and Table 2 is also not listed, and Table 1 can be referred to. For other values of K, refer to Table 2.

[0172] As shown in Table 2, the first row of Table 2 represents the code weight, that is, the number of 1s in the code word, and the numbers in the corresponding column represent the number of code words with the code weight. For a code, the code weight distribution of all code words (such as a row in Table 2, not the first row) is the distance spectrum of the code. The first column of Table 2 represents the encoding method used by the outer code of the polar code. The second column of Table 2 represents the information length K of a sub-block (also referred to as a sub-sequence). For example, the information bit sequence is [u0 u1 u2 u3 u4 u5], which is divided into [u0], [u1 u2] and [u3 u4 u5] three sub-blocks. The information length of the first sub-block [u0] is equal to 1, so the repetition code corresponding to K = 1 is selected for outer code encoding, and the generator matrix used for outer code encoding is G1 (see Table 1). The information length of the second sub-block [u1 u2] is equal to 2, so the simplex code corresponding to K = 2 is selected from Table 2 for outer code encoding, and the generator matrix used for outer code encoding is G2. The information length of the third sub-block [u3 u4 u5] is equal to 3, so the simplex code corresponding to K = 3 is selected from Table 2 for outer code encoding, and the generator matrix used for outer code encoding is G3. Since B is set to 16, after the first level of outer code encoding of the three sub-blocks, three first code words with a code length of 16 are output. Subsequently, the first code words with a code length of 16 are spliced and subjected to n-level polar encoding to output a second code word, that is, a concatenated code word, and the code length is B x 2 n = 16 x 2 n .

[0173] Given the value of K, two corresponding rows can be found in Table 2, one of which is the distance spectrum when the outer code and the inner code both use polar codes, and the other is the distance spectrum when the outer code uses a block code and the inner code uses a polar code. In these two rows, the value of the first non-zero element represents the number of code weights in the column where the non-zero element is located. Among them, the later the non-zero element appears in the row, the larger the corresponding code weight, indicating better performance. At the same time, for the same code weight, the smaller the corresponding non-zero element, the fewer the number of code weights, the less likely it is to occur error, indicating better performance. The following is an example.

[0174] For example, when K = 2, the first nonzero element of the row corresponding to the polar encoding is 2, and the code weight corresponding to the first nonzero element is 8, indicating that there are 2 rows with a code weight of 8. The first nonzero element of the row corresponding to the Simplex encoding is 1, and the code weight corresponding to the first nonzero element is 10, indicating that there is 1 row with a code weight of 10. According to the above principle for judging the decoding performance, the greater the code weight corresponding to the first nonzero element, the better the performance. Further, the smaller the value of the first nonzero element, the better. As can be seen, when K = 2, the performance of the Simplex encoding is better than that of the polar encoding.

[0175] For another example, when K = 3, the first nonzero element of the row corresponding to the polar encoding is 6, and the code weight corresponding to the first nonzero element is 8, indicating that there are 6 rows with a code weight of 8. The first nonzero element of the row corresponding to the Simplex encoding is 1, and the code weight corresponding to the first nonzero element is also 8, indicating that there is 1 row with a code weight of 8. In this example, the positions of the first nonzero elements of the two rows are the same, and the sizes of the nonzero elements are considered. Obviously, there are 6 rows with a code weight of 8, and the probability of error is higher than that of only one row with a code weight of 8. Therefore, when K = 3, the performance of the Simplex encoding is better than that of the polar encoding.

[0176] For another example, when K = 6, the first nonzero element of the row corresponding to the polar encoding is 4, and the code weight corresponding to the first nonzero element is 4. The first nonzero element of the row corresponding to the eBCH encoding is 16, and the code weight corresponding to the first nonzero element is 6. First, the smaller the code weight corresponding to the first nonzero element, the better the performance. Therefore, the performance of the eBCH encoding is better than that of the polar encoding.

[0177] For another example, when K = 10, the first nonzero element of the row corresponding to the polar encoding is 76, and the code weight corresponding to the first nonzero element is 4. The first nonzero element of the row corresponding to the Dual of eBCH encoding is 60, and the code weight corresponding to the first nonzero element is 4. When the positions of the first nonzero elements are the same (i.e., the code weights corresponding to the first nonzero elements are the same), the smaller the value of the first nonzero element, the better the performance. Therefore, the performance of the Dual of eBCH encoding is better than that of the polar encoding.

[0178] The performance comparison in Table 1 is illustrated above, and the principle of performance comparison is the same when K takes other values, which will not be described herein again.

[0179] In addition, when K = 5, 8, and 11, the performance of the polar code used as the outer code of the concatenated encoding is already better than that of the block encoding, and therefore the polar code can not be replaced by other encodings. Therefore, when K = 5, 8, and 11, only the rows corresponding to the polar encoding are listed in Table 1.

[0180] In addition, in Table 1, Dual of eBCH represents the dual code of the eBCH code. Dual of Simplex represents the dual code of the simplex code.

[0181] As can be seen from Table 1, except for the case of K = 5, 8, 11, the code distance spectrum of the sub-block corresponding to each information length is obviously improved relative to the polar outer code without replacement, by replacing the polar outer code with the block code shown in Table 2.

[0182] The above B = 3 and B = 16 are two examples of the method of concatenated coding provided by the present application. In theory, B can be set to any positive integer. As introduced above, the setting of B is related to the requirements of decoding complexity and decoding delay, and is usually a compromise between the two. Therefore, in order to adapt to the hardware conditions in the communication system, according to the idea of concatenated coding provided by the present application, the person skilled in the art can also design some specific implementations when B is set to other values, for example, B = 8, 32, 64, etc., but the design idea is the same as that when B = 3 and B = 16 in the present application, which will not be listed here.

[0183] According to the method of concatenated coding provided by the present application, given a concatenated code length and a target code rate, the code rate allocation before polarization can be obtained recursively by existing technology until the code rate of each outer code (block code) is obtained, and the corresponding block code is selected for outer code encoding.

[0184] For example, the existing "polar weight" method can be used to obtain the code rate allocation result of the original polar code on each sub-block, and the allocation result is used as the code rate allocation scheme of each sub-block of the concatenated code.

[0185] Alternatively, when using the method of concatenated coding of the present application, the above-mentioned code rate allocation scheme can not be followed, and the decoding complexity can be reduced by avoiding certain specific code rates. For example, the "full expansion algorithm" and "symptom list" can be used to avoid intermediate code rates of the concatenated code. Among them, the full expansion algorithm is suitable for low code rate sub-blocks, and the symptom list method is suitable for high code rate sub-blocks, which is a parallel decoding method.

[0186] The decoding method 300 of the present application will be described below taking the symptom list method as an example. The decoding method 300 of the embodiment of the present application can include the following steps 301-306.

[0187] 301, obtain a bit sequence to be decoded, the length of the bit sequence to be decoded is N, and N is a positive integer.

[0188] 302, perform SCL decoding on the bit sequence to be decoded to obtain N / B sub-code blocks.

[0189] It should be understood that, at the encoding side, N is the length of the codeword after the concatenated encoding is completed. B is the length of each sub-block into which the information bit sequence is divided. At the decoding side, N is the length of the bit sequence to be decoded. B has the same meaning as at the encoding side.

[0190] Specifically, it is well known to those skilled in the art that, according to the SCL decoding method, each bit of the bit sequence to be decoded is associated with a log-likelihood ratio (LLR). Then, the N bits of the bit sequence to be decoded of length N are each associated with an N LLR. When decoding according to the SCL decoding algorithm, the N LLRs are subjected to F operation or G operation according to the level, and recursive operation is performed. When the level at which the sub-block of the outer code is located is reached, step 303 is performed.

[0191] Here, the F operation and the G operation are well-known concepts for recursive operation on the LLR in the SCL decoding algorithm. The sub-block of the outer code has the same meaning as the sub-block of the outer code described in the method 200 of concatenated encoding, and will not be described again.

[0192] 303, performing hard decision on the bits in each of the N / B sub-blocks to obtain a hard decision result of each sub-block.

[0193] 304, querying a syndrome diagnosis table with the hard decision result of each sub-block to obtain a plurality of candidate codewords of each sub-block.

[0194] Here, the plurality of candidate codewords of a sub-block is exactly the plurality of candidate decoding paths of the sub-block.

[0195] For the syndrome diagnosis table, please refer to the description of the prior art.

[0196] 305, calculating the path metric values of the plurality of candidate codewords of each sub-block, and determining the decoding path of each sub-block according to the path metric values of the plurality of candidate codewords of each sub-block.

[0197] Here, the path metric (PM) can be used to measure the pros and cons of the decoding path. Generally, the smaller a PM value is, the better the candidate decoding path is. After the PM of each candidate codeword of each sub-block is calculated, the optimal path of each sub-block is selected according to the size of the PM, as the decoding path of the sub-block.

[0198] 306, sequentially outputting the plurality of decoding paths corresponding to the plurality of sub-blocks as the decoding result.

[0199] The above is a description of the decoding process.

[0200] It should be understood that the steps 301-306 above are only several steps divided for the convenience of illustrating the decoding process. In actual implementation, more steps can be designed on the basis of the steps 301-306. Alternatively, some of the steps 301-306 above can be combined together, and the decoding method 300 is described as fewer steps. The present application is not limited.

[0201] As can be seen from the decoding process, the concatenated coding method 200 provided by the present application performs outer code encoding and inner code encoding on the information bit sequence, and the outer code adopts a block code and the inner code adopts a polar code, so that the receiving end can decode in "blocks" during the decoding process, thereby the decoding result of each sub-block can be output at a time. Compared with the existing SCL decoding method which decodes in "bits", the decoding delay can be reduced.

[0202] Further, compared with the existing polar coding method, in addition to the decoding delay being reduced, a large number of experimental results show that the decoding performance of the concatenated coding method 200 provided by the present application is also greatly improved.

[0203] Two performance comparison diagrams of the concatenated coding method 200 of the present application and the existing polar coding are given below. Figures 7-8 In the above, N represents the code length, and K represents the length of the information sequence. In which, Figure 7 and Figure 8 The K in the above

[0204] Referring to Figure 7 , Figure 7 is a performance comparison diagram of the concatenated code and the polar code with N=256 and K=124.

[0205] Referring to Figure 8 , Figure 8 is a performance comparison diagram of the concatenated code and the polar code with N=1024 and K=512.

[0206] In the above Figure 7 and Figure 8In the figures, SCL represents a successive cancellation list (SCL) decoding algorithm, and a polar SCL curve indicates that polar encoding is used and SCL decoding is used for decoding. Hybrid polar indicates that the cascaded encoding method provided in the present application is used, and when performing outer code encoding, the plurality of sub-sequences obtained by dividing the information bit sequence are selected according to their information lengths from Table 2. For the information bit sequence, the encoding methods corresponding to the plurality of sub-sequences are not the same, so it is called hybrid encoding. Hybrid polar FSL refers to a decoding method that adopts a "block-by-block" manner rather than a "bit-by-bit" manner for outer code sub-codes, and has lower decoding latency.

[0207] Figure 7 and Figure 8 The ordinate BLER in the figures represents the block error ratio (BLER), and the abscissa E S / N0 represents the signal-to-noise ratio. Among them, Figure 7 and Figure 8 The performance curves shown in the figures are obtained by simulation under the channel condition of additive white Gaussian noise (AWGN).

[0208] As can be seen, Figure 7 and Figure 8 In the figures, under the condition that the signal-to-noise ratios are the same, the block error rate of the curve corresponding to the hybrid polar FSL is always lower than the block error rate of the curve corresponding to the polar SCL. It can be seen that by using the technical solution provided in the present application, the outer code of the polar code is encoded in groups, and the inner code is encoded by polar, and the decoding performance is improved.

[0209] The above combines Figures 1 to 8 , and the cascaded encoding method provided in the present application is described in detail. For the receiving end (or referred to as the decoding end) receiving the bit sequence to be decoded from the sending end, the decoding process in "block" units can refer to the prior art. It should be understood that the present application provides a cascaded encoding method, so that the receiving end can decode in block units rather than in bit units, and a large number of simulation results show that the decoding performance is improved. For example, the decoding latency is reduced, and the bit error rate is reduced. However, the process of the receiving end decoding in block units can refer to the prior art, and will not be described in detail herein.

[0210] The communication apparatus, the encoding apparatus, the network device and the terminal device provided in the present application will be described below in combination with Figures 9-14 .

[0211] Referring toFigure 9 , Figure 9 is a schematic block diagram of a communication apparatus 500 provided by the present application. As shown in Figure 9 , the apparatus 500 includes a processing unit 510 and a communication unit 520.

[0212] The processing unit 510 is configured to perform group encoding on a sequence of information bits to obtain a plurality of first code words with a code length of B, where B is an integer greater than or equal to 0; and perform n-stage polar encoding on the plurality of first code words to obtain a second code word with a length of B×2 n , where n is an integer greater than or equal to 1.

[0213] The communication unit 520 is configured to send the second code word generated by the processing unit 510.

[0214] Referring to Figure 10 , Figure 10 is a schematic structural diagram of a communication apparatus 600 provided by the present application. The communication apparatus 600 is configured to implement the function of encoding, and the communication apparatus 600 includes:

[0215] A processing apparatus 601 is configured to obtain a sequence of information bits to be encoded, and perform group encoding on the sequence of information bits to obtain a plurality of first code words with a code length of B, where B is an integer greater than or equal to 0; and perform n-stage polar encoding on the plurality of first code words to obtain a second code word with a length of B×2 n , where n is an integer greater than or equal to 1.

[0216] A transceiver 602 is configured to send the second code word.

[0217] Optionally, the transceiver is connected with an antenna 603.

[0218] In a specific implementation, the processing apparatus 601 can be a processor, a chip or an integrated circuit.

[0219] The present application further provides a processing apparatus 601 configured to implement the cascade encoding method of the method embodiments. Part or all of the processes of the cascade encoding method 200 of the embodiments of the present application can be implemented by hardware, or can also be implemented by software. When implemented by hardware, the processing apparatus 601 described above can be a processor.

[0220] Optionally, when all or part of the processes of the cascade encoding method 200 of the present application are implemented by hardware, the processing apparatus 601 described above can also be as shown in Figure 11 . Referring to Figure 11 , Figure 11 is an internal structure diagram of the processing apparatus 601. The processing apparatus 601 includes:

[0221] An input interface circuit 6011 is configured to obtain an input sequence of information bits.

[0222] a logic circuit 6012, configured to group encode the information bit sequence to obtain a plurality of first code words with a code length of B, B≥0 and is an integer; and perform n-stage polar encoding on the plurality of first code words to obtain a second code word with a length of B×2n, n≥1 and is an integer. n

[0223] an output interface circuit 6013, configured to output the second code word.

[0224] The logic circuit 6012 described above can be configured to perform the cascade encoding method described in the embodiments of the present application. For details, refer to the description in the method embodiments above, which will not be repeated here.

[0225] Optionally, part or all of the processes of the cascade encoding method 200 provided in the present application can also be implemented by software. In this case, the processing device 601 can be a processor, and the processor is configured to execute a computer program stored in a memory, and when the computer program is executed, the processor performs the cascade encoding method in the above method embodiments.

[0226] Here, the memory can be a physically independent unit. Alternatively, the memory can also be integrated with the processor, which is not limited in the present application.

[0227] In another optional embodiment, the processing device 601 can only include a processor. The processor is connected with the memory through a circuit / wire, and is configured to read and execute the computer program stored in the memory. Optionally, the processing device 601 also includes the memory.

[0228] Optionally, when the processing device 601 is a chip, the chip can also include an input interface and an output interface. The input interface is configured to receive the input information bit sequence to be encoded. The output interface is configured to output the second code word.

[0229] Based on the cascade encoding method 200 provided in the present application, the present application further provides a communication device 700. The communication device 700 is configured to perform the above method 300.

[0230] Referring to Figure 12 Figure 12 is a schematic block diagram of the communication device 700 provided in the present application. The communication device 700 includes a communication unit 701 and a processing unit 702.

[0231] The communication unit 701 is configured to receive a bit sequence to be decoded from a sending end;

[0232] The processing unit 702 is configured to perform the decoding method 300 described above to decode the bit sequence to be decoded to obtain a decoding result.

[0233] Referring to Figure 13 ​​, Figure 13 A schematic structural diagram of a communication device 800 is provided in the present application. The communication device 800 is used to implement the decoding function, and the decoding device 800 comprises:

[0234] A transceiver 801 is configured to receive a bit sequence to be decoded from a sending end.

[0235] A processing device 802 is configured to acquire the bit sequence to be decoded, and perform the decoding method of the above method 300 to decode the bit sequence to be decoded to obtain a decoding result.

[0236] Optionally, the transceiver 801 is connected with an antenna 803.

[0237] In a specific implementation, the processing device 802 can be a processor, a chip or an integrated circuit.

[0238] The present application further provides a processing device 802 used to implement the above decoding method 300. Part or all of the processes of the decoding method 300 of the present application embodiment can be implemented by hardware, or also can be implemented by software.

[0239] Optionally, when implemented by hardware, the processing device 802 can be a processor.

[0240] Optionally, when part or all of the processes of the decoding method 300 of the present application embodiment are implemented by hardware, the processing device 802 can further comprise a processor and a memory. Figure 14

[0241] Referring to Figure 14 , Figure 14 A schematic diagram of an internal structure of the processing device 802 is provided in the present application. The processing device 601 comprises:

[0242] An input interface circuit 8021 is configured to acquire a bit sequence to be decoded.

[0243] A logic circuit 8022 is configured to perform the above decoding method 300 to decode the bit sequence to be decoded to obtain a decoding result.

[0244] An output interface circuit 8023 is configured to output the decoding result.

[0245] Optionally, the processing device 802 can be a processor, and the processor is used to execute a computer program stored in a memory, and when the computer program is executed, the processor executes the above decoding method 300.

[0246] Here, the memory can be a physically independent unit. Alternatively, the memory can also be integrated with the processor, and the present application does not make any limitation.

[0247] ​In another alternative embodiment, the processing device 802 only includes a processor. The processor is connected with the memory through circuitry / wires for reading and executing the computer program stored in the memory. Alternatively, the processing device 802 further includes the memory.

[0248] Alternatively, when the processing device 802 is a chip, the chip can further include an input interface and an output interface. The input interface is used for receiving the inputted bit sequence to be decoded. The output interface is used for outputting the decoding result.

[0249] It should be understood that the method 200 of concatenated coding provided by the present application can be executed by a sending end. For example Figure 1 The wireless communication system shown, when the network device 101 sends a signal, the network device 101 is the sending end. When the terminal device 102 or 103 sends a signal, the terminal device 102 or 103 is the sending end. Therefore, the present application further provides a network device and a terminal device having the function of implementing the above-mentioned method of concatenated coding.

[0250] Referring to Figure 15 , Figure 15 is a schematic structural diagram of the network device 3000 provided by the present application. As Figure 15 shown, the network device 3000 can be applied in the wireless communication system shown above Figure 1 and has the function of executing the method of concatenated coding provided by the present application. The network device 3000 can be, for example, a base station.

[0251] The network device 3000 can include one or more radio frequency units, such as a remote radio unit (RRU) 3100 and one or more baseband units (BBU). The baseband unit can also be referred to as a digital unit (DU) 3200. The RRU 3100 can be referred to as a transceiver unit, which is connected to the BBU 3200 through an air interface and transmits and receives data to and from the terminal device 102 or 103. Figure 9The communication unit 520 in the network device 500 corresponds to the communication unit 520 in the network device 500. Optionally, the transceiver unit 3100 can also be referred to as a transceiver, a transceiver circuit, or a transceiver, etc., which can include at least one antenna 3101 and a radio frequency unit 3102. Optionally, the transceiver unit 3100 can include a receiving unit and a transmitting unit, the receiving unit can correspond to a receiver (or receiver, receiver circuit), and the transmitting unit can correspond to a transmitter (or transmitter, transmitter circuit). The RRU 3100 part is mainly used for the transceiving of radio frequency signals and the conversion between radio frequency signals and baseband signals, for example, for sending configuration information of the first random access resource to the terminal device. The BBU 3200 part is mainly used for baseband processing, controlling the base station, etc. The RRU 3100 and the BBU 3200 can be physically arranged together, or can be physically separated, that is, a distributed base station.

[0252] The BBU 3200 is the control center of the network device 3000, also known as a processing unit, which can be used to control the base station to perform the method 200 of cascaded encoding. Figure 9 The processing unit 510 in the network device 500 corresponds to the processing unit 510 in the network device 500, which is mainly used to complete the baseband processing function, such as channel coding, rate matching (optional), bit interleaving, modulation, etc. For example, the BBU (processing unit) can be used to control the base station to perform the method 200 of cascaded encoding. Specifically, the information bit sequence to be encoded is grouped and encoded to obtain a plurality of first code words with a code length of B; the plurality of first code words are polar encoded at n levels to obtain a second code word with a length of B x 2 n

[0253] In one example, the BBU 3200 can be composed of one or more single boards, and a plurality of single boards can jointly support a single access mode wireless access network (for example, an LTE network), or can separately support wireless access networks of different access modes (for example, an LTE network, a 5G network, or other networks). The BBU 3200 further includes a memory 3201 and a processor 3202. The memory 3201 is used to store necessary instructions and data. The processor 3202 is used to control the network device 3000 to perform necessary actions, for example, to control the network device 3000 to perform the operation processes performed by the network device in the above method embodiments. The memory 3201 and the processor 3202 can serve one or more single boards. That is, the memory and the processor can be separately arranged on each single board. Alternatively, a plurality of single boards can share the same memory and processor. In addition, necessary circuits can also be arranged on each single board.

[0254] It should be understood that Figure 15 ​The network device 3000 shown is capable of implementing the polar coding method. The operation and / or function of each unit in the network device 3000 correspond to the respective processes in the embodiment of the concatenated coding method 200. To avoid repetition, detailed descriptions are omitted here.

[0255] The BBU 3200 described above can be used to perform actions implemented internally by the network device as described in the preceding method embodiments, such as concatenating and encoding information bit sequences. The RRU 3100 can be used to perform actions described in the preceding method embodiments, such as sending a second codeword to or receiving a terminal device from the terminal device.

[0256] exist Figure 1 In the wireless communication system shown, when uplink transmission is performed, terminal device 102 or 103 is the transmitting end. The terminal device provided in this application is described below.

[0257] See Figure 16 , Figure 16 This is a schematic structural diagram of the terminal device 900 provided in this application. Figure 16 As shown, Figure 16 As shown, the terminal device 900 includes: one or more processors 901, one or more memories 902, and one or more transceivers 903. The processor 901 controls the transceivers 903 to transmit and receive signals, the memory 902 stores computer programs, and the processor 901 retrieves and runs the computer programs from the memory 902 to execute the corresponding flow of the concatenated encoding method 200 provided in this application. For brevity, further details are omitted here.

[0258] For example, terminal device 700 could be Figure 1 The terminal device 102 or 103 in the wireless communication system shown. Processor 901 can correspond to... Figure 9 The processing unit 510 and transceiver 903 in the middle can correspond to Figure 9 The communication unit 520 shown is shown.

[0259] Furthermore, this application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform corresponding operations and / or processes of the concatenated encoding method 200 of the embodiments of this application.

[0260] This application also provides a computer program product including computer program code, which, when run on a computer, causes the computer to perform corresponding operations and / or processes of the concatenated encoding method 200 of the embodiments of this application.

[0261] The application further provides a chip comprising a processor. The processor is configured to read and execute a computer program stored in a memory to perform corresponding operations and / or procedures of the method 200 for concatenated encoding.

[0262] Optionally, the chip further comprises a memory connected to the processor via a circuit or a wire. Further optionally, the chip further comprises a communication interface connected to the processor. The communication interface is configured to receive a bit sequence to be encoded. The processor obtains the bit sequence to be encoded from the communication interface and performs the concatenated encoding on the bit sequence to be encoded by using the method 200 for concatenated encoding. The communication interface outputs the encoded bit sequence. The communication interface can be an input / output interface.

[0263] The application provides a computer readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer is caused to perform corresponding operations and / or procedures of the method 300 for decoding.

[0264] The application further provides a computer program product comprising computer program codes. When the computer program codes are executed on a computer, the computer is caused to perform corresponding operations and / or procedures of the method 300 for decoding.

[0265] The application further provides a chip comprising a processor. The processor is configured to read and execute a computer program stored in a memory to perform corresponding operations and / or procedures of the method 300 for decoding.

[0266] Optionally, the chip further comprises a memory connected to the processor via a circuit or a wire. Further optionally, the chip further comprises a communication interface connected to the processor. The communication interface is configured to receive a bit sequence to be encoded. The processor obtains the bit sequence to be encoded from the communication interface and performs the concatenated encoding on the bit sequence to be encoded by using the method 200 for concatenated encoding. The communication interface outputs the encoded bit sequence. The communication interface can be an input / output interface.

[0267] The chip in the embodiments of the present application can be a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), and can also be a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chip.

[0268] The processor in the embodiments of the present application can be an integrated circuit chip with a processing capability of signals. In the implementation process, each step of the method embodiments can be completed by integrated logic circuits of hardware in the processor or instructions in the form of software. The processor can be a general processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware coding processor to execute, or be executed by a combination of hardware and software modules in the coding processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, or other mature storage medium in the art. The storage medium is located in the storage memory, and the processor reads information in the storage memory and combines hardware to complete the steps of the above method.

[0269] The memory in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the system and method described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0270] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware, depending on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0271] The device embodiments described above in the present application are only schematic, for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0272] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0273] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit.

[0274] The functions, if realized in the form of software functional units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0275] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of concatenated coding, characterized by, The method comprises: Obtaining a target code length N of a second code word and a code length B of the first code word, N = B x 2 n N is an integer; grouping the information bit sequence according to a target code length N of the one second codeword and a code length B of the first codeword, to obtain a plurality of sub-sequences; determining a generator matrix required for encoding each of the sub-sequences according to a number of bits included in each of the sub-sequences; encoding the plurality of sub-sequences using the generator matrix corresponding to each of the sub-sequences, to obtain a plurality of first codewords with the code length B, B≥1 and being an integer; performing n-stage polar encoding on the plurality of first codewords to obtain a second codeword with a code length of B x 2 n , n is an integer greater than or equal to 1. sending the one second codeword, wherein each of the sub-sequences of the information bit sequence is encoded using at least any one of the following codes: a repetition code, a BCH code, a simplex code, a dual code of the BCH code, a polar code, a parity check code, a dual code of a repetition code of the simplex code, in the case of B=16, the determining of the generator matrix required for encoding each of the sub-sequences according to the number of bits included in each of the sub-sequences comprises: When the number of bits included in the subsequence is 1, the generation matrix is , and the subsequence is encoded using the repetition code. When the number of bits included in the subsequence is 2, the generator matrix is , wherein the subsequence is encoded using the simplex code. When the number of bits included in the subsequence is 3, the generator matrix is , , the subsequence is encoded by using the simplex code. When the number of bits included in the subsequence is 4, the generator matrix is , , the subsequence is encoded by using the simplex code. When the number of bits included in the subsequence is 6, the generator matrix is , and the subsequence is encoded using the BCH code. When the number of bits included in the subsequence is 7, the generator matrix is , and the subsequence is encoded using the BCH code. when the number of bits included in the sub-sequence is 9 or 10, the generator matrix is a check matrix of the BCH code, and the sub-sequence is encoded using a dual code of the BCH code; when the number of bits included in the sub-sequence is 12, 13 or 14, the generator matrix is a check matrix of a dual code of a repetition code of the simplex code, and the sub-sequence is encoded using the dual code of the repetition code of the simplex code; when the number of bits included in the sub-sequence is 15, the generator matrix is G1, and the sub-sequence is encoded using a single-bit parity check code.

2. The method of claim 1, wherein, The method further comprises: According to the target code length N and the code length B of the first code word, if it is determined that there is no positive integer R such that R = 2 n , a positive integer L is selected, and m-stage polarization encoding is performed on the plurality of first code words with the code length B to obtain third code words with the code length B x L, L = 2 m , L > R, m > n, m, L and R are positive integers; rate match the third code word of the code length of B x L to obtain a second code word of the code length of B x 2 n .

3. A communication device, characterized by The method comprises: A processing unit is configured to obtain a target code length N of a second code word and a code length B of a first code word, N = B x 2 n , N is an integer; The processing unit is further configured to group the information bit sequence according to a target code length N of the one second codeword and a code length B of the first codeword, to obtain a plurality of sub-sequences; The processing unit is further configured to determine a generator matrix required for encoding each of the sub-sequences according to a number of bits included in each of the sub-sequences; The processing unit is further configured to encode the plurality of sub-sequences using a generator matrix corresponding to each of the plurality of sub-sequences to obtain a plurality of first codewords with the code length B, B≥1 and is an integer; and the processing unit is further configured to perform n-stage polarization encoding on the plurality of first codewords to obtain a second codeword with a code length of B×2n n , n≥1 and is an integer. The communication unit is configured to send the one second codeword generated by the processing unit, wherein the processing unit encodes each of the sub-sequences of the information bit sequence using any one of the following codes: a repetition code, a BCH code, a simplex code, a dual code of the BCH code, a polar code, a parity check code, a dual code of a repetition code of the simplex code, in the case of B=16, the processing unit is configured to: A subsequence with a bit number of 1 is encoded by using the repetition code, and the generator matrix is ; encode a subsequence with a bit number of 2, wherein the generator matrix is , ; The subsequence with bit number 3 is encoded by using the simplex code, and the generation matrix is , ; The subsequence with the bit number of 4 is encoded by using the simplex code, and the generating matrix is , ; A subsequence with a bit number of 6 is encoded by using the BCH code, and the generator matrix is ; A subsequence with a bit number of 7 is encoded by using the BCH code, and the generator matrix is ; encode the sub-sequence with the number of bits being 9 or 10 using a dual code of the BCH code, and the generator matrix is a check matrix of the BCH code; encode the sub-sequence with the number of bits being 12, 13 or 14 using a dual code of a repetition code of the simplex code, and the generator matrix is a check matrix of the dual code of the repetition code of the simplex code; encode the sub-sequence with the number of bits being 15 using a single-bit parity check code, and the generator matrix is G1.

4. The communication apparatus according to claim 3, wherein The processing unit is further configured to: According to the target code length N and the code length B of the first code word, if it is determined that there is no positive integer R such that R = 2 n , a positive integer L is selected, and m-stage polarization encoding is performed on the plurality of first code words with the code length B to obtain third code words with the code length B x L, L = 2 m , L > R, m > n, m, L and R are positive integers; rate match the third code word of the code length of B x L to obtain a second code word of the code length of B x 2 n .

5. A computer readable storage medium, characterized in that, The computer readable storage medium stores instructions, which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 2.

6. A chip, characterized by comprising: a memory for storing a computer program; a processor for reading and executing the computer program stored in the memory, the processor executing the method of any of claims 1-2 when the computer program is executed.

7. A computer program product, characterised in that, The computer program product comprises computer program code which, when run on a computer, causes the computer to execute the method of any of claims 1-2.

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