Storage Devices

Abstract

The present disclosure provides a memory chip and a memory device. The memory device includes a first memory chip, the first memory chip including: a first input pad configured to receive a first input signal; a first initialization circuit configured to generate a first initialization signal; a first input delay circuit configured to delay the first input signal by a first delay time to generate a first output signal; a first output pad configured to receive the first output signal and output the first output signal; a first clock delay circuit configured to delay the first initialization signal by a second delay time to generate a first clock signal; a second clock delay circuit configured to delay the first clock signal by a third delay time to generate a second clock signal; a first latch configured to store the first input signal based on the first clock signal; and a second latch configured to store the first input signal based on the second clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0109474 filed on September 13, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts relate to a memory device. Background Art

[0004] In order to construct a large-capacity storage device, a package can be formed by stacking multiple memory chips (e.g., NAND flash memory, PRAM, etc.). Since multiple memory chips generally use control signals input to the package, different chip addresses can be set for each memory chip in order to distinguish the corresponding memory chips. When the address is directly assigned to the address pad of each memory chip using wire bonding, the number of address pads and bonding wires will increase as the number of memory chips increases. When the number of address pads increases, it is difficult to miniaturize the memory chip or the package due to the increase in the size of the memory chip. In addition, when the number of bonding wires increases, defects in the package are likely to occur. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a memory device having improved reliability and product integration.

[0006] According to an example embodiment conceived by the present invention, a memory chip may include: a first input pad, which is configured to receive a first input signal; a first initialization circuit, which is configured to generate a first initialization signal; a first input delay circuit, which is configured to set a first delay time based on the first initialization signal, and delay the first input signal by the first delay time to generate a first output signal; a first output pad, which is configured to receive the first output signal and output the first output signal to the outside; a first clock delay circuit, which is configured to delay the first initialization signal by a second delay time to generate a first clock signal, and the second delay time is different from the first delay time; a second clock delay circuit, which is configured to delay the first clock signal by a third delay time to generate a second clock signal, and the third delay time is different from the second delay time; a first latch, which is configured to store the first input signal based on the first clock signal; and a second latch, which is configured to store the first input signal based on the second clock signal.

[0007] According to an example embodiment conceived in the present invention, a storage device includes: a controller; a first memory chip, which includes a first address setting circuit, the first address setting circuit is configured to receive an address setting command from the controller to generate a first initialization signal, receive a signal from the outside to generate a first input signal, set a first delay time based on the first initialization signal, delay the first input signal by the first delay time to generate a first output signal, delay the first initialization signal by a second delay time to generate a first clock signal, determine a first output time point based on the first clock signal, and output the level of the first input signal as a first value of a first address of the first memory chip at the first output time point; and a second memory chip, which includes a second address setting circuit, the second address setting circuit is configured to receive the first output signal from the first address setting circuit.

[0008] According to an example embodiment conceived by the present invention, a memory chip includes: a first input pad, which is configured to receive a first input signal; a first initialization circuit, which is configured to provide a first initialization signal; a first input delay circuit, which is configured to delay the first input signal based on the first initialization signal; a first ring oscillator, which is configured to generate a first clock signal and a second clock signal, so that the second clock signal is the first clock signal delayed by a first delay time; a first latch, which is configured to store the first input signal based on the first clock signal; a second latch, which is configured to store the first input signal based on the second clock signal; and a first clock controller, which is configured to provide the first clock signal and the second clock signal to the first latch and the second latch, respectively.

[0009] However, exemplary embodiments of the inventive concept are not limited to the embodiments set forth herein. The above and other exemplary embodiments of the inventive concept will become more apparent to those skilled in the art to which the inventive concept pertains by referring to the detailed description of exemplary embodiments of the inventive concept given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is an exemplary diagram for explaining a configuration of a data storage system according to some example embodiments.

[0012] Figure 2 is an example diagram for explaining a chip selection circuit according to some example embodiments.

[0013] Figure 3is an exemplary diagram for explaining a connection relationship between a plurality of memory chips according to some example embodiments.

[0014] Figure 4 is an example diagram for describing an address setting circuit according to some example embodiments.

[0015] Figure 5 is an example timing diagram for explaining the operation of an address setting circuit according to some example embodiments.

[0016] Figure 6 is an example diagram illustrating an address setting circuit according to some example embodiments.

[0017] Figure 7 is an example diagram for describing an address setting circuit according to some example embodiments.

[0018] Figure 8 is an example timing diagram for explaining the operation of an address setting circuit according to some example embodiments.

[0019] Fig. 9 is an example diagram for describing an address setting circuit according to some example embodiments.

[0020] Fig.10 is an example timing diagram for explaining the operation of an address setting circuit according to some example embodiments.

[0021] Fig.11 is an exemplary diagram for explaining a case where an address setting circuit abnormally operates according to some example embodiments.

[0022] Fig.12 is an example diagram for explaining an address setting circuit for reducing (or alternatively, preventing) an address setting failure according to some example embodiments.

[0023] Fig.13 is an example timing diagram for illustrating the operation of an address setting circuit for reducing (or alternatively, preventing) address setting failures according to some example embodiments.

[0024] Fig.14 is an exemplary diagram for explaining an address setting circuit according to some example embodiments.

[0025] Fig.15 is an example diagram for describing an address setting circuit according to some example embodiments.

[0026] Fig.16 is an example flow chart for explaining the operation of an address setting circuit according to some example embodiments.

[0027] Fig.17is an exemplary diagram for explaining a modified example of a storage device according to some example embodiments.

[0028] Fig.18 are exemplary diagrams for explaining modified examples of storage devices according to some other example embodiments. DETAILED DESCRIPTION

[0029] Figure 1 is an exemplary diagram for explaining a configuration of a data storage system according to some example embodiments.

[0030] Reference Figure 1 , a data storage system according to some example embodiments may include a storage device 100 and a host 200. The host 200 according to some example embodiments may send data to the storage device 100 or receive data from the storage device 100, or may transmit a command to the storage device 100. The host 200 may include a user device, such as a personal / portable computer, a PDA, a PMP, and an MP3 player. The host 200 and the storage device 100 may be connected to each other via a host interface. The host interface may be, for example, a standardized interface, such as a USB, SCSI, ESDI, SATA, SAS, PCI-express, or IDE interface. The interface type used to connect the host 200 and the storage device 100 is not limited to a specific form, and various modifications may be made.

[0031] The storage device 100 according to some example embodiments may be a solid state drive (SSD) using a flash memory, but the embodiment is not limited thereto. For example, the storage device 100 may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, and MMC-micro), an SD card (SD, miniSD, microSD, and SDHC), a universal flash storage device (UFS), etc.

[0032] The memory device 100 according to some example embodiments may include a controller 110 and a plurality of memory chips 120 .

[0033] The plurality of memory chips 120 may be, for example, NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive RAM (RRAM), phase change memory (PRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), and spin injection magnetization reversal memory (STT-RAM), but example embodiments are not limited thereto.

[0034] Each of the plurality of memory chips 120 may include an address setting circuit 122 and a memory cell region 124. The memory cell region 124 may be a region for storing data. The memory cell region 124 may be used in the sense of including a buffer memory region. The address setting circuit 122 may be a circuit for setting the address of each of the plurality of memory chips 120. A detailed description of the address setting circuit 122 will be provided later. As used herein, the term "address" refers to the chip address of each memory chip 120, and is not used to refer to the address of the corresponding memory cell region 124 in the memory chip 120.

[0035] The controller 110 may include an address setting command circuit 112 and a chip selection circuit 114. According to some example embodiments, the address setting command circuit 112 may provide an address setting command ( Figure 3 For example, when the controller 110 detects that power is supplied to the storage device 100, the controller 110 may send an address setting command (CMD) to the storage device 100 through the address setting command circuit 122. Figure 3 In another example, when the controller 110 receives a specific command from the host 200, the controller 110 may send the address setting command (CMD) to each of the plurality of memory chips 120 through the address setting command circuit 112. Figure 3 The address setting command (CMD) is provided to each of the plurality of memory chips 120. However, example embodiments are not limited thereto, and a person having ordinary knowledge in the technical field of the inventive concept may determine that the address setting command ( Figure 3 CMD) is provided to the address setting circuit 122 in various situations.

[0036] According to some example embodiments, as shown below Figure 2 Discussing in more detail, the chip selection circuit 114 may select an appropriate memory chip 120. For example, the chip selection circuit 114 may enable a memory chip including an address specified from the host 200, and may disable the remaining memory chips.

[0037] Figure 2 1 is an example diagram for illustrating a chip selection circuit according to some example embodiments. For ease of explanation, the following description will be made assuming that the memory device 100 includes a first memory chip 120_1 to a third memory chip 120_3, but the example embodiments are not limited to the number of memory chips. For example, the memory device 100 may include more or fewer memory chips than those shown in some of the drawings. In addition, in the following description, for ease of explanation, the address setting circuit 122 of the memory chip 120 is mainly shown, and the memory cell area 124 and the like are omitted.

[0038] Reference Figure 2 , the process of selecting one of the three memory chips 120_1, 120_2 and 120_3 by the chip selection circuit 114 will be described. Hereinafter, in order to distinguish each of the multiple memory chips 120, the first memory chip 120_1 to the third memory chip 120_3, etc. will be described separately. The underline "_" shown in each figure is used to distinguish each memory chip and its related constituent elements. For example, the reference numerals associated with the first memory chip 120_1 are represented by "xxx_1", and the reference numerals associated with the second memory chip 120_2 are represented by "xxx_2". Similarly, the reference numerals associated with the third memory chip 120_3 are represented by "xxx_3". This is for ease of explanation, and the example embodiments are not limited to these divisions.

[0039] According to some example embodiments, the chip selection circuit 114 may include a first comparator 115, a second comparator 116, and a third comparator 117. For example, the first to third comparators 115 to 117 may be XNOR gates, but example embodiments are not limited thereto. The first to third memory chips 120_1 to 120_3 may include first to third address setting circuits 122_1 to 122_3, respectively, and each of the first to third memory chips 120_1 to 120_3 may include a chip enable terminal CE.

[0040] When the chip enable terminal CE receives an enable signal (e.g., a logic high level), each memory chip may be enabled. In addition, when the chip enable terminal CE receives a disable signal (e.g., a logic low level), each memory chip may be disabled. For example, when the chip enable terminal CE of the first memory chip 120_1 receives an enable signal, the first memory chip 120_1 may be enabled. In addition, when the chip enable terminal CE of the first memory chip 120_1 receives a disable signal, the first memory chip 120_1 may be disabled.

[0041] The first address setting circuit 122_1 outputs the first address ADD_1, the second address setting circuit 122_2 outputs the second address ADD_2, and the third address setting circuit 122_3 may output the third address ADD_3. When the first to third address setting circuits 122_1 to 122_3 operate normally, the first to third addresses ADD_1 to ADD_3 may be distinguished from each other.

[0042] According to some example embodiments, in order to control the first memory chip 120_1, the host 200 may send a first memory chip selection command CHIPSEL_ADD_1 to the controller 110. The chip selection circuit 114 compares the first address ADD_1 included in the first memory chip selection command CHIPEL_ADD_1 with each of the addresses output from the first address setting circuit 122_1 to the third address setting circuit 122_3 to enable only a specific memory chip, and the remaining chips may be disabled. For example, the first comparator 115 compares the first address included in the first memory chip selection command CHIPSEL_ADD_1 with the address output of the first address setting circuit 122_1, and may provide an enable signal (e.g., a logic high level) to the chip enable terminal CE of the first memory chip 120_1. In addition, the second comparator 116 compares the first address ADD_1 included in the first memory chip selection command CHIPSEL_ADD_1 with the address output of the second address setting circuit 122_2, and can provide a disable signal (e.g., a logic low level) to the chip enable terminal CE of the second memory chip 120_2. Similarly, the third comparator 117 compares the first address ADD_1 included in the first memory chip selection command CHIPSEL_ADD_1 with the address output of the third address setting circuit 122_3, and can provide a disable signal (e.g., a logic low level) to the chip enable terminal CE of the third memory chip 120_3. At this time, the first memory chip 120_1 is enabled, and the second memory chip 120_2 and the third memory chip 120_3 can be disabled. For example, the first memory chip selection command CHIPSEL_ADD_1 can be included in a read command or a program command. In another example, the first memory chip selection command CHIPSEL_ADD_1 can be another command before the read command or the program command.

[0043] Figure 3 is an exemplary diagram for explaining a connection relationship between a plurality of memory chips according to some example embodiments.

[0044] Reference Figure 1 and Figure 3 , the first memory chip 120_1 may include a first I / O pad IOPAD_1, a first input pad IPAD_1, a first output pad OPAD_1, and a first address setting circuit 122_1.

[0045] The first I / O pad IOPAD_1 may provide data and a command received from the controller 110 to the first memory chip 120_1 , or may provide data received from the first memory chip 120_1 to the controller 110 .

[0046] For example, the first I / O pad IOPAD_1 may be implemented as eight fins to be able to receive the provided 8-bit information, but example embodiments are not limited thereto. The command received from the controller 110 may include an address setting command CMD. The address setting command CMD may be provided to the first address setting circuit 122_1 through the first I / O pad IOPAD_1.

[0047] The first input pad IPAD_1 may receive a first signal V1 from the outside. The first input pad IPAD_1 may provide the received first signal V1 as a first input signal IN_1 to the first address setting circuit 122_1. The first address setting circuit 122_1 may output a first output signal OUT_1 and a first address ADD_1. The first output signal OUT_1 may be provided to the first output pad OPAD_1.

[0048] The second memory chip 120_2 may include a second I / O pad IOPAD_2, a second input pad IPAD_2, a second output pad OPAD_2, and a second address setting circuit 122_2. Since the second I / O pad IOPAD_2 and the second address setting circuit 122_2 are similar to the first I / O pad IOPAD_1 and the first address setting circuit 122_1, a description thereof will not be provided.

[0049] The second input pad IPAD_2 may be connected to the first output pad OPAD_1 of the first memory chip 120_1. In other words, the second input pad IPAD_2 may receive the provided first output signal OUT_1. The second input pad IPAD_2 may provide the received first output signal OUT_1 as the second input signal IN_2 to the second address setting circuit 122_2. In other words, the second input signal IN_2 may be substantially the same as the first output signal OUT_1. The second address setting circuit 122_2 may output the second output signal OUT_2 and the second address ADD_2. The second output signal OUT_2 may be provided to the second output pad OPAD_2.

[0050] The third memory chip 120_3 may include a third I / O pad IOPAD_3, a third input pad IPAD_3, a third output pad OPAD_3, and a third address setting circuit 122_3. Since the third I / O pad IOPAD_3 and the third address setting circuit 122_3 are similar to the first I / O pad IOPAD_1 and the first address setting circuit 122_1, respectively, a description thereof will not be provided.

[0051] The third input pad IPAD_3 may be connected to the second output pad OPAD_2 of the second memory chip 120_2. In other words, the third input pad IPAD_3 may receive the provided second output signal OUT_2. The third input pad IPAD_3 may provide the received second output signal OUT_2 as the third input signal IN_3 to the third address setting circuit 122_3. In other words, the third input signal IN_3 may be substantially the same as the second output signal OUT_2. The third address setting circuit 122_3 may output the third output signal OUT_3 and the third address ADD_3. The third output signal OUT_3 may be provided to the third output pad OPAD_3. That is, the first output pad OPAD_1 of the first memory chip 120_1 is connected to the second input pad IPAD_2 of the second memory chip 120_2, and the second output pad OPAD_2 of the second memory chip 120_2 may be connected to the third input pad IPAD_3 of the third memory chip 120_3. In other words, the first to third memory chips 120_1 to 120_3 may be connected in a daisy chain manner. Figure 4 and Figure 5 The address setting circuit 122 will be described in detail.

[0052] Figure 4 is an example diagram for describing an address setting circuit according to some example embodiments. Figure 4 The configuration of the address setting circuit 122 shown in FIG. 1 can be similarly applied to all of the first to third address setting circuits 122_1 to 122_3 .

[0053] Reference Figure 3 and 4 , the address setting circuit 122 may include an initialization circuit 401, a first AND gate 402, an input delay circuit 403, a first latch 404, a second latch 405, a third latch 406, a first clock delay circuit 407, a second clock delay circuit 408, and a third clock delay circuit 409. The number of latches and the number of clock delay circuits included in the address setting circuit 122 according to some example embodiments may be determined according to the number of latches and the number of clock delay circuits included in the storage device ( Figure 1 100).

[0054] The initialization circuit 401 may receive the address setting command CMD through the I / O pad IOPAD. When the initialization circuit 401 receives the address setting command CMD, the initialization circuit 401 may generate an initialization signal INI. At this time, the initialization signal INI may be provided to the first AND gate 402 and the first clock delay circuit 407.

[0055] The input signal IN may be provided to the first AND gate 402 and the first latch 404 to the third latch 406. As described above, the input signal IN may be a signal received from the outside through the input pad IPAD. For example, the first input signal IN_1 of the first memory chip 120_1 may be a first signal V1 provided from the outside. The first signal V1 may be a DC signal or a ground signal having a specific voltage level. Hereinafter, it will be described based on the assumption that the first signal V1 is a DC signal having a logic high level. According to some example embodiments, the second input signal IN_2 of the second memory chip 120_2 may be substantially the same as the first output signal OUT_1 provided from the first output pad OPAD_1 of the first memory chip 120_1. In addition, the third input signal IN_3 of the third memory chip 120_3 may be substantially the same as the second output signal OUT_2 provided from the second output pad OPAD_2 of the second memory chip 120_2.

[0056] The first AND gate 402 may perform AND gating of the initialization signal INI and the input signal IN to output the initialization input signal IN'. The initialization input signal IN' may be provided to the input delay circuit 403. In other words, the initialization input signal IN' may be provided to the input delay circuit 403 based on the initialization signal INI.

[0057] The input delay circuit 403 may delay the initialization input signal IN′. The input delay circuit 403 may provide the delayed initialization input signal IN′ as an output signal OUT to the output pad OPAD.

[0058] The first clock delay circuit 407 can delay the initialization signal INI to generate a first clock signal CLK1. The first clock signal CLK1 can be provided to the first latch 404 and the second clock delay circuit 408. The second clock delay circuit 408 can delay the first clock signal CLK1 to generate a second clock signal CLK2. The second clock signal CLK2 can be provided to the second latch 405 and the third clock delay circuit 409. The third clock delay circuit 409 can delay the second clock signal CLK2 to generate a third clock signal CLK3. The third clock signal CLK3 can be provided to the third latch 406.

[0059] The first latch 404 can store the input signal IN based on the first clock signal CLK1. In other words, the first latch 404 can store the level of the input signal IN at the time point when the level of the first clock signal CLK1 changes (rises or falls). The level of the input signal IN stored in the first latch 404 can be provided as the output Q1 of the first latch. The second latch 405 can store the input signal IN based on the second clock signal CLK2. In other words, the second latch 405 can store the level of the input signal IN when the level of the second clock signal CLK2 changes (rises or falls). The level of the input signal IN stored in the second latch 405 can be provided as the output Q2 of the second latch. The third latch 406 can store the input signal IN based on the third clock signal CLK3. In other words, the third latch 406 can store the level of the input signal IN when the level of the third clock signal CLK3 changes (rises or falls). The level of the input signal IN stored in the third latch 406 can be provided as the output Q3 of the third latch.

[0060] The combination of the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch may be the address ADD of the memory chip 120. In other words, the address setting circuit 122 may output the combination of the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch as the address ADD of the memory chip. Figure 5 The timing diagram describes specific operations of the first address setting circuit 122_1 of the first memory chip 120_1 to the third address setting circuit 122_3 of the third memory chip 120_3.

[0061] Figure 5is an example timing diagram for illustrating the operation of the address setting circuit according to some example embodiments. For ease of explanation, the initialization signal INI, the initialization input signal IN', the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 of the first address setting circuit 122_1 are named as the first initialization signal INI_1, the first initialization input signal IN'_1, the first_1 clock signal CLK1_1, the second_1 clock signal CLK2_1, and the third_1 clock signal CLK3_1, respectively. In addition, the initialization signal INI, the initialization input signal IN', the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 of the second address setting circuit 122_2 are named as the second initialization signal INI_2, the second initialization signal input signal IN'_2, the first_2 clock signal CLK1_2, the second_2 clock signal CLK2_2, and the third_2 clock signal CLK3_2, respectively. Similarly, the initialization signal INI, initialization input signal IN', first clock signal CLK1, second clock signal CLK2 and third clock signal CLK3 of the third address setting circuit 122_3 are respectively named third initialization signal INI_3, third initialization signal input signal IN'_3, first_3 clock signal CLK1_3, second_3 clock signal CLK2_3 and third_3 clock signal CLK3_3.

[0062] Reference Figures 3 to 5 , because the address setting command CMD is substantially provided to the first I / O pad IOPAD_1, the second I / O pad IOPAD_2 and the third I / O pad IOPAD_3 at the same time, the first initialization signal INI_1, the second initialization signal INI_2 and the third initialization signal INI_3 are all at the first time point T i In other words, the first initialization signal INI_1, the second initialization signal INI_2, and the third initialization signal INI_3 may be generated at the first time point T i Substantially generated at the same time. Here, the term "substantially" includes PVT variations between each element or circuit. For example, although there may be a slight difference between the time point at which the initialization circuit 401 of the first address setting circuit 122_1 generates the first initialization signal INI_1 and the time point at which the initialization circuit 401 of the second address setting circuit 122_2 generates the second initialization signal INI_2 due to PVT variations, this is considered to be "substantially the same" in this specification. In addition, although the levels of the first initialization signal INI_1, the second initialization signal INI_2, and the third initialization signal INI_3 are shown as being at the first time point T iThe logic level of the first initialization signal INI_1, the second initialization signal INI_2, and the third initialization signal INI_3 may be changed from a logic low level to a logic high level, but example embodiments are not limited thereto. i From a logic high level to a logic low level. In this case, a person of ordinary skill in the technical field of the inventive concept may appropriately change the circuit to implement some example embodiments of the inventive concept.

[0063] The first input signal IN_1 may be a first signal V1 input from the outside. In some example embodiments, the first signal V1 is shown as a logic high level, but example embodiments are not limited thereto. For example, the first signal V1 may be a logic low level (e.g., a ground level), and in this case, a person of ordinary skill in the technical field of the inventive concept may appropriately change the circuit to implement some example embodiments of the inventive concept. Assuming that the delay of the first AND gate 402 of the first address setting circuit 122_1 is ignored, the level of the first initialization input signal IN'_1 may be based on the first time point T i From a logic low level to a logic high level.

[0064] The first_1 clock signal CLK1_1 may be a signal obtained by delaying the first initialization signal INI_1 by the first delay time ΔT1. According to some example embodiments, the first clock delay circuit 407 of the first address setting circuit 122_1 may delay the first initialization signal INI_1 by the first delay time ΔT1. In other words, the first clock delay circuit 407 of the first address setting circuit 122_1 may generate the first initialization signal INI_1 delayed by the first delay time ΔT1 as the first_1 clock signal CLK1_1. The second_1 clock signal CLK2_1 may be a signal obtained by delaying the first_1 clock signal CLK1_1 by the second delay time ΔT2. According to some example embodiments, the second clock delay circuit 408 of the first address setting circuit 122_1 may delay the first_1 clock signal CLK1_1 by the second delay time ΔT2. In other words, the second clock delay circuit 408 of the first address setting circuit 122_1 may generate the first_1 clock signal CLK1_1 delayed by the second delay time ΔT2 as the second_1 clock signal CLK2_1. The third _1 clock signal CLK3_1 may be a signal obtained by delaying the second _1 clock signal CLK2_1 by the third delay time ΔT3. According to some example embodiments, the third clock delay circuit 409 of the first address setting circuit 122_1 may delay the second _1 clock signal CLK2_1 by the third delay time ΔT3. In other words, the third clock delay circuit 409 of the first address setting circuit 122_1 may generate the second _1 clock signal CLK2_1 delayed by the third delay time ΔT3 as the third _1 clock signal CLK3_1. According to some example embodiments, the second delay time ΔT2 and the third delay time ΔT3 may be substantially the same. In addition, the first delay time ΔT1 may be less than the second delay time ΔT2 and the third delay time ΔT3. For example, the first delay time ΔT1 may be half of the second delay time ΔT2, but example embodiments are not limited thereto.

[0065] The first latch 404, the second latch 405, and the third latch 406 of the first address setting circuit 122_1 can store the level of the first input signal IN_1 at the time point when the level of the first_1 clock signal CLK1_1, the second_1 clock signal CLK2_1, and the third_1 clock signal CLK3_1 changes. Therefore, the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch of the first address setting circuit 122_1 can be 1 (logical high level), 1 (logical high level), and 1 (logical high level), respectively. As described above, the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch can be the address ADD of the memory chip 120. Therefore, the first address ADD_1 of the first memory chip 120_1 can be (1 1 1).

[0066] According to some example embodiments, the input delay circuit 403 of the first address setting circuit 122_1 may delay the first initialization input signal IN'_1 by a fourth delay time ΔT4. The input delay circuit 403 of the first address setting circuit 122_1 may provide the first initialization input signal IN'_1 delayed by the fourth delay time ΔT4 to the first output pad OPAD_1. The signal provided to the first output pad OPAD_1 may be provided to the second input pad IPAD_2 connected thereto. Therefore, the second input signal IN_2 may be substantially the same as the first initialization input signal IN'_1 delayed by the fourth delay time ΔT4. Assuming that the delay of the first AND gate 402 of the second address setting circuit 122_2 is ignored, the second input signal IN_2 may be substantially the same as the second initialization input signal IN'_2. In other words, the second input signal IN_2 and the second initialization input signal IN'_2 may be substantially the same as the first initialization input signal IN'_1 delayed by the fourth delay time ΔT4.

[0067] Similarly, the first_2 clock signal CLK1_2 may be a signal obtained by delaying the second initialization signal INI_2 by a fifth delay time ΔT5. In addition, the second_2 clock signal CLK2_2 may be a signal obtained by delaying the first_2 clock signal CLK1_2 by a sixth delay time ΔT6. In addition, the third_2 clock signal CLK3_2 may be a signal obtained by delaying the second_2 clock signal CLK2_2 by a seventh delay time ΔT7. In addition, the third input signal IN_3 and the third initialization input signal IN'_3 may be substantially the same as the second initialization input signal IN'_2 delayed by an eighth delay time ΔT8. In addition, the first_3 clock signal CLK1_3 may be a signal obtained by delaying the third initialization signal INI_3 by a ninth delay time ΔT9. In addition, the second_3 clock signal CLK2_3 may be a signal obtained by delaying the first_3 clock signal CLK1_3 by a tenth delay time ΔT10. In addition, the third_3 clock signal CLK3_3 may be a signal obtained by delaying the second_3 clock signal CLK2_3 by an eleventh delay time ΔT11.

[0068] According to some example embodiments, the first delay time ΔT1, the fifth delay time ΔT5, and the ninth delay time ΔT9 may be substantially the same as each other. In addition, the second delay time ΔT2, the sixth delay time ΔT6, and the tenth delay time ΔT10 may be substantially the same as each other. In addition, the third delay time ΔT3, the seventh delay time ΔT7, and the eleventh delay time ΔT11 may be substantially the same as each other. In addition, the fourth delay time ΔT4 and the eighth delay time ΔT8 may be substantially the same as each other.

[0069] According to some example embodiments, the second delay time ΔT2 to the fourth delay time ΔT4, the sixth delay time ΔT6 to the eighth delay time ΔT8, and the tenth delay time ΔT10 to the eleventh delay time ΔT11 may be substantially the same as each other. In other words, the delay time of the input delay circuit 403, and the delay time of the second clock delay circuit 408 and the third clock delay circuit 409 may be substantially the same as each other. In addition, the first delay time ΔT1, the fifth delay time ΔT5, and the ninth delay time ΔT9 may be less than the second delay time ΔT2 to the fourth delay time ΔT4, the sixth delay time ΔT6 to the eighth delay time ΔT8, and the tenth delay time ΔT10 to the eleventh delay time ΔT11.

[0070] According to some example embodiments, the first latch 404, the second latch 405, and the third latch 406 of the second address setting circuit 122_2 may store the level of the second input signal IN_2 (i.e., the first initialization input signal IN'_1 delayed by the fourth delay time ΔT4) at the time point when the levels of the first_2 clock signal CLK1_2, the second_2 clock signal CLK2_2, and the third_2 clock signal CLK3_2 change, respectively. Therefore, the output Q1 of the first latch of the second address setting circuit 122_2, the output Q2 of the second latch, and the output Q3 of the third latch may be 0 (logic low level), 1 (logic high level), and 1 (logic high level). Therefore, the second address ADD_2 of the second memory chip 120_2 may be (0 1 1). According to some example embodiments, the first latch 404, the second latch 405, and the third latch 406 of the third address setting circuit 122_3 may store the level of the third input signal IN_3 (i.e., the second initialization input signal IN'_2 delayed by the eighth delay time ΔT8) at the time point when the levels of the first_3 clock signal CLK1_3, the second_3 clock signal CLK2_3, and the third_3 clock signal CLK3_3 are changed, respectively. Therefore, the output Q1 of the first latch of the third address setting circuit 122_3, the output Q2 of the second latch, and the output Q3 of the third latch may be 0 (logic low level), 0 (logic low level), and 1 (logic high level), respectively. Therefore, the third address ADD_3 of the third memory chip 120_3 may be (0 0 1).

[0071] Figure 6 is an example diagram illustrating an address setting circuit according to some example embodiments. Figure 6 The configuration of the address setting circuit 122 shown in FIG. 1 can be similarly applied to all of the first to third address setting circuits 122_1 to 122_3. For the sake of convenience, contents that overlap with the above contents will be omitted or briefly described.

[0072] Reference Figure 6 , the input signal IN can be provided to the first AND gate 402. The first AND gate 402 can perform AND gating on the initialization signal INI and the input signal IN to output the initialization input signal IN'. The initialization input signal IN' can be provided to the input delay circuit 403, the first latch 404, the second latch 405 and the third latch 406.

[0073] The first latch 404 can store the initialization input signal IN' based on the first clock signal CLK1. In other words, the first latch 404 can store the level of the initialization input signal IN' when the level of the first clock signal CLK1 changes (rises or falls). The second latch 405 can store the initialization input signal IN' based on the second clock signal CLK2. In other words, the second latch 405 can store the level of the initialization input signal IN' at the time point when the level of the second clock signal CLK2 changes (rises or falls). The third latch 406 can store the initialization input signal IN' based on the third clock signal CLK3. In other words, the third latch 406 can store the level of the initialization input signal IN' at the time point when the level of the third clock signal CLK3 changes (rises or falls). According to Figure 6 The operation of the address setting circuit 122 can be similar to Figure 5 The timing diagram shown in .

[0074] Figure 7 is an example diagram for describing an address setting circuit according to some example embodiments. Figure 7 The configuration of the address setting circuit 122 shown in FIG. 1 can be similarly applied to all of the first to third address setting circuits 122_1 to 122_3. For the sake of convenience, contents that overlap with the above contents will be omitted or briefly described.

[0075] Reference Figure 7 According to some example embodiments, the address setting circuit 122 may include an initialization circuit 401, a first AND gate 402, a second AND gate 701, a third AND gate 703, a fourth AND gate 705, an input delay circuit 403, a first latch 404, a second latch 405, a third latch 406, a first clock delay circuit 407, a second clock delay circuit 408, a third clock delay circuit 409, a fourth clock delay circuit 410, a first inverter 702, a second inverter 704, and a third inverter 706.

[0076] The first clock delay circuit 407 can generate a first clock signal CLK1 by delaying the initialization signal INI. The second clock delay circuit 408 can generate a second clock signal CLK2 by delaying the first clock signal CLK1. The third clock delay circuit 409 can generate a third clock signal CLK3 by delaying the second clock signal CLK2. The fourth clock delay circuit 410 can generate a fourth clock signal CLK4 by delaying the third clock signal CLK3.

[0077] The first inverter 702 can invert the second clock signal CLK2 to generate an inverted signal of the second clock signal The second inverter 704 can invert the third clock signal CLK3 to generate an inverted signal of the third clock signal The third inverter 706 can invert the fourth clock signal CLK4 to generate an inverted signal of the fourth clock signal

[0078] The second AND gate 701 can generate an inverted signal of the first clock signal CLK1 and the second clock signal CLK2. The AND gate 703 performs AND gating to generate the first pulse clock signal PCLK1. The third AND gate 703 can generate the inverted signal of the second clock signal CLK2 and the third clock signal. The AND gate 705 performs AND gating to generate the second pulse clock signal PCLK2. The fourth AND gate 705 can generate the inverted signal of the third clock signal CLK3 and the fourth clock signal. AND gating is performed to generate the third pulse clock signal PCLK3. The first to third pulse clock signals PCLK1 to PCLK3 may be provided to the first to third latches 404 to 406, respectively.

[0079] Figure 8 1 is an example timing diagram for illustrating the operation of the address setting circuit according to some example embodiments. For ease of explanation, the first pulse clock signal PCLK1, the second pulse clock signal PCLK2, and the third pulse clock signal PCLK3 of the first address setting circuit 122_1 are defined as the first_1 pulse clock signal PCLK1_1, the second_1 pulse clock signal PCLK2_1, and the third_1 pulse clock signal PCLK3_1, respectively. In addition, the first pulse clock signal PCLK1, the second pulse clock signal PCLK2, and the third pulse clock signal PCLK3 of the second address setting circuit 122_2 are defined as the first_2 pulse clock signal PCLK1_2, the second_2 pulse clock signal PCLK2_2, and the third_2 pulse clock signal PCLK3_2, respectively. Similarly, the first pulse clock signal PCLK1, the second pulse clock signal PCLK2 and the third pulse clock signal PCLK3 of the third address setting circuit 122_3 are defined as the first_3 pulse clock signal PCLK1_3, the second_3 pulse clock signal PCLK2_3 and the third_3 pulse clock signal PCLK3_3, respectively. For the convenience of explanation, the contents repeated with the above contents will be omitted or briefly described.

[0080] The pulse widths of the first_1 pulse clock signal PCLK1_1 to the third_3 pulse clock signal PCLK3_3 may be the first width W1 to the ninth width W9, respectively. According to some example embodiments, the first width W1 may be substantially the same as the delay time (e.g., the second delay time ΔT2) of the second clock delay circuit 408 of the first address setting circuit 122_1. In other words, the time point at which the level of the first_1 pulse clock signal PCLK1_1 falls may be substantially the same as the time point at which the level of the second_1 pulse clock signal PCLK2_1 rises. Similarly, the time point at which the level of the second_1 pulse clock signal PCLK2_1 falls may be substantially the same as the time point at which the level of the third_1 pulse clock signal PCLK3_1 rises. Similarly, the time point at which the level of the first_2 pulse clock signal PCLK1_2 falls may be substantially the same as the time point at which the level of the second_2 pulse clock signal PCLK2_2 rises. Similarly, the time point at which the level of the second_2-pulse clock signal PCLK2_2 falls can be substantially the same as the time point at which the level of the third_2-pulse clock signal PCLK3_2 rises. In addition, the time point at which the level of the first_3-pulse clock signal PCLK1_3 falls can be substantially the same as the time point at which the level of the second_3-pulse clock signal PCLK2_3 rises, and the time point at which the second_3-pulse clock signal PCLK2_3 falls can be substantially the same as the time point at which the level of the third_3-pulse clock signal PCLK3_3 rises. That is, the first width W1 to the ninth width W9 can be substantially the same as the delay time of the second clock delay circuit 408 to the fourth clock delay circuit 410 of each address setting circuit 122.

[0081] Each latch included in the first address setting circuit 122_1 to the third address setting circuit 122_3 can store the level of the input signal IN at a time point when the levels of the first_1 pulse clock signal PCLK1_1, the second_1 pulse clock signal PCLK2_1, the third_1 pulse clock signal PCLK3_1, the first_2 pulse clock signal PCLK1_2, the second_2 pulse clock signal PCLK2_2, the third_2 pulse clock signal PCLK3_2, the first_3 pulse clock signal PCLK1_3, the second_3 pulse clock signal PCLK2_3 and the third_3 clock signal PCLK3_3 change from a logic low level to a logic high level.

[0082] Although not shown, the address setting circuit 122 according to some example embodiments may store the level of the initialization input signal IN' at a time point when the levels of the first to third pulse clock signals PCLK1 to PCLK3 change. A person of ordinary skill in the technical field of the inventive concept may change the circuit configuration in various ways.

[0083] Fig. 9 is an example diagram for describing an address setting circuit according to some example embodiments. Fig. 9 The configuration of the address setting circuit 122 shown in FIG. 1 can be similarly applied to all of the first to third address setting circuits 122_1 to 122_3 . Fig.10 1 is an example timing diagram for explaining the operation of the address setting circuit according to some example embodiments. For the convenience of explanation, the contents repeated with the above contents will be omitted or briefly explained.

[0084] Reference Fig. 9 and Fig.10 According to some example embodiments, the address setting circuit 122 may include an initialization circuit 401, a first AND gate 402, a second AND gate 701, a third AND gate 703, a fourth AND gate 705, an input delay circuit 403, a first latch 404, a second latch 405, a third latch 406, a first clock delay circuit 407, a first sub-clock delay circuit 901, a second sub-clock delay circuit 902, a third sub-clock delay circuit 903, a fourth sub-clock delay circuit 904, a fifth sub-clock delay circuit 905, a sixth sub-clock delay circuit 906, a first inverter 702, a second inverter 704, and a third inverter 706.

[0085] The first clock delay circuit 407 can generate a first clock signal CLK1 by delaying the initialization signal INI. The first sub-clock delay circuit 901 can generate a first sub-clock signal CLK2' by delaying the first clock signal CLK1. The second sub-clock delay circuit 902 can generate a second clock signal CLK2 by delaying the first sub-clock signal CLK2'. The third sub-clock delay circuit 903 can generate a second sub-clock signal CLK3' by delaying the second clock signal CLK2. The fourth sub-clock delay circuit 904 can generate a third clock signal CLK3 by delaying the second sub-clock signal CLK3'. The fifth sub-clock delay circuit 905 can generate a third sub-clock signal CLK4' by delaying the third clock signal CLK3.

[0086] The first inverter 702 can invert the first sub-clock signal CLK2' to generate an inverted signal of the first sub-clock signal The second inverter 704 can invert the second sub-clock signal CLK3' to generate an inverted signal of the second sub-clock signal The third inverter 706 can invert the third sub-clock signal CLK4′ to generate an inverted signal of the third sub-clock signal

[0087] The second AND gate 701 can generate an inverted signal of the first clock signal CLK1 and the first sub-clock signal. The AND gate 703 performs AND gating to generate the first pulse clock signal PCLK1. The third AND gate 703 can generate the inverted signal of the second clock signal CLK2 and the second sub-clock signal. The fourth AND gate 705 can generate the second pulse clock signal PCLK2 by performing AND gating. AND gating is performed to generate the third pulse clock signal PCLK3.

[0088] The time point at which the level of the first pulse clock signal PCLK1_1 falls may be before the time point at which the level of the second_1 pulse clock signal PCLK2_1 rises. Similarly, the time point at which the level of the second_1 pulse clock signal PCLK2_1 falls may be before the time point at which the level of the third_1 pulse clock signal PCLK3_1 rises. Similarly, the time point at which the level of the first_2 pulse clock signal PCLK1_2 falls may be before the time point at which the level of the second_2 pulse clock signal PCLK2_2 rises. Similarly, the time point at which the level of the second_2 pulse clock signal PCLK2_2 falls may be before the time point at which the level of the third_2 pulse clock signal PCLK3_2 rises. In addition, the time point at which the level of the first_3 pulse clock signal PCLK1_3 falls may be before the time point at which the level of the second_3 pulse clock signal PCLK2_3 rises, and the time point at which the level of the second_3 pulse clock signal PCLK2_3 rises may be before the time point at which the level of the third_3 pulse clock signal PCLK3_3 rises. That is, the first width W1 to the ninth width W9 may be smaller than Figure 7 The delay time from the second clock delay circuit 408 to the fourth clock delay circuit 410 is as follows.

[0089] Each latch included in the first to third address setting circuits 122_1 to 122_3 may store an input signal when the level of the first_1 pulse clock signal PCLK1_1, the second_1 pulse clock signal PCLK2_1, the third_1 pulse clock signal PCLK3_1, the first_2 pulse clock signal PCLK1_2, the second_2 pulse clock signal PCLK2_2, the third_2 pulse clock signal PCLK3_2, the first_3 pulse clock signal PCLK1_3, the second_3 pulse clock signal PCLK2_3, and the third_3 pulse clock signal PCLK3_3 changes from a logic low level to a logic high level. Even though not shown, the address setting circuit 122 according to some example embodiments may store the level of the initialization input signal IN' at a time point when the level of the first to third pulse clock signals PCLK1 to PCLK3 changes. A person of ordinary skill in the technical field of the inventive concept may change the circuit configuration in various ways.

[0090] Fig.11 is an exemplary diagram for explaining a case where an address setting circuit abnormally operates according to some example embodiments. Fig.11 A case where an error occurs in the first clock delay circuit 407 and the first to sixth sub-clock delay circuits 901 to 906 included in the third address setting circuit 122_3 is hypothetically shown.

[0091] Reference Figure 3 , Fig. 9 and Fig.11 , due to external factors (e.g., PVT changes), the delay time of the first clock delay circuit 407 and the first sub-clock delay circuit 901 to the sixth sub-clock delay circuit 906 becomes shorter than the preset delay time. At this time, the third address ADD_3 output by the third address setting circuit 122_3 is not the target address (0 0 1), but may output (0 0 0). When these problems occur, due to the host ( Figure 1 200) may not recognize the change of the third address ADD_3, so the third memory chip 120_3 may not be selected, and the storage device ( Figure 1 An error occurred in the operation of 100).

[0092] Fig.12 is an example diagram for explaining an address setting circuit for reducing (or alternatively, preventing) a failure of address setting according to some example embodiments. Fig.12 The configuration of the address setting circuit 122 shown in FIG. 1 can be similarly applied to all of the first to third address setting circuits 122_1 to 122_3 . Fig.13 is an example timing diagram for explaining the operation of an address setting circuit for reducing (or alternatively, preventing) a failure of address setting according to some example embodiments. For ease of explanation, contents repeated with the above contents will be omitted or briefly described.

[0093] Reference Fig.12 The second AND gate 701 can be used to generate the inverted signal of the first clock signal CLK1 and the first sub-clock signal The third AND gate 703 performs AND gating on the second clock signal CLK2 and the inverted signal of the second sub-clock signal. The fourth AND gate 705 performs AND gating with the input signal IN to generate the second pulse clock signal PCLK2. The fourth AND gate 705 can generate the inverted signal of the third clock signal CLK3 and the third sub-clock signal AND gate is performed with the input signal IN to generate the third pulse clock signal PCLK3.

[0094] The first latch 404 to the third latch 406 may initially store 0 (logical low level), respectively. In other words, the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch may initially be set to 0 (logical low level). Although not shown in the drawings, for example, the signals stored in the first latch 404 to the third latch 406 may be initialized to 0 (logical low level) based on the initialization signal INI. However, the example embodiments are not limited thereto, and a person of ordinary skill in the technical field of the inventive concept may implement several embodiments of the inventive concept in various ways.

[0095] Reference Fig.13 , since the level of the third input signal IN_3 is 0 (logic low level), the levels of the first 3-pulse clock signal PCLK1_3 and the second 3-pulse clock signal PCLK2_3 may not change. Therefore, only the third 3-pulse clock signal PCLK3_3 may be generated, and the third 3-pulse clock signal PCLK3_3 is generated after the level of the third input signal IN_3 becomes 1 (logic high level). At this time, since 0 (logic low level) is stored in each of the first latch 404 and the second latch 405, the third address setting circuit 122_3 may output the third address ADD_3 as (0 0 1).

[0096] Even when the delay time of some delay circuits is shortened and the third address setting circuit 122_3 operates abnormally, the third_3 pulse clock signal PCLK3_3 may be generated. In other words, when there is a portion where the third_3 pulse clock signal PCLK3_3 remains at 1 (logic high level) after the time point at which the level of the third input signal IN_3 becomes 1 (logic high level), the third_3 pulse clock signal PCLK3_3 may still be generated. According to some example embodiments, the third_3 pulse clock signal PCLK3_3 may be generated by the fourth AND gate 705 of the third address setting circuit 122_3 that performs AND gating on the third input signal IN_3. Therefore, when the third input signal IN_3 undergoes AND gating, due to the occurrence of fine delay, the time point at which the level of the third_3 pulse clock signal PCLK3_3 changes becomes later than the time point at which the level of the third input signal IN_3 changes. In other words, since the third latch 406 of the third address setting circuit 122_3 stores the level of the third input signal IN_3 after the time point when the level of the third input signal IN_3 changes, the third address setting circuit 122_3 can successfully output the third address ADD_3 as (0 0 1).

[0097] Fig.141 is an example diagram for explaining an address setting circuit according to some example embodiments. For ease of description, the contents repeated with the above contents will be omitted or briefly described. The address setting circuit 122 according to some example embodiments may include an initialization circuit 401, a first AND gate 402, a first latch 404, a second latch 405, a third latch 406, a ring oscillator 1410, and a clock controller 1420.

[0098] The ring oscillator 1410 may include a fifth AND gate 1411 and an odd number of fourth inverters 1412. The ring oscillator 1410 may generate a first pulse clock signal PCLK1, a second pulse clock signal PCLK2, and a third pulse clock signal PCLK3.

[0099] The clock controller 1420 may provide the pulse clock generated by the ring oscillator 1410 to the first latch 404 to the third latch 406, respectively. In other words, the clock controller 1420 may provide the first pulse clock signal PCLK1 to the first latch 404, may provide the second pulse clock signal PCLK2 to the second latch 405, and may provide the third pulse clock signal PCLK3 to the third latch 406. For example, the clock controller 1420 may determine the signal of the first cycle of the ring oscillator 1410 as the first pulse clock signal PCLK1, may determine the signal of the second cycle as the second pulse clock signal PCLK2, and may determine the signal of the third cycle as the third pulse clock signal PCLK3. The first pulse clock signal PCLK1 to the third pulse clock signal PCLK3 may be pulse clock signals having different delay times from each other. For example, the first pulse clock signal PCLK1 may be before the second pulse clock signal PCLK2, and the second pulse clock signal PCLK2 may be before the third pulse clock signal PCLK3. According to some example embodiments, even when the number of latches included in the address determination circuit increases (i.e., when the number of memory chips increases), since the number of ring oscillators 1410 does not increase, it may be advantageous in reducing the size and cost of the memory chip 120.

[0100] Fig.15 is an example diagram for describing an address setting circuit according to some example embodiments. Fig.16 is an example flow chart for explaining the operation of an address setting circuit according to some example embodiments. Fig.15 Shows Figure 4 The address setting circuit further includes a sixth AND gate 1520, a seventh AND gate 1530 and a control circuit 1510, but example embodiments are not limited thereto. Figure 6 , Figure 7 , Fig. 9 , Fig.12 and Fig.14 The described address setting circuit may further include a sixth AND gate 1520, a seventh AND gate 1530, and a control circuit 1510. For the convenience of description, the contents repeated with the above contents will be omitted or briefly described.

[0101] Reference Fig.15 and Fig.16 The address setting circuit 122 may include an initialization circuit 401, a first AND gate 402, a sixth AND gate 1520, a seventh AND gate 1530, an input delay circuit 403, a first latch 404, a second latch 405, a third latch 406, a control circuit 1510, a first clock delay circuit 407, a second clock delay circuit 408 and a third clock delay circuit 409.

[0102] The sixth AND gate 1520 may perform AND gating on the address setting command CMD transmitted through the I / O pad IOPAD and the input block signal BK1 of the control circuit 1510, and may output them to the initialization circuit 401. The seventh AND gate 1530 may perform AND gating on the input signal IN and the input block signal BK1, and provide them to the first AND gate 402.

[0103] The control circuit 1510 receives the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch as input, and can output the address ADD, the input block signal BK1, the first delayed feedback signal FD1, the second delayed feedback signal FD2, and the third delayed feedback signal FD3.

[0104] In operation S1610, the initialization circuit 401 may receive an address setting command CMD, and in operation S1620, the address setting circuit 122 may perform the above-described address setting operation. According to some example embodiments, the input block signal BK1 of the control circuit 1510 may have 1 (logic high level) as an initial value.

[0105] In operation S1630, the control circuit 1510 may compare the address set by the address setting operation with the target address. For example, the control circuit 1510 may compare the target address with the output Q1 of the first latch, the output Q2 of the second latch, and the output Q3 of the third latch.

[0106] If the set address matches the target address, the control circuit 1510 outputs the set address ADD, cuts off the signal input to the address setting circuit 122, and may end the address setting operation in operation S1640.

[0107] For example, the control circuit 1510 may output 0 (logic low level) to the input block signal BK1 to cut off the signal input to the address setting circuit 122. Therefore, all inputs input to the address setting circuit 122 are cut off by the sixth and seventh AND gates 1520 and 1530 to minimize external influences (e.g., PVT changes). In some example embodiments, a match between the set address and the target address may indicate a case where the set address is a success code (e.g., 1 1 1).

[0108] In operation S1650 , if the set address does not match the target address, the control circuit 1510 may adjust the delay time of the first to third clock delay circuits 407 to 409 .

[0109] For example, the control circuit 1510 may send the first delayed feedback signal FD1 to the third delayed feedback signal FD3 to the first clock delay circuit 407 through the third clock delay circuit 409, thereby adjusting the delay time from the first clock delay circuit 407 to the third clock delay circuit 409. The first clock delay circuit 407 to the third clock delay circuit 409 receiving the first delayed feedback signal FD1 to the third delayed feedback signal FD3 may increase or decrease the corresponding delay time. In some example embodiments, the mismatch between the set address and the target address may indicate a case where the set address is a fail code (e.g., 0 0 0).

[0110] According to some example embodiments, the success code may be a code predetermined (or expected) to be used as the address of the memory chip 120, and the failure code may represent another code instead of the success code.

[0111] After the control circuit 1510 adjusts the delay time of the first to third clock delay circuits 407 to 409 , the address setting circuit 122 may perform the address setting operation again ( S1620 ).

[0112] Fig.17 is an exemplary diagram for explaining a modified example of a storage device according to some example embodiments.

[0113] Reference Fig.17 , the memory device 1700 may include a controller 1710 , a first memory chip 1720_1 , a second memory chip 1720_2 , and a third memory chip 1720_3 .

[0114] The first memory chip 1720_1 may include a first latch 1722_1. The second memory chip 1720_2 may include a second latch 1722_2. The third memory chip 1720_3 may include a third latch 1722_3. The controller 1710 may provide a first signal S1 to each of the first to third memory chips 1720_1 to 1720_3. The time points at which the first signal S1 is applied to the first to third memory chips 1720_1 to 1720_3 may be different from each other. For example, the time point at which the first signal S1 is applied to the first memory chip 1720_1 may be before the time point at which the first signal S1 is applied to the second memory chip 1720_2. For example, the time point at which the first signal S1 is applied to the second memory chip 1720_2 may be before the time point at which the first signal S1 is applied to the third memory chip 1720_3.

[0115] The controller 1710 may provide a second signal S2 to each of the first to third memory chips 1720_1 to 1720_3. The time points at which the second signal S2 is applied to the first to third memory chips 1720_1 to 1720_3 may be substantially the same as each other. In other words, the second signal S2 may be provided to the first to third memory chips 1720_1 to 1720_3 substantially at the same time. The first latch 1722_1 included in the first memory chip 1720_1 may store the first signal S1 based on the second signal S2. For example, the first latch 1722_1 may store the level of the first signal S1 at a time point at which the level of the second signal S2 changes. The second latch 1722_2 included in the second memory chip 1720_2 may store the first signal S1 based on the second signal S2. For example, the second latch 1722_2 may store the level of the first signal S1 at a time point at which the level of the second signal S2 changes. The third latch 1722_3 included in the third memory chip 1720_3 may store the first signal S1 based on the second signal S2. For example, the third latch 1722_3 may store the level of the first signal S1 at a time point when the level of the second signal S2 changes.

[0116] Since the first signal S1 may be provided to the first to third memory chips 1720_1 to 1720_3 at different time points, the levels of the first signal S1 stored in the first to third latches 1722_1 to 1722_3 may be different from each other. According to some example embodiments, the levels of the first signal S1 stored in the first to third latches 1722_1 to 1722_3 may be address information of the corresponding memory chip.

[0117] Fig.18are exemplary diagrams for explaining modified examples of storage devices according to some other example embodiments.

[0118] Reference Fig.18 , the memory device 1800 may include a controller 1810, a first memory chip 1820_1, and a second memory chip 1820_2. According to some example embodiments, the controller 1810 may include a signal generator 1812, a timing controller 1814, a signal delay circuit 1816, and a chip selector 1818. The first memory chip 1820_1 may include a first input delay circuit 1824_1, and the second memory chip 1820_2 may include a second input delay circuit 1824_2. Each of the first memory chip 1820_1 and the second memory chip 1820_2 may include chip enable terminals CE1 and CE2.

[0119] The signal generator 1812 may generate a third signal S3. The generated third signal S3 may be provided to the timing controller 1814 and the signal delay circuit 1816. The timing controller 1814 may delay the third signal S3 by a twelfth delay time and provide it to the first memory chip 1820_1 as a fourth signal S4. The twelfth delay time is a variable time, and the timing controller 1814 may determine the twelfth delay time based on a command from the host. The signal delay circuit 1816 may delay the third signal S3 by a thirteenth delay time and provide it to the chip selector 1818 as a fifth signal S5, the thirteenth delay time being greater than the twelfth delay time. The first input delay circuit 1824_1 may receive the fourth signal S4, delay the fourth signal S4, and provide it to the second input delay circuit 1824_2 as a first delay signal D1. The second input delay circuit 1824_2 may receive the first delay signal D1, and delay the first delay signal D1 to generate a second delay signal D2. The chip selector 1818 may compare the fifth signal S5 with the first and second delayed signals D1 and D2 to provide a chip enable signal to a chip enable terminal ( CE1 or CE2 ) of the first or second memory chip 1820_1 or 1820_2 .

[0120] For example, it is assumed that the delay value of the signal delay circuit 1816 is 10, and the delay value of each of the first input delay circuit 1824_1 and the second input delay circuit 1824_2 is 2. The timing controller 1814 can set the twelfth delay time to 8 according to the command from the host so as to select the first memory chip 1820_1. At this time, the fifth signal S5 obtained by delaying the third signal S3 by 10 and the first delay signal D1 obtained by delaying the third signal S3 by 8 and 2 are substantially the same signal. Since the fifth signal S5 and the first delay signal D1 are substantially the same, the chip selector 1818 can provide a chip enable signal to the chip enable terminal CE1 of the first memory chip 1820_1.

[0121] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the disclosed exemplary embodiments are only used in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A memory chip, comprising: a first input pad configured to receive a first input signal, a first initialization circuit configured to generate a first initialization signal, a first input delay circuit configured to set a first delay time based on a first initialization signal and delay the first input signal by the first delay time to generate a first output signal, a first output pad configured to receive the first output signal and output the first output signal to the outside, a first clock delay circuit configured to delay the first initialization signal by a second delay time to generate a first clock signal, wherein the second delay time is different from the first delay time, a second clock delay circuit configured to delay the first clock signal by a third delay time to generate a second clock signal, wherein the third delay time is different from the second delay time, a first latch configured to store the first input signal based on the first clock signal, and A second latch is configured to store the first input signal based on the second clock signal.

2. The memory chip according to claim 1, further comprising: a first AND gate configured to perform AND gating on the first clock signal and the inverted signal of the second clock signal to generate a first pulse clock signal, wherein The first latch is configured to store the first input signal based on the first pulse clock signal.

3. The memory chip according to claim 1, wherein: The second clock delay circuit includes a first sub-clock delay circuit and a second sub-clock delay circuit, the first sub-clock delay circuit is configured to delay the first clock signal by a fourth delay time to generate a first sub-clock signal, and the second sub-clock delay circuit is configured to delay the first sub-clock signal by a fifth delay time to generate a second clock signal, and the first memory chip further includes: a first AND gate configured to perform AND gating on the first clock signal and the inverted signal of the first sub-clock signal to generate a first pulse clock signal, wherein The first latch is configured to store the first input signal based on the first pulse clock signal.

4. The memory chip according to claim 3, wherein: The fourth delay time is shorter than the fifth delay time.

5. The memory chip according to claim 3, wherein: The first AND gate is configured to perform AND gating on the first input signal, the first clock signal, and an inverted signal of the first sub-clock signal to generate the first pulse clock signal.

6. The memory chip according to claim 1, wherein: The first delay time is substantially the same as the third delay time.

7. The memory chip according to claim 1, wherein: The second delay time is smaller than each of the first delay time and the third delay time.

8. The memory chip according to claim 1, further comprising: A first control circuit is configured to compare the signals stored in the first latch and the second latch with a desired target address.

9. The memory chip according to claim 8, wherein: The first control circuit is configured to adjust the delay time of the first clock delay circuit and the second clock delay circuit in response to the signals stored in the first latch and the second latch being different from the expected target address, and The first control circuit is configured to output the signals stored in the first latch and the second latch as a first address of the memory chip in response to the signals stored in the first latch and the second latch being identical to the desired target address.

10. A storage device, comprising: Controller; A first memory chip includes a first address setting circuit, wherein the first address setting circuit is configured as follows: receiving an address setting command from the controller to generate a first initialization signal, receiving a signal from outside to generate a first input signal, Setting a first delay time based on the first initialization signal, delaying the first input signal by the first delay time to generate a first output signal, delaying the first initialization signal by a second delay time to generate a first clock signal, determining a first output time point based on the first clock signal, and outputting the level of the first input signal at the first output time point as the first value of the first address of the first memory chip; as well as A second memory chip includes a second address setting circuit configured to receive the first output signal from the first address setting circuit.

11. The storage device according to claim 10, wherein: The second delay time is shorter than the first delay time.

12. The storage device according to claim 10, wherein: The first address setting circuit is configured as follows: delaying the first clock signal by a third delay time to generate a second clock signal, and AND gate is performed on the first clock signal and the inverted signal of the second clock signal to generate a first pulse clock signal, wherein The first address setting circuit is configured to determine the first output time point as a time point at which a level of the first pulse clock signal changes.

13. The storage device according to claim 10, wherein: The first address setting circuit is configured as follows: delaying the first clock signal by a third delay time to generate a first sub-clock signal, delaying the first sub-clock signal by a fourth delay time to generate a second clock signal, and The first clock signal and the inverted signal of the first sub-clock signal are AND-gated to generate a first pulse clock signal, wherein The first address setting circuit is configured to determine the first output time point as a time point at which a level of the first pulse clock signal changes.

14. The storage device according to claim 13, wherein: The third delay time is shorter than the fourth delay time.

15. The storage device according to claim 10, wherein: The first address setting circuit is configured as follows: delaying the first clock signal by a third delay time to generate a first sub-clock signal, delaying the first sub-clock signal by a fourth delay time to generate a second clock signal, and The first clock signal, the inverted signal of the first sub-clock signal and the first input signal are AND-selected to generate a first pulse clock signal, wherein The first address setting circuit is configured to determine the first output time point as a time point at which a level of the first pulse clock signal changes.

16. The storage device according to claim 10, wherein: The second address setting circuit is configured as follows: receiving the address setting command from the controller to generate a second initialization signal, receiving the first output signal to generate a second input signal, delaying the second initialization signal by a third delay time to generate a second clock signal, determining a second output time point based on the second clock signal, and At the second output time point, the level of the second input signal is output as the first value of the second address of the second memory chip, wherein The first initialization signal and the second initialization signal are generated substantially simultaneously.

17. The storage device according to claim 16, wherein: The third delay time is substantially the same as the second delay time.

18. The storage device according to claim 16, wherein: The third delay time is shorter than the first delay time.

19. A memory chip, comprising: a first input pad configured to receive a first input signal; a first initialization circuit configured to provide a first initialization signal; a first input delay circuit configured to delay the first input signal based on the first initialization signal; A first ring oscillator configured to generate a first clock signal and a second clock signal, such that the second clock signal is the first clock signal delayed by a first delay time; a first latch configured to store the first input signal based on the first clock signal; a second latch configured to store the first input signal based on the second clock signal; as well as A first clock controller is configured to provide the first clock signal and the second clock signal to the first latch and the second latch, respectively.

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