Electronic chip with analog input and output

Abstract

Embodiments of the present disclosure relate to electronic chips with analog inputs and outputs. An electronic chip includes analog input connection pads and analog output connection pads. A switch is coupled between the analog input connection pads and the analog output connection pads. In one embodiment, the chip operates in a self-test mode and an active mode. The switch is closed only in the self-test mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French Patent Application No. 1858150 filed on September 12, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic circuits and, in particular embodiments, to electronic integrated circuits designed to generate and / or receive analog signals. Background Art

[0004] Some electronic integrated circuit chips include analog circuits. Typically, analog signals generated and / or received by these circuits flow out of and into the chip through analog outputs and inputs, respectively. Summary of the invention

[0005] One embodiment overcomes all or some of the disadvantages of known electronic chips with analog input / output.

[0006] One embodiment overcomes all or part of the disadvantages of known analog electronic chip circuits

[0007] One embodiment provides an electronic chip comprising at least two corresponding analog input and output connection pads and at least one electrical link having the capability of being temporarily activated between the input and output pads.

[0008] According to one embodiment, a chip includes an analog signal generator configured to apply an analog signal to an output pad.

[0009] According to one embodiment, the chip is configured so as to be always disabled outside of a self-test phase.

[0010] According to one embodiment, a chip includes a receiver configured to receive an analog signal applied to an input pad.

[0011] According to one embodiment, the link comprises a switch connected between the pads, or comprises a plurality of switches connected in series between the pads.

[0012] According to one embodiment, the chip comprises one or more first memory locations for storing control logic levels of the switch(es).

[0013] According to one embodiment, the chip is configured to protect writing to the first memory location by a password.

[0014] According to one embodiment, the chip comprises an additional chip which can be activated during a use phase of the chip and comprises a second memory location for storing a control logic level of the additional switch.

[0015] According to one embodiment, the first memory location is configured to further store additional control logic levels of additional switches during the self-test phase.

[0016] One embodiment provides a method of designing a chip as defined above.

[0017] According to one embodiment, the design method comprises associating each of the pads with one of the switches in a design block in a computer design library, the design block being identical for a plurality of pads, preferably each design block comprising a resistor connected to the pad.

[0018] According to one embodiment, the design block comprises a plurality of switches connected to the pads, preferably, the number of the switches is three.

[0019] One embodiment provides a method of self-testing an electronic chip, comprising activating at least one electrical link between at least two corresponding analog signal input and analog signal output pads.

[0020] According to one embodiment, a self-test method includes simultaneously testing an analog signal generator and an analog signal receiver.

[0021] According to one embodiment, a self-test method includes receiving, by a receiver, a signal generated by a generator and transmitted over a link from an output pad to an input pad.

[0022] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 One embodiment of an electronic chip with analog input / output is schematically shown;

[0024] Figure 2 Another embodiment of an electronic chip with analog input / output is schematically shown; and

[0025] Figure 3 A further embodiment of an electronic chip with analog input / output is schematically shown. DETAILED DESCRIPTION

[0026] In different drawings, the same elements are represented by the same reference numerals. In particular, the common structural and / or functional elements of different embodiments can be represented by the same reference numerals and can have the same structure, size and material properties.

[0027] For the sake of clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the digital circuits of an electronic chip with analog input / output are not described in detail, the described embodiments are compatible with conventional electronic chips with analog input / output. Further, the packaging of the integrated circuit is not shown, the described embodiments are compatible with conventional packaging.

[0028] Throughout this disclosure, the term "connected" is used to indicate an electrical connection between circuit elements that is direct and has no intermediate elements other than conductors, while the term "coupled" is used to indicate an electrical connection between circuit elements. The electrical connection may be direct or via one or more intermediate elements.

[0029] In the following description, unless otherwise specified, when referring to terms indicating absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative positions (such as terms "above", "below", "upper", "lower", etc.), or terms indicating directions (such as terms "horizontal", "vertical", etc.), they refer to the orientation in the drawings.

[0030] In this document, the terms “approximately”, “substantially”, “about” are used to indicate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0031] Figure 1 One embodiment of an electronic chip 100 with analog input / output is schematically shown.

[0032] Chip 100 generally includes a semiconductor wafer, not shown, and circuits formed inside and above the wafer. Chip 100 is preferably a chip of a system-on-chip (SOC). SOC-type chips are particularly used for carrying or mobile applications, such as mobile phones, connected objects, household appliances or transporters. Preferably, chip 100 is intended to be arranged in an integrated circuit package (not shown). The package is preferably intended to be connected (e.g., welded or soldered) to an external electronic device, such as a PCB-type ("printed circuit board") circuit.

[0033] The chip 100 includes a digital circuit 110. The circuit 110 generally includes at least one sequential data processing unit (eg, of the microprocessor type), and various peripheral devices (eg, memory and / or interfaces for digital communication with the outside of the chip).

[0034] The circuit 110, in particular the microprocessor, communicates with the analog circuit 120 of the chip, preferably through a digital / analog interface circuit. The digital / analog interface circuit is typically of the digital-to-analog converter (DAC) 130 type or the analog-to-digital converter (ADC) 132 type. Although two DAC and ADC circuits are shown as examples, the chip may include more than two digital / analog interface circuits, for example, multiple DAC-type circuits and / or multiple ADC-type circuits. In addition, the digital / analog interface circuit of the chip may be of any type, possibly not a DAC or an ADC. The chip may, for example, include a digital / analog interface circuit (such as a comparator) that outputs a digital signal from an analog signal.

[0035] Analog circuit 120 is coupled to connection pads 140 and 142. As an example, Figure 1 A single output pad 142 and a single input pad 140 are shown. However, the chip preferably includes more than two input connection pads 140, and the chip preferably includes more than two output connection pads 142. The connection pads 140, 142 are typically formed by conductive areas (e.g., metal areas) located on the surface of the chip 100. These areas have, for example, the same rectangular or square shape. Preferably, the side length d1 of these areas is in the range of 50 μm to 150 μm. The connection pads can be connected to circuits outside the chip, preferably circuits outside the package in which the chip is intended to be arranged. Preferably, the pads can be connected to, for example, pins of the package by soldering or welding. These pins are intended to be soldered or welded to devices outside the package.

[0036] Pad 140 is an analog input pad and pad 142 is an analog output pad, which are used to allow analog signals to enter and output analog signals respectively. The term "analog signal" here means an electrical signal that represents information and has a continuously changing value when the information represented changes continuously. Preferably, the signal can take any value within a continuous range of values. The signal cannot take a value outside of this range. Preferably, the value of the signal is a voltage or current value.

[0037] Preferably, the voltage value corresponds to the potential of the relevant input or output pad relative to a reference potential (eg ground).As a variant, the signal corresponds to the difference between the potentials of two input pads of a signal, or to the difference between the potentials of two output pads of a signal.

[0038] As an example, the analog signal has a voltage value range, preferably, the voltage value range is included in the range of 0V to 5V (for example, included in the range of 0V to 3.6V). In another example, the analog signal has a current value range, for example, it is included in the range of -10mA to 10mA. When used, the analog input signal is generally derived from a sensor external to the chip. The analog output signal is generally used by an actuator external to the chip.

[0039] In this embodiment, the chip includes a link 150 between the output pad 142 and the input pad 140. The link 150 includes a switch 152. As a variation, the link 150 includes a plurality of switches (e.g., two or more switches) connected in series. Preferably, the switch includes a transistor, or the switch is formed by a transistor. For example, the transistor is a field effect transistor (such as a MOS transistor), or a bipolar transistor.

[0040] In operation, link 150 is active when switch 152 is on or conducting, i.e., any signal applied to one of its coupled pads (e.g., pad 140) is transmitted to another of its coupled pads (e.g., pad 142). When switch 152 is off or non-conducting, link 150 is inactive. Thus, link 150 can be temporarily activated by switching switch 152 on and then off. As a variant, the chip can include other links 150 that can be temporarily activated between analog input and output pads.

[0041] Preferably, output pad 142 is coupled (eg, connected) to the output of DAC circuit 130. Preferably, input pad 140 is coupled (eg, connected) to the input of ADC circuit 132.

[0042] Preferably, a built-in self-test ("BIST") phase of chip self-test is provided. During this phase, digital circuit 110 specifically verifies the correct operation of analog circuit 120 and digital / analog interface circuits 130 and 132. Preferably, link 150 is active during at least a portion of the self-test phase.

[0043] When link 150 is active, the digital circuit 110 of the chip sends a digital value 160 to the DAC circuit 130. Based on the digital value 160, the DAC circuit 130 generates an analog signal 162. The signal 162 is applied to the pad 142. The link 150 then applies the signal 162 to the pad 140. The signal 162 is received by the ADC circuit 132. The ADC circuit 132 converts the signal into a digital value 164. The digital value 164 is received by the digital circuit 110. The digital circuit 110 then verifies that the received digital value 164 is the digital value that is expected to be obtained in the case of correct operation of the circuits 130 and 132. Therefore, the activation of the link 150 can test the circuits 130 and 132 at the same time.

[0044] Thus, the operation of DAC circuit 130 is tested without measuring signal 162 applied to pad 142 by a device external to the chip. In addition, the operation of ADC circuit 132 is tested without applying a signal generated by a device external to the chip to pad 140. Thus, chip testing is simplified. Further, none of the chip's connection pads are used to test circuits 130 and 132, thereby reducing the number of analog and / or digital connection pads used to test all chip circuits.

[0045] Preferably, the same chip is capable of performing multiple functions corresponding to multiple applications. Therefore, multiple identical chips are intended to be arranged in different integrated circuit packages. This enables the package to be selected according to the target application. Preferably, for some applications, some connection pads 140, 142 are set to be connected or coupled to the pins of the package, and for other applications, some connection pads 140, 142 are set to be not connected to the pins. Therefore, packages with different numbers of pins are provided for the same chip. When the chip is in the package and (multiple) pads 140 and / or 142 are not connected, the link 150 allows the operation of the DAC circuit 130 and the ADC circuit 132 to be tested.

[0046] Furthermore, signal 162 may have a shorter path to diagnostic ADC circuit 132 and be less exposed to interference (e.g., electromagnetic interference) than signals generated by devices external to the chip. Thus, the accuracy of the test is improved relative to testing using devices external to the chip.

[0047] Preferably, link 150 is always inactive outside of the self-test phase. In particular, link 150 preferably remains inactive during the use phase of the chip. This enables DAC circuit 130 and ADC circuit 132 to be used independently of each other, i.e., DAC circuit 130 and ADC circuit 132 can generate and receive different analog signals used by and originating from devices external to the chip.

[0048] As a variation, the DAC circuit 130 can be replaced by any other analog signal generating circuit, such as an amplifier or a reference voltage generator. The ADC circuit 132 can be replaced by any other analog signal receiving circuit, such as an amplifier or a comparator. Due to the link 150, the generator and the receiver can be tested simultaneously during the self-test phase and can be used independently of each other during the use phase. Preferably, the chip includes a plurality of links 150, which couple the output pads of a plurality of analog signal generators to the input pads of one or more analog signal receivers. During the self-test, each link 150 enables the generator and the receiver to be tested simultaneously.

[0049] Figure 2 One embodiment of an electronic chip 200 with analog input / output is schematically shown. The chip 200 includes Figure 1 100, which are identical or similarly coupled together, except that pad 140 is coupled to ADC circuit 132 via switch 210. The chip also includes analog input connection pad 140A, which is coupled to ADC circuit 132 via switch 210A. Preferably, switches 210 and 210A are each coupled to a different input channel of ADC circuit 132. Preferably, switches 210 and 210A can be activated during the self-test phase. Preferably, the chip also includes an amplifier 230 (AMP) between pads 140 and 140A. In this configuration, as an example, pad 140A is further an analog output connection pad.

[0050] Preferably, the chip also includes a memory location 220, which stores the control logic levels of the switches 150, 210 and 210A during the self-test phase. Preferably, the memory location 220 is located in a rewritable non-volatile memory, which is included in the digital circuit 110 of the chip. Thus, those switches that are turned on during the self-test phase can be selected from the switches 152, 210 and / or 210A. To achieve this, the corresponding logic levels are written to the memory location 220.

[0051] In the self-test phase, when the switch 210 is turned on, Figure 1 The self-test described is performed. When switch 210A is turned on, signal 162 arriving at pad 140 is amplified by amplifier 230. Amplifier 230 provides signal 163. Signal 163 is received by ADC circuit 132, which provides signal 164 to digital circuit 110. Thus, the operation of DAC circuit 130, ADC circuit 132, and amplifier 230 are tested simultaneously. By selecting which of switches 210 and 210A is turned on during the self-test phase, it is selected whether to test amplifier 230 while testing circuits 130 and 132.

[0052] In the case where the chip comprises a plurality of analog signal generators and / or a plurality of analog signal receivers, a plurality of links 150 comprising switches 152 couple the generators to the receivers. In the self-test phase, the switches are controlled according to the content of the memory location 220. This enables, for each generator, one or more receivers to be selected to receive the signal or signals sent by the generator in the self-test phase. This enables, for each receiver, one or more generators to be selected to generate the signal or signals received by the receiver in the self-test phase.

[0053] Preferably, the chip includes a plurality of analog signal receiving and generating circuits, such as amplifier 230. Each of these circuits may have an input and an output that are coupled to an analog signal receiver (such as ADC circuit 132) through switches 210 and 210A. During the self-test phase, the switches are controlled according to the contents of memory location 220. This enables, for each analog signal sent during the self-test phase, a selection to be made as to whether the signal is amplified, and optionally one of the amplifiers to be used for this signal amplification.

[0054] Preferably, protection of writing to the memory location 220 by a password is provided. Preferably, the circuit 240 is configured to write the logic level 242 to the memory location 220 only when the password P has been provided to the circuit 240. Preferably, the circuit 240 is included in the digital circuit 110 of the chip. As an example, the circuit 240 is a microprocessor, which is configured to execute a protection program by a password. Thus, only a user who knows the password can select from the switches those switches that are turned on during the self-test phase.

[0055] Preferably, during the use phase of the chip, switches 210 and 210A are controlled by logic signals having levels stored in memory location 250. Preferably, memory location 250 is non-volatile and rewritable. Thus, those switches that are turned on during the use phase can be selected from switches 210 and / or 210A. To achieve this, corresponding content 252 is written in memory location 250 in advance. In the example shown, when it is desired to convert an analog signal by ADC circuit 132, it can be selected whether to amplify the signal with amplifier 230 before conversion.

[0056] Preferably, the chip includes a plurality of switches that couple the chip's input / output pads to a plurality of analog signal generators and / or receiver circuits. The states of these switches are then controlled by the contents of memory location 250. The analog circuits of the chip can be reconfigured by modifying the contents of memory location 250. The user can select these contents so that the chip performs the desired functions according to the target application. Thus, the same chip can perform various functions for various target applications.

[0057] Due to the fact that the control levels are stored in the respective locations 220 and 250, the control levels applied to the switches in the self-test phase and in the use phase may be different. The tests performed during the self-test phase may be selected independently of the functions performed during the use phase. This enables a more complete self-test to be performed compared to a chip where only the functions performed during the use phase may be self-tested.

[0058] Figure 3 Another embodiment of an electronic chip 300 with analog input / output is schematically shown. The chip 300 comprises Figure 2 The components of the chip 200 that are identical or similar are coupled together. The link 150 here includes two switches 152A and 152B connected in series between the pads 142 and 140. Preferably, the control levels of the switches 152A and 152B are stored in the memory location 220 ( Figure 2 As an example, the chip also includes an additional input connection pad 140B coupled to the amplifier 240.

[0059] In order to design the electronic chip 300, a computer design method is used. Computer design methods for integrated circuit chips usually use a library of design blocks. Each block defines a set of components of the chip circuit and the connections between these components. During design, the connections between blocks are defined. Therefore, the obtained connections and blocks are compatible with common wiring techniques, making it possible to define the layout of the components in the chip and the traces connecting these components.

[0060] Each connection pad 142, 140, 140B, 140A of chip 300 is included in a design block, 310A, 310B, 310C, 310D, respectively. In addition to the connection pads, each design block also includes one or more switches, preferably three switches. These switches are coupled to the connection pads, preferably connected to the connection pads. Preferably, each design block also includes a resistive element 315, which is coupled (e.g., connected) to the connection pads. Preferably, each design block also includes a direct connection 316 to the connection pads.

[0061] Preferably, some of the design blocks are identical. In the illustrated example, four blocks are identical. Switch 152A is one of the switches of block 310A, and switch 152B is one of the switches of block 310B. Thus, each switch 152A, 152B is associated with a corresponding pad 140, 142 in one of the design blocks. As an example, switch 210 is one of the switches of block 310B. Switch 210A is one of the switches of block 310D.

[0062] Preferably, amplifier 240 is defined by design block 320. Preferably, the block includes an operational amplifier 322, a multiplexer 324, a multiplexer 326, and a feedback circuit 328, wherein the output of multiplexer 324 is coupled to the non-inverting input of amplifier 322, the output of multiplexer 326 is coupled to the inverting input of inverting amplifier 322, and feedback circuit 328 couples the inverting input and the output of amplifier 322. Preferably, the connections of resistors 315 of blocks 310B and 310C to the inputs of respective multiplexers 324 and 326 are defined.

[0063] For example, a DAC circuit 130A is provided that couples the digital circuit 110 to the input of the multiplexer 326. Preferably, the DAC circuits 130 and 130A correspond to (eg, the same) design blocks. Preferably, the ADC circuit 132 corresponds to one design block.

[0064] In order to design link 150, it is sufficient to define the connection between switches 152A and 152B. Thus, the design of chip 300 can be performed in a particularly simple manner based on a similar chip which does not include link 150.

[0065] In such a designed chip, preferably a memory location 220 ( Figure 2 ) and the control values ​​of multiplexers 324 and 326 and the configuration parameters of feedback circuit 328. Then, the origin of the signal applied to the input of amplifier 322 in the self-test phase can be selected. The configuration parameters of feedback circuit 328 in the test phase can be further selected.

[0066] Preferably, there is provided a memory location 250 ( Figure 2 ), the control values ​​of multiplexers 324 and 326 and the configuration parameters of feedback circuit 328 are stored. Thus, the origin of the signal applied to the input of amplifier 322 in the use phase and the configuration parameters of the feedback circuit can be selected. Such selection is preferably selected to perform a function corresponding to the application.

[0067] Thus, the selected inputs to multiplexers 324 and 326 and the parameters of feedback circuit 328 may be different during the self-test phase and the use phase. This enables the selection of the test of the amplifier during the self-test phase to be independent of the function the amplifier performs when in use.

[0068] Various embodiments and variations have been described above. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0069] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0070] Such changes, modifications and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the present invention. Therefore, the foregoing description is only exemplary and not intended to be restrictive. The present invention is limited only by the definition of the claims and their equivalents.

Claims

1. A method for performing a self-test of an electronic chip, the electronic chip comprising: A plurality of pins, a first analog input connection pad and a second analog input connection pad; an analog output connection pad; Digital circuits; an analog-to-digital converter coupled between the first analog input connection pad and the second analog input connection pad and the digital circuit; a digital-to-analog converter coupled between the first analog input connection pad and the second analog input connection pad and the digital circuit; a first switch coupled between the first analog input connection pad and the analog output connection pad; an amplifier having an input coupled to the first analog input connection pad and an output coupled to the second analog input connection pad; a second switch coupled between the input of the amplifier and the analog-to-digital converter; and a third switch coupled between the output of the amplifier and the analog-to-digital converter, the method comprising: controlling the first switch, the second switch, and the third switch to selectively test the amplifier using the analog-to-digital converter and the digital-to-analog converter, wherein controlling the first switch, the second switch, and the third switch comprises: closing the first switch; Using the digital-to-analog converter, sending a test signal from the analog output connection pad to the first analog input connection pad through the first switch; and The test signal is tested using the analog-to-digital converter, wherein the analog output connection pad or the first analog input connection pad is not connected to any of the plurality of pins of the chip. 2 . The method according to claim 1 , wherein the chip is configured to operate in a self-test mode and an active mode, the first switch being closed only in the self-test mode.

3. The method according to claim 1, further comprising: converting a digital test signal into an analog test signal using the digital-to-analog converter, wherein the test signal is the analog test signal; After transmitting the test signal, converting the analog test signal into a converted digital test signal using the analog-to-digital converter; and The digital test signal and the converted digital test signal are compared.

4. The method according to claim 3, further comprising: The analog test signal is amplified using the amplifier before converting the analog test signal into the converted digital test signal.

5. A system on chip, comprising: a first analog input and a second analog input; Analog output; Digital circuits; an analog-to-digital converter coupled between the first analog input and the second analog input and the digital circuit; a digital-to-analog converter coupled between the digital circuit and the analog output; as well as a first switch coupled between the first analog input and the analog output; an amplifier having an input coupled to the first analog input and an output coupled to the second analog input; a second switch coupled between the input of the amplifier and the analog-to-digital converter; as well as A third switch is coupled between the output of the amplifier and the analog-to-digital converter, wherein the system on chip is configured to control the first switch, the second switch, and the third switch to selectively test the amplifier with the analog-to-digital converter and the digital-to-analog converter. 6 . The system on chip of claim 5 , wherein the system on chip comprises a plurality of switches connected in series between the first analog input and the analog output.

7. The system on chip of claim 6, further comprising a first memory location storing control logic levels of the plurality of switches.

8. The system on chip of claim 7, wherein the system on chip is configured such that writing to the first memory location is protected by a password.

9. The system on chip according to claim 5, further comprising: A second memory location stores a control logic level for the second switch.

10. The system on chip of claim 7, wherein the first memory location is configured to further store an additional control logic level of the second switch.

11. A method of operating a system on chip according to claim 5, the method comprising operating the system on chip in a self-test mode, the method comprising: sending a digital signal from the digital circuit to the digital-to-analog converter; Converting the digital signal into an analog signal; applying the analog signal to the analog-to-digital converter via the first switch; converting the analog signal into a converted digital signal; as well as The converted digital signal is output to the digital circuit. 12 . The method of claim 11 , further comprising comparing, at the digital circuit, the digital signal and the converted digital signal.

13. The method of claim 11, further comprising amplifying the analog signal using the amplifier before converting the analog signal into the converted digital signal.

14. The method of claim 11, further comprising operating the system on chip in a normal operating mode, wherein the first switch is open throughout the normal operating mode.

15. A method for designing a chip, the chip comprising: a plurality of analog input connection pads, a plurality of analog output connection pads, a plurality of switches coupled between the plurality of analog input connection pads and the plurality of analog output connection pads, and; a digital circuit, an analog-to-digital converter, a digital-to-analog converter, and an amplifier, wherein the plurality of analog input connection pads include a first analog input connection pad and a second analog input connection pad, wherein the analog-to-digital converter is coupled between the first analog input connection pad and the second analog input connection pad and the digital circuit, wherein the digital-to-analog converter is coupled between the digital circuit and a first analog output connection pad of the plurality of analog output connection pads, wherein the plurality of switches include a first switch, a second switch, and a third switch coupled between the first analog input connection pad and the first analog output connection pad; the second switch is coupled between an input of the amplifier and the analog-to-digital converter, and the third switch is coupled between an output of the amplifier and the analog-to-digital converter; wherein the input of the amplifier is coupled to the first analog input connection pad, and the output of the amplifier is coupled to the second analog input connection pad, and wherein the first switch, the second switch, and the third switch are controlled to selectively test the amplifier with the analog-to-digital converter and the digital-to-analog converter, the method comprising: associating each of the plurality of analog input connection pads with an associated analog output connection pad of the plurality of analog output connection pads such that there are a plurality of associated pairs of input and output connection pads; and Each pair is associated with one of the plurality of switches in a design block in a computer design library, the design block being identical for the analog input connection pad and the analog output connection pad, wherein each design block includes a resistor connected to an associated pad.

16. The method of claim 15, wherein each design block comprises a plurality of further switches, each further switch of the plurality of further switches being directly connected to the associated pad.

17. A method for self-testing an electronic chip, the electronic chip comprising: A first analog signal input and a second analog signal input, and an analog signal output; Digital circuits; an analog signal receiver coupled between the first analog signal input and the second analog signal input and the digital circuit; an analog signal generator coupled between the digital circuit and the analog signal output; a first switch coupled between the first analog signal input and the analog signal output; and an amplifier having an input coupled to the first analog signal input and an output coupled to the second analog signal input; a second switch coupled between the input of the amplifier and the analog signal receiver; and a third switch coupled between the output of the amplifier and the analog signal receiver; the method comprising: controlling the first switch, the second switch, and the third switch to selectively test the amplifier using the signal receiver and the analog signal generator, wherein controlling the first switch, the second switch, and the third switch comprises: closing the first switch to couple the analog signal output to the first analog signal input; performing a self-test operation, the self-test operation including testing the analog signal generator and the analog signal receiver simultaneously, and testing the amplifier using the analog signal generator and the analog signal receiver; and The first switch is opened to isolate the analog signal output from the first analog signal input so that the chip can operate in a normal operation mode.

18. The method of claim 17, wherein performing the self-test operation comprises: generating a test signal by the analog signal generator and applying the test signal to the analog signal output; as well as The test signal is received by the analog signal receiver at the first analog signal input, the test signal being sent from the signal output to the first analog signal input via the first switch.

19. The method of claim 18, wherein the analog signal generator comprises a digital-to-analog converter and the analog signal receiver comprises an analog-to-digital converter.

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