Display panel and display device including the same

Abstract

The present invention discloses a display panel and a display device including the display panel. The display panel includes: a glass substrate having an opening area and a display area at least partially surrounding the opening area; a thin film transistor located in the display area and including a semiconductor layer and a gate electrode; a display element electrically connected to the thin film transistor; a multilayer including an insulating layer and a lower insulating layer, wherein the insulating layer is located between the glass substrate and the display element, and the lower insulating layer is located between the glass substrate and the insulating layer; and a thin film encapsulation layer covering the display element and including an inorganic encapsulation layer and an organic encapsulation layer. The multilayer includes a first groove located between the opening area and the display area. A first width of a portion of the first groove in the lower insulating layer is greater than a second width of a portion of the first groove in the insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0109179 filed on September 12, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display panel and a display device including the same. Background Art

[0004] Related art display devices have a variety of uses. In addition, due to their relatively small thickness and light weight, their application range has also increased.

[0005] As the display area of ​​a display device has increased, various functions connected or linked to the display device have been added to the display device. As a method of adding various functions while increasing the display area, a display device forming an area connected or linked to a function in the display area has been developed. Summary of the Invention

[0006] In a display device including an opening, a layer including an organic material and exposed through a side surface of the opening provides a moisture permeation path, and thus a display element at least partially surrounding the opening may be damaged.

[0007] One or more embodiments include a display panel capable of preventing moisture from penetrating through an opening of the display panel and a display device including the display panel. However, the one or more embodiments are merely examples, and the scope of the present invention is not limited thereto.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be taught by practice of the presented embodiments.

[0009] According to one or more embodiments, a display panel includes: a glass substrate including an opening area and a display area at least partially surrounding the opening area; a thin film transistor located in the display area and including a semiconductor layer and a gate electrode; a display element electrically connected to the thin film transistor; a multilayer including a lower insulating layer and at least one insulating layer, wherein the at least one insulating layer is between the glass substrate and the display element, and the lower insulating layer is between the glass substrate and the at least one insulating layer; and a thin film encapsulation layer covering the display element and including at least one inorganic encapsulation layer and at least one organic encapsulation layer, wherein the multilayer includes a first groove located between the opening area and the display area, and a first width of a portion of the first groove in the lower insulating layer is greater than a second width of a portion of the first groove in the at least one insulating layer.

[0010] A bottom surface of the first groove may be located on a virtual surface between an upper surface of the lower insulating layer and an upper surface of the glass substrate, or on the same virtual surface as the upper surface of the glass substrate.

[0011] At least one of the insulating layers may include a first hole corresponding to the first groove, and the lower insulating layer may include a second hole or recess corresponding to the first groove.

[0012] A side surface of the at least one insulating layer facing the center of the first groove may be closer to the center of the first groove than a side surface of the lower insulating layer facing the center of the first groove.The lower insulating layer may be in direct contact with the upper surface of the glass substrate.

[0013] At least one inorganic encapsulation layer may cover an inner surface of the first groove.

[0014] A portion of the at least one inorganic encapsulating layer may be in direct contact with a portion of the glass substrate within the first groove.

[0015] The glass substrate may include a first opening corresponding to the opening region.

[0016] An end portion of the glass substrate defining the first opening may be closer to a center of the opening region than an end portion of the lower insulating layer facing the opening region.

[0017] The multilayer may further include a second groove between the first groove and the open region.

[0018] An end portion of the at least one organic encapsulating layer may be between the first groove and the second groove.

[0019] The display panel may further include a partition wall on the plurality of layers and between the first groove and the second groove.

[0020] The lower insulating layer may include an organic insulating layer, and at least one insulating layer may include an inorganic insulating layer.

[0021] The lower insulating layer may include at least one of silicon nitride and silicon oxycarbide, and the at least one insulating layer may include an inorganic insulating layer including a material different from that of the lower insulating layer.

[0022] According to one or more embodiments, a display device includes: a substrate including an opening; a thin film transistor located in a display area of ​​the substrate and including a semiconductor layer and a gate electrode, the display area at least partially surrounding the opening; a display element electrically connected to the thin film transistor; a multilayer including a lower insulating layer and at least one insulating layer, wherein the lower insulating layer is located on the substrate, and the at least one insulating layer is located on the lower insulating layer and includes a material different from the lower insulating layer; and an encapsulation layer configured to cover the display element, wherein the multilayer includes a first groove recessed in a depth direction of the multilayer, and a width of a portion of the first groove in the lower insulating layer is greater than a width of a portion of the first groove in the at least one insulating layer.

[0023] The substrate may include a glass material, a polymer material, or a metal material.

[0024] A bottom surface of the first groove may be located on a virtual surface between an upper surface of the lower insulating layer and an upper surface of the substrate, or on the same virtual surface as the upper surface of the substrate.

[0025] At least one of the insulating layers may include a first hole corresponding to the first groove, and the lower insulating layer may include a second hole or recess corresponding to the first groove.

[0026] The at least one insulating layer may include an inorganic insulating layer.

[0027] The lower insulating layer may include an organic insulating layer, or may include an inorganic insulating layer different from the at least one insulating layer.

[0028] A side surface of the at least one insulating layer directed toward the center of the first groove may protrude more than a side surface of the lower insulating layer directed toward the center of the first groove.

[0029] An end portion of the substrate directed toward the opening may protrude further toward the opening than an end portion of the lower insulating layer directed toward the opening.

[0030] The multilayer may further include a second groove between the first groove and the opening.

[0031] The encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, and the at least one inorganic encapsulation layer may cover an inner surface of each of the first groove and the second groove.

[0032] A portion of the at least one organic encapsulating layer may at least partially fill the first groove.

[0033] The display device may further include a partition wall on the multiple layers and between the first groove and the second groove.

[0034] The at least one inorganic encapsulating layer may be in direct contact with the upper surface of the substrate within the first groove or the second groove.

[0035] The at least one insulating layer may include a first insulating layer and a second insulating layer on the first insulating layer, the first insulating layer and the second insulating layer including different materials. The first insulating layer and the second insulating layer may each include a hole corresponding to the first groove, and the width of the hole in the second insulating layer may be smaller than the width of the hole in the first insulating layer.

[0036] The display element may include an organic light emitting diode.

[0037] At least one of the organic layer and the counter electrode included in the organic light emitting diode may be disconnected by the first groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] These and / or other aspects will become more apparent and easier to understand from the following description of the embodiments with reference to the accompanying drawings, in which:

[0039] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0040] Figures 2A to 2D is a schematic cross-sectional view of a display device according to an embodiment;

[0041] Figure 3 is a schematic plan view of a display panel according to an embodiment;

[0042] Figure 4 is a circuit diagram of one of a plurality of pixels of a display panel;

[0043] Figure 5 is a plan view of a portion of a display panel according to an embodiment, showing a signal line located in a first non-display area;

[0044] Figure 6 is a plan view of a portion of a display panel according to an embodiment, showing a groove located in a first non-display area;

[0045] Figure 7 yes Figure 6 a cross-sectional view of a display panel;

[0046] Figure 8 is an enlarged cross-sectional view of an organic light emitting diode according to an embodiment;

[0047] Figure 9A is a cross-sectional view of a first groove according to an embodiment, and Figure 9B It shows Figure 9A A cross-sectional view of the stacked structure on the first groove;

[0048] Figure 10A is a cross-sectional view of a first groove according to another embodiment, and Figure 10B It shows Figure 10AA cross-sectional view of the stacked structure on the first groove;

[0049] Figure 11 is a cross-sectional view of a display panel according to another embodiment;

[0050] Figure 12A is a cross-sectional view of a first groove according to another embodiment, and Figure 12B It shows Figure 12A A cross-sectional view of the stacked structure on the first groove;

[0051] Figure 13 is a cross-sectional view of a display panel according to another embodiment;

[0052] Figure 14 is a cross-sectional view of a display panel according to another embodiment;

[0053] Figure 15A is a cross-sectional view of a first groove according to another embodiment, and Figure 15B It shows Figure 15A A cross-sectional view of the stacked structure on the first groove;

[0054] Figure 16 is a cross-sectional view of a display panel according to another embodiment;

[0055] Figure 17 is a cross-sectional view of a display panel according to another embodiment;

[0056] Figure 18 is a plan view of a display panel according to another embodiment;

[0057] Figure 19 is a plan view of the periphery of an opening area according to another embodiment;

[0058] Figure 20 yes Figure 19 a cross-sectional view of a display panel;

[0059] Figure 21 is a plan view of a display panel according to another embodiment;

[0060] Figure 22 is a plan view of the periphery of an opening area according to another embodiment; and

[0061] Figure 23 yes Figure 22 A cross-sectional view of a display panel. DETAILED DESCRIPTION

[0062] Since the present disclosure allows for various changes and multiple embodiments, specific embodiments are shown in the drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and the methods for achieving these effects and features will be more fully described with reference to the drawings in which embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0063] One or more embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The same or corresponding components are given the same reference numerals regardless of the figure number, and redundant explanations are omitted.

[0064] It should be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0065] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0066] It will also be understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0067] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present.

[0068] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0069] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order to the described order.

[0070] It should also be understood that when a layer, region, or component is referred to as being “connected” or “coupled” to another layer, region, or component, it may be directly connected or coupled to the other layer, region, or component, or intervening layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it may be directly electrically connected or coupled to the other layer, region, or component, or intervening layers, regions, or components may be present.

[0071] Figure 1is a schematic perspective view of a display device 1 according to an embodiment of the present disclosure.

[0072] See also Figure 1 The display device 1 includes a display area DA that emits light and a non-display area NDA that does not emit light. The display device 1 can provide an image by using light emitted from a plurality of pixels arranged in the display area DA.

[0073] The display apparatus 1 includes an opening area OA at least partially surrounded by the display area DA. Figure 1 The opening area OA is shown to be completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 surrounding the opening area OA and a second non-display area NDA2 surrounding the display area DA. The first non-display area NDA1 may completely surround the opening area OA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0074] Although an organic light emitting display device is now shown and described as the display device 1, the display device 1 is not limited thereto. According to another embodiment, various types of display devices such as an inorganic light emitting display and a quantum dot light emitting display may be used.

[0075] Figures 2A to 2D is a schematic cross-sectional view of a display device 1 according to an embodiment, and may correspond to a cross-sectional view along Figure 1 The opening area OA is located between two pixels. For example, the opening area OA is located between two OLEDs.

[0076] See also Figure 2A The display device 1 may include a display panel 10 and a component 20 corresponding to the opening area OA of the display panel 10. Although not shown, elements such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may be arranged on the display panel 10.

[0077] The display panel 10 may include a substrate 100 , a display element layer 200 disposed on the substrate 100 , and a thin film encapsulation layer 300 as an encapsulation member covering the display element layer 200 .

[0078] The substrate 100 may include a glass material, a polymer material, or a metal material. The substrate 100 may be rigid or flexible. For example, the substrate 100 may be a transparent glass substrate containing SiO2 as a main component, or a substrate including a polymer resin such as reinforced plastic. The display element layer 200 includes: a pixel circuit including a thin film transistor (TFT) arranged in the display area DA and a display element such as an organic light emitting diode (OLED) electrically connected to the pixel circuit. The thin film encapsulation layer 300 can prevent external moisture or pollutants from penetrating into the display element layer 200 by covering the display element layer 200. The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0079] like Figure 2A As shown, the display panel 10 may include an opening 10H, which corresponds to the opening area OA and penetrates (e.g., completely penetrates) the display panel 10. The substrate 100, the display element layer 200, and the thin film encapsulation layer 300 may respectively include a first opening 100H, a second opening 200H, and a third opening 300H corresponding to the opening area OA, and the first opening 100H, the second opening 200H, and the third opening 300H may together form the opening 10H of the display panel 10. The first opening 100H may penetrate from the top surface to the bottom surface of the substrate 100, the second opening 200H may penetrate from the lowermost layer to the uppermost layer of the display element layer 200, and the third opening 300H may penetrate the thin film encapsulation layer 300.

[0080] The opening area OA is the area where the component 20 is located (eg, at least a portion of the component 20 is laterally aligned with the opening 10H in the display panel 10). Figure 2A In the embodiment, the component 20 is arranged below the substrate 100, but the embodiment is not limited thereto. According to another embodiment, as Figure 2B As shown, the component 20 can be arranged in the opening 10H so that at least a portion of the component 20 overlaps with the side surface of the display panel 10 facing the opening 10H in the thickness direction of the display panel 10 (for example, in one or more embodiments, at least a portion of the component 20 can extend into the opening 10H in the display panel 10).

[0081] Component 20 may include electronic components. For example, component 20 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor that emits and / or receives and uses light, such as an infrared sensor, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. Electronic components that use light can use light of various wavelengths, such as visible light, infrared light, and ultraviolet light. According to some embodiments, the opening area OA may be understood as a transmission area that is capable of transmitting light or / and sound output from component 20 to the outside or traveling from the outside toward component 20.

[0082] According to an embodiment, when the display panel 10 is used as a smart watch or an instrument panel of a car, the component 20 may be a member including a clock hand or a hand indicating predetermined information (eg, the speed of the vehicle, etc.). Figure 2A or Figure 2B As shown, the component 20 is a component that can be arranged at a position corresponding to the opening 10H of the display panel 10. As described above, the component 20 may include elements related to the function of the display panel 10 or elements such as accessories that increase the beauty of the display panel 10.

[0083] exist Figure 2A and Figure 2B In the embodiment, the substrate 100, the display element layer 200 and the thin film encapsulation layer 300 respectively include a first opening 100H, a second opening 200H and a third opening 300H corresponding to the opening area OA. Figure 2C As shown, the substrate 100 may not include the first opening 100H.

[0084] See also Figure 2C , although the substrate 100 does not include the first opening 100H, the display element layer 200 and the thin film encapsulation layer 300 may include the second opening 200H and the third opening 300H, respectively. Figure 2C The light transmittance in the opening area OA of the display panel 10 shown in may be about 50% or more, 70% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0085] The component 20 is arranged in the opening area OA. Figure 2C As shown by the solid line in FIG, the component 20 may be arranged below the display panel 10 so that the component 20 does not overlap with the side surface of the display panel 10 facing the opening 10H, or as shown in FIG. Figure 2C As shown by the dotted lines, at least a portion of the component 20 may be arranged within the second opening 200H and the third opening 300H such that the component 20 overlaps with the side surface of the display panel 10 facing the opening 10H in the thickness direction of the display element layer 200 and the thin film encapsulation layer 300 .

[0086] See also Figure 2D , the substrate 100 and the thin film encapsulation layer 300 may not include the first opening 100H and the third opening 300H, respectively, but the display element layer 200 may include the second opening 200H. Figure 2D In an embodiment, the thin film encapsulation layer 300 may include a recessed portion extending along a side surface of the display element layer 200 facing the opening 10H and an upper surface of the substrate 100 facing the opening 10H. Figure 2D , the component 20 is arranged in the opening area OA so that the component 20 does not overlap with the side surface of the display panel 10 facing the opening 10H. However, the component 20 may be arranged in Figure 2C At the position indicated by the dotted line.

[0087] Figure 3 is a schematic plan view of a display panel 10 according to an embodiment, and Figure 4 1 is a circuit diagram of one of the plurality of pixels P of the display panel 10 .

[0088] See also Figure 3 The display panel 10 includes a plurality of pixels P arranged in a display area DA. Each of the pixels P may include an OLED. Each of the pixels P may emit, for example, red light, green light, blue light, or white light via the OLED.

[0089] See also Figure 4 , the pixel P includes a pixel circuit PC and an OLED connected to the pixel circuit PC. The pixel circuit PC may include a first TFT T1, a second TFT T2, and a storage capacitor Cst.

[0090] The second TFT T2, which serves as a switching TFT, is connected to the scan line SL and the data line DL and transmits a data voltage received via the data line DL to the first TFT T1 according to a switching voltage received via the scan line SL. The storage capacitor Cst is connected to the second TFT T2 and the driving voltage line PL and stores a voltage corresponding to a difference between a voltage received from the second TFT T2 and the first power supply voltage ELVDD supplied to the driving voltage line PL.

[0091] The first TFT T1, which serves as a driving TFT, is connected to the driving voltage line PL and the storage capacitor Cst and can control the driving current flowing from the driving voltage line PL to the OLED according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a certain brightness due to the driving current. The counter electrode (e.g., cathode) of the OLED can receive the second power supply voltage ELVSS.

[0092] Despite Figure 4, the pixel circuit PC includes two TFTs and one storage capacitor, but the embodiment is not limited thereto. The number of TFTs and the number of storage capacitors may vary according to the design of the pixel circuit PC.

[0093] Return to see Figure 3 , the first non-display area NDA1 may surround the opening area OA. The first non-display area NDA1 is an area in which no light-emitting display elements are arranged. Conductive lines (e.g., signal lines) connected to the pixels P arranged around the opening area OA may extend across the first non-display area NDA1, or a groove described below may be arranged in the first non-display area NDA1. In the second non-display area NDA2, a scan driver 1100 that provides a scan signal to each of the pixels P, a data driver 1200 that provides a data signal to each of the pixels P, and a main power line (not shown) for providing a first power supply voltage ELVDD and a second power supply voltage ELVSS may be arranged.

[0094] Figure 3 It can be understood as a diagram of the substrate 100 of the display panel 10. For example, the substrate 100 can be understood as including an opening area OA, a display area DA, and first and second non-display areas NDA1 and NDA2.

[0095] Figure 5 is a plan view of a portion of a display panel according to an embodiment, and illustrates lines located in the first non-display area NDA1.

[0096] See also Figure 5 , the pixels P may be arranged in the display area DA around the opening area OA, and the first non-display area NDA1 may be located between the opening area OA and the display area DA.

[0097] The pixels P may be spaced apart from each other around the opening area OA. The pixels P may be spaced apart from each other vertically around the opening area OA, or spaced apart from each other horizontally around the opening area OA.

[0098] Among the signal lines supplying signals to the pixels P, signal lines adjacent to the opening area OA may be routed around the opening area OA. Some of the data lines DL passing through the display area DA may extend in the y-direction to supply data signals to the pixels P vertically arranged around the opening area OA and may route along the edge of the opening area OA (e.g., in an arc) in the first non-display area NDA1. Some of the scan lines SL passing through the display area DA may extend in the x-direction to supply scan signals to the pixels P horizontally arranged around the opening area OA and may route along the edge of the opening area OA (e.g., in an arc) in the first non-display area NDA1.

[0099] Figure 6is a plan view of a portion of a display panel according to an embodiment, and illustrates a groove located in the first non-display area NDA1.

[0100] The groove is located between the opening area OA and the display area DA. Figure 6 The embodiment shows the first groove G1 and the second groove G2 located between the opening area OA and the display area DA. However, according to another embodiment, only one groove or three or more grooves may be disposed between the opening area OA and the display area DA.

[0101] Each of the first groove G1 and the second groove G2 may have a ring shape completely surrounding the opening area OA in the first non-display area NDA1. Figure 6 In the embodiment, since the opening area OA has a circular shape, the first groove G1 and the second groove G2 are circular rings (for example, in one or more embodiments, the shapes of the grooves G1 and G2 correspond to the shape of the opening area OA). However, the opening area OA may be an elliptical or polygonal shape, and therefore, each of the first groove G1 and the second groove G2 may also have any of various types of annular shapes. The diameter of each of the first groove G1 and the second groove G2 relative to the center point of the opening area OA may be larger than the diameter of the opening area OA, and the first groove G1 and the second groove G2 may be spaced apart from each other by a distance (for example, a gap) in the first non-display area NDA1.

[0102] Figure 7 is a cross-sectional view of a display panel according to an embodiment, and corresponds to a cross-sectional view of a display panel along Figure 6 A cross section taken along line VII-VII'. Figure 8 yes Figure 7 Magnified cross-sectional view of an OLED. Figure 9A is a cross-sectional view of the first groove G1, and Figure 9B It shows Figure 9A FIG. 5 is a cross-sectional view of the stacked structure on the first groove G1. FIG.

[0103] See also Figure 7 In the display area DA, the substrate 100 may be a substrate including the glass material, polymer material or / and metal material as described above.

[0104] A buffer layer 201 for preventing impurities from penetrating into a semiconductor layer of a TFT may be disposed on the substrate 100. The buffer layer 201 may include an inorganic insulating material such as silicon nitride or silicon oxide, and may be a single layer or multiple layers including the inorganic insulating material.

[0105] A pixel circuit PC including a TFT and a storage capacitor Cst may be disposed on the buffer layer 201. The TFT may include a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 7 The TFT can correspond to Figure 4 According to the present embodiment, the TFT is a top-gate type in which the gate electrode GE is arranged on the semiconductor layer ACT with the gate insulating layer 203 therebetween. However, according to another embodiment, the TFT may be a bottom-gate type in which the gate electrode is arranged below the gate insulating layer and the semiconductor layer is arranged above the gate insulating layer.

[0106] The semiconductor layer ACT may include polycrystalline silicon. Alternatively, the semiconductor layer ACT may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or single layer including the above materials.

[0107] The gate insulating layer 203 may be interposed between the semiconductor layer ACT and the gate electrode GE, and may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide.

[0108] The source electrode SE and the drain electrode DE may include a highly conductive material. Each of the source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, and Ti, and may be a multilayer or single layer including the above materials. According to an embodiment, each of the source electrode SE and the drain electrode DE may be formed as a multilayer (trilayer) of Ti / Al / Ti.

[0109] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 with a first interlayer insulating layer 205 therebetween. The lower electrode CE1 and the upper electrode CE2 overlap each other. The storage capacitor Cst may be covered with a second interlayer insulating layer 207.

[0110] The storage capacitor Cst may overlap with the TFT. Figure 7 A case where the gate electrode GE of the TFT is the lower electrode CE1 of the storage capacitor Cst is shown, but the present disclosure is not limited thereto. According to another embodiment, the storage capacitor Cst may not overlap with the TFT.

[0111] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide, and may each be a multilayer or single layer.

[0112] The pixel circuit PC including the TFT and the storage capacitor Cst may be covered with a planarization insulating layer 209. The planarization insulating layer 209 may be an organic insulating layer including a commercial polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an acrylate polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof. According to an embodiment, the planarization insulating layer 209 may include polyimide.

[0113] The OLED may be disposed on the planarization insulating layer 209 . The pixel electrode 221 of the OLED may be disposed on the planarization insulating layer 209 and may be connected to the pixel circuit PC via a contact hole of the planarization insulating layer 209 .

[0114] The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). According to another embodiment, the pixel electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound of these materials. According to another embodiment, the pixel electrode 221 may further include a film formed of ITO, IZO, ZnO or In2O3 above / below the reflective layer.

[0115] The pixel defining layer 211 includes an opening and covers the edge of the pixel electrode 221, and the upper surface of the pixel electrode 221 is exposed through the opening. The pixel defining layer 211 may include an organic insulating material. The pixel defining layer 211 may include the organic insulating material described above in the above description of the planarization insulating layer 209. The pixel defining layer 211 may include an organic insulating material and / or an inorganic insulating material. According to an embodiment, the pixel defining layer 211 may include polyimide.

[0116] The intermediate layer 222 of the OLED includes an emission layer 222b. The emission layer 222b may include a low molecular weight or high molecular weight organic material that emits light of a specific color. Figure 8 As shown, the intermediate layer 222 may further include a first functional layer 222a disposed below the emission layer 222b, and / or a second functional layer 222c disposed above the emission layer 222b.

[0117] The first functional layer 222a may be a single layer or a multilayer. For example, when the first functional layer 222a is formed of a high molecular weight material, the first functional layer 222a is a hole transport layer (HTL) having a single layer structure and may be formed of poly (3,4) -ethylenedioxythiophene (PEDOT) or polyaniline (PANI). On the other hand, when the first functional layer 222a is formed of a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0118] The second functional layer 222c is optional. For example, when the first functional layer 222a and the emission layer 222b are formed of a high molecular weight material, the second functional layer 222c may be formed to improve the characteristics of the OLED. The second functional layer 222c may be a single layer or a multilayer. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0119] Some of the multiple layers constituting the intermediate layer 222, for example, the first functional layer 222a and the second functional layer 222c, may be arranged not only in the display area DA but also in the first non-display area NDA1, and may be disconnected in the first non-display area NDA1 by the first groove G1 and the second groove G2 described below.

[0120] The counter electrode 223 of the OLED can be arranged to face the pixel electrode 221 with an intermediate layer 222 therebetween. The counter electrode 223 can be formed of a conductive material having a low work function. For example, the counter electrode 223 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy of these materials. Alternatively, the counter electrode 223 may further include a layer such as ITO, IZO, ZnO or In2O3 located on the (semi) transparent layer including any of the above materials.

[0121] The OLED is covered with a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 7 The thin film encapsulation layer 300 includes first and second inorganic encapsulation layers 310 and 330 and an organic encapsulation layer 320 therebetween, but the stacking order of the first and second inorganic encapsulation layers 310 and 330 and the organic encapsulation layer 320 and the number of inorganic and organic encapsulation layers may be changed.

[0122] The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may include an inorganic insulating material of at least one of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed via chemical vapor deposition (CVD) or the like. The organic encapsulating layer 320 may include a polymer material. Examples of polymer materials may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0123] See also Figure 7 The first non-display area NDA1 may include a first sub-non-display area SNDA1 located at a far side of the opening area OA and a second sub-non-display area SNDA2 close to the opening area OA (for example, the second sub-non-display area SNDA2 is closer to the opening area OA than the first sub-non-display area SNDA1).

[0124] The first sub non-display area SNDA1 is a conductive line (for example, see above Figure 5 The area through which the signal line described by Figure 7 The data line DL located in the first sub non-display area SNDA1 is shown. Figure 7 The data line DL and see Figure 5 The data lines DL described above may correspond to the data lines DL arranged around the opening area OA. The data lines DL may be arranged alternately with an insulating layer (e.g., the second interlayer insulating layer 207) located therebetween. In this case, the gap (spacing) between adjacent data lines DL may be reduced, and the width of the first non-display area NDA1 may be reduced. According to another embodiment, the data lines DL may all be arranged on the same layer, for example, on the second interlayer insulating layer 207.

[0125] although Figure 7 The data line DL in the first sub non-display area SNDA1 is shown, but see Figure 5 The scan line SL described as bypassing the opening area OA may also be located in the first sub non-display area SNDA1 .

[0126] The second sub non-display area SNDA2 may be a region where a first groove G1 and a second groove G2 are arranged. The first groove G1 and the second groove G2 are formed in a multilayer ML arranged on the substrate 100. The multilayer ML includes a lower insulating layer 250 and at least one insulating layer AIL arranged on the lower insulating layer 250. The lower insulating layer 250 may be interposed between the substrate 100 and the pixel circuit PC, for example, between the substrate 100 and the TFT. Figure 7 The embodiment shows the lower insulating layer 250 disposed directly on the substrate 100. The at least one insulating layer AIL may include an inorganic insulating layer. Figure 7In the illustrated embodiment, the at least one insulating layer AIL includes a buffer layer 201, a gate insulating layer 203, a first interlayer insulating layer 205, and a second interlayer insulating layer 207. The at least one insulating layer AIL may refer to one or more insulating layers selected from the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207.

[0127] The first and second grooves G1 and G2 may have a certain depth in the thickness direction of the multilayer ML, and each of the first and second grooves G1 and G2 may have an undercut structure, wherein the width of the portion of each of the first and second grooves G1 and G2 that passes through the lower insulating layer 250 is greater than the width of the portion of each of the first and second grooves G1 and G2 that passes through the at least one insulating layer AIL. Just as the at least one insulating layer AIL is an inorganic insulating layer and the lower insulating layer 250 is an organic insulating layer, the at least one insulating layer AIL and the lower insulating layer 250 may include different materials from each other. The lower insulating layer 250 may include, for example, polyimide.

[0128] See also Figure 9A , a first width W1 of a portion of the first groove G1 that penetrates the lower insulating layer 250 in the depth direction is greater than a second width W2 of a portion of the first groove G1 that penetrates the at least one insulating layer AIL. A side surface of the at least one insulating layer AIL may protrude further toward the center of the first groove G1 than a side surface 250IE of the lower insulating layer 250, and the protruding portion of the at least one insulating layer AIL may form a tip (or eaves) (for example, the lower surface of the at least one insulating layer AIL may overhang the portion of the first groove G1 in the lower insulating layer 250). Figure 9A A pair of ends (or eaves) are shown. The ends may protrude further than the side surface 250IE of the lower insulating layer 250 in the x-direction by about 0.9 μm to about 1.2 μm.

[0129] The first groove G1 may be formed by etching the at least one insulating layer AIL and the lower insulating layer 250. The etchant or etching gas used during the etching process for removing a portion of the at least one insulating layer AIL may include a material different from the etchant or etching gas used during the etching process for removing a portion of the lower insulating layer 250.

[0130] Through etching, a first hole 250h may be formed in the lower insulating layer 250, and a second hole AIL-h may be formed in at least one insulating layer AIL. The first hole 250h and the second hole AIL-h may be connected to each other (e.g., communicate with each other) to form a first groove G1. The first width W1 of the first hole 250h is greater than the second width W2 of the second hole AIL-h, and the first groove G1 may have an undercut structure in which the lower width is greater than the upper width. Figure 9AThe side surface AIL-IE of the at least one insulating layer AIL defining the second hole AIL-h is shown to protrude a first distance d1 toward the center of the first groove G1 in the lateral direction (x direction), protruding further than the side surface 250IE of the lower insulating layer 250 defining the first hole 250h. In the illustrated embodiment, the first hole 250h of the first groove G1 that penetrates the lower insulating layer 250 can gradually narrow from a relatively wide end at the upper surface of the lower insulating layer 250 facing the at least one insulating layer AIL to a relatively narrow end at the lower surface of the lower insulating layer 250 facing the substrate 100 (for example, the side surface 250IE can gradually narrow from a relatively wide upper end to a relatively narrow lower end). In addition, the first width W1 can refer to the width of the relatively wide upper end of the first hole 250h at the upper surface of the lower insulating layer 250.

[0131] The first distance d1 may be less than the thickness t of the lower insulating layer 250, may be equal to the thickness t of the lower insulating layer 250, or may be greater than the thickness t of the lower insulating layer 250. The first distance d1 may be greater than the thickness of the first inorganic encapsulation layer 310, or may be greater than the sum of the respective thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. According to an embodiment, the first distance d1 may be equal to or greater than approximately 1 μm. In other words, the end may protrude further than the side surface 250IE of the lower insulating layer 250 toward the center of the first groove G1 by the first distance d1.

[0132] In such Figure 9A After the first groove G1 is formed in the multilayer ML, the intermediate layer 222 and the counter electrode 223 may be formed by thermal deposition or the like. Some of the multiple layers constituting the intermediate layer 222 (e.g., the first functional layer 222a and / or the second functional layer 222c) and the counter electrode 223 may be formed on the substrate 100 by deposition. At this time, the first functional layer 222a and / or the second functional layer 222c and the counter electrode 223 may be separated by the first groove G1 and the second groove G2 located in the first non-display area NDA1, respectively. Figure 9B It is shown that the first functional layer 222 a and / or the second functional layer 222 c of the intermediate layer 222 and the counter electrode 223 are all disconnected by the first groove G1 .

[0133] Although the above description is made by focusing on the first groove G1 Figure 9A and Figure 9B However, the second groove G2 has the same structure as the first groove G1, and as described above, the first functional layer 222a and / or the second functional layer 222c and the counter electrode 223 are disconnected by the second groove G2.

[0134] Return to see Figure 7, the thin film encapsulation layer 300 also covers the first non-display area NDA1. Because the first inorganic encapsulation layer 310 formed by CVD or the like has a relatively high step coverage compared to the intermediate layer 222 and the counter electrode 223, the first inorganic encapsulation layer 310 can cover the entire inner surface of each of the first groove G1 and the second groove G2. Figure 9B As shown, the first inorganic encapsulating layer 310 may cover the side surface 250IE and the bottom surface of the lower insulating layer 250 and the side surface AIL-IE and the bottom surface of the at least one insulating layer AIL. These surfaces define a first groove G1. The bottom surface of the lower insulating layer 250 may correspond to the upper surface of the substrate 100, and the bottom surface of the at least one insulating layer AIL may correspond to the lower surface of the buffer layer 201.

[0135] The first inorganic encapsulating layer 310 may cover the disconnected first and second functional layers 222a and 222c and the disconnected counter electrode 223 located within the first and second grooves G1 and G2, and may directly contact a portion of the upper surface of the substrate 100 exposed through the first groove G1. The thickness of the first inorganic encapsulating layer 310, for example, its thickness in a direction perpendicular to the substrate 100 (z direction), may be less than the thickness t of the lower insulating layer 250. A portion of the first groove G1 may be at least partially filled with the organic encapsulating layer 320 on the first inorganic encapsulating layer 310.

[0136] like Figure 7 As shown, the organic encapsulation layer 320 may not only cover the display area DA but also a portion of the first non-display area NDA1. For example, an end portion 320E of the organic encapsulation layer 320 may be between the first groove G1 and the second groove G2. The organic encapsulation layer 320 may be formed by coating a monomer, etc., on the substrate 100 and then curing the coated monomer. When the organic encapsulation layer 320 is exposed through the opening 10H, moisture may penetrate through the organic encapsulation layer 320. To address this issue, a portion of the organic encapsulation layer 320, such as a portion of the organic encapsulation layer 320 corresponding to the area HA between the opening area OA and the first groove G1, may be removed through an ashing process, etc. Therefore, when viewed in a direction perpendicular to the upper surface of the substrate 100, the area HA excluding the organic encapsulation layer 320 may be in the shape of a ring surrounding the opening area OA, and the end portion 320E of the organic encapsulation layer 320 may be located between the first groove G1 and the second groove G2.

[0137] Since the end portion 320E of the organic encapsulating layer 320 is positioned closer to the display area DA than the corresponding ends of the first and second inorganic encapsulating layers 310 and 330, the first and second inorganic encapsulating layers 310 and 330 may be in direct contact with each other in the area HA. ​​The first and second inorganic encapsulating layers 310 and 330 may be in direct contact with each other in the second groove G2 and around the opening 10H of the display panel 10.

[0138] The end portion 100E of the substrate 100 directed toward the opening 10H of the display panel 10 may protrude further toward the opening 10H than the end portion 250E of the lower insulating layer 250 directed toward the opening 10H. Figure 7 Shown in the vertical Figure 6 and Figure 7 Both are cross-sectional views observed in the direction of the upper surface of the substrate 100, but like the substrate 100 including the first opening 100H corresponding to the opening area OA, the lower insulating layer 250 may include an opening 250H corresponding to the opening area OA, and the opening 250H of the lower insulating layer 250 may have a diameter larger than the first opening 100H of the substrate 100.

[0139] The first opening 100H of the substrate 100 can be formed by laser cutting, drilling, etc. When an impact is applied to the at least one insulating layer AIL, which is an inorganic insulating layer, during the process of forming the first opening 100H, cracks may be generated, and foreign matter such as external moisture may penetrate through the cracks of the at least one insulating layer AIL. However, when the portion of the multilayer ML corresponding to the opening area OA is removed during the etching process of forming the first groove G1 and the second groove G2, and then the above-mentioned laser cutting or drilling is performed to form the first opening 100H in the substrate 100, cracks can be prevented from forming in the inorganic insulating layer. The second distance d2 can be understood as a margin sufficient to prevent cracks from forming in the inorganic insulating layer during laser cutting or drilling. The second distance d2 is the distance between the end 100E of the substrate 100 and the end 250E of the lower insulating layer 250, and can be approximately 0.1 μm or greater.

[0140] Figure 10A is a cross-sectional view of a first groove G1 according to another embodiment, and Figure 10B It shows Figure 10A A cross-sectional view of the stacked structure on the first groove G1. Figure 9A and Figure 9B In the first groove G1, at least one side surface AIL-IE of the insulating layer AIL is relatively flat. Figure 10A and Figure 10B , an undercut structure is locally formed in the at least one insulating layer AIL, and a side surface of the at least one insulating layer AIL facing the first groove G1 is uneven.

[0141] At least one insulating layer AIL may include an inorganic insulating layer, for example, a plurality of inorganic insulating layers including silicon. Depending on various conditions during the etching process (for example, time, composition of an etchant or etching gas, etc.) and / or various materials included in the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, the amounts of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 etched away during the etching process may be different from each other. For example, when the first interlayer insulating layer 205 includes silicon oxide and the buffer layer 201, the gate insulating layer 203, and the second interlayer insulating layer 207 include silicon nitride, even when the same etching gas is used, the amounts of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 etched away may be different from each other depending on the etching conditions (for example, time, etc.), as shown in FIG. Figure 10A As shown. The side surface 201IE of the buffer layer 201, the side surface 203IE of the gate insulating layer 203, and the side surface 207IE of the second interlayer insulating layer 207 may protrude more toward the center of the first groove G1 than the side surface 205IE of the first interlayer insulating layer 205 adjacent thereto and the side surface 250IE of the lower insulating layer 250 adjacent thereto. Therefore, a plurality of undercut structures may be formed in the at least one insulating layer AIL, so that the at least one insulating layer AIL has an uneven side surface facing the first groove G1. The uneven side surface of the first groove G1 is not only a concave-convex surface, but is also obtained because the multiple inorganic insulating layers included in the at least one insulating layer AIL have different materials from each other. Therefore, the uneven side surface can be understood as an uneven surface based on the change of the material in the thickness direction of the inorganic insulating layer.

[0142] exist Figure 10A After the first groove G1 is formed, for example, the intermediate layer 222 of the first functional layer 222a and the second functional layer 222c and the counter electrode 223 are formed by deposition and are all disconnected by the first groove G1, as shown above. Figure 9B As mentioned above. Figure 9B As described above, the first inorganic encapsulating layer 310 and the organic encapsulating layer 320 are sequentially stacked on the counter electrode 223 .

[0143] Figure 11 is a cross-sectional view of a display panel according to another embodiment, and is Figure 6 It corresponds to the cross section taken along line VII-VII'. Figure 12A is included in Figure 11 A cross-sectional view of the first groove G1 in the display panel, and Figure 12B It shows Figure 12AFIG. 5 is a cross-sectional view of the stacked structure on the first groove G1. FIG. Figures 11 to 12B Display panel and Figures 7 to 9B The display panels of FIG. 1 and 2 are basically the same, and therefore, the differences between them will now be mainly described.

[0144] See also Figure 11 , the first groove G1 and the second groove G2 may be formed in the multilayer ML, and the bottom surfaces of the first groove G1 and the second groove G2 may be located on a virtual surface different from the upper surface of the substrate 100. For example, Figure 7 and Figure 9A Unlike the bottom surfaces of the first and second grooves G1 and G2 being arranged on the same virtual surface as the upper surface of the substrate 100, Figure 11 and Figure 12A Bottom surfaces of the first and second grooves G1 and G2 may be located on a virtual surface above (eg, over) the upper surface of the substrate 100 and also below the upper surface of the lower insulating layer 250 .

[0145] 12A , the first groove G1 may be formed by etching the multilayer ML. The second hole AIL-h penetrating the at least one insulating layer AIL may be formed by etching a portion of the at least one insulating layer AIL. The first recess 250r that does not completely penetrate the lower insulating layer 250 may be formed by etching a portion of the lower insulating layer 250 (e.g., the first recess 250r may extend only through a portion of the lower insulating layer 250). The first recess 250r and the second hole AIL-h may together form the first groove G1.

[0146] The depth h of the first recess 250r may be less than the thickness t of the lower insulating layer 250. The depth h of the first recess 250r may be equal to or greater than 50%, 60%, 70%, 80%, 90%, 95%, or 97% of the thickness t of the lower insulating layer 250, but less than the thickness t of the lower insulating layer 250. The first recess 250r and the second hole AIL-h may be connected to each other to form a first groove G1, and a bottom surface of the first groove G1 may be located on a virtual surface between the upper surface of the substrate 100 and the upper surface of the lower insulating layer 250.

[0147] Because the lower insulating layer 250 is an organic insulating layer, when the lower insulating layer 250 remains below the first groove G1, there is a small possibility that external moisture enters through the remaining lower insulating layer 250 and flows into the OLED through cracks in the inorganic insulating layer. However, when the substrate 100 is a rigid substrate as in the embodiment, there is little or no possibility of cracks being generated in the inorganic insulating layer stacked on the substrate 100, and thus the above problem can be minimized.

[0148] When the intermediate layer 222 and the counter electrode 223 are formed on the first and second functional layers 222a and 222c, for example Figure 12A When the first functional layer 222a, the second functional layer 222c and the counter electrode 223 are all disconnected by the first groove G1. Figure 12B shown.

[0149] A first recess 250r is formed in the lower insulating layer 250 instead of a first hole. Figures 11 to 12B The same structure applies to the above Figure 10A and Figure 10B The structure of the first groove G1 and its derivative structures are described.

[0150] Figure 13 is a cross-sectional view of a display panel according to another embodiment.

[0151] Figure 13 The display panel has Figure 7 The display panel has substantially the same structure as that of the embodiment, except that a partition wall 400 is further included between the first groove G1 and the second groove G2.

[0152] The partition wall 400 may include an organic insulating material and, when viewed in a direction perpendicular to the upper surface of the substrate 100, may have an annular shape surrounding the opening area OA (e.g., the opening 10H). The partition wall 400 may include a first sub-partition wall layer 410 and a second sub-partition wall layer 420, the first sub-partition wall layer 410 including the same material as that included in the planarization insulating layer 209, and the second sub-partition wall layer 420 including the same material as that included in the pixel defining layer 211. The partition wall 400 may control the flow of monomers during the process of forming the organic encapsulation layer 320.

[0153] Figure 13 The partition wall 400 may be included in the above see Figure 10A and Figure 10B The display panel of the first groove G1 and the second groove G2 described above has Figures 11 to 12B In the display panel having the first groove G1 and the second groove G2 described above, or in various display panels derived from these display panels.

[0154] Figure 14 is a cross-sectional view of a display panel according to another embodiment, and is Figure 6 It corresponds to the cross section taken along line VII-VII'. Figure 15A yes Figure 14 A cross-sectional view of the first groove G1 of the display panel, and Figure 15B It shows Figure 15AIn addition to the lower insulating layer 250' and the structure of the first and second grooves G1 and G2 based on the lower insulating layer 250', Figure 14 The display panel is the same as that shown above. Figure 7 The display panels described in the examples are basically the same, so the differences between the two display panels will now be mainly described.

[0155] Figure 14 The lower insulating layer 250' in the display panel includes an inorganic insulating layer. The lower insulating layer 250' may include an inorganic insulating layer different from the at least one insulating layer AIL. For example, the lower insulating layer 250' may include silicon nitride or silicon oxycarbide (SiOC).

[0156] The first groove G1 and the second groove G2 may be formed by etching the at least one insulating layer AIL and the lower insulating layer 250'. The etchant or etching gas used during the process of etching the at least one insulating layer AIL may be the same as or different from the etchant or etching gas used during the process of etching the lower insulating layer 250'.

[0157] According to an embodiment, when lower insulating layer 250′ includes silicon nitride or silicon oxycarbide (SiOC), buffer layer 201, gate insulating layer 203, and lower second interlayer insulating layer 207a include silicon oxide, and first interlayer insulating layer 205 and upper second interlayer insulating layer 207b include silicon nitride, the amounts by which these layers are etched away may be different from each other, as shown in FIG. Figure 15A shown.

[0158] The side surfaces 201IE and 203IE of the buffer layer 201 and the gate insulating layer 203 directly on the lower insulating layer 250' may protrude further toward the center of the first groove G1 than the side surface 250'IE of the lower insulating layer 250', thereby forming an undercut structure. The side surface 207aIE of the lower second interlayer insulating layer 207a may protrude further toward the center of the first groove G1 than the side surface 205IE of the first interlayer insulating layer 205, thereby having an undercut structure.

[0159] Figure 15A The second interlayer insulating layer 207 is shown as a multilayer structure having different materials, and thus the side surfaces 207aIE and 207bIE of the lower second interlayer insulating layer 207a and the upper second interlayer insulating layer 207b form steps, but the embodiment is not limited thereto. According to another embodiment, each of the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205 may have a multilayer structure having different materials. In this case, at least one insulating layer AIL may partially have an undercut structure of various shapes.

[0160] The side surface 250'IE of the lower insulating layer 250', which is an inorganic insulating layer, may have an inclination angle β greater than the inclination angle α of the side surface 250IE of the lower insulating layer 250, which is an organic insulating layer, as described above. Figure 9A For example, the inclination angle β of the side surface 250 ′IE of the lower insulating layer 250 ′ may be 80° or more or 85° or more.

[0161] exist Figure 15A After the first groove G1 is formed, the intermediate layer 222 of the first functional layer 222a and the second functional layer 222c and the counter electrode 223 can be formed by deposition and can be disconnected by the first groove G1. Figure 7 、 Figure 9B As described above, the first inorganic encapsulating layer 310 and the organic encapsulating layer 320 are sequentially stacked on the counter electrode 223 .

[0162] Figure 16 is a cross-sectional view of a display panel according to another embodiment, and is Figure 6 It corresponds to the cross-sectional view taken along line VII-VII'. Figure 16 Display panel and Figure 14 The display panels of the OLED and OLED panels are basically the same. Therefore, the differences between them will now be mainly described.

[0163] See also Figure 16 , the first and second grooves G1 and G2 may be formed in the multi-layer ML, and bottom surfaces of the first and second grooves G1 and G2 may be located on a virtual surface different from the upper surface of the substrate 100 . Figure 14 The bottom surfaces of the first and second grooves G1 and G2 are arranged on the same virtual surface as the upper surface of the substrate 100, and Figure 16 Bottom surfaces of the first and second grooves G1 and G2 may be located on a virtual surface above (eg, over) the upper surface of the substrate 100 and also below the upper surface of the lower insulating layer 250 ′.

[0164] The portions of the first groove G1 and the second groove G2 in the lower insulating layer 250' are formed by partially etching the lower insulating layer 250', and thus Figure 12A As described above, a recess may be formed in the lower insulating layer 250'. The depth h of the recess may be less than the thickness t of the lower insulating layer 250'. For example, the depth h of the recess of the lower insulating layer 250' may be equal to or greater than 50%, 60%, 70%, 80%, 90%, 95%, or 97% of the thickness t of the lower insulating layer 250', but less than the thickness t of the lower insulating layer 250'.

[0165] Figure 17 is a schematic cross-sectional view of a display panel according to another embodiment. Figure 17 Display panel and Figure 14 The display panels of FIG. 1 and 2 are basically the same, and therefore, the differences between them will now be mainly described.

[0166] See also Figure 17 The partition wall 400 may be located between the first groove G1 and the second groove G2. The partition wall 400 includes a first sub-partition wall layer 410 and a second sub-partition wall layer 420, and the materials thereof have been described above. Figure 13 Because the partition wall 400 can control the flow of the monomer during the formation of the organic encapsulation layer 320, the end of the organic encapsulation layer 320 formed when the monomer is hardened can be arranged near one side surface of the partition wall 400. The end of the organic encapsulation layer 320 does not extend beyond the partition wall 400 toward the opening 10H. Figure 17 The partition wall 400 may also be included in the Figure 16 in the display panel.

[0167] Figure 18 is a plan view of a display panel 10 ′ according to another embodiment, and Figure 19 yes Figure 18 A plan view of the area around the opening OA. Figures 3 to 6 The components and structure of the display panel 10 are the same Figure 18 The description of the components and structure of the display panel 10 ′ will not be repeated, and the differences between the two display panels will now be focused on and described.

[0168] See also Figure 18 and Figure 19 , the opening area OA of the display panel 10' may be partially surrounded by the display area DA. The pixels P may be spaced apart from each other on the left and right sides of the opening area OA. The scan line SL, which transmits scan signals to the pixels P on the left and right sides of the opening area OA, may be arranged around the opening area OA in the first non-display area NDA1.

[0169] The opening area OA may be at least partially surrounded by the first groove G1 and the second groove G2. Figure 19 The first groove G1 is shown to surround a portion of the opening area OA (e.g., the first groove G1 partially surrounds the opening area OA), and the second groove G2 completely surrounds the entire opening area OA. When the first groove G1 surrounds a portion of the opening area OA, both ends of the first groove G1 may be connected to the third groove G3 located in the second non-display area NDA2. When the second groove G2 completely surrounds the entire opening area OA, the second groove G2 may be connected to the fourth groove G4 located in the second non-display area NDA2. The third groove G3 and the fourth groove G4 may extend along the edge of the substrate 100. In addition, the third groove G3 and the fourth groove G4 may be parallel to each other.

[0170] Figure 20 It is along Figure 19 A cross-sectional view taken along line XX-XX'.

[0171] See also Figure 20 The scan line SL located in the first sub non-display area SNDA1 corresponds to Figure 19 The scanning line SL described in FIG. 1 bypasses the opening area OA. Figure 20 In the embodiment, the scan lines SL are alternately arranged with an insulating layer (eg, the first interlayer insulating layer 205) therebetween. In this case, the spacing between the scan lines SL can be reduced. According to another embodiment, the scan lines SL can be arranged on the same insulating layer.

[0172] The second sub non-display area SNDA2 includes a first groove G1 and a second groove G2. Figure 20 The structure of the first groove G1 and the second groove G2 and the components around the first groove G1 and the second groove G2 are shown. Figure 7 The same as those described above, but the second sub non-display area SNDA2 may have Figures 10A to 17 The structures of the described embodiments and structures derived therefrom.

[0173] Although not in Figure 20 , the third groove G3 and the fourth groove G4 may have a cross-sectional structure substantially the same as that of the first groove G1 and the second groove G2. For example, each of the third groove G3 and the fourth groove G4 may be formed to penetrate at least one of the insulating layer AIL and the lower insulating layer 250, thereby having an undercut structure.

[0174] Figure 21 is a plan view of a display panel 10 ″ according to another embodiment, and Figure 22 yes Figure 21 A plan view of the area around the opening OA. Figures 3 to 6 The components and structure of the display panel 10 are the same Figure 21 The description of the components and structure of the display panel 10 ″ will not be repeated, and the differences between them will now be focused on and described.

[0175] See also Figure 21 and Figure 22 , the opening area OA of the display panel 10″ may be partially surrounded by the display area DA. The pixels P may be spaced apart from each other at upper and lower sides of the opening area OA. The data lines DL transmitting data signals to the pixels P at the upper side of the opening area OA and the pixels P at the lower side of the opening area OA may be arranged around the opening area OA in the first non-display area NDA1.

[0176] The opening area OA may be at least partially surrounded by the first groove G1 and the second groove G2. Figure 22 In the illustrated embodiment, the first groove G1 surrounds a portion of the opening area OA (e.g., the first groove G1 partially surrounds the opening area OA), and the second groove G2 completely surrounds the entire opening area OA. When the first groove G1 surrounds a portion of the opening area OA, both ends of the first groove G1 may connect to the third groove G3 located in the second non-display area NDA2. When the second groove G2 surrounds the entire opening area OA, the second groove G2 may connect to the fourth groove G4 located in the second non-display area NDA2. The third groove G3 and the fourth groove G4 may extend along the edge of the substrate 100. In addition, the third groove G3 and the fourth groove G4 may be parallel to each other.

[0177] Figure 23 It is along Figure 22 A cross-sectional view taken along line XXIII-XXIII'.

[0178] See also Figure 23 The data line DL located in the first sub non-display area SNDA1 corresponds to Figure 22 The data line DL described above bypasses the opening area OA. The second sub non-display area SNDA2 includes a first groove G1 and a second groove G2. Figure 23 The structure of the second sub non-display area SNDA2 is the same as that of the above-mentioned Figure 7 According to another embodiment, the second sub non-display area SNDA2 may have the same Figures 10A to 17 The structures of the described embodiments and structures derived therefrom.

[0179] Although not in Figure 23 , the third groove G3 and the fourth groove G4 may have a cross-sectional structure substantially the same as that of the first groove G1 and the second groove G2. For example, each of the third groove G3 and the fourth groove G4 may be formed to penetrate at least one of the insulating layer AIL and the lower insulating layer 250, thereby having an undercut structure.

[0180] According to an embodiment, multiple layers are formed on a substrate, and grooves can be formed in the multiple layers including at least one insulating layer and a lower insulating layer. The grooves can be formed regardless of the material of the substrate and can effectively block and prevent moisture from penetrating in the lateral direction. In one or more embodiments, in a display panel including a substrate comprising glass, polymer, or metal, since a groove having an undercut structure can be formed without removing the substrate, the material used to form the substrate may not be limited. However, the above effects are exemplary.

[0181] It should be understood that the embodiments described herein should be understood in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.

[0182] Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A display panel, comprising: A glass substrate comprising an opening area and a display area at least partially surrounding the opening area; a thin film transistor located in the display area and comprising a semiconductor layer and a gate electrode; a display element electrically connected to the thin film transistor; a multilayer including a lower insulating layer and at least one insulating layer, wherein the at least one insulating layer is between the glass substrate and the display element, and the lower insulating layer is between the glass substrate and the at least one insulating layer; as well as a thin film encapsulation layer covering the display element and comprising at least one inorganic encapsulation layer and at least one organic encapsulation layer, wherein the multilayer includes a first groove between the opening area and the display area, and wherein a first width of a portion of the first groove in the lower insulating layer is greater than a second width of a portion of the first groove in the at least one insulating layer, and A portion of the at least one organic encapsulation layer at least partially fills the portion of the first groove in the lower insulating layer.

2. The display panel according to claim 1 , wherein a bottom surface of the first groove is located on a virtual surface between an upper surface of the lower insulating layer and an upper surface of the glass substrate, or on the same virtual surface as the upper surface of the glass substrate.

3. The display panel according to claim 1, wherein: The at least one insulating layer includes a first hole corresponding to the first groove, and the lower insulating layer includes a second hole or recess corresponding to the first groove.

4. The display panel according to claim 3, wherein: A side surface of the at least one insulating layer facing the center of the first groove is closer to the center of the first groove than a side surface of the lower insulating layer facing the center of the first groove. The display panel according to claim 1 , wherein the lower insulating layer is in direct contact with an upper surface of the glass substrate. The display panel according to claim 1 , wherein: The at least one inorganic encapsulation layer covers an inner surface of the first groove. 7 . The display panel according to claim 1 , wherein a portion of the at least one inorganic encapsulation layer is in direct contact with a portion of the glass substrate within the first groove.

8. The display panel according to claim 1, wherein: The glass substrate includes a first opening corresponding to the opening area.

9. The display panel according to claim 8, wherein: An end portion of the glass substrate defining the first opening is closer to the center of the opening region than an end portion of the lower insulating layer facing the opening region.

10. The display panel according to claim 1, wherein: The multilayer further includes a second groove between the first groove and the open area. The display panel according to claim 10 , wherein an end portion of the at least one organic encapsulating layer is between the first groove and the second groove. 12 . The display panel of claim 10 , further comprising a partition wall on the multiple layers and between the first groove and the second groove. 13 . The display panel of claim 1 , wherein the lower insulating layer comprises an organic insulating layer, and the at least one insulating layer comprises an inorganic insulating layer. 14 . The display panel of claim 1 , wherein the lower insulating layer comprises at least one of silicon nitride and silicon oxycarbide, and the at least one insulating layer comprises an inorganic insulating layer comprising a material different from that of the lower insulating layer.

15. A display device comprising: a substrate including an opening; a thin film transistor, located in a display area of ​​the substrate and comprising a semiconductor layer and a gate electrode, wherein the display area at least partially surrounds the opening; a display element electrically connected to the thin film transistor; a multilayer including a lower insulating layer and at least one insulating layer, wherein the lower insulating layer is located on the substrate, and the at least one insulating layer is located on the lower insulating layer and includes a different material from the lower insulating layer; as well as an encapsulation layer configured to cover the display element and comprising at least one inorganic encapsulation layer and at least one organic encapsulation layer, wherein the multilayer includes a first groove recessed in a depth direction of the multilayer, and a width of a portion of the first groove in the lower insulating layer is greater than a width of a portion of the first groove in the at least one insulating layer, and A portion of the at least one organic encapsulation layer at least partially fills the portion of the first groove in the lower insulating layer.

16. The display device according to claim 15, wherein The substrate includes a glass material, a polymer material or a metal material.

17. The display device according to claim 15, wherein A bottom surface of the first groove is located on a virtual surface between an upper surface of the lower insulating layer and an upper surface of the substrate, or on the same virtual surface as the upper surface of the substrate.

18. The display device according to claim 15, wherein The at least one insulating layer includes a first hole corresponding to the first groove, and the lower insulating layer includes a second hole or recess corresponding to the first groove.

19. The display device according to claim 15, wherein The at least one insulating layer includes an inorganic insulating layer. 20 . The display device of claim 19 , wherein the lower insulating layer comprises an organic insulating layer or an inorganic insulating layer different from the at least one insulating layer.

21. The display device according to claim 15, wherein A side surface of the at least one insulating layer directed toward a center of the first groove protrudes more than a side surface of the lower insulating layer directed toward the center of the first groove.

22. The display device according to claim 15, wherein An end portion of the substrate directed toward the opening protrudes further toward the opening than an end portion of the lower insulating layer directed toward the opening.

23. The display device according to claim 15, wherein The multilayer further includes a second groove between the first groove and the opening.

24. The display device according to claim 23, wherein The at least one inorganic encapsulation layer covers an inner surface of each of the first groove and the second groove. 25 . The display device of claim 24 , further comprising a partition wall on the multiple layers and between the first groove and the second groove.

26. The display device according to claim 24, wherein The at least one inorganic encapsulation layer is in direct contact with an upper surface of the substrate within the first groove or the second groove.

27. The display device according to claim 15, wherein The at least one insulating layer includes a first insulating layer and a second insulating layer on the first insulating layer, the first insulating layer and the second insulating layer include different materials; and The first insulating layer and the second insulating layer respectively include a hole corresponding to the first groove, and a width of the hole in the second insulating layer is smaller than a width of the hole in the first insulating layer.

28. The display device of claim 15, wherein the display element comprises an organic light emitting diode. 29 . The display device of claim 28 , wherein at least one of an organic layer and a counter electrode included in the organic light emitting diode is disconnected by the first groove.

30. The display device according to any one of claims 15 to 29, further comprising: An electronic component corresponds to the opening of the substrate, wherein the electronic component includes a sensor or a camera.

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