A current limiting protection circuit for high voltage linear regulator

Abstract

The present invention relates to a current limiting protection circuit applied to a high-voltage linear voltage stabilizer, characterized in that: the circuit includes an error amplifier, a main path and a current limiting protection circuit; the error amplifier and the main path form a negative feedback loop, amplify the small error signal between the output feedback voltage and the reference voltage, and amplify it to the output through an adjustment tube, thereby ensuring that the output voltage is stable at a specified value; the current limiting protection circuit and the main path form a current loop, thereby realizing the output current limitation and protection function, when the linear voltage stabilizer works under the condition of a large input-output voltage difference, the load current of the high-voltage linear voltage stabilizer can be limited within a certain range, avoiding long-term large current from damaging the power tube, thereby burning the chip. The circuit has a stable current limiting protection function, a simple structure, and greatly improves the reliability of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-voltage linear voltage regulator, and in particular relates to a current limiting protection circuit applied to a high-voltage linear voltage regulator. Background Art

[0002] At present, with the proliferation of portable electronic products, linear regulators and switching power managers are increasingly widely used. Compared with switching power managers, linear regulators have the advantages of being integrable, having low ripple, low noise, no electromagnetic interference, and low cost, and are particularly favored by major electronic product design and manufacturing companies. However, when linear regulators work for a long time under the condition of large input-output voltage difference, the high current will damage the power tube, thus burning the chip.

[0003] Therefore, providing a current limiting protection circuit applied to a high-voltage linear regulator is a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0004] In order to solve the above problem, the present invention provides a current limiting protection circuit applied to a high voltage linear regulator.

[0005] A current limiting protection circuit for a high-voltage linear regulator comprises a main path, an error amplifier and a current limiting protection circuit; the main path comprises a P-type MOS tube, an N-type MOS tube, a first resistor R1 and a second resistor R2; the error amplifier comprises eight P-type MOS tubes, eleven N-type MOS tubes, a current source IBIAS, a resistor R and a capacitor C; the current limiting protection circuit comprises a current limiting circuit and a protection circuit; the current limiting circuit comprises eight P-type MOS tubes, eleven N-type MOS tubes, a first current source IBIAS1 and a second current source IBIAS2; the protection circuit comprises three P-type MOS tubes, one N-type MOS tube, a first resistor r1, a second resistor r2, a first inverter INV1, a second inverter INV2 and a third inverter INV3.

[0006] A further solution is: an input terminal VINP of the error amplifier is connected to the input port VINP, another input terminal VINN of the error amplifier is connected to one end of the first resistor R1 and one end of the second resistor R2 of the main path, an output terminal VOUT of the error amplifier is connected to the gate of the first N-type MOS transistor N1 of the main path, a source of the first P-type MOS transistor P1 of the main path is connected to the power supply, a gate of the first P-type MOS transistor P1 of the main path is connected to the output terminal DRV of the current limiting protection circuit, a drain of the first P-type MOS transistor P1 of the main path and a drain of the first N-type MOS transistor N1 are connected to the input terminal CSV of the current limiting protection circuit, a source of the first N-type MOS transistor N1 of the main path and the other end of the first resistor R1 are connected to the output port Vout, and the other end of the second resistor R2 of the main path is connected to the ground.

[0007] A further solution is that in the error amplifier, one end of the current source IBIAS, the source of the first P-type MOS tube MP1, the source of the second P-type MOS tube MP2, the source of the fifth P-type MOS tube MP5, the source of the sixth P-type MOS tube MP6, and the source of the seventh P-type MOS tube MP7 are connected to the power supply, the gate of the first P-type MOS tube MP1, the drain of the first P-type MOS tube MP1, the gate of the second P-type MOS tube MP2 and the drain of the third N-type MOS tube MN3 are connected, the drain of the second P-type MOS tube MP2, the source of the third P-type MOS tube MP3 and the source of the fourth P-type MOS tube MP4 are connected, and the third The gate of the P-type MOS transistor MP3 is connected to the input port VINP, the drain of the third P-type MOS transistor MP3, the drain of the fifth N-type MOS transistor MN5, the gate of the fifth N-type MOS transistor MN5 and the gate of the tenth N-type MOS transistor MN10 are connected, the gate of the fourth P-type MOS transistor MP4 is connected to the input port VINN, the drain of the fourth P-type MOS transistor MP4, the drain of the sixth N-type MOS transistor MN6, the gate of the sixth N-type MOS transistor MN6 and the gate of the ninth N-type MOS transistor MN9 are connected, the gate of the fifth P-type MOS transistor MP5, the drain of the fifth P-type MOS transistor MP5, the gate of the sixth P-type MOS transistor MP6 and the gate of the tenth N-type MOS transistor MN10 are connected, the gate of the fourth P-type MOS transistor MP4 is connected to the input port VINN, the drain of the fourth P-type MOS transistor MP4, the drain of the sixth N-type MOS transistor MN6, the gate of the sixth N-type MOS transistor MN6 and the gate of the ninth N-type MOS transistor MN9 are connected, The gate of the seventh P-type MOS transistor MP7 is connected to the drain of the seventh N-type MOS transistor MN7, the drain of the sixth P-type MOS transistor MP6, the gate of the eighth P-type MOS transistor MP8, and the drain of the eighth N-type MOS transistor MN8 are connected to one end of the resistor R, the drain of the seventh P-type MOS transistor MP7 and the source of the eighth P-type MOS transistor MP8 are connected to the output port VOUT, the drain of the eighth P-type MOS transistor MP8 is connected to the drain of the eleventh N-type MOS transistor MN11, the drain of the first N-type MOS transistor MN1, the gate of the first N-type MOS transistor MN1, the gate of the third N-type MOS transistor MN3, the gate of the seventh N-type MOS transistor MN7, and the gate of the eighth N-type MOS transistor MN8 are connected to the output port VOUT, and the drain of the eighth P-type MOS transistor MP8 is connected to the drain of the eleventh N-type MOS transistor MN11. The gate of the eighth N-type MOS transistor MN8 is connected to the other end of the current source IBIAS, the source of the first N-type MOS transistor MN1, the drain of the second N-type MOS transistor MN2, the gate of the second N-type MOS transistor MN2, the gate of the fourth N-type MOS transistor MN4 and the gate of the eleventh N-type MOS transistor MN11 are connected, the source of the third N-type MOS transistor MN3 is connected to the drain of the fourth N-type MOS transistor MN4, the source of the seventh N-type MOS transistor MN7 is connected to the drain of the ninth N-type MOS transistor MN9, the source of the eighth N-type MOS transistor MN8 is connected to the drain of the tenth N-type MOS transistor MN10, the other end of the resistor R is connected to one end of the capacitor C,The source of the second N-type MOS transistor MN2, the source of the fourth N-type MOS transistor MN4, the source of the fifth N-type MOS transistor MN5, the source of the sixth N-type MOS transistor MN6, the source of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10, the source of the eleventh N-type MOS transistor MN11, and the other end of the capacitor C are connected to the ground.

[0008] A further solution is: in the current limiting circuit, the source of the first P-type MOS tube mP1, the source of the second P-type MOS tube mP2, the source of the third P-type MOS tube mP3, the source of the fourth P-type MOS tube mP4, the source of the fifth P-type MOS tube mP5, the source of the sixth P-type MOS tube mP6, the gate of the third N-type MOS tube mN3, one end of the first current source IBIAS1, and one end of the second current source IBIAS2 are connected to the power supply, the gate of the first P-type MOS tube mP1, the drain of the first P-type MOS tube mP1, the gate of the second P-type MOS tube mP2 and the drain of the third N-type MOS tube mN3 are connected, the drain of the second P-type MOS tube mP2, the gate of the third P-type MOS tube mP3, the third P-type MOS tube mN4 are connected to the drain of the third N-type MOS tube mN5, and the gate of the third P-type MOS tube mP5 is connected to the drain of the third N-type MOS tube mN6. The drain of the fourth P-type MOS tube mP3, the gate of the fourth P-type MOS tube mP4 and the drain of the fourth N-type MOS tube mN4 are connected, the drain of the fourth P-type MOS tube mP4, the gate of the fifth P-type MOS tube mP5, the gate of the sixth P-type MOS tube mP6, the drain of the eighth N-type MOS tube mN8 and the drain of the ninth N-type MOS tube mN9 are connected to the output port DRV, the drain of the fifth P-type MOS tube mP5 is connected to the source of the eighth P-type MOS tube mP8, the source of the seventh P-type MOS tube mP7 is connected to the input port CSV, the gate of the seventh P-type MOS tube mP7, the drain of the seventh P-type MOS tube mP7 and the gate of the eighth P-type MOS tube mP8 are connected to the sixth N-type MOS tube The drain of the eighth P-type MOS tube mP8, the gate of the fifth N-type MOS tube mN5, the gate of the sixth N-type MOS tube mN6, the gate of the seventh N-type MOS tube mN7 and the drain of the seventh N-type MOS tube mN7 are connected, the drain of the first N-type MOS tube mN1, the gate of the first N-type MOS tube mN1 and the gate of the second N-type MOS tube mN2 are connected to the other end of the first current source IBIAS1, the drain of the second N-type MOS tube mN2 is connected to the source of the third N-type MOS tube mN3, the gate of the fourth N-type MOS tube mN4 and the gate of the ninth N-type MOS tube mN9 are connected to the input signal OCP, the source of the fourth N-type MOS tube mN4 is connected to the fifth N-type MOS tube mN 5, the gate of the eighth N-type MOS tube mN8, the gate of the tenth N-type MOS tube mN10, the gate of the eleventh N-type MOS tube mN11, and the drain of the eleventh N-type MOS tube mN11 are connected to the other end of the second current source IBIAS2, the source of the ninth N-type MOS tube mN9 is connected to the drain of the tenth N-type MOS tube mN10, the source of the first N-type MOS tube mN1, the source of the second N-type MOS tube mN2, the source of the fifth N-type MOS tube mN5, the source of the sixth N-type MOS tube mN6, the source of the seventh N-type MOS tube mN7, the source of the eighth N-type MOS tube mN8, the source of the tenth N-type MOS tube mN10, and the source of the eleventh N-type MOS tube mN11 are connected to ground;.

[0009] In the protection circuit, the source of the first P-type MOS transistor Mp1, the gate of the first N-type MOS transistor Mn1, and one end of the first resistor r1 are connected to the power supply, the gate of the first P-type MOS transistor Mp1, the drain of the first P-type MOS transistor Mp1 and the source of the second P-type MOS transistor Mp2 are connected, the gate of the second P-type MOS transistor Mp2, the drain of the second P-type MOS transistor Mp2, and the gate of the third P-type MOS transistor Mp3 are connected to the input port CSV, and the source of the third P-type MOS transistor Mp3 is connected to the other end of the first resistor r1. The drain of the third P-type MOS transistor Mp3 and the drain of the first N-type MOS transistor Mn1 are connected to one end of the second resistor r2, the source of the first N-type MOS transistor Mn1 is connected to the input end A of the first inverter INV1, the output end Y of the first inverter INV1 is connected to the input end A of the second inverter INV2, the output end Y of the second inverter INV2 is connected to the input end A of the third inverter INV3, the output end Y of the third inverter INV3 is connected to the output signal OCP, and the other end of the second resistor r2 is connected to ground.

[0010] Compared with the related art, the beneficial effects of the present invention are as follows: the circuit of the present application has a stable current limiting protection function and a simple structure. When the linear regulator operates under the condition of a large input-output voltage difference, the load current of the high-voltage linear regulator can be limited within a certain range, thereby avoiding long-term high current from damaging the power tube and burning the chip, thereby improving the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a high voltage linear regulator system with current limiting protection function;

[0012] Figure 2 is the error amplifier circuit diagram;

[0013] Figure 3 is the current limiting circuit diagram;

[0014] Figure 4 To protect the circuit diagram. DETAILED DESCRIPTION

[0015] The present invention will be further described below in conjunction with the accompanying drawings and implementation examples.

[0016] The present application discloses a current limiting protection circuit applied to a high-voltage linear regulator, comprising a main path, an error amplifier and a current limiting protection circuit; the main path comprises a P-type MOS tube, an N-type MOS tube, a first resistor R1, and a second resistor R2; the error amplifier comprises eight P-type MOS tubes, eleven N-type MOS tubes, a current source IBIAS, a resistor R, and a capacitor C; the current limiting protection circuit comprises a current limiting circuit and a protection circuit; the current limiting circuit comprises eight P-type MOS tubes, eleven N-type MOS tubes, a first current source IBIAS1, and a second current source IBIAS2; the protection circuit comprises three P-type MOS tubes, one N-type MOS tube, a first resistor r1, a second resistor r2, a first inverter INV1, a second inverter INV2, and a third inverter INV3.

[0017] An input terminal VINP of the error amplifier is connected to the input port VINP, another input terminal VINN of the error amplifier is connected to one end of the first resistor R1 and one end of the second resistor R2 of the main path, an output terminal VOUT of the error amplifier is connected to the gate of the first N-type MOS transistor N1 of the main path, a source of the first P-type MOS transistor P1 of the main path is connected to a power supply, a gate of the first P-type MOS transistor P1 of the main path is connected to an output terminal DRV of the current limiting protection circuit, a drain of the first P-type MOS transistor P1 of the main path and a drain of the first N-type MOS transistor N1 are connected to an input terminal CSV of the current limiting protection circuit, a source of the first N-type MOS transistor N1 of the main path and the other end of the first resistor R1 are connected to the output port Vout, and the other end of the second resistor R2 of the main path is connected to ground.

[0018] In the error amplifier, one end of the current source IBIAS, the source of the first P-type MOS tube MP1, the source of the second P-type MOS tube MP2, the source of the fifth P-type MOS tube MP5, the source of the sixth P-type MOS tube MP6, and the source of the seventh P-type MOS tube MP7 are connected to the power supply, the gate of the first P-type MOS tube MP1, the drain of the first P-type MOS tube MP1, the gate of the second P-type MOS tube MP2 and the drain of the third N-type MOS tube MN3 are connected, the drain of the second P-type MOS tube MP2, the source of the third P-type MOS tube MP3 and the source of the fourth P-type MOS tube MP4 are connected, the gate of the third P-type MOS tube MP3 is connected to the input port VINP, and the drain of the third P-type MOS tube MP3 is connected to the input port VINP. The drain of the fifth N-type MOS transistor MN5, the drain of the fifth N-type MOS transistor MN5, the gate of the fifth N-type MOS transistor MN5 are connected to the gate of the tenth N-type MOS transistor MN10, the gate of the fourth P-type MOS transistor MP4 is connected to the input port VINN, the drain of the fourth P-type MOS transistor MP4, the drain of the sixth N-type MOS transistor MN6, the gate of the sixth N-type MOS transistor MN6 are connected to the gate of the ninth N-type MOS transistor MN9, the gate of the fifth P-type MOS transistor MP5, the drain of the fifth P-type MOS transistor MP5, the gate of the sixth P-type MOS transistor MP6, the gate of the seventh P-type MOS transistor MP7 are connected to the drain of the seventh N-type MOS transistor MN7, the drain of the sixth P-type MOS transistor MP6, the gate of the eighth P-type MOS transistor MP8, the gate of the eighth N-type MOS transistor MP9 are connected to the drain of the seventh N-type MOS transistor MN9 ... The drain of the seventh P-type MOS transistor MP7 and the source of the eighth P-type MOS transistor MP8 are connected to the output port VOUT, the drain of the eighth P-type MOS transistor MP8 is connected to the drain of the eleventh N-type MOS transistor MN11, the drain of the first N-type MOS transistor MN1, the gate of the first N-type MOS transistor MN1, the gate of the third N-type MOS transistor MN3, the gate of the seventh N-type MOS transistor MN7, and the gate of the eighth N-type MOS transistor MN8 are connected to the other end of the current source IBIAS, the source of the first N-type MOS transistor MN1, the drain of the second N-type MOS transistor MN2, the gate of the second N-type MOS transistor MN2, and the gate of the fourth N-type MOS transistor MN4 are connected to the eleventh N-type MOS transistor MN11. The gate of the N-type MOS transistor MN11 is connected, the source of the third N-type MOS transistor MN3 is connected to the drain of the fourth N-type MOS transistor MN4, the source of the seventh N-type MOS transistor MN7 is connected to the drain of the ninth N-type MOS transistor MN9, the source of the eighth N-type MOS transistor MN8 is connected to the drain of the tenth N-type MOS transistor MN10, the other end of the resistor R is connected to one end of the capacitor C, the source of the second N-type MOS transistor MN2, the source of the fourth N-type MOS transistor MN4, the source of the fifth N-type MOS transistor MN5, the source of the sixth N-type MOS transistor MN6, the source of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10, the source of the eleventh N-type MOS transistor MN11, and the other end of the capacitor C are connected to ground.The input port VINP is connected to the reference voltage VREF, and the input port VINN is connected to the feedback voltage VFB of the output Vout. When the output voltage is about to reach the specified value, the feedback voltage VFB is also close to the reference voltage VREF. At this time, the error amplifier amplifies the small error signal between the output feedback voltage and the reference voltage, and amplifies it to the output through the adjustment tube, thereby forming negative feedback and ensuring that the output voltage is stable at the specified value.

[0019] In the current limiting circuit, the source of the first P-type MOS transistor mP1, the source of the second P-type MOS transistor mP2, the source of the third P-type MOS transistor mP3, the source of the fourth P-type MOS transistor mP4, the source of the fifth P-type MOS transistor mP5, the source of the sixth P-type MOS transistor mP6, the gate of the third N-type MOS transistor mN3, one end of the first current source IBIAS1, and one end of the second current source IBIAS2 are connected to the power supply, the gate of the first P-type MOS transistor mP1, the drain of the first P-type MOS transistor mP1, the gate of the second P-type MOS transistor mP2 and the drain of the third N-type MOS transistor mN3 are connected, the drain of the second P-type MOS transistor mP2, the gate of the third P-type MOS transistor mP3, the gate of the third P-type MOS transistor m The drain of the fourth P-type MOS tube mP3, the gate of the fourth P-type MOS tube mP4 and the drain of the fourth N-type MOS tube mN4 are connected, the drain of the fourth P-type MOS tube mP4, the gate of the fifth P-type MOS tube mP5, the gate of the sixth P-type MOS tube mP6, the drain of the sixth P-type MOS tube mP6, the drain of the eighth N-type MOS tube mN8 and the drain of the ninth N-type MOS tube mN9 are connected to the output port DRV, the drain of the fifth P-type MOS tube mP5 and the source of the eighth P-type MOS tube mP8 are connected, the source of the seventh P-type MOS tube mP7 is connected to the input port CSV, the gate of the seventh P-type MOS tube mP7, the drain of the seventh P-type MOS tube mP7, the gate of the eighth P-type MOS tube mP8 and the drain of the sixth ... The drain of the eighth P-type MOS tube mP8, the gate of the fifth N-type MOS tube mN5, the gate of the sixth N-type MOS tube mN6, the gate of the seventh N-type MOS tube mN7 and the drain of the seventh N-type MOS tube mN7 are connected, the drain of the first N-type MOS tube mN1, the gate of the first N-type MOS tube mN1 and the gate of the second N-type MOS tube mN2 are connected to the other end of the first current source IBIAS1, the drain of the second N-type MOS tube mN2 is connected to the source of the third N-type MOS tube mN3, the gate of the fourth N-type MOS tube mN4 and the gate of the ninth N-type MOS tube mN9 are connected to the input signal OCP, the source of the fourth N-type MOS tube mN4 is connected to the source of the fifth N-type MOS tube mN5, and the gate of the ninth N-type MOS tube mN9 are connected to the input signal OCP. The drain of the eighth N-type MOS tube mN8, the gate of the tenth N-type MOS tube mN10, the gate of the eleventh N-type MOS tube mN11, and the drain of the eleventh N-type MOS tube mN11 are connected to the other end of the second current source IBIAS2, the source of the ninth N-type MOS tube mN9 is connected to the drain of the tenth N-type MOS tube mN10, and the source of the first N-type MOS tube mN1, the source of the second N-type MOS tube mN2, the source of the fifth N-type MOS tube mN5, the source of the sixth N-type MOS tube mN6, the source of the seventh N-type MOS tube mN7, the source of the eighth N-type MOS tube mN8, the source of the tenth N-type MOS tube mN10, and the source of the eleventh N-type MOS tube mN11 are connected to ground;

[0020] In the protection circuit, the source of the first P-type MOS transistor Mp1, the gate of the first N-type MOS transistor Mn1, and one end of the first resistor r1 are connected to the power supply, the gate of the first P-type MOS transistor Mp1, the drain of the first P-type MOS transistor Mp1 and the source of the second P-type MOS transistor Mp2 are connected, the gate of the second P-type MOS transistor Mp2, the drain of the second P-type MOS transistor Mp2, and the gate of the third P-type MOS transistor Mp3 are connected to the input port CSV, and the source of the third P-type MOS transistor Mp3 is connected to the other end of the first resistor r1. The drain of the third P-type MOS transistor Mp3 and the drain of the first N-type MOS transistor Mn1 are connected to one end of the second resistor r2, the source of the first N-type MOS transistor Mn1 is connected to the input end A of the first inverter INV1, the output end Y of the first inverter INV1 is connected to the input end A of the second inverter INV2, the output end Y of the second inverter INV2 is connected to the input end A of the third inverter INV3, the output end Y of the third inverter INV3 is connected to the output signal OCP, and the other end of the second resistor r2 is connected to the ground. The current of the sixth P-type MOS transistor mP6 of the current limiting circuit is obtained by amplifying the current of the second current source IBIAS2 through a current mirror, and at the same time, the sixth P-type MOS transistor mP6 of the current limiting circuit forms a current mirror with the first P-type MOS transistor P1 of the main path, so the maximum value of the output current can be determined by setting the current value of the second current source IBIAS2 of the current limiting circuit and the ratio of the MOS transistors forming the current mirror. When the output current reaches the set limit value, the current flowing through the third P-type MOS tube mP3 of the current limiting circuit increases accordingly, and through the current mirror, the current of the fourth P-type MOS tube mP4 is increased, thereby increasing the pull-up capability of the output signal DRV, thereby limiting the further increase of the current of the first P-type MOS tube P1 of the main path. If the output current continues to increase, the pull-down capability is enhanced, and the input signal CSV of the protection circuit decreases accordingly, causing the second P-type MOS tube Mp2 of the protection circuit to be turned on, and then the third P-type MOS tube Mp3 to be turned on, and finally the output signal OCP of the protection circuit changes from high to low, turning off the ninth N-type MOS tube mN9 of the current limiting circuit, reducing the current of the sixth P-type MOS tube mP6 of the current limiting circuit, thereby reducing the current flowing through the power adjustment tube in the main path, avoiding long-term large current from damaging the power adjustment tube, thereby burning the chip, and improving the stability of the system.

[0021] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A current limiting protection circuit for a high voltage linear regulator, characterized in that: It includes a main path, an error amplifier and a current limiting protection circuit; the main path includes a P-type MOS tube, an N-type MOS tube, a first resistor R1, and a second resistor R2; the current limiting protection circuit includes a current limiting circuit and a protection OCP circuit; the current limiting circuit includes eight P-type MOS tubes, eleven N-type MOS tubes, a first current source IBIAS1 and a second current source IBIAS2; the protection OCP circuit includes three P-type MOS tubes, one N-type MOS tube, a first resistor r1, a second resistor r2, a first inverter INV1, a second inverter INV2, and a third inverter INV3; The input terminal VINP of the error amplifier is connected to the input port VINP, the other input terminal VINN of the error amplifier is connected to one end of the first resistor R1 of the main path and one end of the second resistor R2, and the output terminal VOUT of the error amplifier is connected to the gate of the first N-type MOS transistor N1 of the main path; the input port CSV of the current limiting protection circuit is connected to the drain of the first P-type MOS transistor of the main path and the drain of the first N-type MOS transistor N1, and the output port DRV of the current limiting protection circuit is connected to the gate of the first P-type MOS transistor P1 of the main path; the source of the first N-type MOS transistor N1 of the main path and the other end of the first resistor R1 are connected to the output port Vout, the source of the first P-type MOS transistor P1 of the main path is connected to the power supply, and the other end of the second resistor R2 of the main path is connected to the ground; In the current limiting circuit, the source of the first P-type MOS tube mP1, the source of the second P-type MOS tube mP2, the source of the third P-type MOS tube mP3, the source of the fourth P-type MOS tube mP4, the source of the fifth P-type MOS tube mP5, the source of the sixth P-type MOS tube mP6, the gate of the third N-type MOS tube mN3, one end of the first current source IBIAS1, and one end of the second current source IBIAS2 are connected to the power supply, the gate of the first P-type MOS tube mP1, the drain of the first P-type MOS tube mP1, the gate of the second P-type MOS tube mP2 and the drain of the third N-type MOS tube mN3 are connected, the drain of the second P-type MOS tube mP2, the gate of the third P-type MOS tube mP3, the gate of the third P-type MOS tube mN4 are connected to the drain of the third N-type MOS tube mN5, and the gate of the third P-type MOS tube mN6 is connected to the drain of the third N-type MOS tube mN7. The drain of the fourth P-type MOS tube mP3, the gate of the fourth P-type MOS tube mP4 and the drain of the fourth N-type MOS tube mN4 are connected, the drain of the fourth P-type MOS tube mP4, the gate of the fifth P-type MOS tube mP5, the gate of the sixth P-type MOS tube mP6, the drain of the sixth P-type MOS tube mP6, the drain of the eighth N-type MOS tube mN8 and the drain of the ninth N-type MOS tube mN9 are connected to the output port DRV, the drain of the fifth P-type MOS tube mP5 and the source of the eighth P-type MOS tube mP8 are connected, the source of the seventh P-type MOS tube mP7 is connected to the input port CSV, the gate of the seventh P-type MOS tube mP7, the drain of the seventh P-type MOS tube mP7 and the gate of the eighth P-type MOS tube mP8 are connected to the sixth N-type MOS The drain of the eighth P-type MOS tube mP8, the gate of the fifth N-type MOS tube mN5, the gate of the sixth N-type MOS tube mN6, the gate of the seventh N-type MOS tube mN7 and the drain of the seventh N-type MOS tube mN7 are connected, the drain of the first N-type MOS tube mN1, the gate of the first N-type MOS tube mN1 and the gate of the second N-type MOS tube mN2 are connected to the other end of the first current source IBIAS1, the drain of the second N-type MOS tube mN2 is connected to the source of the third N-type MOS tube mN3, the gate of the fourth N-type MOS tube mN4 and the gate of the ninth N-type MOS tube mN9 are connected to the signal OCP, the source of the fourth N-type MOS tube mN4 is connected to the source of the fifth N-type MOS tube mN5 ... drain of the first N-type MOS tube mN1, the gate of the first N-type MOS tube mN1 and the gate of the second The drain of the eighth N-type MOS tube mN8, the gate of the tenth N-type MOS tube mN10, the gate of the eleventh N-type MOS tube mN11, and the drain of the eleventh N-type MOS tube mN11 are connected to the other end of the second current source IBIAS2, the source of the ninth N-type MOS tube mN9 is connected to the drain of the tenth N-type MOS tube mN10, and the source of the first N-type MOS tube mN1, the source of the second N-type MOS tube mN2, the source of the fifth N-type MOS tube mN5, the source of the sixth N-type MOS tube mN6, the source of the seventh N-type MOS tube mN7, the source of the eighth N-type MOS tube mN8, the source of the tenth N-type MOS tube mN10, and the source of the eleventh N-type MOS tube mN11 are connected to ground; In the protection OCP circuit, the source of the first P-type MOS transistor Mp1, the gate of the first N-type MOS transistor Mn1, and one end of the first resistor r1 are connected to the power supply, the gate of the first P-type MOS transistor Mp1, the drain of the first P-type MOS transistor Mp1 and the source of the second P-type MOS transistor Mp2 are connected, the gate of the second P-type MOS transistor Mp2, the drain of the second P-type MOS transistor Mp2, and the gate of the third P-type MOS transistor Mp3 are connected to the input port CSV, and the source of the third P-type MOS transistor Mp3 is connected to the first resistor r1. The other end of the second resistor r2 is connected, the drain of the third P-type MOS transistor Mp3 and the drain of the first N-type MOS transistor Mn1 are connected to one end of the second resistor r2, the source of the first N-type MOS transistor Mn1 is connected to the input end A of the first inverter INV1, the output end Y of the first inverter INV1 is connected to the input end A of the second inverter INV2, the output end Y of the second inverter INV2 is connected to the input end A of the third inverter INV3, the output end Y of the third inverter INV3 is connected to the signal OCP, and the other end of the second resistor r2 is connected to ground.

2. The current limiting protection circuit for a high voltage linear regulator according to claim 1, characterized in that: The error amplifier includes eight P-type MOS tubes, eleven N-type MOS tubes, a current source IBIAS, a resistor R and a capacitor C. Among the eight P-type MOS tubes, eleven N-type MOS tubes, the current source IBIAS, the resistor R and the capacitor C of the error amplifier, one end of the current source IBIAS, the source of the first P-type MOS tube MP1, the source of the second P-type MOS tube MP2, the source of the fifth P-type MOS tube MP5, the source of the sixth P-type MOS tube MP6 and the source of the seventh P-type MOS tube MP7 are connected to the power supply, and the gate of the first P-type MOS tube MP1, the drain of the first P-type MOS tube MP1, the gate of the second P-type MOS tube MP2 and the third N-type MOS tube MN3 are connected to the power supply. The drain of the second P-type MOS tube MP2 and the source of the third P-type MOS tube MP3 are connected to the source of the fourth P-type MOS tube MP4. The gate of the third P-type MOS tube MP3 is connected to the input port VINP. The drain of the third P-type MOS tube MP3, the drain of the fifth N-type MOS tube MN5, the gate of the fifth N-type MOS tube MN5 and the gate of the tenth N-type MOS tube MN10 are connected. The gate of the fourth P-type MOS tube MP4 is connected to the input port VINN. The drain of the fourth P-type MOS tube MP4, the drain of the sixth N-type MOS tube MN6, the gate of the sixth N-type MOS tube MN6 and the gate of the ninth N-type MOS tube MN9 are connected. The fifth P-type MOS tube MP The gate of the fifth P-type MOS transistor MP5, the drain of the sixth P-type MOS transistor MP6, the gate of the seventh P-type MOS transistor MP7 and the drain of the seventh N-type MOS transistor MN7 are connected, the drain of the sixth P-type MOS transistor MP6, the gate of the eighth P-type MOS transistor MP8 and the drain of the eighth N-type MOS transistor MN8 are connected to one end of the resistor R, the drain of the seventh P-type MOS transistor MP7 and the source of the eighth P-type MOS transistor MP8 are connected to the output port VOUT, the drain of the eighth P-type MOS transistor MP8 and the drain of the eleventh N-type MOS transistor MN11 are connected, the drain of the first N-type MOS transistor MN1, the gate of the first N-type MOS transistor MN1 and the gate of the third N-type MOS transistor MN3 ... The gate of the seventh N-type MOS transistor MN7 and the gate of the eighth N-type MOS transistor MN8 are connected to the other end of the current source IBIAS, the source of the first N-type MOS transistor MN1, the drain of the second N-type MOS transistor MN2, the gate of the second N-type MOS transistor MN2, the gate of the fourth N-type MOS transistor MN4 and the gate of the eleventh N-type MOS transistor MN11 are connected, the source of the third N-type MOS transistor MN3 is connected to the drain of the fourth N-type MOS transistor MN4, the source of the seventh N-type MOS transistor MN7 is connected to the drain of the ninth N-type MOS transistor MN9, the source of the eighth N-type MOS transistor MN8 is connected to the drain of the tenth N-type MOS transistor MN10, the other end of the resistor R is connected to one end of the capacitor C,The source of the second N-type MOS transistor MN2, the source of the fourth N-type MOS transistor MN4, the source of the fifth N-type MOS transistor MN5, the source of the sixth N-type MOS transistor MN6, the source of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10, the source of the eleventh N-type MOS transistor MN11, and the other end of the capacitor C are connected to the ground.

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